BU9831F

Memory ICs Non-volatile electronic potentiometer BU9831 / BU9831F The BU9831 / BU9831F is a non-volatile electronic potentiometer with an internal 2k bit EEPROM. The resistance value can be set by means of serial communications, and because the product contains an internal memory, conditions can be retained. In addition, the 2k bit memory capacity enables digital data to be stored in the memory. •Applicationsbacklight adjustment devices for notebook computers, and other sound adjustment devices for sets Portable LCD •Features2k bit EEPROM 1) Internal 2) 100kΩ (1kΩ × 100 steps) electronic potentiometer 3) Data in memory is automatically read when power supply is turned on, and resistance value is set. 4) Resistance value can be set using serial communications. 5) Low current consumption When operating: 3mA (max.) In standby mode: 200µA (max.) •Absolute maximum ratings (Ta = 25°C) Parameter Applied voltage Power dissipation BU9831 BU9831F Tstg Topr — IW Symbol VCC Pd Limits – 0.3 ~ + 7.0 500∗1 350∗2 – 65 ~ + 125 – 20 ~ + 85 – 0.3 ~ VCC + 0.3 ± 1.0 Unit V mW °C °C V mA Storage temperature Operating temperature Input voltage Wiper current ∗1 Reduced by 5.0mW for each increase in Ta of 1°C over 25°C. ∗2 Reduced by 3.5mW for each increase in Ta of 1°C over 25°C. •Recommended operating conditions Parameter Power supply voltage Power supply voltage for writing Input voltage Voltage at resistor ends Wiper pin voltage Symbol VCC Vccwr VIN VRHL VW Limits 2.7 ~ 5.5 2.8 ~ 5.5 0 ~ VCC 0 ~ VCC 0 ~ VCC Unit V V V V V 1 Memory ICs BU9831 / BU9831F •Block diagram CS VH SK Command decode Control Timing Counter 7bit DIO 16bit Wiper decoder Transistor switch Register array EEPROM Array Write Disable High voltage generator Power supply voltage detector VL VW •Pin assignments VCC VH VW VL 8 7 6 5 BU9831 1 CS 2 SK 3 DIO 4 GND •Pin desoriptions Pin No. 1 2 3 4 5 6 7 8 Pin name CS SK DIO I/O I I I/O — Chip select input Serial data clock input Function Input / output of operating codes, addresses, and serial data Reference voltage of 0V for all input / output GND VL VW VH Resistance pin Resistance low-potential Resistance pin Wiper Resistance pin Resistance high-potential VCC — Connection for power supply 2 Memory ICs BU9831 / BU9831F •Input circuits RESET int. CS SK CS int. •Output circuits DIO OE int. CS int. •Electrical characteristics (unless otherwise noted, Ta = – 20 to + 85°C, V Parameter Input low level voltage Input high level voltage Output low level voltage Output high level voltage Input leakage current Output leakage current Operating current consumption Standby current SK frequency Total resistance Wiper resistance Resistance potential on High side Resistance potential on Low side Symbol VIL VIH VOL VOH ILI ILO ICC ISB fSK RT RW VVH VVL Min. — CC = 5V ± 10%) Conditions Measurement Circuit — — Fig.1 Fig.6 Fig.3 Fig.4 Fig.5 Fig.6 — Typ. — — — — — — — — — Max. 0.2 × VCC — Unit V V V V µA µA mA µA MHz kΩ kΩ V V If = 10µA IW = – 1mA CS, SK, DIO pin CS, SK, DIO pin IOL = 2.1mA IOH = – 0.4mA VIN = 0 ~ VCC VOUT = 0 ~ VCC, CS = VCC f = 1MHz, tE / W = 10ms (WRITE) CS, SK, DIO, VH, VL, VW = VCC 0.8 × VCC 0 VCC – 0.4 –1 –1 — — — — — 0 0 0.4 VCC 1 1 3 200 1 — 100 0.5 — — Fig.7 Fig.8 — — 1 VCC VCC 3 Memory ICs (unless otherwise noted, Ta = – 20 to + 85°C, VCC = 3V ± 10%) Parameter Input low level voltage Input high level voltage Output low level voltage Output high level voltage Input leakage current Output leakage current Operating current consumption Standby current SK frequency Total resistance Wiper resistance Resistance potential on High side Resistance potential on Low side Symbol VIL VIH VOL VOH ILI ILO ICC ISB fSK RT RW VVH VVL Min. — BU9831 / BU9831F Typ. — — — — — — — — — Max. 0.2 × VCC — Unit V V V V µA µA mA µA kHz kΩ kΩ V V If = 10µA Conditions CS, SK, DIO pin CS, SK, DIO pin IOL = 100µA IOH = – 100µA VIN = 0 ~ VCC VOUT = 0 ~ VCC, CS = VCC f = 1MHz, tE / W = 10ms (WRITE) CS, SK, DIO, VH, VL, VW = VCC Measurement Circuit — — Fig.1 Fig.6 Fig.3 Fig.4 Fig.5 Fig.6 0.8 × VCC 0 VCC – 0.4 –1 –1 — — — — — 0 0 0.4 VCC 1 1 2 100 500 — 100 1 — — Fig.7 Fig.8 — — 2 VCC VCC IW = – 500µA •Measurement circuits VCC VCC VCC IOL DIO VCC IOH DIO GND GND V VOL V VOH Data set when output is LOW Data set when output is HIGH Fig. 1 LOW output voltage measurement circuit VCC VCC Fig. 2 HIGH output voltage measurement circuit VCC VCC ILI VCC ILO A VIN = 0 ~ VCC DIO, SK, CS CS DIO A VO = 0 ~ VCC GND GND Fig. 3 Input leakage current measurement circuit Fig. 4 Output leakage current measurement circuit 4 Memory ICs VCC VCC BU9831 / BU9831F VCC VCC ISB A VCC ICC A VCC 1MHz Clock Input VIL SK DIO CS SK DIO CS VH, VL, VW GND GND Fig. 5 Current consumption measurement circuit Fig. 6 Standby current measurement circuit CS SK DIO VCC VH RT = VW VL V I force V I force I force = 10µA GND Fig. 7 Total resistance measurement circuit CS SK DIO VCC VH VW VL Measured after wiper position is set to 00h V IW V force GND R WL = V / I W V force = 1 / 2 · VCC Fig. 8 Wiper resistance measurement circuit on Low side CS VCC VH V SK DIO VW V force GND VL IW Measured after wiper position is set to 64h R WL = V / I W V force = 1 / 2 · VCC Fig. 9 Wiper resistance measurement circuit on High side 5 Memory ICs BU9831 / BU9831F •Command modes Command Write enabled Write disabled Wiper counter data output Wiper counter data input Data read Data write Transmission memory data read Transmission memory data write Increment / decrement wiper WEN WDS WCR WCW DRD DWR TDWR TWDW INC/DEC Start bit 1010 1010 1010 1010 1010 1010 1010 1010 1010 Operation code 0011 0000 1011 0110 1000 0100 1001 0101 1111 Address XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX A0 - A6 X A0 - A6 X A0 - A6 X A0 - A6 X Data — — D8 - D14 X XXXXXXXX D8 - D14 X D0 - D15 D0 - D15 — — — Operation — — Wiper counter → output Input → wiper counter Memory → output Input → memory Memory → wiper counter Wiper counter → memory Wiper counter → INC / DEC X: Don't Care (data may be either 0 or 1) Auto recall function (ARF) • After the power supply is turned on, the data for address 00h is automatically loaded and the wiper position set. At this point, if the data for address 00h is larger than 64h, the wiper position is set to 32h. Since the wiper position is set using seven bits, the eighth bit may be set to any value. This function is carried out 10ms after the power supply is turned on, and subsequently the IC enters the standby state. •Operation timing characteristics (unless otherwise noted, Ta = – 20 to + 85°C, V Parameter CS setup time CS hold time Data setup time Data hold time DO rise delay time DO fall delay time Self-timed programming cycle CS minimum HIGH time Time during which READY / BUSY display is effective Time that DO is HIGH-Z from (CS) Data clock HIGH time Data clock LOW time Resistance value stabilization time Symbol tCSS tCSH tDIS tDIH tPD1 tPD0 tE / W tCS tSV tOH tWH tWL tAW Min. 200 0 150 150 — — — 1 — 0 450 450 — Typ. — — — — — — — — — — — — — Max. — — — — 350 350 10 — 1 400 — — 500 Unit ns ns ns ns ns ns ms µs µs ns ns ns µs CC = 5V ± 10%) 6 Memory ICs (unless otherwise noted, Ta = – 20 to + 85°C, VCC = 5V ± 10%) Parameter CS setup time CS hold time Data setup time Data hold time DO rise delay time DO fall delay time Self-timed programming cycle CS minimum HIGH time Time during which READY / BUSY display is effective Time that DO is HIGH-Z from (CS) Data clock HIGH time Data clock LOW time Resistance value stabilization time Symbol tCSS tCSH tDIS tDIH tPD1 tPD0 tE / W tCS tSV tOH tWH tWL tAW Min. 400 0 300 300 — — — 2 — 0 900 900 — Typ. — — — — — — — — — — — — — Max. — — — — 700 700 15 — 2 800 — — 1000 Unit ns ns ns ns ns ns ms µs µs ns ns ns µs BU9831 / BU9831F •Synchronous data I / O timing CS t CSS SK t WL t DIS Input DIO t PD Output DIO t PD t OH t DIH t WH t CSH t CS Fig. 10 Synchronous data I / O timing Reading of input data is done at the rising edge of SK. Output of data is synchronized to the falling edge of SK. Between commands, CS should be set to HIGH for longer than tCS. If CS remains LOW, the next command cannot be received. 7 Memory ICs BU9831 / BU9831F •Timing charts / disabled (1) Writing enabled H SK L H CS L 1 4 8 12 16 ENABLE = 1 1 DISABLE = 0 0 H DIO L 1 0 1 0 0 0 Fig. 11 Writing enabled and disabled 1) When the power supply is turned on, the writing recognition latch is reset in the same way as when the write disable command is executed. The write enable command must be input before the write command is input. 2) Once the write enable command has been set, it remains effective until either the write disable command is input, or the power supply is turned off. 3) No clocks longer than 16 clocks are required. These will be ignored by the IC if input. The command is received following the clock input for the eight bits of the address subsequent to input of the operation code. The contents of the address are not related to either of these commands, however, and will be ignored. (2) Wiper counter data output (WCR) H SK L t CS H CS L 1 4 8 16 24 H DIO L HIGH-Z HIGH-Z 1 0 1 0 1 0 1 1 (DO) D8 D14 Fig. 12 Wiper counter data output 1) When the Wiper Counter Data Output (WCR) command is received, seven bits of the data at the current wiper position are output to D8, D9, D10, ..., D14, in sequential order. If a clock of longer than 24 clocks is input, indefinite data may be output. (For the DIO output, the data may change at the tPD0 and tPD1 time delays, in response to the internal circuit delay starting from the falling edge of the SK signal. During the tPD0 and tPD1 time internals, data should be loaded after the tPD time has been assured, in case the previous data is indefinite. Refer to Fig. 10, Synchronous data I / O timing.) 8 Memory ICs (3) Wiper counter data input (WCW) H SK L H CS L 1 4 8 24 BU9831 / BU9831F 32 H DIO L 1 0 1 0 0 1 1 0 D8 D14 VW t AW Fig. 13 Wiper counter data input 1) This command is used for direct input of wiper position data. Since the data is 7-bit data sequentially input in the order of D8, D9, D10, ..., D14, it determines one wiper position among 100 taps. Since no address exists at this point, the address is ignored. The resistance stabilizes after an interval of tAW from the rise of the 32nd clock. (4) Data read (DRD) H SK L t CS H CS L 1 4 8 16 32 H DIO L HIGH-Z HIGH-Z 1 0 1 0 1 0 0 0 A0 A6 (DO) D0 D15 Fig. 14 Data read 1) When the data read (DRD) command is received, data is output from the addresses specified by A1 and A0. 2) Output is synchronized to the fall of SK, in order of D0, D1, D2, ..., D15, at the fall of the 16th clock. After 32 clocks have elapsed, the D15 data is retained even if other clocks are input. 9 Memory ICs (5) Data write (DWR) H SK L H CS L 1 4 8 16 32 BU9831 / BU9831F H DIO L tE/W 1 0 1 0 0 1 0 0 A0 A6 D0 D15 Fig. 15 Data write 1) This command stores the input data in the address specified by A0 to A6. 2) CS must be LOW during the write mode input, but once writing begins, CS may be either HIGH or LOW. 3) The internal timer circuit in the IC begins to function after the rising edge of the SK at which the last data D0 was read, and data is written to memory cells during the time period tE / W. The process is terminated automatically. At this point, the SK input during the tE / W time period may be either HIGH or LOW. 4) The time period between input of this command and the automatic termination of the writing of data is the time during which data is written to the internal non-volatile memory, so commands input during this interval will not be accepted. The maximum time interval must be within tE / W. 5) After the write command has been input, if CS is set to LOW after having been set to HIGH, command reception is enabled following termination of the automatic data writing. Data can then be received from SK and DIO. If CS is left at LOW following input of the command, however, without being set to HIGH, input of the command is canceled. (6) Transmission memory data read (TDWR) H SK L 1 4 8 16 H CS L 0 H DIO L 1 0 1 0 1 0 0 1 A0 A6 VW t AW Fig. 16 Transmission memory data read 1) This command transmits the data from the addresses specified by A0 to A6 to the wiper counter. The wiper moves to the position indicated by the seven bits D8 to D14 of the specified address, and the resistance value stabilizes after the tAW time period starting with the fall of the 15th clock. Data subsequent to the 16th clock is ignored. 10 Memory ICs (7) Transmission memory data write (TWDW) H SK L 1 4 8 16 BU9831 / BU9831F H CS L H DIO L tE/W 1 0 1 0 0 1 0 1 A0 A6 Fig. 17 Transmission memory data write 1) This command transmits the wiper position data to the addresses specified by A0 to A6. The data from the seven bits D8 to D14 of the specified address are stored in the memory during the time tE / W, starting from the rise of the 16th clock. 2) Writing is done to the internal non-volatile memory during the time when this command is input and automatic writing of the data is completed. Commands input during this time will not be accepted. The maximum time for this period must be within tE / W. 3) After the write command has been input, if CS is set to LOW after having been set to HIGH, command reception is enabled following termination of the automatic data writing. Data can then be received from SK and DIO. If CS is left at LOW following input of the command, however, without being set to HIGH, input of the command is canceled. (8) INC / DEC H SK L H CS L H DIO L 1 0 1 0 1 1 1 1 DEC INC 1 4 8 9 10 11 VW t AW t AW t AW Fig. 18 Increment / decrement wiper 1) The wiper position is incremented or decremented starting from the next clock following input of the INC / DEC command, based on the status of the INC pin. DIO = H: Incremented. The wiper position moves from the VL to the VH side by 1 tap per clock. DIO = L: Decremented. The wiper position moves from the VH to the VL side by 1 tap per clock. 2) The tap is moved at each rise of the clock, until CS is set to HIGH. When the tap is farthest to the VH side, incrementing is ignored. In the same way, when the tap is farthest to the VL side, decrementing is ignored. 11 Memory ICs BU9831 / BU9831F •Application examples BU9831 VH VW VL Fig. 19 Operation amplifier gain adjustment BU9831 Fine adjustment of the input offset voltage can be done in order to suppress the error voltage of the output based on the input voltage. Fig. 20 Adjustment of the operation amplifier offset voltage BU9831 Reg Output current can be adjusted by adjusting the output load. Fig. 21 Variable output adjustment of regulator •Operation notes (1) When turning the power supply on and off 1) When turning the power supply on and off, CS should be set to HIGH ( = VCC). 2) When CS is LOW, the BU9831 is active, meaning that input can be received. If the power supply is turned on in this state, noise and other factors can cause malfunctioning and erroneous writing. To prevent this, when turning the power supply on, make sure that CS is HIGH ( = VCC). (Example of proper operation) The CS pin is pulled up to VCC. After turning the power supply off, wait at least 10ms before turning it on again. If the power supply is turned on without observing this condition, please be aware that there may be times when the circuits in the IC are not reset. (Example of incorrect operation) The CS pin is LOW when the power supply is turned on or off. In this case, CS is normally LOW, and the EEPROM may cause malfunctioning or erroneous writing because of noise. ∗ Be aware that the case shown in this example may occur even if the CS input is HIGH-Z. 12 Memory ICs BU9831 / BU9831F VCC VCC GND VCC CS GND Correct example Incorrect example (2) Noise countermeasures 1) SK noise If there is noise in the rise of the SK clock input, the system may recognize more clocks than were actually input, and malfunctioning may occur because of offset bits. 2) VCC noise Noise and surges in the power supply line can cause malfunctioning. To eliminate these factors, we recommend installing a bypass capacitor between the power supply and the ground. •External dimension (Units: mm) BU9831 BU9831F 9.3 ± 0.3 6.5 ± 0.3 8 5 5.0 ± 0.2 8 6.2 ± 0.3 4.4 ± 0.2 5 0.51Min. 7.62 3.2 ± 0.2 3.4 ± 0.3 1.5 ± 0.1 1 4 0.3 ± 0.1 0.11 1.27 0.4 ± 0.1 0.3Min. 0.15 2.54 0.5 ± 0.1 0° ~ 15° DIP8 SOP8 0.15 ± 0.1 1 4 13