BU9844GUL-W

High Reliability Series Serial EEPROMs WL-CSP EEPROM family I2C BUS BU9844GUL-W No.10001EAT18 ●Description 2 BU9844GUL-W series is a serial EEPROM of I C BUS interface method. 1.7V single power source action and actions available at 400kHz. ●Features 2 1) Completely conforming to the world standard I C BUS. All controls available by 2 ports of serial clock (SCL) and serial data(SDA) 2) Other devices than EEPROM can be connected to the same port, saving microcontroller port. 3) Actions available at 400kHz clock (1.7V～5.5V) 4) 1.7～5.5V single power source action most suitable for battery use. 5) Page write mode useful for initial value write at factory shipment. 6) Auto erase and auto end function at data rewrite. 7) Low current consumption At write action (5V) : 1.2mA (Typ.) At read action (5V) : 0.2mA (Typ.) At standby action (5V) : 0.1μA (Typ.) 8) Write mistake prevention function Write (write protect) function added. Write mistake prevention function at low voltage. 9) Data rewrite up to 1,000,000times. 10) Data kept for 40 years. 11) Noise filter built in SCL / SDA terminal 12) Shipment data all address FFh. ●Page write Product number BU9844GUL-W ●BU9844GUL-W Type BU9844GUL-W Capacity 16Kbit Bit format 2048×8 Power source voltage 1.7~5.5V Package VCSP50L1 Number of pages 16Byte ●Absolute maximum ratings (Ta=25℃) Parameter Impressed voltage Permissible dissipation Storage temperature range Operating temperature range Terminal voltage * Symbol Vcc Pd Tstg Topr - Ratings -0.3~+6.5 220 *1 Unit V mW ℃ ℃ V -65~125 -40~85 -0.3~Vcc+1.0 When using at Ta=25℃ or higher, 2.2mW (*1) to be reduced per 1℃ ●Recommended action conditions Parameter Power source Input voltage voltage Symbol Vcc Vin Ratings 1.7~5.5 0~Vcc Unit V www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 1/18 2010.09 - Rev.A BU9844GUL-W ●Memory cell characteristics (Ta=25℃, Vcc=1.7~5.5V) Limits Parameter Min Typ. Number of data rewrite times *1 Data hold years *1 Not 100% TESTED Technical Note Max - Unit Times Years 1,000,000 40 - ●Electrical characteristics (Unless otherwise specified, Ta=-40~+85℃, Vcc=1.7~5.5V) Limits Parameter Symbol Min. Typ. “HIGH” input voltage1 “LOW” Input voltage1 “HIGH” input voltage2 “LOW” input voltage2 “LOW” output voltage1 “LOW output voltage2 Input leak current Output leak current VIH1 VIL1 VIH2 VIL2 VOL1 VOL2 ILI ILO ICC1 Current consumption at action ICC2 ISB 0.7Vcc 0.9Vcc -1 -1 - Max. 0.3Vcc 0.1Vcc 0.3 0.2 1 1 2.0 0.5 2.0 Unit V V V V V V μA μA mA mA μA Conditions 2.5V≦Vcc≦5.5V 2.5V≦Vcc≦5.5V 1.7V≦Vcc＜2.5V 1.7V≦Vcc＜2.5V IOL=3.0mA, 2.5V≦Vcc≦5.5V, (SDA) IOL=1.5mA, 1.7V≦Vcc＜2.5V, (SDA) VIN=0V~Vcc VOUT=0V~Vcc(SDA) Vcc=5.5V, fSCL=400kHz, tWR=5ms, Byte write, Page write Vcc=5.5V, fSCL=400kHz Random read, Current read, sequential read Vcc=5.5V, SDA·SCL=Vcc, A2=GND, WP=GND Standby current ○This product is not designed for protection against radioactive rays. www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 2/18 2010.09 - Rev.A BU9844GUL-W ●Action timing characteristics (Unless otherwise specified, Ta=-40～+85℃, Vcc=1.7～5.5V) Parameter SCL frequency Data clock “HIGH” time Data clock “LOW” time SDA, SCL rise time *1 SDA< SCL fall time *1 Start condition hold time Start condition setup time Input data hold time Input data setup time Output data delay time Output data hold time Stop condition setup time Bus release time before transfer start Internal write cycle time Noise removal valid period (SDA, SCL terminal) WP hold time WP setup time WP valid time *1 Not 100% tested. Technical Note Symbol fSCL tHIGH tLOW tR *1 tF *1 tHD:STA tSU:STA tHD:DAT tSU:DAT tPD tDH tSU:STO tBUF tWR tI tHD:WP tSU:WP tHIGH:WP FAST-MODE 2.5V≦Vcc≦5.5V Min. 0.6 1.2 0.6 0.6 0 100 0.1 0.1 0.6 1.2 0 0.1 1.0 Typ. Max. 400 0.3 0.3 0.9 5 0.1 - STANDARD-MODE 1.7V≦Vcc≦5.5V Min. 4.0 4.7 4.0 4.7 0 250 0.2 0.2 4.7 4.7 0 0.1 1.0 Typ. Max. 100 1.0 0.3 3.5 5 0.1 - Unit kHz μs μs μs μs μs μs ns ns μs μs μs μs ms μs ns μs μs ●Sync data input / output timing tR SCL tHD:STA SDA (Input) tBUF SDA (Output) tPD tDH tSU:DAT tLOW tHD:DAT tF tHIGH SCL DATA(1) SDA D1 D0 ACK DATA(n) ACK ｔWR WP stop condition tSU：WP ｔHD：WP ○Input read at the rise edge of SCL ○Data output in sync with the fall of SCL Fig.-1(a) Sync data input / output timing fig.1-(d) WP timing at write execution SCL tSU:STA SDA SCL tHD:STA tSU:STO SDA DATA(1) D1 D0 ACK tHIGH:WP START BIT STOP BIT WP DATA(n) ACK tWR Fig.1-(b) Start – stop bit timing Fig.1-(e) WP timing at write cancel SCL SDA D0 Write data (n-th address) ACK tWR Stop condition Start condition ○At write execution, in the area from the DO taken clock rise of the first DATA (1), to tWR, set WP=”LOW” ○By setting WP “HIGH” in the area, write can be cancelled. When it is set WP=”HIGH” during tWR, write is forcibly ended, and data of address under access is not guaranteed, therefore write it once again. Fig.1-(c) Write cycle timing www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 3/18 2010.09 - Rev.A BU9844GUL-W ●Block diagram VCC GND 9bit Address decoder 9bit Slave – word address register Technical Note 16Kbit EEPROM array 8bit Data register WP START STOP A2 Control circuit ACK SCL High voltage generating circuti Power source voltage detection SDA Fig.2 Block diagram ●Pin assignment and description C B A C2 C1 ○○ B1 B2 ○○ A1 A2 ○○ INDEX post 1 2 Fig.3 BU9844GUL-W(bottom view) Land No. A1 A2 B1 B2 C1 C2 Terminal name VCC A2 WP GND SCL SDA Input/ Output － Input Input Input Input Input /Output Function Power Supply Out of Use (Vcc or GND or OPEN) Write Protect Input Ground （0V） Serial Clock Input Slave and Word Address, Serial Data Input, Serial Data Output *1 *1 An open drain output requires a pull-up resistor. ●Characteristic data (The following values are Typ. ones.) 6 5 4 VIL1,2,3[V] VIH1,2,3[V] SPEC 3 2 1 0 0 1 2 3 Vcc[V] 4 5 6 6 5 4 3 2 1 SPEC 0 0 1 2 3 Vcc[V] 4 5 6 0 0 1 2 3 IOL2[mA] 4 5 6 1 0.8 Ta=85℃ Ta=-40℃ Ta=25℃ VOL2[V] 0.6 0.4 SPEC 0.2 Ta=25℃ Ta=85℃ Ta=85℃ Ta=-40℃ Ta=25℃ Ta=-40℃ Fig.4 H input voltage VIH1,2,3 (A2,SCL,SDA,WP) www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. Fig.5 L input voltage VIL1,2,3 (A2,SCL,SDA,WP) Fig.6 L output voltage VOL2-IOL2 (VCC=1.7V) 4/18 2010.09 - Rev.A BU9844GUL-W 1 1.2 1 0.8 VOL1[V] 1.2 Technical Note SPEC SPEC 1 0.8 ILO[μA] 0.6 0.4 0.8 ILI[μA] 0.6 SPEC 0.4 0.6 0.4 Ta=85℃ Ta=25℃ Ta=85℃ 0.2 0.2 Ta=85℃ 0.2 0 Ta=25℃ Ta=-40℃ Ta=25℃ Ta=-40℃ Ta=-40℃ 0 0 1 2 3 IOL1[mA] 4 5 6 0 0 1 2 3 Vcc[V] 4 5 6 0 1 2 3 Vcc[V] 4 5 6 Fig.7 L input voltage VOL1-IOL1 (Vcc=2.5V) 2.5 0.6 Fig.8 Input leak current ILI(A2,SCL, WP) 2.5 Fig.9 Output leak current ILO (SDA) SPEC 2 fSCL=400kHz DATA=AAh SPEC 0.5 0.4 ICC2[mA] 0.3 0.2 SPEC 2 fSCL=400kHz DATA=AAh ICC1[mA] Ta=25℃ Ta=85℃ 1 Ta=25℃ Ta=85℃ ISB[μA] 1.5 1.5 1 Ta=85℃ Ta=-40℃ 0.5 0.5 Ta=-40℃ 0.1 0 Ta=25℃ Ta=-40℃ 0 0 1 2 3 Vcc[V] 4 5 6 0 0 1 2 3 Vcc[V] 4 5 6 0 1 2 3 Vcc[V] 4 5 6 Fig.10 Consumption current at write action Icc1 (fSCL=400kHz) 10000 Fig.11 Consumption current at write action Icc2 (fSCL=400kHz) 1 1.6 Fig.12 Standby current ISB Ta=-40℃ Ta=25℃ 1000 0.8 1.2 SPEC Ta=85℃ tHIGH [μs] fSCL[kHz] SPEC 100 tLOW[μs] 0.6 SPEC 0.8 0.4 Ta=85℃ Ta=25℃ 10 0.2 0.4 Ta=85℃ Ta=25℃ Ta=-40℃ Ta=-40℃ 1 0 1 2 3 Vcc[V] 4 5 6 0 0 1 2 3 Vcc[V] 4 5 6 0 0 1 2 3 Vcc[V] 4 5 6 Fig.13 SCL frequency fSCL 1 Fig.14 Data clock “H” time tHIGH 1 0.8 tHD:DAT(HIGH)[ns] Fig.15 Data clock “L” time tLOW 50 SPEC 0 tHD:DAT(HIGH)[ns] 0.8 tHD:STA[μs] 0.6 SPEC 0.6 0.4 SPEC Ta=85℃ -50 0.4 Ta=85℃ Ta=25℃ Ta=25℃ Ta=-40℃ Ta=85℃ 0.2 0 -0.2 -100 Ta=25 ℃ Ta=-40℃ 0.2 Ta=-40℃ -150 0 0 1 2 3 Vcc[V] 4 5 6 -200 0 1 2 3 Vcc[V] 4 5 6 0 1 2 3 Vcc[V] 4 5 6 Fig.16 Start condition hold time tHD:STA 200 Fig.17 Start condition setup time tSU:STA 1 1 Fig.18 Input data hold time tHD:DAT SPEC 100 tSU:DAT(HIGH)[ns] SPEC 0.8 SPEC Ta=85 ℃ 0.8 tPD0 [μs] 0 Ta=85℃ Ta=-40℃ Ta=25℃ Ta=25℃ tPD1 [μs] 0.6 0.6 Ta=85℃ Ta=25℃ 0.4 0.4 -100 Ta=-40℃ 0.2 0.2 Ta=-40℃ SPEC 0 SPEC -200 0 1 2 3 Vcc[V] 4 5 6 0 0 1 2 3 Vcc[V] 4 5 6 0 1 2 3 Vcc[V] 4 5 6 Fig.19 Input data setup time tSU:DAT Fig.20 Output data delay time tPD0 Fig.21 Output data delay time tPD1 www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 5/18 2010.09 - Rev.A BU9844GUL-W 1 4 5 Technical Note 0.8 Ta=85℃ Ta=25℃ Ta=-40℃ tDH1[μs] 3 tSU:STO[μs] 4 tDH0[μs] 0.6 3 2 0.4 Ta=85℃ 1 2 Ta=85℃ Ta=25℃ Ta=25℃ Ta=-40℃ SPEC 0 1 2 3 Vcc[V] 4 5 6 1 0.2 SPEC 0 SPEC Ta=-40℃ 0 0 1 2 3 Vcc[V] 4 5 6 0 0 1 2 3 Vcc[V] 4 5 6 Fig.22 Output data hold time tDH1 5 4 Fig.23 Output data hold time tDH1 6 5 4 Fig.24 Stop condition setup time tSU:STO 0.6 0.5 SPEC tBUF[μs] 3 tWR[ms] tI(SCL H) [μs] Ta=-40℃ 0.4 Ta=-40℃ 0.3 0.2 0.1 0 Ta=25℃ Ta=-40℃ 2 3 2 1 0 SPEC 1 Ta=25℃ Ta=85℃ Ta=85℃ Ta=25℃ SPEC Ta=85℃ 0 0 1 2 3 Vcc[V] 4 5 6 0 1 2 3 Vcc[V] 4 5 6 0 1 2 3 Vcc[V] 4 5 6 Fig.25 Bus release time before transfer start tBUF 0.6 0.5 0.4 0.3 0.6 0.5 0.4 Fig.26 Internal write cycle time tWR 0.6 0.5 Fig.27 Noise removal time tI (SCL H) Ta=-40℃ Ta=25℃ tI(SDA H) [μs] 0.3 0.2 0.1 0 Ta=25℃ Ta=85℃ SPEC tI(SDA L) [μs] tI(SCL L) [μs] Ta=-40℃ 0.4 0.3 Ta=-40℃ Ta=25℃ 0.2 0.1 0 0.2 Ta=85℃ Ta=85℃ 0.1 0 0 1 2 3 Vcc[V] 4 5 6 SPEC SPEC 0 1 2 3 Vcc[V] 4 5 6 0 1 2 3 Vcc[V] 4 5 6 Fig.28 Noise removal time tI (SCL L) 0.2 Fig.29 Noise removal time tI (SDA H) 1.2 1 Fig.30 Noise removal time tI (SDA L) 0 SPEC tHIGH:WP[μs] SPEC 0.8 0.6 0.4 0.2 0 tSU:WP[μs] -0.2 Ta=85℃ Ta=-40℃ Ta=25℃ -0.4 Ta=25℃ Ta=-40℃ Ta=85℃ -0.6 0 1 2 3 Vcc[V] 4 5 6 0 1 2 3 Vcc[V] 4 5 6 Fig.31 WP setup time tSU:WP Fig.32 WP valid time tHIGH: WP www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 6/18 2010.09 - Rev.A BU9844GUL-W Technical Note ●I2C BUS communication 2 ○I C BUS data communication 2 I C BUS data communication starts by start condition input, and ends by stop condition input. Data is always 8bit long, and acknowledge is always required after each byte. I2C BUS carries out data transmission with plural devices connected by 2 communication lines of serial data (SDA) and serial clock (SCL). Among devices, there are “master” that generates clock and control communication start and end, and “slave” that is controlled by addresses peculiar to devices. EEPROM becomes “slave”. And the device that outputs data to bys during data communication is called “transmitter”, and the device that receives data is called “receiver “. SDA SCL 1-7 S START ADDRESS condition 8 9 1-7 8 9 1-7 8 9 P STOP condition R/W ACK DATA ACK DATA ACK Fig.33 Data transfer timing ○Start condition (start bit recognition) ・Before executing each command, start condition (start bit) where SDA goes from “HIGH” down to “LOW” when SCL is “HIGH” is necessary. ・This IC always detects whether SDA and SCL are in start condition (start bit) of not, therefore, unless this condition is satisfied, any command is executed. ○Stop condition (stop bit recognition) ・Each command can be ended by SDA rising from “LOW” to “HIGH” when stop condition (stop bit), namely, SCL is “HIGH”. ○Acknowledge (ACK) signal ・This acknowledge (ACK) signal is a software rule to show whether data transfer has been made normally or not. In master and slave, the device (μ-COM at slave address input of write command, read command, and this IC at data output of read command) at the transmitter (sending) side releases the bus after output of 8bit data. ・This device (this IC at slave address input of write command , read command , and μ-COM at data output of read command) at the receiver (receiving) side sets SDA “LOW” during 9 clock cycles, and outputs acknowledge signal (ACK signal) showing that it has received the 8bit data. ・This IC, after recognizing start condition and slave address (8bit), outputs acknowledge signal (ACK signal) “LOW”. ・Each write action outputs acknowledge signal (ACK signal) “LOW”, at receiving 8bit data (word address and write data). ・Each read action outputs 8bit data (read data), and detects acknowledge signal (ACK signal) “LOW”. ・When acknowledge signal (ACK signal) is detected, and stop condition is not sent from the master (μ-COM) side, this IC continues data output. When acknowledge signal (ACK signal) is not detected, this IC stops data transfer, and recognizes stop condition (stop bit), and ends read action. And this IC gets in standby status. ○Device addressing ・Output slave address after start condition from master. ・The significant 4 bits of slave address are used for recognizing a device type. The device code of this IC is fixed to “1010”. ・Next slave addressed (A2 --- device address) are for selecting devices, and plural ones can be used on a same bus according to the number of device addresses. ・The most insignificant bit ( R / W --- READ / WRITE ) of slave address is used for designating write or read action, and is as shown below. Setting R / W to 0 --- write (setting 0 to word address setting of random read) Setting R / W to 1 --- read Type BU9844GUL-W PS is page select bits. Slave address 1 0 1 0 A2 0 PS R / W Maximum number of connected buses 2 www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 7/18 2010.09 - Rev.A BU9844GUL-W Technical Note ●Command ○Write cycle ・Arbitrary data is written to EEPROM. When to write only 1 byte, byte write is normally used, and when to write continuous data of 2 bytes or more, simultaneous write is possible by page write cycle. S T A R T SDA LINE SLAVE ADDRESS W R I T E WA 7 RA /C WK WP WORD ADDRESS WA 0 A C K DATA S T O P 1 0 1 0 P2 P1 P0 D7 D0 A C K Fig.34 Byte write cycle S T A R T SDA LINE SLAVE ADDRESS W R I T E WA 7 RA /C WK WP WORD ADDRESS(n) WA 0 A C K S T O P D0 A C K A C K DATA(n) DATA(n+15) 1 0 1 0 P2 P1 P0 D7 D0 Fig.35 Page write cycle ・Data is written to the address designated by word address (n-th address). ・By issuing stop bit after 8bit data input, write to memory cell inside starts. ・When internal write is started, command is not accepted for tWR (5ms at maximum). ・By page write cycle, the following can be written in bulk. Up to 16 bytes. And when data of the maximum bytes or higher is sent, data from the first byte is overwritten. (Refer to “Internal address increment” of “Notes on page write cycle” in P8/16.) ・As for page write cycle of BU9844GUL-W, after page select bit (PS) of slave address is designated arbitrarily, by continuing data input of 2 bytes or more, the address of insignificant 4 bits is incremented internally, and data up to 16 bytes can be written. Note) 1 0 1 0 P2 P1 P0 Fig.36 Difference of slave address of each type www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 8/18 2010.09 - Rev.A BU9844GUL-W ○Notes on write cycle continuous input S T A R T SDA LINE W R I T E WA 7 Technical Note At STOP (stop bit), Write starts. SLAVE ADDRESS WORD ADDRESS(n) WA 0 DATA(n) DATA(n+15) S T O P S T A R T 1 0 10 1 0 1 0 P2P1P0 D7 D0 D0 RA /C WK A C K A C K A C K Next command Fig.37 Page write cycle Note) 1 tWR (maximum : 5ms) Command is not accepted for this period. 0 1 0 P2 P1 P0 Fig.38 Difference of each type of slave address ○Notes on page write cycle List of numbers of page write Number of Pages Product number 16Byte BU9844GUL-W ○Internal address increment Page write mode WA7 ----0 ----0 ----0 ------------WA4 0 0 0 WA3 0 0 0 WA2 0 0 0 WA1 0 0 0 --------WA0 0 0 0 Increment The above numbers are maximum bytes for respective types. Any types below these can be written. 1page = 16 bytes, but the page write cycle write time is 5ms at maximum for 16byte bulk write. It does not stand 5ms at maximum x 16 bytes = 80ms (Max.). 0Eh 0 0 0 ------------- 0 0 0 1 1 0 1 1 0 1 1 0 0 1 0 Significant bit is fixed. No digit up ○Write protect terminal (WP) ・Write protect function When WP terminal is set Vcc (H level), data rewrite of all addresses is prohibited. When it is set GND (L level), data rewrite of all addresses is enabled. Be sure to connect this terminal to Vcc or GND, or control it to H level or L level. Do not use it open. At extremely low voltage at power ON/OFF, by setting the WP terminal “H”, mistake write can be prevented. During tWR, set the WP terminal always to “L”. If it is set “H”, write is forcibly terminated. For example, when it is started from address 0Eh, therefore, increment is made as below, 0Eh→0Fh→00h→01h ---, which please note. *0Eh --- 0E in hexadecimal, therefore, 00001110 becomes a binary number. www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 9/18 2010.09 - Rev.A BU9844GUL-W ●Command Technical Note ○Read cycle Data of EEPROM is read. In read cycle, there are random read cycle and current read cycle. Random read cycle is a command to read data by designating address, and is used generally. Current read cycle is a command to read data of internal address register without designating address, and is used when to verify just after write cycle. In both the read cycles, sequential read cycle is available, and the next address data next address data can be read in succession. S T A R T SDA LINE W R I T E WA 7 RA /C WK S T A R T R E A D S T O P SLAVE ADDRESS WORD ADDRESS(n) WA 0 A C K SLAVE ADDRESS 1 0 1 0 A2 0 0 DATA(n) 1 0 1 0 P 2 P 1 P0 D7 RA /C WK D0 A C K It is necessary to input “H” to the last ACK. Fig.39 Random Read cycle S T A R T SDA LINE SLA VE ADDRES S R E A D DATA S T O P 1 0 1 0 P2 P1 P0 R / W A C K D7 D0 A C K It is necessary to input “H” to the last ACK. Fig.40 Current read cycle S T A R T SDA LINE R E A D S T O P D0 A C K SLAVE ADDRESS DATA(n) DATA (n+x) 1 0 1 0 P2 P1 P0 RA /C WK D7 D0 A C K A C K D7 Fig.41 Sequential read cycle ・In random read cycle, data of designated word address can be read. ・When the command just before current read cycle is random read cycle, current read cycle (each including sequential read cycle), data of incremented last read address (n-th) address, i.e., data of the (n+1)-th address is output. ・When ACK signal “LOW” after D0 is detected, and stop condition is not sent from the master (μ-COM) side, the next address data can be read in succession. ・Read cycle is ended by stop condition where “H” is input to ACK signal after D0 and SDA signal is started at SCL signal “H”. ・When “H” is not input to ACK signal after D0, sequential read gets in, and the next data is output. Therefore, read command cycle cannot be ended. When to end read command cycle, be sure input stop condition to input “H” to ACK signal after D0, and to start SDA at SCL signal “H”. ・Sequential read is ended by stop condition where “H” is input to ACK signal after arbitrary D0 and SDA is started at SCL signal “H”. Note) 1 0 1 0 P2 P1 P0 Fig.42 Difference of slave address of each type www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 10/18 2010.09 - Rev.A BU9844GUL-W Technical Note ●Software reset Software reset is executed when to avoid malfunction after power on, and to reset during command input. Software reset has several kinds, and 3 kinds of them are shown in the figure below. (Refer to Fig.43(a), Fig.43(b) and Fig.43(c).) In dummy clock input area, release the SDA bus (“H” by pull up). In dummy clock area, ACK output and read data “0” (both “L” level) may be output from EEPROM, therefore, if “H” is input forcibly, output may conflict and over current may flow, leading to instantaneous power failure of system power source or influence upon devices. Dummy clock x14 Start x2 SCL SDA 1 2 13 14 Normal command Normal command Fig.43-(a) The case of dummy clock + START + START + command input Dummy clock x9 Start Start SCL SDA 1 2 8 9 Normal command Normal command Fig.43-(b) The case of START + 9 dummy clocks + START + command input Start x 9 SCL SDA 1 2 3 7 8 9 Normal command Normal command Fig.43-(c) START x 9 + command input * Start normal command from START input. ●Acknowledge polling During internal write execution, all input commands are ignored, therefore ACK is not sent back. During internal automatic write execution after write cycle input, next command (slave address) is sent, and if the first ACK signal sends back “L”, then it means end of write action, while if it sends back “H”, it means now in writing. By use of acknowledge polling, next command can be executed without waiting for tWR=5ms. When to write continuously, R / W = 0, when to carry out current read cycle after write, slave address R / W = 1 is sent, and if ACK signal sends back “L”, then execute word address input and data output and so forth. During internal write, First write command ACK = HIGH is sent back. S T A R T S Slave T A address R T S T A R T Write command S T O P A C address K H Slave A C K H … tWR Second write command S T A R T A C address K H Slave S T Slave A R address T A C K L Word address A C K L A C K L S T O P … Data tWR After completion of internal write, ACK = LOW is sent back, so input next word address and data in succession. Fig.44 Case to continuously write by acknowledge polling www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 11/18 2010.09 - Rev.A BU9844GUL-W ●WP valid timing (write cancel) Technical Note WP is usually to “H” or “L”, but when WP is used to cancel write cycle and so forth, pay attention to the following WP valid timing. During write cycle execution, in cancel valid area, by setting WP = “H”, write cycle can be cancelled. In both byte write cycle and page write cycle, the area from the first start condition of command to the rise of clock to taken in D0 of data (in page write cycle, the first byte data) is cancel invalid area. WP input in this area becomes don’t care. Set the setup time to rise of D0 taken SCL 100ns or more. The area from the rise of SCL to take in D0 to the end of internal automatic write (tWR) is cancel valid area. And, when it is set WP = “H” during tWR, write is ended forcibly, data of address under access is not guaranteed, therefore, write it once again. (Refer to Fig.45.) After execution of forced end by WP, standby status gets in, so there is no need to wait for tWR (5ms at maximum). ·Rise of D0 taken clock SCL SDA D1 D0 ACK SCL ·Rise of SDA SDA Enlarged view S A A T Slave C Word C D7 D6 D5 D4 D3 D2 D1 D0 A K address K R address L L T WP cancel invalid area D0 ACK Enlarged view A C K L S T O P tWR SDA A C K L Data WP cancel valid area Write forced end WP Data is not written Data not guaranteed Fig. 45 WP valid timing ●Command cancel by start condition and stop condition During command input, by continuously inputting start condition and stop condition, command can be cancelled. (Refer to fig.46) However, in ACK output area and during data read, SDA bus may output “L”, and in this case, start condition and stop condition cannot be input, so reset is not available. Therefore, execute software reset. and when command is cancelled by start, stop condition, during random read cycle, sequential read cycle, or current read cycle, internal setting address is not determined, therefore, it is not possible to carry out current read cycle in succession. When to carry out read cycle in succession, carry out random read cycle. SCL SDA 1 0 1 0 Start condition Stop condition Fig. 46 Case of cancel by start, stop condition during slave address input www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 12/18 2010.09 - Rev.A BU9844GUL-W ●I/O peripheral circuit Technical Note ○Pull up resistance of SDA terminal SDA is NMOS open drain, so requires pull up resistance. As for this resistance value (RPU), select an appropriate value to this resistance value from microcontroller VIL, IL, and VOL-IOL characteristics of this IC. If RPU is large, action frequency is limited. The smaller the RPU, the larger the consumption current at action. ○Maximum value of RPU The maximum value of RPU is determined by the following factors. (1) SDA rise time to be determined by the capacity (CBUS) of bus line of RPU and SDA should be tR or below. And AC timing should be satisfied even when SDA rise time is late. A (2) The bus electric potential ○ to be determined by input leak total (IL) of device connected to bus at output of “H” to SDA bus and RPU should sufficiently secure the input “H” level (VIH) of microcontroller and EEPROM including recommended noise margin 0.2Vcc. VCC-ILRPU-0.2 VCC ≥ VIH ∴ RPU ≦ 0.8VCC-VIH IL IL Microcontroller RPU A IL Bus line capacity CBUS BU9844GUL-W SDA terminal Ex.) When VCC =3V, IL=10μA, VIH=0.7 Vcc from (2) 0.8×3-0.7×3 ≦ RPU 10×10-6 ≦ 300 ［kΩ］ Fig.47 I/O circuit diagram ○Minimum value of RPU The minimum value of RPU is determined by the following factors. (1) When IC outputs LOW, it should be satisfied that VOLMAX = 0.4V and IOLMAX = 3mA. VCC-VOL VCC-VOL ∴ RPU ≧ ≦ IOL RPU IOL (2) VOLMAX = 0.4V should secure the input “L” level (VIL) of microcontroller and EEPROM including recommended noise margin 0.1VCC. VOLMAX ≤ VIL – 0.1VCC Ex.) When VCC = 3V, VOL = 0.4V, IOL = 3mA, microcontroller, EEPROM VIL = 0.3VCC From (1), RPU ≧ 3-0.4 -3 3×10 ［Ω］ ≧ 867 And VOL VIL =0.4 ［V］ =0.3×3 =0.9 ［V］ Therefore, the condition (2) is satisfied. ○Pull up resistance of SCL terminal When SCL control is made at CMOS output port, there is no need, but in the case there is timing where SCL becomes “Hi-Z”, add a pull up resistance. As for the pull up resistance, one of several kΩ ~ several ten kΩ is recommended in consideration of drive performance of output port of microcontroller. ●A2, WP process ○Process of device address terminals (A2) Check whether the set device address coincides with device address input sent from the master side or not, and select one among plural devices connected to a same bus. Connect this terminal to pull up of pull down, or VCC or GND. ○Process of WP terminal WP terminal is the terminal that prohibits and permits write in hardware manner. In “H” status, only READ is available and WRITE of all addresses is prohibited. In the case of “L”, both are available. In the case to use it as an ROM, it is recommended to connect it to pull up or VCC. In the case to use both READ and WRITE, control WP terminal or connect it to pull down or GND. www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 13/18 2010.09 - Rev.A BU9844GUL-W ●Cautions on microcontroller connection Technical Note ○Rs 2 In I C BUS, it is recommended that SDA port is of open drain input / output. However, when to use COMS input / output of tri state to SDA port, insert a series resistance Rs between the pull up resistance RPU and the SDA terminal of EEPROM. This controls over protection of SDA terminal against surge. Therefore, even when SDA port is open drain input / output, Rs can be used. ACK SCL RPU RS SDA “H” output of microcontroller “L” output of EEPROM Microcontroller EEPROM Over current flows to SDA line by “H” output of microcontroller and “L” output of EEPROM. Fig.48 I/O circuit diagram Fig.49 Input / output collision timing ○Maximum value of Rs The maximum value of Rs is determined by the following relations. (1) SDA rise time to be determined by the capacity (CBUS) of bus line of RPU and SDA should be tR or below. And AC timing should be satisfied even when SDA rise time is late. (2) The bus electric potential A to be determined by RPU and Rs at the moment when EEPROM outputs “L” to SDA bus should sufficiently secure the input “L” level (VIL) of microcontroller including recommended noise margin 0.1VCC. VCC RPU A RS IOL Bus line capacity CBUS (VCC-VOL)×RS RPU+RS VOL + VOL+0.1VCC≦VIL × RPU ∴ RS ≦ VIL-VOL-0.1VCC 1.1VCC-VIL Example) When VCC=3V, VIL=0.3VCC, VOL=0.4V, RPU=20kΩ, From(2) RS ≦ 0.3×3-0.4-0.1×3 1.1×3-0.3×3 × 20×103 VIL Microcontroller EEPROM ≦ 1.67［kΩ］ Fig.50 I/O circuit diagram ○Minimum value of Rs The minimum value of Rs is determined by over current at bus collision. When over current flows, noises in power source line, and instantaneous power failure of power source may occur. When allowable over current is defined as I, the following relation must be satisfied. Determine the allowable current in consideration of impedance of power source line in set and so forth. Set the over current to EEPROM 10mA or below. VCC ≦ I RS RP U RS O ver current I "H" output "L" output ∴ RS ≧ VCC I Example) When Vcc =3V, I = 10mA RS ≧ 3 -3 10×10 Microcontroller EEPROM Fig.51 I/O Circuit diagram ≧ 300［Ω］ www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 14/18 2010.09 - Rev.A BU9844GUL-W ●I2C BUS input / output circuit ○Input (A2,SCL) Technical Note Fig.52 Input pin circuit diagram ○Input / output (SDA) Fig.53 Input / output pin circuit diagram ○Input (WP) Fig.54 Input pin circuit diagram www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 15/18 2010.09 - Rev.A BU9844GUL-W ●Notes on power ON Technical Note At power on, in IC internal circuit and set, Vcc rises through unstable low voltage area, and IC inside is not completely reset, and malfunction may occur. To prevent this, function of POR circuit and LVCC circuit are equipped. To assure the action, observe the following conditions at power on. 1. Set SDA= “H” and SCL = “L” or “H”. 2. Start power source so as to satisfy the recommended conditions of tR, tOFF, and Vbot for operating POR circuit. tR VCC Recommended conditons of tR, tOFF, Vbot tR tOFF tOFF 10ms or higher 10ms or higher Vbot 0.3V or below 0.2V or below 10ms or below Vbot 0 100ms or below Fig. 55 Rise waveform diagram 3. Set SDA and SCL so as not to become “Hi-Z”. When the above conditions 1 and 2 cannot be observed, take the following countermeasures. a) In the case when the above condition 1 cannot be observed. When SDA becomes “L” at power on. → Control SCL and SDA as shown below, to make SCL and, “H” and “H”. V CC SCL tLOW SDA A fter Vcc becomes stable tDH tSU:DAT After Vcc becomes stable tSU:DAT Fig.56 When SCL =”H” and SDA = “L” Fig.57 When SCL = “H” and SDA = “L” b) In the case when the above condition 2 cannot be observed. → After power source becomes stable, execute software reset (P10). c) In the case when the above conditions 1 and 2 cannot be observed. → Carry out a), and then carry out b). ●Low voltage malfunction prevention function LVCC circuit prevents data rewrite action at low power, and prevents wrong write. At LVCC voltage (Typ. = 1.2V) or below, it prevent data rewrite. ●Vcc noise countermeasures ○Bypass capacitor When noise or surge gets in the power source line, malfunction may occur, therefore, for removing tese, it is recommended to attach a by pass capacitor (0.1μF) between IC Vcc and GND. At that moment , attach it as close to IC as possible. And, it is also recommended to attach a bypass capacitor between board Vcc and GND. www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 16/18 2010.09 - Rev.A BU9844GUL-W ●Notes for use Technical Note (1) Described numeric values and data are design representative values, and the values are not guaranteed. (2) We believe that application circuit examples are recommendable, however, in actual use, confirm characteristics further sufficiently. In the case of use by changing the fixed number of external parts, make your decision with sufficient margin in consideration of static characteristics and transition characteristics and fluctuations of external parts and our LSI. (3) Absolute maximum ratings If the absolute maximum ratings such as impressed voltage and action temperature range and so forth are exceeded, LSI may be destructed. Do not impress voltage and temperature exceeding the absolute maximum ratings. In the case of fear exceeding the absolute maximum ratings, take physical safety countermeasures such as fuses, and see to it that conditions exceeding the absolute maximum ratings should not be impressed to LSI. (4) GND electric potential Set the voltage of GND terminal lowest at any action condition. Make sure that each terminal voltage is lower than that of GND terminal. (5) Thermal design In considereation of permissible loss in actual use condition, carry out heat design with sufficient margin. (6) Terminal to terminal shortcircuit and wrong packaging When to package LSI onto a board, pay sufficient attention to LSI direction and displacement. Wrong packaging may destruct LSI. And in the case of shortcircuit between LSI terminals and terminals and power source, terminal and GND owing to foreign matter, LSI may be destructed. (7) Use in a strong electromagnetic field may cause malfunction, therefore, evaluate design sufficiently. www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 17/18 2010.09 - Rev.A BU9844GUL-W ●Ordering part number Technical Note B Part No. U 9 Part No. 8 4 4 G U L -W W-CELL E 2 Package GUL : VCSP50L1 Packaging and forming specification E2: Embossed tape and reel VCSP50L1(BU9844GUL-W) 1PIN MARK 1.84±0.1 Tape Quantity 0.1±0.05 0.55MAX Embossed carrier tape 3000pcs E2 The direction is the 1pin of product is at the upper left when you hold 1.60±0.1 Direction of feed S ( reel on the left hand and you pull out the tape on the right hand ) 0.06 S 6-φ0.25±0.05 0.05 A B (φ0.15)INDEX POST C B A B A 1 2 P=0.5×2 0.42±0.1 0.55±0.1 0.5 1pin (Unit : mm) Reel Direction of feed ∗ Order quantity needs to be multiple of the minimum quantity. www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 18/18 2010.09 - Rev.A Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). The Products specified in this document are not designed to be radiation tolerant. While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuelcontroller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law. Thank you for your accessing to ROHM product informations. More detail product informations and catalogs are available, please contact us. ROHM Customer Support System http://www.rohm.com/contact/ www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. R1010A