FEDD56V62160MTA-02
Issue Date : Oct, 7, 2011
MD56V62160M-xxTA
4-Bank×1,048,576-Word×16-Bit SYNCHRONOUS DYNAMIC RAM
DESCRIPTION
The MD56V62160M-xxTA is a 4-Bank 1,048,576-word 16-bit Synchronous dynamic RAM. The
device operates at 3.3V. The inputs and outputs are LVTTL compatible.
FEATURES
Product Name
MD56V62160M-XXTA
Organization
4Bank x 1,048,576Word x 16Bit
Address Size
4,096Row x 256Column
Power Supply VCC (Core)
3.3V0.3V
Power Supply VCCQ (I/O)
3.3V0.3V
Interface
LVTTL compatible
Operating Frequency
Max. 143MHz (Speed Rank 7)
Operating Temperature
0 to +70°C
/CAS Latency
2, 3
Burst Length
1, 2, 4, 8, Full page
Burst Type
Sequential, Interleave
Write Mode
Burst, Single
Refresh
Auto-Refresh, 4,096cycle/64ms, Self-Refresh
PRODUCT FAMILY
VCC
Family
Max. Frequency
MD56V62160M -7TA
Access Time (Max.)
tAC2
tAC3
143MHz
5.4ns
5.4ns
MD56V62160M -75TA
133MHz
5.4ns
5.4ns
MD56V62160M -8TA
125MHz
6ns
6ns
MD56V62160M -10TA
100MHz
6ns
6ns
3.0V～3.6V
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FEDD56V62160MTA-02
MD56V62160M-xxTA
PIN CONFIGURATION (TOP VIEW)
VCC 1
54 VSS
DQ1 2
53 DQ16
VCCQ 3
DQ2 4
52 VSS
51 DQ15
DQ3 5
50 DQ14
VSSQ 6
49 VCCQ
DQ4 7
48 DQ13
DQ5 8
VCCQ 9
47 DQ12
46 VSSQ
DQ6 10
45 DQ11
DQ7 11
44 DQ10
VSSQ 12
43 VCCQ
DQ8 13
42 DQ9
41 VSS
VCC 14
40 NC
LDQM 15
/WE 16
39 UDQM
38 CLK
/CAS 17
/RAS 18
37 CKE
/CS 19
36 NC
A13 20
35 A11
A12 21
34 A9
A10 22
33 A8
A0 23
A1 24
32 A7
A2 25
30 A5
A3 26
29 A4
28 VSS
31 A6
VCC 27
54-Pin Plastic TSOP(II)
(K Type)
Pin Name
Function
Pin Name
Function
CLK
System Clock
UDQM, LDQM
Data Input / Output Mask
/CS
Chip Select
DQi
Data Input / Output
CKE
Clock Enable
VCC
Power Supply (3.3V)
A0 – A11
Address
VSS
Ground (0V)
A12,A13
Bank Select Address
VCCQ
Data Output Power Supply (3.3V)
/RAS
Row Address Strobe
VSSQ
Data Output Ground (0V)
/CAS
Column Address Strobe
NC
No Connection
/WE
Write Enable
Note : The same power supply voltage must be provided to every VCC pin .
The same power supply voltage must be provided to every VCCQ pin.
The same GND voltage level must be provided to every VSS pin and VSSQ pin.
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FEDD56V62160MTA-02
MD56V62160M-xxTA
PIN DESCRIPTION
CLK
Clock (Input)
Fetches all inputs at the “H” edge.
Clock Enable (Input)
CKE
Masks system clock to deactivate the subsequent CLK operation.
If CKE is deactivated, system clock will be masked so that the subsequent CLK operation is
deactivated. CKE should be asserted at least one cycle prior to a new command.
Chip Select (Input)
/CS
Disables or enables device operation by asserting or deactivating all inputs except CLK, CKE
and UDQM, LDQM.
Row Address Strobe (Input)
/RAS
Functionality depends on the combination with other signals. For detail, see the function truth
table.
Column Address Strobe (Input)
/CAS
Functionality depends on the combination with other signals. For detail, see the function truth
table.
Write Enable (Input)
/WE
A12,A13
Functionality depends on the combination with other signals. For detail, see the function truth
table.
Bank Address (Input)
(BA0,BA1)
Slects bank to be activated during row address latch time and selects bank for precharge and
read/write during column address latch time.
A0 to A11
Row & column multiplexed. (Input)
Row address
: RA0 – RA11
Column Address
: CA0 – CA7
DQ0 to DQ15
3-state Data Bus (Input/Output)
DQ Mask (Input)
UDQM, LDQM
Masks the read data of two clocks later when DQM are set “H” at the “H” edge of the clock
signal. Masks the write data of the same clock when DQM are set “H” at the “H” edge of the
clock signal. UDQM controls DQ15 to DQ8, LDQM controls DQ7 to DQ0.
Power Supply (Core), Ground (Core)
VCC, VSS
The same power supply voltage must be provided to every VCC pin.
The same GND voltage level must be provided to every VSS pin.
Power Supply (I/O), Ground (I/O)
VCCQ, VSSQ
The same power supply voltage must be provided to every VCCQ pin.
The same GND voltage level must be provided to every VSSQ pin.
NC
No Connection
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FEDD56V62160MTA-02
MD56V62160M-xxTA
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
VIN, VOUT
–0.5 to VCC+0.5
V
VCC
–0.5 to 4.6
V
VCCQ
–0.5 to 4.6
V
Power Dissipation (Ta=25°C)
PD
1000
mW
Short Circuit Output Current
IOS
50
mA
Storage Temperature
Tstg
–55 to 150
°C
Ta
0 to +70
°C
Voltage on Input/Output Pin Relative to VSS
VCC Supply Voltage
VCCQ Supply Voltage
Operating Temperature
Notes: 1. Permanent device damage may occur if Absolute Maximum Ratings are exceeded.
2. Functional operation should be restricted to recommended operating condition.
3. Exposure to higher than recommended voltage for extended periods of time could affect device
reliability.
Recommended Operating Conditions (1/2)
Voltages referenced to VSS = 0 V
Parameter
Symbol
Min.
Typ.
Max.
Unit
Note
Power Supply Voltage (Core)
VCC
3.0
3.3
3.6
V
1,2
Power Supply Voltage (I/O)
VCCQ
3.0
3.3
3.6
V
1,2
Ground
VSS, VSSQ
0
0
0
V
Notes: 1. The voltages are referenced to VSS.
2. The power supply voltages should input stable voltage. The power supply voltages should not input
oscillated voltage. If voltages are oscillating, please insert capacitor near the power supply pins and stop
oscillation of voltage.
Recommended Operating Conditions (2/2)
Ta= 0 to +70°C
Parameter
Symbol
Min.
Max.
Unit
Note
Input High Voltage
VIH
2.0
VCC + 0.3
V
1, 2
Input Low Voltage
VIL
0.3
0.8
V
1, 3
Notes: 1. The voltages are referenced to VSS.
2. The input voltage is VCC + 0.5V when the pulse width is less than 20ns (the pulse width is with respect
to the point at which VCC is applied).
3. The input voltage is 0.5V when the pulse width is less than 20ns (the pulse width respect to the point at
which VSS and VSSQ are applied).
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FEDD56V62160MTA-02
MD56V62160M-xxTA
Pin Capacitance
Ta = 25°C, VCC＝VCCQ＝3.3V, f＝1MHz
Parameter
Symbol
Min.
Max.
Unit
CCLK
2
pF
CIN
2
pF
COUT
3.5
pF
Input Capacitance (CLK)
Input Capacitance
(A0 to A13, /RAS, /CAS, /WE, /CS, CKE, UDQM, LDQM)
Input/Output Capacitance (DQ0 to DQ15)
DC Characteristics (Input/Output)
Parameter
Ta= 0 to +70°C
VCC = VCCQ = 3.3V0.3V
Max.
Unit
Symbol
Condition
Min.
Output High Voltage
VOH
IOH = 0.2mA
2.4
V
Output Low Voltage
VOL
IOL = 0.2mA
0.4
V
Input Leakage Current
ILI
0V VIN VCCQ
10
10
µA
Output Leakage Current
ILO
10
10
µA
Note : The voltages are referenced to VSS.
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FEDD56V62160MTA-02
MD56V62160M-xxTA
DC Characteristics (Power Supply Current)
Ta= 0 to +70°C
VCC = VCCQ = 3.3V0.3V
Parameter
MD56V62160M-xxTA
Condition
Symbol
Bank
CKE
Unit Note
-7
-7.5
-8
-10
Max.
Max.
Max.
Max.
100
90
80
70
mA
1, 2
tCC =
Min.
40
35
35
30
mA
3
tCC =
Min.
3
3
3
3
mA
2
tCC =
Min.
45
40
40
35
mA
3
tCC =
Min.
140
130
120
100
mA
1, 2
140
130
120
100
mA
2
Other
CKE VIH
Average Power
Supply Current
(Operating)
ICC1
Power Supply
Current
(Standby)
ICC2
All Banks
Precharge
Average Power
Supply Current
(Clock
Suspension)
ICC3S
All Banks
Active
Average Power
Supply Current
(Active Standby)
ICC3
One Bank
Active
Power Supply
Current (Burst)
ICC4
All Banks
Active
Power Supply
Current
(Auto-Refresh)
ICC5
All Bank
Active
CKE
VIH
Average Power
Supply Current
(Self-Refresh)
ICC6
All Banks
Precharge
CKE
VIL
tCC =
Min.
2
2
2
2
mA
Average Power
Supply Current
(Power Down)
ICC7
All Banks
Precharge
CKE
VIL
tCC =
Min.
2
2
2
2
mA
One Bank
Active
tCC = Min.
tRC = Min.
No Burst
CKE
VIH
CKE
VIL
CKE
VIH
CKE
VIH
tCC =
Min.
tRC =
Min.
Notes: 1. Measured with outputs open.
2. The address and data can be changed once or left unchanged during one cycle.
3. The address and data can be changed once or left unchanged during two cycles.
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FEDD56V62160MTA-02
MD56V62160M-xxTA
AC Characteristics (1/2)
Ta= 0 to +70°C
VCC = VCCQ = 3.3V0.3V
Note1,2
MD56V62160M-xxTA
Parameter
Clock Cycle
Time
CL=3
Symbol
tCC3
CL=2 tCC2
Access
CL=3 tAC3
Time from
CL=2 tAC2
Clock
Clock High Pulse
tCH
Time
-7
-75
Unit
-8
Note
-10
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
7
7.5
8
10
ns
10
10
10
10
ns
5.4
5.4
6
6
ns
3,4
5.4
5.4
6
6
ns
3,4
2
2.5
3
3
ns
4
4
Clock Low Pulse
Time
tCL
2
2.5
3
3
ns
Input Setup Time
tSI
1.5
1.5
2
2
ns
Input Hold Time
tHI
0.8
0.8
1
1
ns
Output Low
Impedance Time
tOLZ
2
2
2
2
ns
tOHZ
5.4
5.4
6
6
ns
tOH
2
2
2
2
ns
tRC
60
65
70
70
ns
RAS Precharge
Time
tRP
18
18
20
20
ns
RAS Pulse Width
tRAS
42
105
45
105
50
105
50
105
ns
tRCD
16
16
20
20
ns
Write Recovery
Time
tWR
2
2
2
2
Cy
cle
/RAS to /RAS Bank
Active Delay Time
tRRD
10
15
20
20
ns
Refresh Time
tREF
64
64
64
64
ms
tPDE
tSI+1C
LK
tSI+1C
LK
tSI+1C
LK
tSI+1C
LK
ns
tRCA
60
65
70
70
ns
from Clock
Output High
Impedance Time
from Clock
Output Hold from
Clock
Random Read or
Write Cycle Time
/RAS to /CAS Delay
Time
Power-down Exit
setup Time
Refresh cycle Time
3
5
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MD56V62160M-xxTA
AC Characteristics (2/2)
Ta= 0 to +70°C
VCC = VCCQ = 3.3V0.3V
Note1,2
Parameter
Symbol
/CAS to /CAS Delay Time
(Min.)
MD56V62160M-xxTA
Unit
-7
-7.5
-8
-10
lCCD
1
1
1
1
Cycle
Clock Disable Time from
CKE
lCKE
1
1
1
1
Cycle
Data Output High
Impedance Time from
UDQM, LDQM
lDOZ
2
2
2
2
Cycle
Dada Input Mask Time
from UDQM, LDQM
lDOD
0
0
0
0
Cycle
Data Input Mask Time from
Write Command
lDWD
0
0
0
0
Cycle
Data Output High
Impedance Time from
Precharge Command
lROH
CL
CL
CL
CL
Cycle
Active Command Input
Time from Mode Register
Set Command Input (Min.)
lMRD
2
2
2
2
Cycle
Write Command Input Time
from Output
lOWD
2
2
2
2
Cycle
Note
Notes: 1. AC measurements assume that tT = 1ns,.
2. Test condition
Parameter
Test Condition
Input voltage for AC measurement
2.4
0.4
Transition Time for AC measurement
Reference level for timing of input signal (tT1ns)
Reference level for timing of input signal (tT>1ns)
Reference level for timing of output signal
Unit
V
tT＝1
ns
1.4
V
VIH Min.
VIL Max.
1.4
V
V
1.4V
3. Output load.
Z=50
50
30pF (External Load)
4. If tT is longer than 1ns, then the reference level for timing of input signals is VIH and VIL.
5. It is necessary to operate auto-refresh 4096 cycles within tREF.
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MD56V62160M-xxTA
POWER ON AND INITIALIZE
Power on Sequence
1. Apply power and attempt to maintain CKE=”H” and other pins are NOP condition at the input.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200 s.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue mode register set command to initialize the mode register.
6. Issue extended mode register set command to initialize the extended mode register.
Mode Register Set Command (MRS)
The mode register stores the data for controlling the various operating
modes. It programs the /CAS latency, burst type, burst length and write
mode. The default value of the mode register is not defined, therefore the
mode register must be written after power up to operate the SDRAM.
The mode register is written by mode register set command MRS. The
state of address pins A13 to A0 in the same cycle as MRS is the data
written in the mode register. Refer to the table for specific codes for
various /CAS latencies, burst type, burst length and write mode.
MRS
CLK
CKE
n-1
n
H
X
/CS
L
/RAS
X
L
/CAS
(Idle)
L
/WE
L
BA1(A12)
X
0
BA0(A13)
X
0
A11~A0
X
V
V: The value of mode register set
Extended Mode Register Set Command (EMRS)
EMRS
CLK
The extended mode register stores the data for controlling output driver
strength. The default value of the extended mode register is defined.
Therefore the mode register must be written after power up to operate the
SDRAM. The extended mode register is written by extended mode
register set command EMRS. The state of address pins A13 to A0 in the
same cycle as EMRS is the data written in the extended mode register.
Refer to the table for specific codes for various self-Refresh operations.
CKE
n-1
n
H
X
/CS
L
/RAS
X
/CAS
(Idle)
/WE
L
L
L
BA1(A12)
X
BA0(A13)
X
0
A11~A0
X
V
1
V: The value of extended mode
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FEDD56V62160MTA-02
MD56V62160M-xxTA
Mode Register Field Table To Program Mode
Write Burst Mode
/CAS Latency
Burst Type
Burst Length
A9
WM
A6
A5
A4
CL
A3
BT
A2
A1
A0
BT = 0
BT = 1
0
Burst
0
0
0
Reserved
0
Sequential
0
0
0
1
1
1
Single
0
0
1
Reserved
1
Interleave
0
0
1
2
2
0
1
0
2
0
1
0
4
4
0
1
1
3
0
1
1
8
8
1
0
0
Reserved
1
0
0
Reserved
Reserved
1
0
1
Reserved
1
0
1
Reserved
Reserved
1
1
0
Reserved
1
1
0
Reserved
Reserved
1
1
1
Reserved
1
1
1
Full Page
Reserved
Notes: 1. A13 and A12 should stay “0” during mode set cycle.
2. A7, A8, A10 and A11 should stay “0” during mode set cycle.
3. Don’t set address keys of “Reserved”.
Extended Mode Register Set Address Keys
Output Driver Strength
A6
A5
DS
0
0
Full (Default)
0
1
1/2
1
0
Reserved
1
1
1/4
Notes: 1. A12 should stay “H” and A13 should stay “0” during mode set cycle.
2. A0, A1, A2, A3, A4, A7, A8, A9, A10 and A11 should stay “0” during mode set cycle.
3. Don’t set address keys of “Reserved”.
4. If don’t set EMRS, DS is set to default (Full).
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MD56V62160M-xxTA
Output Driver Characteristics
Output Driver Strengt=1/4
Driver Strength Pull Up
V-I Characteristics
0
80
Ta=-40℃～85℃
VCC、VCCQ=3.0V～3.6V
70
-10
min.
-20
60
-30
50
-40
Typical
-50
Ids[mA]
Ids[mA]
Driver Strength Pull Down
V-I Characteristics
Ta=-40℃～85℃
VCC、VCCQ=3.0V～3.6V
max.
Typical
40
30
20
-60
max.
-70
min.
10
-80
0
0
0.5
1
1.5
2
Vgs[V]
2.5
3
0.0
0.5
1.0
1.5
2.0
Vgs[V]
2.5
3.0
Output Driver Strengt=1/2
Driver Strength Pull Up
V-I Characteristics
Ta=-40℃～85℃
VCC、VCCQ=3.0V～3.6V
0
140
-20
120
-40
-60
-80
Ta=-40℃～85℃
VCC、VCCQ=3.0V～3.6V
max.
100
max.
Ids[mA]
Ids[mA]
Driver Strength Pull Down
V-I Characteristics
Typical
80
60
Typical
40
-100
min.
-120
min.
20
0
-140
0.0
0.5
1.0
1.5
2.0
Vgs[V]
2.5
0.0
3.0
0.5
1.0
1.5
2.0
Vgs[V]
2.5
3.0
Output Driver Strengt= Full (Default)
Driver Strength Pull Down
V-I Characteristics
Ta=-40℃～85℃
VCC、VCCQ=3.0V～3.6V
0
200
-20
180
-40
160
-60
-80
max.
Ids[mA]
Ids[mA]
Driver Strength Pull Up
V-I Characteristics
-100
-120
-140
Typical
-160
-180
0.0
0.5
1.0
1.5
2.0
Vgs[V]
max.
140
120
Typical
100
80
60
min.
40
20
min.
-200
Ta=-40℃～85℃
VCC、VCCQ=3.0V～3.6V
0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
Vgs[V]
2.5
3.0
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FEDD56V62160MTA-02
MD56V62160M-xxTA
Burst Mode
Burst operation is the operation to continuously increase a column address inputted during read or write command.
The upper bits select a column address block,
Access order in column address block
Burst Type
Start Address
(Lower bit)
BT=Sequential
BT=Interleave
0
0, 1
0, 1
1
1, 0
1, 0
A0
BL=2
A1
A0
0
0
0, 1, 2, 3
0, 1, 2, 3
0
1
1, 2, 3, 0
1, 0, 3, 2
1
0
2, 3, 0, 1
2, 3, 0, 1
1
1
3, 0, 1, 2
3, 2, 1, 0
A2
A1
A0
0
0
0
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
0
0
1
1, 2, 3, 4, 5, 6, 7, 0
1, 0, 3, 2, 5, 4, 7, 6
0
1
0
2, 3, 4, 5, 6, 7, 0, 1
2, 3, 0, 1, 6, 7, 4, 5
0
1
1
3, 4, 5, 6, 7, 0, 1, 2
3, 2, 1, 0, 7, 6, 5, 4
1
0
0
4, 5, 6, 7, 0, 1, 2, 3
4, 5, 6, 7, 0, 1, 2, 3
1
0
1
5, 6, 7, 0, 1, 2, 3, 4
5, 4, 7, 6, 1, 0, 3, 2
1
1
0
6, 7, 0, 1, 2, 3, 4, 5
6, 7, 4, 5, 2, 3, 0, 1
1
1
7, 0, 1, 2, 3, 4, 5, 6
7, 6, 5, 4, 3, 2, 1, 0
Burst Length
BL=4
BL=8
1
A7A0
BL=Full Page
(256)
0
0, 1… 255
Yn
Yn, Yn+1… 255, 0…
…Yn-1
Non Support
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MD56V62160M-xxTA
READ / WRITE OPERATION
Bank
Bank Address
This SDRAM is organized as four independent banks of 1,048,576 words
x 16 bits memory arrays. The A12 and A13 input is latched at the time of
assertion of /RAS and /CAS to select the bank to be used for operation.
The bank address A12 and A13 are latched at bank active, read, write,
mode register set and precharge operations.
Activate
A12
A13
Bank
0
0
A
0
1
B
1
0
C
1
1
D
ACT
CLK
The bank activate command is used to select a random row in an idle bank.
By asserting low on /RAS and /CS with desired row and bank address, a
row access is initiated. The read or write operation can occur after a time
delay of tRCD(min) from the time of bank activation.
CKE
n-1
n
H
X
/CS
/RAS
L
X
(Idle)
H
A13,A12
X
BA
A11~A0
X
RA
/CAS
/WE
L
H
BA: Bank Address
RA: Row Address (Page)
Precharge
PRE
PALL
CLK
CLK
The precharge operation is
n-1
n
n-1
n
performed on an active bank by
CKE
H
X
CKE
H
X
precharge command (PRE) with
/CS
L
/CS
L
valid A13 and A12 of the bank to
X
X
be precharged. The precharge
/RAS
L
/RAS
L
(Page
(Page
command can be asserted anytime
/CAS
H
/CAS
H
Open)
Open)
after tRAS(min) is satisfied from
/WE
L
/WE
L
the bank active command in the
A13,A12
X
BA
A13,A12
X
X
desired bank. All bank can
precharged at the same time by
A10
X
0
A10
X
1
using precharge all command
A11,A9~A0
X
X
A11,A9~A0
X
X
(PALL). Asserting low on /CS,
BA: Bank Address
/RAS and /WE with high on A10
after all banks have satisfied tRAS(min) requirement, performs precharge on al banks. At the end of tRP after
performing precharge to all banks, all banks are in idle state.
13/42
FEDD56V62160MTA-02
MD56V62160M-xxTA
Write / Write with Auto-Precharge
The write command is used to
write data into the SDRAM on
consecutive clock cycles in
adjacent address depending on
burst length and burst sequence.
By asserting low on /CS, /CAS
and /WE with valid column
address, a write burst is initiated.
The data inputs are provided for
the initial address in the same
clock cycle as the burst write
command. The input buffer is
deselected at the end of the burst
length, even through the internal
writing can be completed yet. The
writing can be completed by
issuing a burst read and DQM for
blocking data inputs or burst write
in the same or another active bank.
The burst stop command is valid
at every burst length.
WRT
WRTA
CLK
CKE
/CS
n-1
n
H
X
X
/RAS
(Page
Open)
/CAS
/WE
A13, A12
X
CLK
n-1
n
H
X
CKE
L
/CS
H
/RAS
L
/CAS
X
(Page
Open)
L
/WE
BA
A13, A12
X
L
H
L
L
BA
A10
X
0
A10
X
1
A11,A9, A8
X
X
A11,A9, A8
X
X
A7~A0
X
CA
A7~A0
X
CA
DQ
X
D-in
DQ
X
D-in
BA: Bank Address
CA: Column Address
D-in: Data inputs
BA: Bank Address
CA: Column Address
D-in: Data inputs
Write Cycle
CLK
CL=2 or 3, BL=1 or WM=Single
Command
ACT
tRCD
DQ
tRAS
tRP
WRT
PRE
ACT
D0
Valid Single Data In
CL=2 or 3, BL=4, WM=Burst
Command
Page Open
DQ
WRT
D0
tWR
D1
D2
DQ
tRCD
ACT
D3
tRAS
ACT
tRP
Valid Burst Data In
CL=2 or 3, BL=4, WM=Burst
Command
PRE
Auto Precharge Start
WRTA
D0
tWR
D1
D2
tRP
ACT
D3
14/42
FEDD56V62160MTA-02
MD56V62160M-xxTA
Read / Read with Auto-Precharge
The read command is used to
access burst of data on
consecutive clock cycles from an
active row in an active bank. The
read command is issued by
asserting low on /CS and /CAS
with /WE being high on the
positive edge of the clock. The
bank must be active for at least
tRCD(min) before the read
command is issued. The first
output appears in /CAS latency
number of clock cycles after the
issue of read command. The burst
length, burst sequence and latency
from the read command are
determined by the mode register
that is already programmed.
RD
RDA
CLK
CKE
/CS
n-1
n
H
X
X
/RAS
(Page
Open)
/CAS
/WE
A13, A12
X
CLK
CKE
L
/CS
H
/RAS
L
/CAS
n-1
n
H
X
X
(Page
Open)
H
/WE
BA
A13, A12
X
L
H
L
H
BA
A10
X
0
A10
X
1
A11, A9, A8
X
X
A11, A9, A8
X
X
A7~A0
X
CA
A7~A0
X
CA
DQ
X
X
DQ
X
X
BA: Bank Address
CA: Column Address
BA: Bank Address
CA: Column Address
Read Cycle
CLK
CL=2, BL=4
Command
tRAS
ACT
tRCD
RD
DQ
/CAS Latency (CL) = 2
Q0
Page Open
RD
/CAS Latency (CL) = 3
DQ
Q0
CL=2, BL=4
Command
Q1
PRE
Q2
ACT
Q3
Valid Burst Data Out
CL=3, BL=4
Command
tRP
PRE
Q1
ACT
tRP
Q2
Q3
Valid Burst Data Out
tRCD
Auto Precharge Start
ACT
RDA
DQ
tRAS
Q0
Q1
ACT
tRP
Q2
Q3
CL=3, BL=4
Command
DQ
Auto Precharge Start
Page Open
RDA
ACT
tRP
Q0
Q1
Q2
Q3
15/42
FEDD56V62160MTA-02
MD56V62160M-xxTA
Write / Write interrupt
When a new write command is issued to same bank during write cycle or another active bank, current burst write is
terminated and new burst write start. When a new write command is issued to another bank during a write with
auto-precharge cycle, current burst is terminated and a new write command start. Then, current bank is precharged
after specified time. Don’t issue a new write command to same bank during write with auto-precharge cycle.
Write / Write interrupt cycle
CLK
CL=2 or 3, BL=4, WM=Burst
Command
DQ
tCCD
tCCD
WRTa
WRTb
Da0
Db0
WRTc
Db1
Dc0
Dc1
Dc2
Dc3
CL=2 or 3, BL=4, WM=Burst
Auto Precharge Start
Command
DQ
WRTa
Da0
tCCD
Da1
WRTAb
Db0
tWR
Db1
Db2
tRP
Db3
CL=2 or 3, BL=4, WM=Burst
Command
Bank Address
WRTA
tCCD
A
WRTA
ACT
B
A
tWR + 1clk
Bank A Internal State
Burst Write
Burst Interrupt,
Write Recovery
DQ
Row Active
DA0
DA1
Auto Precharge
Write
Recovery
Burst Write
DB0
DB1
ACT
B
tRP
tWR
Bank B Internal State
tRRD
DB2
Row Active
tRP
Auto Precharge
Row
Active
DB3
16/42
FEDD56V62160MTA-02
MD56V62160M-xxTA
Read / Read interrupt
When a new read command is issued to same bank during read cycle or another active bank, current burst read is
terminated after the cycle same as /CAS latency and new burst read start. When a new read command is issued to
another bank during a read with auto-precharge cycle, current burst is terminated after the cycle same as /CAS
latency and a new read command start. Then, current bank is precharged after specified time. Don’t issue a new
read command to same bank during read with auto-precharge cycle.
Read / Read interrupt cycle
CLK
CL=2, BL=4
Command
tCCD
RDa
RDb
DQ
RDc
Qa0
CL=3, BL=4
Command
tCCD
Qb0
Qb1
Qc0
Qc1
tCCD
Qc2
High-Z
Auto Precharge Start
RDAb
RDa
Qc3
ACT
tRP
DQ
Qa0
Qa1
Qb0
Qb1
Qb2
Qb3
High-Z
CL=2, BL=4
Command
Bank Address
RDA
tCCD
A
RDA
ACT
B
A
tRRD
ACT
B
tRP + 1clk
Bank A Internal State
Burst Read
Burst
Interrupt
Bank B Internal State
Row Active
Burst Read
DQ
QA0
Auto Precharge
QA1
Row Active
Auto Precharge
QB0
QB1
QB2
Row
Active
QB3
17/42
FEDD56V62160MTA-02
MD56V62160M-xxTA
Write / Read interrupt
When a new read command is issued to same bank during write cycle or another active bank, current burst write is
terminated and new burst read start. When a new read command is issued to another bank during a write with
auto-precharge cycle, current burst is terminated and a new read command start. Then, current bank is precharged
after specified time. Don’t issue a new read command to same bank during write with auto-precharge cycle. DQ
must be hi-Z till 1 or more clock from first read data.
Write / Read interrupt cycle
CLK
CL=3, BL=4, WM=Burst
Command
tCCD
WRTa
DQ
RDb
Da0
High-Z
Qb0
Qb2
Qb1
Qb3
Invalid Data Input
CL=2, BL=4, WM=Burst
Command
tCCD
RDAb
WRTa
DQ
Da0
Auto Precharge Start
Da1
tRP
High-Z
Qb0
Qb2
Qb1
ACT
Qb3
Invalid Data Input
CL=2, BL=4, WM=Burst
Command
Bank Address
WRTA
tCCD
A
RDA
ACT
B
A
tWR + 1clk
Bank A Internal State
Burst Write
Burst Interrupt,
Write Recovery
tRRD
ACT
B
tRP
Auto Precharge
Row Active
tRP
Bank B Internal State
DQ
Row Active
DA0
DA1
Burst Read
High-Z
Auto Precharge
QB0
QB1
QB2
Row
Active
QB3
Invalid Data Input
18/42
FEDD56V62160MTA-02
MD56V62160M-xxTA
Read / Write interrupt
When a new write command is issued to same bank during read cycle or another active bank, current burst read is
terminated and new burst write start. When a new write command is issued to another bank during a read with
auto-precharge cycle, current burst is terminated and a new write command start. Then, current bank is precharged
after specified time. Don’t issue a new write command to same bank during read with auto-precharge cycle. DQ
must be Hi-Z till 1 or more clock from new write command. Therefore, DQM must be high till 3 clocks from new
write command.
Read / Write interrupt cycle
CLK
CL=3, BL=4, WM=Burst
Command
RDa
tOWD
WRTb
DQM
DQ
Qa0
Db0
High-Z
Db1
Db2
Db3
CL=2, BL=4, WM=Burst
Command
Bank Address
RDA
WRTA
ACT
A
B
A
tRP + 1clk
Bank A Internal State
Burst
Interrupt
Burst Read
Auto Precharge
Row Active
tWR
Bank B Internal State
Row Active
Write
Recovery
Burst Write
Auto
Precharge
tOWD
DQM
DQ
QA0
High-Z
DB0
DB1
DB2
DB3
19/42
FEDD56V62160MTA-02
MD56V62160M-xxTA
Burst Stop
When a burst stop command is issued during read cycle, current burst
read is terminated. The DQ is to Hi-Z after the cycle same as /CAS
latency and page keep open. When a burst stop command is issued during
write cycle, current burst write is terminated. The input data is ignored
after burst stop command. Don’t issue burst stop command during read
with auto-precharge cycle or write with auto-precharge cycle.
BST
CLK
n-1
n
H
H
/RAS
X
H
/CAS
(Burst)
H
A13, A12
X
X
A11~A0
X
X
CKE
/CS
L
/WE
L
Read / Burst Stop cycle
CLK
CL=2, BL=4~Full
Command
RD
BST
DQ
Q0
Q1
Q2
High-Z
CL=3, BL=4~Full
Command
RD
BST
DQ
Q0
Q1
Q2
High-Z
Write / Burst Stop cycle
CLK
CL=2 or 3, BL=4~Full, WM=Burst
Command
DQ
WRT
D0
BST
D1
D2
High-Z
Invalid Data Input
20/42
FEDD56V62160MTA-02
MD56V62160M-xxTA
Precharge Break
When a precharge command is issued to the same bank during read cycle or precharge all command is issued,
current burst read is terminated and DQ is to Hi-Z after the cycle same as /CAS latency. The objected bank is
precharged. When a precharge command is issued to the same bank during write cycle or precharge all command is
issued, current burst write is terminated and the objected bank is precharged. The input data after precharge
command is ignored.
Read / Precharge Break cycle
CLK
CL=2, BL=4~Full
Command
ACT
tRP
tRAS
tRCD
RD
PRE
DQ
Q0
CL=3 BL=4~Full
Command
ACT
Q1
ACT
tRAS
tRCD
High-Z
Q2
tRP
RD
ACT
PRE
DQ
Q0
Q1
High-Z
Q2
Write / Precharge Break cycle
CLK
CL=2, BL=4~Full
tRAS
ACT
Command
tRCD
tRP
WRT
tWR
PRE
ACT
DQM
DQ
D0
D1
Invalid Data Input
CL=3, BL=4~Full
Command
ACT
tRAS
tRCD
tRP
WRT
tWR
PRE
ACT
DQM
DQ
D0
D1
D2
チ
21/42
FEDD56V62160MTA-02
MD56V62160M-xxTA
DQM Function
DQM masks input / output data at every byte. UDQM controls DQ15 to DQ8 and LDQM controls DQ7 to DQ0.
During read cycle, DQM mask output data after 2 clocks. During write cycle, DQM mask input data at same clock.
Read / DQM Function
CLK
CL=3, BL=8
Command
RD
UDQM
DQ15～DQ8
QU0
QU1
High-Z
High-Z
QU4
High-Z
QU6
QU7
QL6
QL7
LDQM
DQ7～DQ0
QL0
High-Z
High-Z
QL3
QL4
High-Z
Write / DQM Function
CLK
CL=2 or 3, BL=8
Command
WRT
UDQM
DQ15～DQ8
DU0
DU1
DU4
DU6
DU7
DL4
DL6
DL7
LDQM
DQ7～DQ0
DL0
DL3
Invalid Data Input
22/42
FEDD56V62160MTA-02
MD56V62160M-xxTA
Clock Suspend
The read / write operation can be stopped by CKE temporarily. When CKE is set low, the next clock is ignored.
When CKE is set low during read cycle, the burst read is stopped temporarily and the current output data is kept.
When CKE is set high, burst read is resumed. When CKE is set low during write cycle, the burst write is stopped
temporarily. When CKE is set high, burst write is resumed.
Read / Clock Suspend
CLK
CL=2, BL=8
CKE
Command
RD
Valid Data Output
DQ
Q0
Q1
Q2
Q3
Suspend
Q4
Q5
D5
D6
Suspend
Write / Clock Suspend
CLK
CL=2 or 3, BL=8
CKE
Command
DQ
WRT
D0
Invalid Data Input
D1
D2
Suspend
D3
D4
Suspend
23/42
FEDD56V62160MTA-02
MD56V62160M-xxTA
REFRESH
The data of memory cells are maintained by refresh operation. The refresh operation is to activate all row addresses
within a refresh time. The method that row addresses are activated by activate and precharge command is called
RAS only refresh cycle. This method needs to input row address with activate command. But, auto-refresh and self
refresh don’t need to input address. Because, row addresses are generated in SDRAM automatically.
Auto Refresh
REF
All memory area is refreshed by 4,096 times refresh command REF. The
refresh command REF can be entered only when all the banks are in an
idle state. SDRAM is in idle state after refresh cycle time tRCA.
CLK
CKE
n-1
n
H
H
/CS
L
/RAS
X
L
/CAS
(Idle)
L
/WE
H
A13, A12
X
X
A11~A0
X
X
Auto-Refresh Cycle
CLK
Command
PALL
REF
REF
tRP
ACT
tRCA
tRCA
Intensive Refresh
4,096 times refresh command can be entered every refresh time tREF.
CLK
Read or Write
State
Auto Refresh
tREF=64ms
Read or Write
REF x 4,096
Auto Refresh
tREF=64ms
REF x 4,096
Dispersed Refresh
Refresh command can be entered every 15.625s (tREF 64ms / 4,096 cycles).
CLK
State
REF
R/W
15.625µ
REF
R/W
15.625µ
REF
R/W
4,096 times
REF
R/W
REF
15.625µ
tREF=64ms
24/42
FEDD56V62160MTA-02
MD56V62160M-xxTA
Self Refresh
When read or write is not operated in the long period, self refresh can
reduce power consumption for refresh operation. Refresh operation is
controlled automatically by refresh timer and row address counter during
self refresh mode. All signals except CKE are ignored and data bus DQ is
set Hi-Z during self refresh mode.
When CKE is set to high level, self refresh mode is finished. Then, CLK
must be operated before 1 clock or more. And, maintain NOP condition
within a period of tRCA(Min.) after CKE is set to be high level.
SREF
CLK
n-1
n
H
L
CKE
/CS
L
/RAS
X
L
/CAS
(Idle)
L
/WE
H
A13, A12
X
X
A11~A0
X
X
Self Refresh Cycle
CLK
Self Refresh
CKE
Command
REF
SREF
tRCA
REF
tRCA
Notes : 1. When intensive refresh is used, 4,096 times refresh must be issued before and after the self refresh.
25/42
FEDD56V62160MTA-02
MD56V62160M-xxTA
Power Down
SDRAM can be set to low power consumption condition with CKE function. CKE is reflected at 2 clocks later
regardless /CAS latency. When CKE is set to low level, SDRAM go into power down mode. All signals except
CKE are ignored and DQ is set to High impedance in this state. When CKE is set to high level, SDRAM exit power
down mode. Then, Clock must be resumed before 2 or more clocks.
Power Down
CLK
CL=2, BL=4, Case 1
Active Power Down Mode
CKE
Command
DQ
High-Z
D3
D2
RD
Page Open Stand-by
Write Cycle
D1
New Command
Q0
Q1
CL=2, BL=4, Case 2
CKE
Power Down Mode
Command
New Command
Auto Precharge Start
REF
Precharge Stand-by / Idle
DQ
Q1
Q2
High-Z
Q3
Signal Condition in Power Down Mode
Signal
Input to SDRAM
Output from SDRAM
CLK
Don’t Care
CKE
“L” level
/CS,/RAS, /CAS, /WE
Don’t Care
A13, A12, A11~A0
Don’t Care
DQ15~DQ0
Don’t Care
High-Z
UDQM,LDQM
Don’t Care
VCC,VCCQ,VSS,VSSQ
Power Supply
Notes : 1. “Don’t Care” means high or low level input.
26/42
FEDD56V62160MTA-02
MD56V62160M-xxTA
FUNCTION TRUTH TABLE (Table 1) (1/3)
Current
State *1
Idle
Row
Active
Read
Write
/CS
/RAS
/CAS
/WE
ADDR
Command
Action
H
X
X
X
X
NOP
NOP
L
H
H
X
X
NOP/BST
NOP
L
H
L
H
BA, CA, A10
RD/RDA
ILLEGAL *2
L
H
L
L
BA, CA, A10
WRT/WRTA
ILLEGAL *2
Row Active
L
L
H
H
BA, RA
ACT
L
L
H
L
BA, A10
PRE/PALL
L
L
L
H
X
REF
Auto-Refresh or Self-Refresh *4
L
L
L
L
MRS
Mode Register Set *4
L
L
L
L
V, A12=0,
A13=0
V, A12=1,
A13=0
EMRS
NOP *3
Extended Mode Register Set *4
H
X
X
X
X
NOP
NOP
L
H
H
X
X
NOP/BST
NOP
L
H
L
H
BA, CA, A10
RD/RDA
Read
L
H
L
L
BA, CA, A10
WRT/WRTA
Write
L
L
H
H
BA, RA
ACT
L
L
H
L
BA, A10
PRE/PALL
Precharge
L
L
L
H
X
REF
ILLEGAL
ILLEGAL *6
L
L
L
L
X
MRS/EMRS
H
X
X
X
X
NOP
Continue Row Active after Burst ends
ILLEGAL
L
H
H
H
X
NOP
Continue Row Active after Burst ends
L
H
H
L
X
BST
L
H
L
H
BA, CA, A10
RD/RDA
Term Burst, start new Burst Read
L
H
L
L
BA, CA, A10
WRT/WRTA
Term Burst, start new Burst Write
L
L
H
H
BA, RA
ACT
L
L
H
L
BA, A10
PRE/PALL
Term Burst --> Row Active
ILLEGAL *6
Term Burst, execute Row Precharge
L
L
L
H
X
REF
L
L
L
L
X
MRS/EMRS
ILLEGAL
H
X
X
X
X
X
Continue Row Active after Burst ends
L
H
H
H
X
X
Continue Row Active after Burst ends
L
H
H
L
X
X
Term Burst --> Row Active
L
H
L
H
BA, CA, A10
CA, A10
Term Burst, start new Burst Read
L
H
L
L
BA, CA, A10
CA, A10
Term Burst, start new Burst Write
L
L
H
H
BA, RA
RA
ILLEGAL *6
L
L
H
L
BA, A10
A10
Term Burst, execute Row Precharge
L
L
L
H
X
REF
ILLEGAL
L
L
L
L
X
MRS/EMRS
ILLEGAL
ILLEGAL
27/42
FEDD56V62160MTA-02
MD56V62160M-xxTA
FUNCTION TRUTH TABLE (Table 1) (2/3)
Current
State *1
Read with
Auto
Precharg
e
Write with
Auto
Precharge
Precharge
Write
Recovery
*9
/CS
/RAS
/CAS
/WE
ADDR
Command
Action
H
X
X
X
X
NOP
Continue Burst to End and enter Row Precharge
L
H
H
H
X
NOP
Continue Burst to End and enter Row Precharge
L
H
H
L
X
BST
ILLEGAL
L
H
L
H
BA, CA, A10
RD/RDA
ILLEGAL *7
L
H
L
L
BA, CA, A10
WRT/WRTA
ILLEGAL *7
L
L
H
H
BA, RA
ACT
ILLEGAL *6
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL *8
L
L
L
H
X
REF
ILLEGAL
L
L
L
L
X
MRS/EMRS
ILLEGAL
H
X
X
X
X
NOP
Continue Burst to End and enter Row Precharge
L
H
H
H
X
NOP
Continue Burst to End and enter Row Precharge
L
H
H
L
X
BST
ILLEGAL
L
H
L
H
BA, CA, A10
RD/RDA
ILLEGAL *7
L
H
L
L
BA, CA, A10
WRT/WRTA
ILLEGAL *7
L
L
H
H
BA, RA
ACT
ILLEGAL *6
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL *8
L
L
L
H
X
REF
L
L
L
L
X
MRS/EMRS
H
X
X
X
X
NOP
ILLEGAL
ILLEGAL
Idle after tRP
L
H
H
H
X
NOP
Idle after tRP
L
H
H
L
X
BST
ILLEGAL
L
H
L
H
BA, CA, A10
RD/RDA
ILLEGAL *2
L
H
L
L
BA, CA, A10
WRT/WRTA
ILLEGAL *2
L
L
H
H
BA, RA
ACT
ILLEGAL *6
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL *3
L
L
L
H
X
REF
ILLEGAL
L
L
L
L
X
MRS/EMRS
ILLEGAL
H
X
X
X
X
NOP
L
H
H
H
X
NOP
Row Active after tWR
Row Active after tWR
L
H
H
L
X
BST
ILLEGAL
L
H
L
H
BA, CA, A10
RD/RDA
ILLEGAL *2
L
H
L
L
BA, CA, A10
WRT/WRTA
ILLEGAL *2
L
L
H
H
BA, RA
ACT
ILLEGAL *6
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL *8
L
L
L
H
X
REF
ILLEGAL
L
L
L
L
X
MRS/EMRS
ILLEGAL
28/42
FEDD56V62160MTA-02
MD56V62160M-xxTA
FUNCTION TRUTH TABLE (Table 1) (3/3)
Current
State *1
Write
Recovery
in Auto
Precharge
*9
Auto
Refresh
Mode
Register
Access
/CS
/RAS
/CAS
/WE
ADDR
Command
Action
H
X
X
X
X
NOP
enter Row Precharge after tWR
L
H
H
H
X
NOP
enter Row Precharge after tWR
L
H
H
L
X
BST
ILLEGAL
L
H
L
H
BA, CA, A10
RD/RDA
ILLEGAL *7
L
H
L
L
BA, CA, A10
WRT/WRTA
ILLEGAL *7
L
L
H
H
BA, RA
ACT
ILLEGAL *6
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL *8
L
L
L
H
X
REF
ILLEGAL
L
L
L
L
X
MRS/EMRS
ILLEGAL
H
X
X
X
X
NOP
L
H
H
H
X
NOP
Idle after tRCA
Idle after tRCA
L
H
H
L
X
BST
ILLEGAL
L
H
L
H
BA, CA, A10
RD/RDA
ILLEGAL
L
H
L
L
BA, CA, A10
WRT/WRTA
ILLEGAL
L
L
H
H
BA, RA
ACT
ILLEGAL
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL
L
L
L
H
X
REF
ILLEGAL
L
L
L
L
X
MRS/EMRS
H
X
X
X
X
NOP
Idle after tMRD
ILLEGAL
L
H
H
H
X
NOP
Idle after tMRD
L
H
H
L
X
BST
ILLEGAL
L
H
L
H
BA, CA, A10
RD/RDA
ILLEGAL
L
H
L
L
BA, CA, A10
WRT/WRTA
ILLEGAL
L
L
H
H
BA, RA
ACT
ILLEGAL
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL
L
L
L
H
X
REF
ILLEGAL
L
L
L
L
X
MRS/EMRS
ILLEGAL
ABBREVIATIONS
ADDR = Address
RA = Row Address
NOP = No OPeration command
BA = Bank Address
CA = Column Address
V = Value of Mode Register Set
Notes : 1. All inputs are enabled when CKE is set high for at least 1 cycle prior to the inputs.
2. RD/RDA or WRT/WRTA command to same bank is forbidden. But RD/RDA or WRT/WRTA
command to activated page in another bank is valid.
3. PRE command to another activated bank is valid. PALL command is valid to only activated bank.
4. Illegal if any bank is not idle.
5. RD/RDA or WRT/WRTA command to activated bank is valid after tRCD(min.) from ACT command.
6. Activate command to the same bank is forbidden. But activate command to another bank in idle state
is valid.
7. RD/RDA or WRT/WRTA command to same bank is forbidden. But RD/RDA or WRT/WRTA
command to activated page in another bank is valid.
8. PRE to same bank is forbidden. PRE to another bank must be issued after tRAS(min.). PALL
command is forbidden.
9. Write recovery states means a period from last data to the time that tWR(min.) passed.
29/42
FEDD56V62160MTA-02
MD56V62160M-xxTA
FUNCTION TRUTH TABLE for CKE (Table 2)
Current State
CKE
CKE
/CS
/RAS
/CAS
/WE
ADDR
n-1
All Banks Idle
n-1
H
n
H
n
X
n
X
n
X
n
X
n
X
Refer to Table 1
(ABI)
H
L
H
X
X
X
X
Enter Power Down
H
L
L
H
H
H
X
Enter Power Down
H
L
L
H
H
L
X
ILLEGAL
H
L
L
H
L
X
X
H
L
L
L
H
H
BA, RA
H
L
L
L
H
L
X
ILLEGAL
H
L
L
L
L
H
X
Enter Self Refresh *2
H
L
L
L
L
L
BA, V
L
X
X
X
X
X
X
Self Refresh
Power Down
Action
ILLEGAL
Enter Active Power Down after Activate
Enter Power Down after MRS
INVALID
H
X
X
X
X
X
X
INVALID
L
H
H
X
X
X
X
Exit Self Refresh --> ABI *3
L
H
L
H
H
H
X
Exit Self Refresh --> ABI *3
L
H
L
H
H
L
X
ILLEGAL
L
H
L
H
L
X
X
ILLEGAL
L
H
L
L
X
X
X
ILLEGAL
L
L
X
X
X
X
X
NOP (Maintain Self Refresh)
H
X
X
X
X
X
X
INVALID
L
H
X
X
X
X
X
Exit Power Down --> ABI *4
L
L
X
X
X
X
X
NOP (Continue Power Down)
Active Power
Down
H
X
X
X
X
X
X
INVALID
L
H
X
X
X
X
X
Exit Active Power Down --> Row Active *4
L
L
X
X
X
X
X
NOP (Continue Active Power Down)
Row Active
H
H
X
X
X
X
X
Refer to Table 1
H
L
H
X
X
X
X
Enter Active Power Down
H
L
L
H
H
H
X
Enter Active Power Down
Any State Other
than Listed
Above
H
L
L
H
H
L
X
ILLEGAL
H
L
L
H
L
X
X
Clock Suspension (Refer to Table 1)
H
L
L
L
H
X
X
Clock Suspension (Refer to Table 1)
H
L
L
L
L
X
X
ILLEGAL
L
X
X
X
X
X
X
INVALID
H
H
X
X
X
X
X
Refer to Table 1
H
L
X
X
X
X
X
Begin Clock Suspend Next Cycle
L
H
X
X
X
X
X
Enable Clock of Next Cycle
L
L
X
X
X
X
X
Continue Clock Suspension
ABBREVIATIONS
ADDR = Address
RA = Row Address
V = Value of Mode Register Set
*Notes : 1.
2.
3.
4.
BA = Bank Address
ABI = All Banks Idle
NOP = No OPeration command
Deep Power Down can be entered only when all the banks are in an idle state.
Self Refresh can be entered only when all the banks are in an idle state.
tRCA must be set after exit self refresh.
New command is enabled in the next clock.
30/42
FEDD56V62160MTA-02
MD56V62160M-xxTA
SIMPLIFIED STATE DIAGRAM
MODE
REGISTER
SET
SELF
AUTO
REFRESH
REFRESH
EXTENDED
MODE
REGISTER
SET
Exit
Self
Refresh
MRS
Refresh
EMRS
IDLE
CKE
CKE
Active
POWER
DOWN
CKE
ACTIVE
CKE
Burst
Stop
Read
Write
AP
WRITE
SUSPEND
CKE
Precharge
Write
Write
READ
Write
CKE
CKE
Read with Auto Precharge
CKE
WRITEA
READA
CKE
ON
Command / input signal
READ
SUSPEND
Write AP
CKE
POWER
Read
CKE
Read
WRITE
Read AP
SUSPEND
Burst
Stop
DOWN
Read
AP
Write with Auto Precharge
WRITEA
ACTIVE
POWER
Precharge
Precharge
Precharge
CKE
READA
SUSPEND
PRECHARGE
Auto Sequence
31/42
FEDD56V62160MTA-02
MD56V62160M-xxTA
TIMING CHART
Synchronous Characteristics
Transition Time tT1ns
Transition Time tT1ns
tCC2/3
tCH
tT ≤ 1ns
tCL
CLK
tCC2/3
tCH
tT > 1ns
tCL
VIH
VCCx0.5
VIL
tSI
tHI
tSI
Input *
Valid
Low
VCCx0.5
DQ Output
tSI
tHI
tAC2/3
tAC2/3
tOLZ
tOH
Valid
Low
VCCQx0.5
High-Z
VIH
Valid
High
tOHZ
tOH
Valid
High
Valid
Low
VIL
High-Z
VOL
Valid
High
tSI
tHI
tAC2/3
tAC2/3
tOLZ
VOH
High-Z
tOH
Valid
Low
tHI
tOHZ2/3
tOH
Valid
High
High-Z
Note : The object of input are CKE, A13,A12, A11 to A0, /CS, /RAS, /CAS, /WE,UDQM to LDQM and DQ15 to
DQ0 (input).
Power on Sequence
Max.
VCC, VCCQ 0V
Min.
200µs
CLK
Stable Clock Input
Command
(/CS, /RAS,
/CAS, /WE)
(NOP)
NOP
PALL
NOP
Don't Care
Address
UDQM,LDQM
DQ15~DQ0
Initialize
Don't Care *1
High-Z
Notes : 1. It is advisable that UDQM and LDQM are set to high for set DQ to high impedance during power on
sequence.
32/42
FEDD56V62160MTA-02
MD56V62160M-xxTA
Initialization
CLK
High
CKE
Command
(CS, RAS,
CAS, WE)
tRP
200µs
PALL
Address
tMRD
tMRD
MRS
EMRS
V
V
tRCA
tRCA
REF
REF
ACT
Ra
A10
Ra
A12,
Ba
A13
Ba
UDQM,LDQM Don't Care *2
High-Z
DQ15~0
Notes :
1. V = Value of mode register, Rx = Row Address, Bx = Bank Address
= NOP command or High or Low
2. It is advisable that UDQM to LDQM are set to be high level for setting DQ to high impedance during
power on sequence.
Mode Register Set cycle
CLK
tSI
CKE
tRC
Command
(CS, RAS,
CAS, WE)
tRCA
REF
Address
tMRD
tRAS
MRS
ACT
V
Ra
tRP
PRE
tMRD
EMRS
SREF
V
A10
Ra
A12
Ba
Ba
A13
Ba
Ba
UDQM,LDQM
DQ15~0
Notes :
High-Z
1. V = Value of mode register, Rx = Row Address, Bx = Bank Address
= NOP command or High or Low
33/42
FEDD56V62160MTA-02
MD56V62160M-xxTA
Burst Write Cycle (BL=4, WM=Burst)
CLK
tSI
tHI
Command
(/CS, /RAS,
ACT
/CAS, /WE) t
tHI
SI
Address
Ra
tSI
A10
tRC
WRT
PRE
tRAS
ACT
tRP
Rb
tWR
tRCD
tWR
Rb
tHI
Ba
A13, A12
Cb
tRCD
Ra
tSI
PRE
tRAS
Ca
tHI
WRT
Ba
Ba
tSI
UDQM,
LDQM
(CL=2, 3)
tSI
Bb
Bb
tHI
tHI
tSI
Da0 Da1 Da2
DQ15~0
(CL=2, 3)
Bb
tSI
tHI
tHI
Db0
Notes :
1. Rx = Row Address, Cx = Column Address, Bx = Bank Address
= NOP command or High or Low level, CKE = High level
Burst Read Cycle (BL=4)
CLK
tRC
Command
(/CS, /RAS,
/CAS, /WE)
ACT
Address
Ra
RD
PRE
tRAS
ACT
tRP
Ra
A13, A12
Ba
UDQM,
LDQM
(CL=2)
DQ15~0
(CL=2)
UDQM,
LDQM
(CL=3)
DQ15~0
(CL=3)
Notes :
PRE
tRAS
Ca
Rb
tRCD
A10
RD
Cb
tRCD
Rb
Ba
Ba
Bb
Bb
tAC2
Bb
tAC2
tOLZ
tOH
tOHZ
tOLZ
tOHZ
Qa0 Qa1 Qa2 Qa3
Qb0
tAC3
tOLZ
tOH
tAC3
tOH
tOHZ
Qa0 Qa1 Qa2 Qa3
tOH
tOLZ
tOHZ
Qb0
1. Rx = Row Address, Cx = Column Address, Bx = Bank Address
= NOP command or High or Low level, CKE = High level
34/42
FEDD56V62160MTA-02
MD56V62160M-xxTA
Bank Interleave Write with Auto Precharge Cycle (CL=2, BL=4)
CLK
Command
(/CS, /RAS,
/CAS, /WE)
Address
tRC (Bank-B)
tRC (Bank-A)
ACT
ACT
WRTA
tWR
tRCD
RAa
tRP
(Bank-A)
tRAS (Bank-A)
CAa
RBa
CBa
RAa
A13, A12
A
UDQM,
LDQM
DQ15~0
Notes :
WRTA
CAb
RBb
CBb
tRP
(Bank-B)
tRAS (Bank-B)
RAb
B
tSI
ACT
tRCD
RAb
RBa
A
WRTA
tWR
tRCD
A10
ACT
WRTA
B
tHI
RBb
A
tSI
tHI
tRCD
A
B
tSI
DAa0 DAa1 DAa2 DAa3 DBa0 DBa1 DBa2 DBa3
tHI
B
tSI
tHI
DAb0 DAb1 DAb2 DAb3 DBb0
1. RXx = Row Address, CXx = Column Address, X = Bank, x = Address
= NOP command or High or Low level, CKE = High level
Bank Interleave Read with Auto Precharge Cycle (CL=2, BL=4)
CLK
Command
(/CS, /RAS,
/CAS, /WE)
Address
tRC (Bank-B)
tRC (Bank-A)
ACT
RDA
tRCD
RAa
ACT
RDA
tRAS (Bank-A)
CAa
RBa
CBa
RAa
A13, A12
A
UDQM,
LDQM
DQ15~0
Notes :
RAb
A
B
ACT
RDA
CAb
RBb
CBb
tRCD
tRP (Bank-B)
tRAS (Bank-B)
RBa
RDA
tRCD
tRP (Bank-A)
tRCD
A10
ACT
RAb
B
A
RBb
A
B
B
tAC2
tOLZ
tOH
tAC2
tOH
tOHZ
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBa2 QBa3
QAb0 QAb1 QAb2
1. RXx = Row Address, CXx = Column Address, X = Bank, x = Address
= NOP command or High or Low level, CKE = High level
35/42
FEDD56V62160MTA-02
MD56V62160M-xxTA
Burst Read Single Write Cycle (CL=2, BL=4,WM=Single)
CLK
Command
(CS, RAS,
CAS, WE)
ACT
Address
RAa
RD
CAa
ACT
WRT
WRT
RD
RBa
CBa
CBb
CAb
tRCD
A10
RAa
A13, A12
A
tRCD
tCCD
RBa
A
B
B
B
A
tOWD
UDQM,LDQM
tAC2
tAC2
tOLZ
tOH
DQ15~0
Notes :
tCCD
tOHZ2 tSI
QAa0 QAa1 QAa2 QAa3
tHI
tSI
DBa
tHI
tOLZ
tOH
DBb
QAb0
1.RXx = Row Address, CXx = Column Address, X = Bank, x = Address
= NOP command or High or Low level, CKE = High level,
= Invalid Data Input
Random Column Read / Write Cycle (CL=3, BL=2, 4, 8, Full Page)
CLK
tRP (Bank-A)
tRCD (Bank-A)
Command (Bank-A=Active)
(/CS, /RAS,
RD RD RD RD PRE ACT
ACT WRT WRT WRT WRT RD RD RD RD
/CAS, /WE)
tCCD tCCD tCCD
tCCD tCCD tCCD tCCD tCCD tCCD tCCD
tRRD
Address
CAa CAb CAc CAd
RBa
RAb CBa CBb CAe CAf CBc CBd CAg CAh
tRCD (Bank-B)
A10
A13, A12
A
A
A
A
A
RBa
RAb
B
A
B
B
A
A
B
B
A
A
tOWD
UDQM,
LDQM
DQ15~0
Notes :
tAC3
tOLZ
tAC3
tOH
tOHZ
QAa0 QAb0 QAc0 QAd0
tSI
tHI
tOLZ
DBa0 DBb0 DAe0 DAf0
tOH
QBc0
1. RXx = Row Address, CXx = Column Address, X = Bank, x = Address
= NOP command or High or Low level, CKE = High level,
= Invalid Data Input
36/42
FEDD56V62160MTA-02
MD56V62160M-xxTA
Burst Stop Read / Write Cycle (BL=Full Page)
CLK
Command
(/CS, /RAS,
/CAS, /WE)
RD
Address
Ca
Cb
Ba
Ba
BST
WRT
BST PRE
A10
A13, A12
tOWD
UDQM,
LDQM
(CL=2)
tWR
tAC2
tOLZ
tOH
DQ15~0
(CL=2)
Qa0 Qa1
UDQM,
LDQM
(CL=3)
tAC3
tOHZ
tSI
Qan-1 Qan
Dbn-1 Dbn
tOWD
tOHZ
Qa0
tHI
Db0 Db1
tOH
tOLZ
DQ15~0
(CL=3)
Notes :
Ba
tWR
tSI
Qan-2 Qan-1 Qan
tHI
Db0 Db1
1. Cx = Column Address, Bx = Bank Address
= NOP command or High or Low level, CKE = High level,
Dbn-1
= Invalid Data Input
Precharge Break Read / Write Cycle (BL=Full Page)
CLK
tRP
Command
(/CS, /RAS,
/CAS, /WE)
RD
Address
Ca
PRE
tRAS
ACT
UDQM,
LDQM
(CL=2)
Rb
DQ15~0
(CL=3)
Notes :
Cb
Rb
Ba
Ba
Ba
Ba
Ba
tOWD
tWR
tAC2
tOLZ
tOH
DQ15~0
(CL=2)
UDQM,
LDQM
(CL=3)
PRE
tRCD
A10
A13, A12
WRT
Qa0 Qa1
tAC3
tOHZ
tSI
Qan-1 Qan
tOHZ
Qa0
Db0 Db1
Dbn-1 Dbn
tOWD
tOH
tOLZ
tHI
Qan-2 Qan-1 Qan
tSI
tWR
tHI
Db0 Db1
Dbn-1
1. RXx = Row Address, CXx = Column Address, X = Bank, x = Address
= NOP command or High or Low level, CKE = High level,
= Invalid Data Input
37/42
FEDD56V62160MTA-02
MD56V62160M-xxTA
Byte Read / Byte Write Cycle (CL=2, BL=8)
CLK
Command
(/CS, /RAS,
/CAS, /WE)
RD
WRT
Address
Ca
Cb
Ba
Ba
A10
A13, A12
UDQM
DQ15~8
Qa0 Qa1
tSI
tHI
tOHZ
Qa0
Qa2
Qa4 Qa5
tOLZ
Db0 Db1
tSI
tHI
Db4 Db5
Qa4 Qa5
Db0
Db4 Db5
LDQM
DQ7~0
Notes :
1. Cx = Column Address, Bx = Bank Address
= NOP command or High or Low level, CKE = High level,
Db2
= Invalid Data Input
Clock Suspend Read / Write Cycle (CL=3, BL=4)
CLK
tSI
tHI
tSI
tHI
CKE
Command
(/CS, /RAS,
/CAS, /WE)
RD
WRT
Address
Ca
Cb
Ba
Ba
A10
A13, A12
UDQM,
LDQM
DQ15~0
Notes :
tAC3
tOLZ
tOWD
tOH
Qa0
Qa1
tOHZ
Qa2
Qa3
1. Cx = Column Address, Bx = Bank Address
= NOP command or High or Low level, CKE = High level,
tSI
Db0 Db1
tHI
Db2 Db3
= Invalid Data Input
38/42
FEDD56V62160MTA-02
MD56V62160M-xxTA
Auto Refresh Cycle
CLK
CKE
Command
(/CS, /RAS,
/CAS, /WE)
High
tRP
PALL
tRCA
REF
tRCA
tRCA
REF
REF
ACT
Address
Ra
A10
Ra
A13, A12
Ba
UDQM,
LDQM
DQ15~0
Notes :
High-Z
1. Rx = Row Address, Bx = Bank Address
= NOP command or High or Low level, CKE = High level,
= Invalid Data Input
Self Refresh Cycle
CLK
tSI
1clk
CKE
tSI
Self Refresh
Command
(/CS, /RAS,
/CAS, /WE)
tRP
PALL
NOP
tRCA
SREF
Don't Care
NOP
ACT
Address
Ra
A10
Ra
A13, A12
Ba
UDQM,
LDQM
DQ15~0
Notes :
High-Z
1. Rx = Row Address, Bx = Bank Address
= High or Low level
39/42
FEDD56V62160MTA-02
MD56V62160M-xxTA
Power Down Cycle
CLK
tSI
1clk
tSI
1clk
tSI
CKE
tSI
Active Power Down
Command
(/CS, /RAS,
/CAS,/WE)
Power Down
1clk
ACT NOP
Don't Care
NOP PRE
1clk
NOP
Don't Care
NOP ACT
Address
Ra
Rb
A10
Ra
Rb
A13, A12
Ba
Ba
Bb
UDQM,
LDQM
DQ15~0
Notes :
High-Z
1. Rx = Row Address, Bx = Bank Address
= High or Low level
40/42
FEDD56V62160MTA-02
MD56V62160M-xxTA
REVISION HISTORY
Document
No.
FEDD56V62160MTA-01
FEDD56V62160MTA-02
Date
July. 14, 2011
Oct. 7, 2011
Page
Previous
Current
Edition
Edition
Description
–
–
First edition
1,42
1.42
4
4
Added operating conditions (1/2)
note 2.
9
11
Added Output Driver
Characteristics
Changed company name
41/42
FEDD56V62160MTA-02
MD56V62160M-xxTA
NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements.
Before using the product, please make sure that the information being referred to is up-to-date.
2. The outline of action and examples for application circuits described herein have been chosen as an explanation
for the standard action and performance of the product. When planning to use the product, please ensure that the
external conditions are reflected in the actual circuit, assembly, and program designs.
3. When designing your product, please use our product below the specified maximum ratings and within the
specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating
temperature.
4. LAPIS Semiconductor assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident,
improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters
beyond the specified maximum ratings or operation outside the specified operating range.
5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted
by us in connection with the use of the product and/or the information and drawings contained herein. No
responsibility is assumed by us for any infringement of a third party’s right which may result from the use
thereof.
6. The products listed in this document are intended for use in general electronics equipment for commercial
applications (e.g., office automation, communication equipment, measurement equipment, consumer
electronics, etc.). These products are not, unless specifically authorized by LAPIS Semiconductor authorized
for use in any system or application that requires special or enhanced quality and reliability characteristics nor
in any system or application where the failure of such system or application may result in the loss or damage of
property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace
equipment, nuclear power control, medical equipment, and life-support systems.
7. Certain products in this document may need government approval before they can be exported to particular
countries. The purchaser assumes the responsibility of determining the legality of export of these products and
will take appropriate and necessary steps at their own expense for these.
8. No part of the contents contained herein may be reprinted or reproduced without our prior permission.
Copyright 2011 LAPIS Semiconductor Co., Ltd.
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