ML610Q421P-NNNTBZ0AA

Dear customer LAPIS Semiconductor Co., Ltd. ("LAPIS Semiconductor"), on the 1st day of October, 2020, implemented the incorporation-type company split (shinsetsu-bunkatsu) in which LAPIS established a new company, LAPIS Technology Co., Ltd. (“LAPIS Technology”) and LAPIS Technology succeeded LAPIS Semiconductor’s LSI business. Therefore, all references to "LAPIS Semiconductor Co., Ltd.", "LAPIS Semiconductor" and/or "LAPIS" in this document shall be replaced with "LAPIS Technology Co., Ltd." Furthermore, there are no changes to the documents relating to our products other than the company name, the company trademark, logo, etc. Thank you for your understanding. LAPIS Technology Co., Ltd. October 1, 2020 FEDL610Q421-03 Issue Date: Feb.9, 2015 ML610Q421/ML610Q422 8-bit Microcontroller with a Built-in LCD driver GENERAL DESCRIPTION This LSI is a high-performance 8-bit CMOS microcontroller into which rich peripheral circuits, such as synchronous serial port, UART, I2C bus interface (master), melody driver, battery level detect circuit, RC oscillation type A/D converter, 12-bit successive approximation type A/D converter, and LCD driver, are incorporated around 8-bit CPU nX-U8/100. The CPU nX-U8/100 is capable of efficient instruction execution in 1-intruction 1-clock mode by 3-stage pipe line architecture parallel procesing. The Flash ROM that is installed as program memory achieves low-voltage low-power consumption operation (read operation) equivalent to mask ROM and is most suitable for battery-driven applications. The on-chip debug function that is installed enables program debugging and programming. FEATURES • CPU − 8-bit RISC CPU (CPU name: nX-U8/100) − Instruction system: 16-bit instructions − Instruction set: Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on − On-Chip debug function − Minimum instruction execution time 30.5 µs (@32.768 kHz system clock) 0.24 4µs (@4.096 MHz system clock) • Internal memory − Internal 32KBbyte Flash ROM (16K×16 bits) (including unusable 1KByte TEST area) − Internal 1KByte Data RAM (1024×8 bits), 1KByte Display Allocation RAM (1024 x 8bit) − Internal 100Byte RAM for display • Interrupt controller − 2 non-maskable interrupt sources (Internal source: 1, External source: 1) − 20 maskable interrupt sources (Internal sources: 16, External sources: 4) • Time base counter − Low-speed time base counter ×1 channel Frequency compensation (Compensation range: Approx. −488ppm to +488ppm. Compensation accuracy: Approx. 0.48ppm) − High-speed time base counter ×1 channel • Watchdog timer − Non-maskable interrupt and reset − Free running − Overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s) • Timers − 8 bits × 4 channels (Timer0-3: 16-bit x 2 configuration available by using Timer0-1 or Timer2-3) − Clock frequency measurement mode (in one channel of 16-bit configuration using Timer2-3) 1/37 FEDL610Q421-03 ML610Q421/ML610Q422 • 1 kHz timer − 10 Hz/1 Hz interrupt function • Capture − Time base capture × 2 channels (4096 Hz to 32 Hz) • PWM − Resolution 16 bits × 1 channel • Synchronous serial port − Master/slave selectable − LSB first/MSB first selectable − 8-bit length/16-bit length selectable • UART − TXD/RXD × 1 channel − Bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits − Positive logic/negative logic selectable − Built-in baud rate generator • I2C bus interface − Master function only − Fast mode (400 kbps@4MHｚ), standard mode (100 kbps@1MHｚ, 50kbps@500kHz) • Melody driver − Scale: 29 types (Melody sound frequency: 508 Hz to 32.768 kHz) − Tone length: 63 types − Tempo: 15 types − Buzzer output mode (4 output modes, 8 frequencies, 16 duty levels) • RC oscillation type A/D converter − 24-bit counter − Time division × 2 channels • Successive approximation type A/D converter − 12-bit A/D converter − Input × 2 channels • General-purpose ports − Non-maskable interrupt input port × 1 channel − Input-only port × 6 channels (including secondary functions) − Output-only port × 3 channels (including secondary functions) − Input/output port ML610Q421: 22 channels (including secondary functions) ML610Q422: 14 channels (including secondary functions) 2/37 FEDL610Q421-03 ML610Q421/ML610Q422 • LCD driver − Dot matrix can be supported. ML610Q421: 400 dots max. (50 seg × 8 com), 1/1 to 1/8 duty ML610Q422: 800 dots max. (50 seg × 16 com) , 1/1 to 1/16 duty − 1/3 or 1/4 bias (built-in bias generation circuit) − Frame frequency selecable (approx. 64 Hz, 73 Hz, 85 Hz, and 102 Hz) − Bias voltage multiplying clock selectable (8 types) − Contrast adjustment (1/3 bias: 32 steps, 1/4 bias: 20 steps) − LCD drive stop mode, LCD display mode, all LCDs on mode, and all LCDs off mode selectable − Programmable display allocation function (available only when 1/1~1/8 duty is selected) • Reset − Reset through the RESET_N pin − Power-on reset generation when powered on − Reset when oscillation stop of the low-speed clock is detected − Reset by the watchdog timer (WDT) overflow • Power supply voltage detect function − Judgment voltages: One of 16 levels − Judgment accuracy: ±2% (Typ.) • Clock − Low-speed clock: (This LSI can not guarantee the operation withoug low-speed clock) Crystal oscillation (32.768 kHz) − High-speed clock: Built-in RC oscillation (500 kHz) Built-in PLL oscillation (8.192 MHz ±2.5%), crystal/ceramic oscillation (4.096 MHz), external clock − Selection of high-speed clock mode by software: Built-in RC oscillation, built-in PLL oscillation, crystal/ceramic oscillation, external clock • Power management − HALT mode: Instruction execution by CPU is suspended (peripheral circuits are in operating states). − STOP mode: Stop of low-speed oscillation and high-speed oscillation (Operations of CPU and peripheral circuits are stopped.) − Clock gear: The frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, or 1/8 of the oscillation clock) − Block Control Function: Power down (reset registers and stop clock supply) the circuits of unused peripherals. • Guaranteed operating range − Operating temperature: −20°C to 70°C (P version: −40°C to +85°C) − Operating voltage: VDD = 1.1V to 3.6V, AVDD = 2.2V to 3.6V 3/37 FEDL610Q421-03 ML610Q421/ML610Q422 •Product name – Supported Function The line-up of the ML610Q421 and the ML610Q422 is below. ROM type Operating temperature Product availability ML610Q421-xxxWA Flash ROM -20°C to +70°C Yes ML610Q422-xxxWA Flash ROM -20°C to +70°C Yes ML610Q421P-xxxWA Flash ROM -40°C to +85°C Yes ML610Q422P-xxxWA Flash ROM -40°C to +85°C Yes -120-pin plastic TQFP - ROM type Operating temperature Product availability ML610Q421-xxxTB Flash ROM -20°C to +70°C Yes ML610Q422-xxxTB Flash ROM -20°C to +70°C Yes ML610Q421P-xxxTB Flash ROM -40°C to +85°C Yes ML610Q422P-xxxTB Flash ROM -40°C to +85°C Yes - Chip (Die) - xxx: ROM code number (xxx of the blank product is NNN) Q: Flash ROM version P: Wide range temperature version (P version) WA: Chip (Die), TB: TQFP 4/37 FEDL610Q421-03 ML610Q421/ML610Q422 BLOCK DIAGRAM ML610Q421 Block Diagram Figure 1 show the block diagram of the ML610Q421. "*" indicates the secondary function of each port. CPU (nX-U8/100) EPSW1～3 GREG 0～15 PSW Timing Controller On-Chip ICE TEST Instruction Decoder IN0* CS0* RS0* RT0* CRT0* RCM* IN1* CS1* RS1* RT1* AIN0, AIN1 PC Instruction Register Program Memory (Flash) 32Kbyte BUS Controller INT 1 RAM 1024byte RESET & TEST Interrupt Controller INT 1 OSC INT 4 Power INT 1 INT 1 WDT TBC SCK0* SIN0* SOUT0* UART RXD0* TXD0* I2C SDA* SCL* INT 1 INT 1 INT 1 PWM 1kHzTC Capture ×2 RC-ADC ×2 INT 4 INT 5 MD0* NMI P00 to P03 P10 to P11 8bit Timer ×4 P20 to P22 P30 to P35 P40 to P47 PA0 to PA7 INT 1 BLD PWM0* INT 1 GPIO 12bit-ADC VPP SSIO Melody AVDD AVSS VREF EA Data-bus LSCLK* OUTCLK* VDDL VDDX DSR/CSR SP XT0 XT1 OSC0* OSC1* ECSR1～3 LR ALU VDD VSS RESET_N ELR1～3 Display Allocation RAM 1024Byte Display RAM 100Byte LCD Driver COM0 to COM7 LCD BIAS VL1, VL2, VL3, VL4 SEG0 to SEG49 C1, C2, C3, C4 Figure 1 ML610Q421 Block Diagram 5/37 FEDL610Q421-03 ML610Q421/ML610Q422 ML610Q422 Block Diagram Figure 2 show the block diagram of the ML610Q422. "*" indicates the secondary function of each port. CPU (nX-U8/100) EPSW1～3 GREG 0～15 PSW Timing Controller On-Chip ICE TEST Instruction Decoder IN0* CS0* RS0* RT0* CRT0* RCM* IN1* CS1* RS1* RT1* VREF EA PC Instruction Register Program Memory (Flash) 32Kbyte BUS Controller INT 1 RAM 1024byte RESET & TEST Interrupt Controller INT 1 OSC INT 4 Power INT 1 INT 1 WDT TBC SCK0* SIN0* SOUT0* UART RXD0* TXD0* I2C SDA* SCL* INT 1 INT 1 INT 1 PWM 1kHzTC Capture ×2 RC-ADC ×2 INT 4 VPP SSIO PWM0* INT 1 Melody INT 5 MD0* NMI P00 to P03 P10 to P11 8bit Timer ×4 GPIO P20 to P22 P30 to P35 AVDD AVSS AIN0, AIN1 DSR/CSR Data-bus LSCLK* OUTCLK* VDDL VDDX LR SP XT0 XT1 OSC0* OSC1* ECSR1～3 ALU VDD VSS RESET_N ELR1～3 INT 1 12bit-ADC BLD P40 to P47 Display Allocation RAM 1024Byte Display RAM 100Byte LCD Driver COM0 to COM15 LCD BIAS VL1, VL2, VL3, VL4 SEG0 to SEG49 C1, C2, C3, C4 Figure 2 ML610Q422 Block Diagram 6/37 FEDL610Q421-03 ML610Q421/ML610Q422 PIN CONFIGURATION 90pin 60pin 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 120pin 1pin VPP RESET_N P42 P43 P44 P45 P46 P47 P30 P31 P34 P32 P33 P35 TEST VDD VDDL VSS VDDX XT0 (NC) XT1 VSS NMI VL1 VL2 VL3 VL4 C1 C2 SEG49 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 P20 P21 P22 P40 P41 VSS (NC) AVSS (NC) VREF AIN0 AIN1 AVDD 61pin 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 91pin SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 ML610Q421 TQFP120 Pin Layout SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 VDD P11 (NC) P10 VSS P03 P02 P01 P00 C4 C3 31pin 30pin Note: The assignment of the pads P30 to P35 are not in order. Figure 3 ML610Q421 TQFP120 Pin Configuration 7/37 FEDL610Q421-03 ML610Q421/ML610Q422 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 ML610Q422 TQFP120 Pin Layout 90pin 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 120pin 1pin VPP RESET_N P42 P43 P44 P45 P46 P47 P30 P31 P34 P32 P33 P35 TEST VDD VDDL VSS VDDX XT0 (NC) XT1 VSS NMI VL1 VL2 VL3 VL4 C1 C2 SEG49 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 P20 P21 P22 P40 P41 VSS (NC) AVSS (NC) VREF AIN0 AIN1 AVDD 60pin 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 91pin 61pin SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 VDD P11 (NC) P10 VSS P03 P02 P01 P00 C4 C3 31pin 30pin Note: The assignment of the pads P30 to P35 are not in order. Figure 4 ML610Q422 TQFP120 Pin Configuration 8/37 FEDL610Q421-03 ML610Q421/ML610Q422 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 ML610Q421 Chip Pin Layout & Dimension SEG49 89 58 SEG18 COM0 90 57 SEG17 COM1 91 56 SEG16 COM2 92 55 SEG15 COM3 93 54 SEG14 COM4 94 53 SEG13 COM5 95 52 SEG12 COM6 96 51 SEG11 COM7 97 50 SEG10 PA0 98 49 SEG9 PA1 99 48 SEG8 PA2 100 47 SEG7 PA3 101 46 SEG6 PA4 102 45 SEG5 PA5 103 44 SEG4 PA6 104 43 SEG3 PA7 105 42 SEG2 P20/LED0 106 41 SEG1 40 SEG0 P21/LED1 107 P22/LED2 108 39 VDD P40/SDA 109 38 P11 P41/SCL 110 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 P47/RT1 P30/IN0 P31/CS0 P34/RCT0 P32/RS0 P33/RT0 P35/RCM TEST VDD VDDL Vss VDDX XT0 XT1 Vss NMI VL1 VL2 VL3 VL4 C1 C2 116 P46/RS1 AVDD 6 115 P45/CS1 AIN1 5 P02 P44/IN1 P03 34 4 35 114 P43 113 AIN0 3 VREF 2 Vss P42 P10 36 1 37 112 VPP 111 RESET_N Vss AVSS 33 P01 32 P00 31 C4 30 C3 3.02mm 2.98mm Note: The assignment of the pads P30 to P35 are not in order. Chip size: PAD count: Minimum PAD pitch: PAD aperture: Chip thickness: Voltage of the rear side of chip: 2.98 mm × 3.02 mm 116 pins 80 µm 70 µm × 70 µm 350 µm VSS level Figure 5 ML610Q421 Chip Layout & Dimension 9/37 FEDL610Q421-03 ML610Q421/ML610Q422 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 ML610Q422 Chip Pin Layout & Dimension SEG49 89 58 SEG18 COM0 90 57 SEG17 COM1 91 56 SEG16 COM2 92 55 SEG15 COM3 93 54 SEG14 COM4 94 53 SEG13 COM5 95 52 SEG12 COM6 96 51 SEG11 COM7 97 50 SEG10 COM8 98 49 SEG9 COM9 99 48 SEG8 COM10 100 47 SEG7 COM11 101 46 SEG6 COM12 102 45 SEG5 COM13 103 44 SEG4 COM14 104 43 SEG3 COM15 105 42 SEG2 P20/LED0 106 41 SEG1 40 SEG0 P21/LED1 107 P22/LED2 108 39 VDD P40/SDA 109 38 P11 P41/SCL 110 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 P47/RT1 P30/IN0 P31/CS0 P34/RCT0 P32/RS0 P33/RT0 P35/RCM TEST VDD VDDL Vss VDDX XT0 XT1 Vss NMI VL1 VL2 VL3 VL4 C1 C2 116 P46/RS1 AVDD 6 115 P45/CS1 AIN1 5 P02 P44/IN1 P03 34 4 35 114 P43 113 AIN0 3 VREF 2 Vss P42 P10 36 1 37 112 VPP 111 RESET_N Vss AVSS 33 P01 32 P00 31 C4 30 C3 3.02mm 2.98mm Note: The assignment of the pads P30 to P35 are not in order. Chip size: PAD count: Minimum PAD pitch: PAD aperture: Chip thickness: Voltage of the rear side of chip: 2.98 mm × 3.02 mm 116 pins 80 µm 70 µm × 70 µm 350 µm VSS level Figure 6 ML610Q422 Chip Layout & Dimension 10/37 FEDL610Q421-03 ML610Q421/ML610Q422 PAD COORDINATES ML610Q421 Pad Coordinates Table 1 ML610Q421 Pad Coordinates Chip Center: X=0,Y=0 PAD No. Pad Name X (μm) Y (μm) PAD No. Pad Name X (μm) Y (μm) PAD No. Pad Name X (μm) Y (μm) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VPP RESET_N P42 P43 P44 P45 P46 P47 P30 P31 P34 P32 P33 P35 TEST VDD VDDL Vss VDDX XT0 XT1 Vss NMI VL1 VL2 VL3 VL4 C1 C2 C3 C4 P00 P01 P02 P03 Vss P10 P11 VDD SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 -1240 -1160 -1080 -1000 -920 -840 -760 -680 -600 -520 -440 -360 -280 -200 -120 -40 40 120 200 360 520 600 680 840 920 1000 1080 1160 1240 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 -1404 -1404 -1404 -1404 -1404 -1404 -1404 -1404 -1404 -1404 -1404 -1404 -1404 -1404 -1404 -1404 -1404 -1404 -1404 -1404 -1404 -1404 -1404 -1404 -1404 -1404 -1404 -1404 -1404 -1240 -1160 -1040 -960 -880 -800 -660 -580 -420 -340 -240 -160 -80 0 80 160 240 320 400 480 560 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 PA0 PA1 PA2 1384 1384 1384 1384 1384 1384 1384 1384 1160 1080 1000 920 840 760 680 600 520 440 360 280 200 120 40 -40 -120 -200 -280 -360 -440 -520 -600 -680 -760 -840 -920 -1000 -1080 -1160 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 640 720 800 880 960 1040 1120 1200 1404 1404 1404 1404 1404 1404 1404 1404 1404 1404 1404 1404 1404 1404 1404 1404 1404 1404 1404 1404 1404 1404 1404 1404 1404 1404 1404 1404 1404 1404 1200 1120 1040 960 880 800 720 640 560 480 400 320 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 PA3 PA4 PA5 PA6 PA7 P20 P21 P22 P40 P41 Vss AVss VREF AIN0 AIN1 AVDD -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 240 160 80 0 -80 -200 -280 -360 -440 -520 -600 -680 -840 -920 -1092 -1172 11/37 FEDL610Q421-03 ML610Q421/ML610Q422 ML610Q422 Pad Coordinates Table 2 ML610Q422 Pad Coordinates Chip Center: X=0,Y=0 PAD No. Pad Name X (μm) Y (μm) PAD No. Pad Name X (μm) Y (μm) PAD No. Pad Name X (μm) Y (μm) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VPP RESET_N P42 P43 P44 P45 P46 P47 P30 P31 P34 P32 P33 P35 TEST VDD VDDL Vss VDDX XT0 XT1 Vss NMI VL1 VL2 VL3 VL4 C1 C2 C3 C4 P00 P01 P02 P03 Vss P10 P11 VDD SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 -1240 -1160 -1080 -1000 -920 -840 -760 -680 -600 -520 -440 -360 -280 -200 -120 -40 40 120 200 360 520 600 680 840 920 1000 1080 1160 1240 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 1384 -1404 -1404 -1404 -1404 -1404 -1404 -1404 -1404 -1404 -1404 -1404 -1404 -1404 -1404 -1404 -1404 -1404 -1404 -1404 -1404 -1404 -1404 -1404 -1404 -1404 -1404 -1404 -1404 -1404 -1240 -1160 -1040 -960 -880 -800 -660 -580 -420 -340 -240 -160 -80 0 80 160 240 320 400 480 560 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 1384 1384 1384 1384 1384 1384 1384 1384 1160 1080 1000 920 840 760 680 600 520 440 360 280 200 120 40 -40 -120 -200 -280 -360 -440 -520 -600 -680 -760 -840 -920 -1000 -1080 -1160 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 640 720 800 880 960 1040 1120 1200 1404 1404 1404 1404 1404 1404 1404 1404 1404 1404 1404 1404 1404 1404 1404 1404 1404 1404 1404 1404 1404 1404 1404 1404 1404 1404 1404 1404 1404 1404 1200 1120 1040 960 880 800 720 640 560 480 400 320 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 COM11 COM12 COM13 COM14 COM15 P20 P21 P22 P40 P41 Vss AVss VREF AIN0 AIN1 AVDD -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 -1384 240 160 80 0 -80 -200 -280 -360 -440 -520 -600 -680 -840 -920 -1092 -1172 12/37 FEDL610Q421-03 ML610Q421/ML610Q422 PIN LIST PAD No. Primary function Q422 Q421 Pin name 18,22, 18,22, 36,111 37,111 16,39 16,39 17 17 19 19 1 1 112 112 116 116 24 24 25 25 26 26 27 27 28 28 29 29 30 30 31 31 15 15 2 2 20 20 21 21 113 113 Vss I/O Function  Negative power supply pin Positive power supply pin Power supply pin for VDDL  internal logic (internally generated) Power supply pin for VDDX  low-speed oscillation (internally generated) Power supply pin for VPP  Flash ROM Negative power supply pin for AVSS  successive approximation type ADC Positive power supply pin for successive AVDD  approximation type ADC Power supply pin for VL1  LCD bias (internally generated) Power supply pin for VL2  LCD bias (internally generated) Power supply pin for VL3  LCD bias (internally generated) Power supply pin for VL4  LCD bias (internally generated) Capacitor connection C1  pin for LCD bias generation Capacitor connection C2  pin for LCD bias generation Capacitor connection C3  pin for LCD bias generation Capacitor connection C4  pin for LCD bias generation Input/output pin for TEST I/O testing RESET_N I Reset input pin Low-speed clock XT0 I oscillation pin Low-speed clock XT1 O oscillation pin Reference power supply pin for VREF  successive approximation type ADC VDD  Secondary function Tertiary function Pin name I/O Function Pin name I/O Function                                                                                                                         13/37 FEDL610Q421-03 ML610Q421/ML610Q422 PAD No. Primary function Q422 Q421 Pin name I/O Function Successive approximation type ADC input Successive approximation type ADC input Non-maskable interrupt pin Secondary function Tertiary function Pin name I/O Function Pin name I/O Function                   114 114 AIN0 I 115 115 AIN1 I 23 23 NMI I 32 32 P00/ EXI0/ CAP0 I Input port, External interrupt 0, Capture 0 input       33 33 P01/ EXI1/ CAP1 I Input port, External interrupt 1, Capture 1 input       34 34 P02/ EXI2/ RXD0 I Input port, External interrupt 2, UART0 receive       35 35 P03/ EXI3 I Input port, External interrupt 3       37 37 P10 I Input port OSC0 I High-speed oscillation    OSC1 O High-speed oscillation    Low-speed clock output    High-speed clock output Melody output RC type ADC0 oscillation input pin             PWM0 O          SIN0 I 38 38 P11 I Input port 106 106 P20/ LED0 O Output port LSCLK O 107 107 P21/LED1 O Output port OUTCLK O 108 108 P22/LED2 O Output port MD0 O 9 9 P30 I/O Input/output port IN0 I 10 10 P31 I/O Input/output port CS0 O 11 11 P34 I/O Input/output port RCT0 O 12 12 P32 I/O Input/output port RS0 O 13 13 P33 I/O Input/output port RT0 O 14 14 P35 I/O Input/output port RCM O 109 109 P40 I/O Input/output port I/O Input/output port SDA I/O RC type ADC0 resistor/capacitor sensor connection pin RC type ADC0 reference resistor connection pin RC type ADC0 resistor sensor connection pin RC type ADC oscillation monitor I2C data input/output I/O I2C clock input/output RC type ADC0 reference capacitor connection pin PWM output SSIO data input P42 RXD0 I UART data input SOUT0 I/O SSIO synchronous clock SSIO data output I P43 TXD0 O UART data output PWM0 O PWM output IN1 I RC type ADC1 oscillation input pin SIN0 I SSIO0 data input CS1 O SCK0 I/O SSIO0 synchronous clock I/O Input/output port RS1 O SOUT0 O SSIO0 data output P47 I/O Input/output port RT1 O    98 PA0       99 PA1 I/O Input/output port I/O Input/output port       100 PA2       101 PA3 I/O Input/output port I/O Input/output port       102 PA4 I/O Input/output port      110 110 P41 3 3 4 4 5 5 6 6 7 7 P46 8 8  I/O Input/output port I/O Input/output port Input/output port, P44/ Timer 0/Timer 2/ I/O PWM0 external clock T02P0CK input Input/output port, P45/ I/O Timer 1/Timer 3 T13P1CK external clock input SCL RC type ADC1 reference capacitor connection pin RC type ADC1 reference resistor connection pin RC type ADC1 resistor sensor connection pin      SCK0 14/37 FEDL610Q421-03 ML610Q421/ML610Q422 PAD No. Primary function Q422 Q421 Pin name I/O Function Secondary function Tertiary function Pin name I/O Function Pin name I/O I/O Input/output port I/O Input/output port Function                                       95 95 COM5 O LCD common pin   96 96 COM6 O LCD common pin             97 97 COM7 O LCD common pin       98  COM8 O LCD common pin       99  COM9 O LCD common pin       100  COM10 O LCD common pin       101  COM11 O LCD common pin       102  COM12 O LCD common pin       103  COM13 O LCD common pin       104  COM14 O LCD common pin       105  COM15 O LCD common pin       40 40 SEG0 O LCD segment pin       41 41 SEG1 O LCD segment pin       42 42 SEG2 O LCD segment pin       43 43 SEG3 O LCD segment pin       44 44 SEG4 O LCD segment pin        103 PA5  104 PA6  105 PA7 90 90 COM0 I/O Input/output port O LCD common pin 91 91 COM1 O LCD common pin   92 92 COM2 O LCD common pin   93 93 COM3 O LCD common pin   94 94 COM4 O LCD common pin   45 45 SEG5 O LCD segment pin       46 46 SEG6 O LCD segment pin       47 47 SEG7 O LCD segment pin       48 48 SEG8 O LCD segment pin       49 49 SEG9 O LCD segment pin       50 50 SEG10 O LCD segment pin       51 51 SEG11 O LCD segment pin       52 52 SEG12 O LCD segment pin       53 53 SEG13 O LCD segment pin       54 54 SEG14 O LCD segment pin       55 55 SEG15 O LCD segment pin       56 56 SEG16 O LCD segment pin       57 57 SEG17 O LCD segment pin       58 58 SEG18 O LCD segment pin       59 59 SEG19 O LCD segment pin       60 60 SEG20 O LCD segment pin       61 61 SEG21 O LCD segment pin       62 62 SEG22 O LCD segment pin       63 63 SEG23 O LCD segment pin       64 64 SEG24 O LCD segment pin       65 65 SEG25 O LCD segment pin       66 66 SEG26 O LCD segment pin       67 67 SEG27 O LCD segment pin       68 68 SEG28 O LCD segment pin       69 69 SEG29 O LCD segment pin       70 70 SEG30 O LCD segment pin       71 71 SEG31 O LCD segment pin       72 72 SEG32 O LCD segment pin       73 73 SEG33 O LCD segment pin       74 74 SEG34 O LCD segment pin       75 75 SEG35 O LCD segment pin       15/37 FEDL610Q421-03 ML610Q421/ML610Q422 PAD No. Primary function Q422 Q421 Pin name I/O Function Secondary function Pin name I/O Function Tertiary function Pin name I/O Function 76 76 SEG36 O LCD segment pin       77 77 SEG37 O LCD segment pin       78 78 SEG38 O LCD segment pin       79 79 SEG39 O LCD segment pin       80 80 SEG40 O LCD segment pin       81 81 SEG41 O LCD segment pin       82 82 SEG42 O LCD segment pin       83 83 SEG43 O LCD segment pin       84 84 SEG44 O LCD segment pin       85 85 SEG45 O LCD segment pin       86 86 SEG46 O LCD segment pin       87 87 SEG47 O LCD segment pin       88 88 SEG48 O LCD segment pin       89 89 SEG49 O LCD segment pin       16/37 FEDL610Q421-03 ML610Q421/ML610Q422 PIN DESCRIPTION Pin name I/O Description Primary/ Secondary/ Tertiary Logic — Negative — — — — Secondary — Secondary — Secondary — Secondary — Primary Positive Primary Positive Primary Positive Primary Positive Primary Positive Primary Positive System Reset input pin. When this pin is set to a “L” level, system reset mode is set and the internal section is initialized. When this pin is set to a “H” level subsequently, program execution starts. A pull-up resistor is internally connected. XT0 I Crystal connection pin for low-speed clock. A 32.768 kHz crystal oscillator (see measuring circuit 1) is connected to XT1 O this pin. Capacitors CDL and CGL are connected across this pin and VSS as required. OSC0 I Crystal/ceramic connection pin for high-speed clock. A crystal or ceramic is connected to this pin (4.1 MHz max.). Capacitors CDH and CGH (see measuring circuit 1) are connected across this pin OSC1 O and VSS. This pin is used as the secondary function of the P10 pin(OSC0) and P11 pin(OSC1). LSCLK O Low-speed clock output pin. This pin is used as the secondary function of the P20 pin. OUTCLK O High-speed clock output pin. This pin is used as the secondary function of the P21 pin. General-purpose input port RESET_N I General-purpose input port. Since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. P10-P11 I General-purpose input port. Since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. General-purpose output port P20-P22 O General-purpose output port. Since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. General-purpose input/output port P30-P35 I/O General-purpose input/output port. Since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. P40-P47 I/O General-purpose input/output port. Since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. PA0-PA7 I/O General-purpose input/output port. These pins are for the ML610Q421, but are not provided in the ML610Q422. P00-P03 I 17/37 FEDL610Q421-03 ML610Q421/ML610Q422 Pin name Primary/ Secondary/ Tertiary Logic Secondary Positive Primary/ Secondary Positive Secondary Positive Secondary Positive I/O Synchronous serial clock input/output pin. This pin is used as the tertiary function of the P41 or P45 pin. I Synchronous serial data input pin. This pin is used as the tertiary function of the P40 or P44 pin. O Synchronous serial data output pin. This pin is used as the tertiary function of the P42 or P46 pin. Tertiary — Tertiary Positive Tertiary Positive PWM0 output pin. This pin is used as the tertiary function of the P43 or P34 pin. PWM0 external clock input pin. This pin is used as the primary function of the P44 pin. Tertiary Positive Primary — External non-maskable interrupt input pin. An interrupt is generated on both edges. External maskable interrupt input pins. Interrupt enable and edge selection can be performed for each bit by software. These pins are used as the primary functions of the P00-P03 pins. Primary Positive/ negative Positive/ negative Capture trigger input pins. The value of the time base counter is captured in the register synchronously with the interrupt edge selected by software. These pins are used as the primary functions of the P00 pin(CAP0) and P01 pin(CAP1). Primary External clock input pin used for both Timer 0 and Timer 2. The clocks for these timers are selected by software. This pin is used as the primary function of the P44 pin. External clock input pin used for both Timer 1 and Timer 3. The clocks for these timers are selected by software. This pin is used as the primary function of the P45 pin. Primary — Primary — I/O UART TXD0 O RXD0 I Description UART data output pin. This pin is used as the secondary function of the P43 pin. UART data input pin. This pin is used as the secondary function of the P42 or the primary function of the P02 pin. 2 I C bus interface 2 SDA I/O I C data input/output pin. This pin is used as the secondary function of the P40 pin. This pin has an NMOS open drain output. When using this pin as 2 a function of the I C, externally connect a pull-up resistor. 2 SCL O I C clock output pin. This pin is used as the secondary function of the P41 pin. This pin has an NMOS open drain output. When using this pin as a 2 function of the I C, externally connect a pull-up resistor. Synchronous serial (SSIO) SCK0 SIN0 SOUT0 PWM PWM0 T02P0CK O O External interrupt NMI I EXI0-3 I Capture CAP0 I CAP1 I Timer T02P0CK I T13P1CK I Melody MD0 O Melody/buzzer signal output pin. This pin is used as the secondary function of the P22 pin. LED drive LED0-2 O Nch open drain output pins to drive LED. Primary Primary Positive/ negative Positive/ negative Secondary Positive/ negative Primary Positive/ negative 18/37 FEDL610Q421-03 ML610Q421/ML610Q422 Pin name Primary/ Secondary/ Tertiary Logic Secondary — Secondary — Secondary — Secondary — Secondary — Secondary — Secondary — Secondary — Secondary — Secondary — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — I/O Input/output pin for testing. A pull-down resistor is internally connected. — — — — — — — — — — — — I/O Description RC oscillation type A/D converter IN0 I Channel 0 oscillation input pin. This pin is used as the secondary function of the P30 pin. CS0 O Channel 0 reference capacitor connection pin. This pin is used as the secondary function of the P31 pin. RS0 O This pin is used as the secondary function of the P32 pin which is the reference resistor connection pin of Channel 0. RT0 O Resistor sensor connection pin of Channel 0 for measurement. This pin is used as the secondary function of the P34 pin. CRT0 O Resistor/capacitor sensor connection pin of Channel 0 for measurement. This pin is used as the secondary function of the P33 pin. RCM O RC oscillation monitor pin. This pin is used as the secondary function of the P35 pin. IN1 I Oscillation input pin of Channel 1. This pin is used as the secondary function of the P44 pin. CS1 O Reference capacitor connection pin of Channel 1. This pin is used as the secondary function of the P45 pin. RS1 O Reference resistor connection pin of Channel 1. This pin is used as the secondary function of the P46 pin. RT1 O Resistor sensor connection pin for measurement of Channel 1. This pin is used as the secondary function of the P47 pin. Successive approximation type A/D converter AVSS — Negative power supply pin for successive approximation type A/D converter. AVDD — Positive power supply pin for successive approximation type A/D converter. VREF — Reference power supply pin for successive approximation type A/D converter. AIN0 I Channel 0 analog input for successive approximation type A/D converter. AIN1 I Channel 1 analog input for successive approximation type A/D converter. LCD drive signal COM0-7 O Common output pins. COM8-15 O Common output pins. These pins are for the ML610Q422, but are not provided in the ML610Q421. SEG0-49 O Segment output pin. LCD driver power supply VL1 — Power supply pins for LCD bias (internally generated). Capacitors Ca, Cb, VL2 — Cc, and Cd (see measuring circuit 1) are connected between VSS and VL1, VL3 — VL2, VL3, and VL4, respectively. VL4 — C1 — Power supply pins for LCD bias (internally generated). Capacitors C12 C2 — and C34 (see measuring circuit 1) are connected between C1 and C2 and C3 — between C3 and C4, respectively. C4 For testing TEST Power supply VSS VDD VDDL — — — VDDX — VPP — Negative power supply pin. Positive power supply pin. Positive power supply pin (internally generated) for internal logic. Capacitors CL0 and CL1 (see measuring circuit 1) are connected between this pin and VSS. Plus-side power supply pin (internally generated) for low-speed oscillation. Capacitor Cx (see measuring circuit 1) is connected between this pin and VSS. Power supply pin for programming Flash ROM. A pull-up resistor is internally connected. 19/37 FEDL610Q421-03 ML610Q421/ML610Q422 TERMINATION OF UNUSED PINS Table 3 shows methods of terminating the unused pins. Table 3 Pin VPP AVDD AVSS VREF AIN0, AIN1 VL1, VL2, VL3, VL4 C1, C2, C3, C4 RESET_N TEST NMI P00 to P03 P10 to P11 P20 to P22 P30 to P35 P40 to P47 PA0 to PA7 COM0 to 15 SEG0 to 49 Termination of Unused Pins Recommended pin termination Open VSS VSS VSS Open Open Open Open Open Open VDD or VSS VDD Open Open Open Open Open Open Note: It is recommended to set the unused input ports and input/output ports to the inputs with pull-down resistors/pull-up resistors or the output mode since the supply current may become excessively large if the pins are left open in the high impedance input setting. 20/37 FEDL610Q421-03 ML610Q421/ML610Q422 ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS (VSS = AVSS = 0V) Parameter Symbol Condition Rating Unit Power supply voltage 1 VDD Ta = 25°C −0.3 to +4.6 V Power supply voltage 2 AVDD Ta = 25°C −0.3 to +4.6 V Power supply voltage 3 VPP Ta = 25°C −0.3 to +9.5 V Power supply voltage 4 VDDL Ta = 25°C −0.3 to +3.6 V Power supply voltage 5 VDDX Ta = 25°C −0.3 to +3.6 V Power supply voltage 6 VL1 Ta = 25°C −0.3 to +1.75 V Power supply voltage 7 VL2 Ta = 25°C −0.3 to +3.5 V Power supply voltage 8 VL3 Ta = 25°C −0.3 to +5.25 V Power supply voltage 9 VL4 Ta = 25°C −0.3 to +7.0 V Input voltage VIN Ta = 25°C −0.3 to VDD+0.3 V Output voltage VOUT Ta = 25°C −0.3 to VDD+0.3 V Output current 1 IOUT1 Port3–A, Ta = 25°C −12 to +11 mA Output current 2 IOUT2 Port2, Ta = 25°C −12 to +20 mA Power dissipation PD Ta = 25°C 1.25 W Storage temperature TSTG  −55 to +150 °C RECOMMENDED OPERATING CONDITIONS (VSS = AVSS = 0V) Parameter Operating temperature Operating voltage Operating frequency (CPU) Capacitor externally connected to VDDL pin Capacitor externally connected to VDDX pin Capacitors externally connected to VL1, 2, 3, 4 pins Capacitors externally connected across C1 and C2 pins and across C3 and C4 pins Symbol Condition Range Unit TOP ML610Q421, ML610Q422 ML610Q421P, ML610Q422P −20 to +70 −40 to +85 °C VDD  1.1 to 3.6 AVDD  2.2 to 3.6 VDD = 1.1 to 3.6V 30k to 36k fOP V VDD = 1.3 to 3.6V 30k to 650k VDD = 1.8 to 3.6V 30k to 4.2M Hz CL0  1.0±30% CL1  0.1±30% CX  0.1±30% µF Ca, b, c, d  1.0±30% µF C12, C34  1.0±30% µF µF 21/37 FEDL610Q421-03 ML610Q421/ML610Q422 CLOCK GENERATION CIRCUIT OPERATING CONDITIONS (VSS = 0V) Parameter Low-speed crystal oscillation frequency Recommended equivalent series resistance value of low-speed crystal oscillation Low-speed crystal oscillation *1 external capacitor Min. Rating Typ. Max.   32.768k  Hz RL    40k Ω  0  CDL/CGL CL=6pF of crystal *2 oscillation CL=9pF of crystal oscillation CL=12pF of crystal oscillation  6   12  Symbol Condition fXTL Unit pF High-speed crystal/ceramic fXTH   4.0M / 4.096M  Hz oscillation frequency High-speed crystal oscillation CDH   24  pF external capacitor CGH   24  *1 : The external CDL and CGL need to be adjusted in consideration of variation of internal loading capacitance CD and CG, and other additional capacitance such as PCB layout. *2 : When using a crystal oscillator CL = 6pF, there is a possibility that can not be adjusted by external CDL and CGL. OPERATING CONDITIONS OF FLASH ROM Parameter Operating temperature Operating voltage Write cycles Data retention Symbol TOP VDD VDDL VPP CEP YDR Condition At write/erase *1 At write/erase *1 At write/erase *1 At write/erase   Range 0 to +40 2.75 to 3.6 2.5 to 2.75 7.7 to 8.3 80 10 (VSS = AVSS = 0V) Unit °C V cycles years *1 : Those voltages must be supplied to VDDL pin and VPP pin when programming and eraseing Flash ROM. VPP pin has an internal pulldown resister. 22/37 FEDL610Q421-03 ML610Q421/ML610Q422 DC CHARACTERISTICS (1/5) (VDD = 1.1 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, unless otherwise specified) (1/5) Rating Measuring Parameter Symbol Condition Unit circuit Min. Typ. Max. Typ. Typ. Ta = 25°C 500 kHz −10% +10% VDD = 1.3 Typ. Ta = −20 to Typ. 500kHz RC oscillation 500 kHz fRC frequency to 3.6V +70°C −25% +25% Typ. Ta = −40 to Typ. 500 kHz +85°C −45% +45% LSCLK = 32.768kHz 4 PLL oscillation frequency* fPLL -2.5% 8.192 +2.5% MHz VDD = 1.8 to 3.6V Low-speed crystal oscillation TXTL   0.3 2 s 2 start time* 500kHz RC oscillation start 1 TRC   50 500 µs time High-speed crystal oscillation TXTH VDD = 1.8 to 3.6V ― 2 20 3 start time* PLL oscillation start time TPLL VDD = 1.8 to 3.6V ― 1 10 ms Low-speed oscillation stop TSTOP  0.2 3 20 *1 detect time Reset pulse width PRST  200   µs Reset noise elimination PNRST    0.3 pulse width Power-on reset activation TPOR    10 ms power rise time 1 * : When low-speed crystal oscillation stops for a duration more than the low-speed oscillation stop detect time, the system is reset to shift to system reset mode. 2 * : Use 32.768KHz Crystal Oscillator C-001R (Epson Toyocom) with capacitance CGL/CDL＝0pF. 3 * : Use 4.096MHz Crystal Oscillator CHC49SFWB (Kyocera). 4 * : 1024 clock average. [Reset pulse width] VIL1 RESET_N VIL1 PRST Reset pulse width (PRST) [Power-on reset activation power rise time] 0.9xVDD VDD 0.1xVDD TPOR Power-on reset activation power rise time (TPOR ) 23/37 FEDL610Q421-03 ML610Q421/ML610Q422 DC CHARACTERISTICS (2/5) (VDD = 1.1 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, unless otherwise specified) (2/5) Rating Measuring Parameter Symbol Condition Unit circuit Min. Typ. Max. CN4–0 = 00H 0.89 0.94 0.99 CN4–0 = 01H 0.91 0.96 1.01 CN4–0 = 02H 0.93 0.98 1.03 CN4–0 = 03H 0.95 1.00 1.05 CN4–0 = 04H 0.97 1.02 1.07 CN4–0 = 05H 0.99 1.04 1.09 CN4–0 = 06H 1.01 1.06 1.11 CN4–0 = 07H 1.03 1.08 1.13 CN4–0 = 08H 1.05 1.10 1.15 CN4–0 = 09H 1.07 1.12 1.17 CN4–0 = 0AH 1.09 1.14 1.19 CN4–0 = 0BH 1.11 1.16 1.21 CN4–0 = 0CH 1.13 1.18 1.23 CN4–0 = 0DH 1.15 1.20 1.25 CN4–0 = 0EH 1.17 1.22 1.27 CN4–0 = 0FH 1.19 1.24 1.29 VDD = 3.0V, VL1 voltage VL1 V Tj = 25°C CN4–0 = 10H 1.21 1.26 1.31 CN4–0 = 11H 1.23 1.28 1.33 CN4–0 = 12H 1.25 1.30 1.35 CN4–0 = 13H 1.27 1.32 1.37 *1 CN4–0 = 14H 1.29 1.34 1.39 *1 CN4–0 = 15H 1.31 1.36 1.41 1 *1 CN4–0 = 16H 1.33 1.38 1.43 *1 CN4–0 = 17H 1.35 1.40 1.45 *1 CN4–0 = 18H 1.37 1.42 1.47 *1 CN4–0 = 19H 1.39 1.44 1.49 *1 CN4–0 = 1AH 1.41 1.46 1.51 *1 CN4–0 = 1BH 1.43 1.48 1.53 *1 CN4–0 = 1CH 1.45 1.50 1.55 *1 CN4–0 = 1DH 1.47 1.52 1.57 *1 CN4–0 = 1EH 1.49 1.54 1.59 *1 CN4–0 = 1FH 1.51 1.56 1.61 VL1 temperature ∆VL1 VDD = 3.0V  −1.5  mV/°C deviation VL1 voltage ∆VL1 VDD = 1.3 to 3.6V  5 20 mV/V dependency VDD = 3.0V, Tj = 25°C, Typ. Typ. * VL2 voltage ２ VL2 VL1×2 500kΩ load (VL4−VSS) −10% +4% 1/3 bias VL1×2 Typ. Typ. VDD = 3.0V, * VL3 voltage ２ VL3 V −10% +4% 1/4 bias VL1×3 Tj = 25°C 500kΩ load 1/3 bias VL1×3 Typ. Typ. * VL4 voltage ２ VL4 (VL4−VSS) −10% +5% 1/4 bias VL1×4 LCD bias voltage TBIAS    600 ms generation time 1 * : When using 1/4 bias, the VL1 voltage is set to typ. 1.32 V (same voltage as in CN4–0 = 13H). 2 * : Boost clock is 2kHz(initial) for the bias generation. C12=C34=1uF. 24/37 FEDL610Q421-03 ML610Q421/ML610Q422 DC CHARACTERISTICS (3/5) (VDD = 1.1 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, unless otherwise specified) (3/5) Rating Measuring Parameter Symbol Condition Unit circuit Min. Typ. Max. LD2–0 = 0H 1.35 LD2–0 = 1H 1.4 LD2–0 = 2H 1.45 LD2–0 = 3H 1.5 LD2–0 = 4H 1.6 LD2–0 = 5H 1.7 LD2–0 = 6H 1.8 LD2–0 = 7H 1.9 Typ. Typ. BLD threshold V VDD = 1.35 to 3.6V VBLD voltage −2% +2% LD2–0 = 8H 2.0 LD2–0 = 9H 2.1 LD2–0 = 0AH 2.2 LD2–0 = 0BH 2.3 LD2–0 = 0CH 2.4 LD2–0 = 0DH 2.5 LD2–0 = 0EH 2.7 LD2–0 = 0FH 2.9 BLD threshold voltage ∆VBLD VDD = 1.35 to 3.6V  0  %/°C temperature deviation Supply current 1 Supply current 2 Supply current 3 Supply current 4 Supply current 5 IDD1 IDD2 IDD3 IDD4 IDD5 CPU: In STOP state. Low-speed/high-speed oscillation: stopped. Ta = 25°C  0.15 0.50 Ta = -20 to +70°C   2.50 Ta = -40 to +85°C   5.00 CPU: In HALT state (LTBC, 3 5 WDT: Operating* * ). High-speed oscillation: Stopped. LCD/BIAS circuits: Stopped. CPU: In 32.768kHz operating 1 3 state.* * High-speed oscillation: Stopped. 2 LCD/BIAS circuits: Operating.* Ta = 25°C  0.5 1.3 Ta = -20 to +70°C   3.5 Ta = -40 to +85°C   6.0 Ta = 25°C  5 7 Ta = -20 to +70°C   12 Ta = -40 to +85°C   16 CPU: In 500kHz CR operating state. 2 LCD/BIAS circuits: Operating.* Ta = 25°C  70 85 Ta = -20 to +70°C   100 Ta = -40 to +85°C   120 CPU: In 4.096MHz operating 2 3 state.* * PLL: In oscillating state. 2 LCD/BIAS circuits: Operating. * VDD = 1.8 to 3.6V Ta = 25°C  0.8 1.0 Ta = -20 to +70°C   1.2 Ta = -40 to +85°C   1.2 µA 1 µA µA µA mA CPU: In 4.096MHz operating Ta = 25°C  1.5 1.6 2 state.* 3 4 PLL: In oscillating state. * * Supply current 6 Ta = -20 to +70°C IDD6   2.5 mA A/D: In operating state. 2 LCD/BIAS circuits: Operating. * Ta = -40 to +85°C   2.5 VDD = AVDD = 3.0V 1 * : When the CPU operating rate is 100% (No HALT state). 2 * : All SEGs: off waveform, No LCD panel load, 1/3 bias, 1/3 duty, Frame frequency: Approx. 64 Hz, Bias voltage multiplying clock: 1/128 LSCLK (256Hz) 3 * : Use 32.768KHz Crystal Oscillator C-001R (Epson Toyocom) with capacitance CGL/CDL＝0pF. 4 * : Use 4.096MHz Crystal Oscillator CHC49SFWB (Kyocera). 5 * : Significant bits of BLKCON0~BLKCON4 registers are all “1”. 25/37 FEDL610Q421-03 ML610Q421/ML610Q422 DC CHARACTERISTICS (4/5) (VDD = 1.1 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, unless otherwise specified) (4/5) Rating Measuring Parameter Symbol Condition Unit circuit Min. Typ. Max. IOH1 = −0.5mA, VDD = 1.8 to 3.6V Output voltage 1 nd (P20–P22/2 function is selected) (P30–P36) (P40–P47) *1 (PA0–PA7) VOH1 IOH1 = -0.1mA, VDD = 1.3 to 3.6V IOH1 = -0.03mA, VDD = 1.1 to 3.6V VOL1 IOL1 = +0.5mA, VDD = 1.8 to 3.6V IOL1 = +0.1mA, VDD = 1.3 to 3.6V IOL1 = +0.03mA, VDD = 1.1 to 3.6V IOH1 = −0.5mA, VDD = 1.8 to 3.6V Output voltage 2 nd (P20–P22/2 function is Not selected) VOH2 IOH1 = -0.03mA, VDD = 1.1 to 3.6V VOL2 Output voltage 3 (P40–P41) Output voltage 4 (COM0–15) (SEG0–49) IOH1 = -0.1mA, VDD = 1.3 to 3.6V VOL3 IOL2 = +5mA, VDD = 1.8 to 3.6V IOL3 = +3mA, VDD = 2.0 to 3.6V 2 (when I C mode is selected) VDD −0.5 VDD −0.3 VDD −0.3    VDD −0.5 VDD −0.3 VDD −0.3           0.5 0.5 0.3        0.5   0.4 VOH4 IOH4 = −0.2mA, VL1=1.2V VL4 −0.2   VOMH4 IOMH4 = +0.2mA, VL1=1.2V   VL3 +0.2 VOMH4S IOMH4S = −0.2mA, VL1=1.2V VL3 −0.2   VOM4 IOM4 = +0.2mA, VL1=1.2V   VL2 +0.2 VOM4S IOM4S = −0.2mA, VL1=1.2V VL2 −0.2   VOML4 IOML4 = +0.2mA, VL1=1.2V   VL1 +0.2 VOML4S IOML4S = −0.2mA, VL1=1.2V   IOL4 = +0.2mA, VL1=1.2V VL1 −0.2   0.2 VOH = VDD (in high-impedance state)   1 VOL4 Output leakage IOOH (P20–P22) (P30–P35) (P40–P47) IOOL *1 (PA0–PA7) 1 * : ML610Q421 only V 2 µA VOL = VSS (in high-impedance state) −1  3  26/37 FEDL610Q421-03 ML610Q421/ML610Q422 (VDD = 1.1 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, unless otherwise specified) (4/5) Rating Measuring Parameter Symbol Condition Unit circuit Min. Typ. Max. IIH1 VIH1 = VDD 0  1 VDD = 1.8 to 3.6V −600 −300 −20 Input current 1 (RESET_N) IIL1 VIL1 = VSS VDD = 1.3 to 3.6V −600 −300 -10 VDD = 1.1 to 3.6V −600 −300 -2 VDD = 1.8 to 3.6V 20 300 600 IIH1 VIH1 = VDD VDD = 1.3 to 3.6V 10 300 600 Input current 1 (TEST) VDD = 1.1 to 3.6V 2 300 600 IIL1 VIL1 = Vss -1   µA 4 VDD = 1.8 to 3.6V 2 30 200 VIH2 = VDD Input current 2 IIH2 VDD = 1.3 to 3.6V 0.2 30 200 (when pulled-down) (NMI) VDD = 1.1 to 3.6V 0.01 30 200 (P00–P03) VDD = 1.8 to 3.6V −200 −30 −2 (P10–P11) VIL2 = VSS IIL2 VDD = 1.3 to 3.6V −200 −30 -0.2 (P30–P35) (when pulled-up) V = 1.1 to 3.6V −200 −30 -0.01 DD (P40–P47) *1 IIH2Z VIH2 = VDD (in high-impedance state)   1 (PA0–PA7) IIL2Z VIL2 = VSS (in high-impedance state) −1   1 * : ML610Q421 only DC CHARACTERISTICS (5/5)) (VDD = 1.1 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, unless otherwise specified) (5/5) Rating Measuring Parameter Symbol Condition Unit circuit Min. Typ. Max. Input voltage 1 (RESET_N) (TEST) (NMI) (P00–P03) (P10–P11) (P31–P35) (P40–P43) (P45–P47) *1 (PA0–PA7) Input voltage 2 (P30, P44) Input pin capacitance (NMI) (P00–P03) (P10–P11) (P30–P35) (P40–P47) *1 (PA0–PA7) 1 * : ML610Q421 only VDD = 1.3 to 3.6V 0.7 ×VDD  VDD VDD = 1.1 to 3.6V 0.7 ×VDD  VDD VDD = 1.3 to 3.6V 0  0.3 ×VDD VDD = 1.1 to 3.6V 0  0.2 ×VDD VIH2  0.7 ×VDD  VDD VIL2  0  0.3 ×VDD CIN f = 10kHz Vrms = 50mV Ta = 25°C   5 VIH1 VIL1 V 5 pF  27/37 FEDL610Q421-03 ML610Q421/ML610Q422 MEASURING CIRCUITS MEASURING CIRCUIT 1 XT0 C4 XT1 C3 C2 C34 32.768kHz crystal CGH P10/OSC0 C12 C1 CDH CV: 1µF CL0: 1µF CL1: 0.1µF CX: 0.1µF Ca,Cb,Cc,Cd: 1µF C12,C34: 1µF CGH: 24pF CDH: 24pF 32.768kHz crystal: C-001R (Epson Toyocom) 4.096MHz crystal: HC49SFWB (Kyocera) P11/OSC1 4.096MHz crystal VDD AVDD VREFVDDL VDDX VL1 VL2 VL3 VL4 VSS AVSS A CV CL1 CL0 CX Ca Cb Cc Cd MEASURING CIRCUIT 2 (*2) VIL Input pins (*1) Output pins VIH VDD VDDL VDDX VL1 VL2 VL3 V VL4 AVDDVREF VSSAVSS (*1) Input logic circuit to determine the specified measuring conditions. (*2) Measured at the specified output pins. 28/37 FEDL610Q421-03 ML610Q421/ML610Q422 MEASURING CIRCUIT 3 (*2) VIL Input pins RS1 Output pins VIH VDD VDDL VDDX VL1 VL2 VL3 A VL4 AVDDVREF VSSAVSS *1: Input logic circuit to determine the specified measuring conditions. *2: Measured at the specified output pins. MEASURING CIRCUIT 4 Input pins Output pins (*3) A VDD VDDL VDDX VL1 VL2 VL3 VL4 AVDD VREF VSSAVSS *3: Measured at the specified output pins. VIL Input pins (*1) Output pins VIH VDD VDDL VDDX VL1 VL2 VL3 Waveform monitoring MEASURING CIRCUIT 5 VL4 AVDDVREF VSSAVSS *1: Input logic circuit to determine the specified measuring conditions. 29/37 FEDL610Q421-03 ML610Q421/ML610Q422 AC CHARACTERISTICS (External Interrupt) (VDD = 1.1 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, unless otherwise specified) Rating Parameter Symbol Condition Unit Min. Typ. Max. Interrupt: Enabled (MIE = 1), External interrupt disable period TNUL CPU: NOP operation 76.8  106.8 µs System clock: 32.768kHz P00–P03 (Rising-edge interrupt) tNUL P00–P03 (Falling-edge interrupt) tNUL NMI, P00–P03 (Both-edge interrupt) tNUL AC CHARACTERISTICS (UART) (VDD = 1.3 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, unless otherwise specified) Rating Parameter Symbol Condition Unit Min. Typ. Max. Transmit baud rate  tTBRT  1 BRT* 1  s 1 BRT* BRT* 1 BRT* s −3% +3% 1 * : Baud rate period (including the error of the clock frequency selected) set with the UART0 baud rate register (UA0BRTL,H) and the UART0 mode register 0 (UA0MOD0). Receive baud rate  tRBRT tTBRT TXD0* tRBRT RXD0* *: Indicates the secondary function of the port. 30/37 FEDL610Q421-03 ML610Q421/ML610Q422 AC CHARACTERISTICS (Synchronous Serial Port) (VDD = 1.3 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, unless otherwise specified) Rating Parameter Symbol Condition Unit Min. Typ. Max. 2 When RC oscillation is active* 10   µs (VDD = 1.3 to 3.6V) SCLK input cycle tSCYC (slave mode) When high-speed oscillation is 1   µs 3 active* (VDD = 1.8 to 3.6V) SCLK output cycle 1 tSCYC   SCLK*  s (master mode) 2 When RC oscillation is active* 4   µs (VDD = 1.3 to 3.6V) SCLK input pulse width tSW (slave mode) When high-speed oscillation is 0.4   µs 3 active* (VDD = 1.8 to 3.6V) 1 1 1 SCLK* SCLK* SCLK* SCLK output pulse width tSW  s (master mode) ×0.4 ×0.5 ×0.6 2 When RC oscillation is active*   500 (VDD = 1.3 to 3.6V) SOUT output delay time ns tSD (slave mode) When high-speed oscillation is   240 3 active* (VDD = 1.8 to 3.6V) 2 When RC oscillation is active*   500 (VDD = 1.3 to 3.6V) SOUT output delay time ns tSD (master mode) When high-speed oscillation is   240 3 active* (VDD = 1.8 to 3.6V) SIN input setup time tSS  80   ns (slave mode) 2 When RC oscillation is active* 500   SIN input (VDD = 1.3 to 3.6V) setup time tSS ns When high-speed oscillation is (master mode) 240   3 active* (VDD = 1.8 to 3.6V) 2 When RC oscillation is active* 300   (VDD = 1.3 to 3.6V) SIN input ns tSH hold time When high-speed oscillation is 80   3 active* (VDD = 1.8 to 3.6V) 1 * : Clock period selected with S0CK3–0 of the serial port 0 mode register (SIO0MOD1) 2 * : When RC oscillation is selected with OSCM1–0 of the frequency control register (FCON0) 3 * : When Crystal/ceramic oscillation, built-in PLL oscillation, or external clock input is selected with OSCM1–0 of the frequency control register (FCON0) tSCYC tSW tSW SCLK0* tSD tSD SOUT0* tSS tSH SIN0* *: Indicates the secondary function of the port. 31/37 FEDL610Q421-03 ML610Q421/ML610Q422 AC CHARACTERISTICS (I2C Bus Interface: Standard Mode 100kHz) (VDD = 1.8 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, unless otherwise specified) Rating Parameter Symbol Condition Unit Min. Typ. Max. SCL clock frequency fSCL  0  100 kHz SCL hold time tHD:STA  4.0   µs (start/restart condition) SCL ”L” level time tLOW  4.7   µs SCL ”H” level time tHIGH  4.0   µs SCL setup time tSU:STA  4.7   µs (restart condition) SDA hold time tHD:DAT  0   µs SDA setup time tSU:DAT  0.25   µs SDA setup time tSU:STO  4.0   µs (stop condition) Bus-free time tBUF  4.7   µs AC CHARACTERISTICS (I2C Bus Interface: Fast Mode 400kHz) (VDD = 1.8 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, unless otherwise specified) Rating Parameter Symbol Condition Unit Min. Typ. Max. SCL clock frequency fSCL  0  400 kHz SCL hold time tHD:STA  0.6   µs (start/restart condition) SCL ”L” level time tLOW  1.3   µs SCL ”H” level time tHIGH  0.6   µs SCL setup time tSU:STA  0.6   µs (restart condition) SDA hold time tHD:DAT  0   µs SDA setup time tSU:DAT  0.1   µs SDA setup time tSU:STO  0.6   µs (stop condition) Bus-free time tBUF  1.3   µs Start condition Restart condition Stop condition P40/SDA P41/SCL tHD:STA tLOW tHIGH tSU:STA tHD:STA tSU:DAT tHD:DAT tSU:STO tBUF 32/37 FEDL610Q421-03 ML610Q421/ML610Q422 AC CHARACTERISTICS (RC Oscillation A/D Converter) (VDD = 1.3 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, unless otherwise specified) Rating Parameter Symbol Condition Unit Min. Typ. Max. RS0, RS1, Resistors for oscillation RT0, CS0, CT0, CS1 ≥ 740pF 1   kΩ RT0-1,RT1 fOSC1 Resistor for oscillation = 1kΩ 209.4 330.6 435.1 kHz Oscillation frequency fOSC2 Resistor for oscillation = 10kΩ 41.29 55.27 64.16 kHz VDD = 1.5V fOSC3 Resistor for oscillation = 100kΩ 4.71 5.97 7.06 kHz Kf1 RT0, RT0-1, RT1 = 1kHz 5.567 5.982 6.225  RS to RT oscillation frequency *1 ratio Kf2 RT0, RT0-1, RT1 = 10kHz 0.99 1 1.01  VDD = 1.5V Kf3 RT0, RT0-1, RT1 = 100kHz 0.104 0.108 0.118  fOSC1 Resistor for oscillation = 1kΩ 407.3 486.7 594.6 kHz Oscillation frequency fOSC2 Resistor for oscillation = 10kΩ 49.76 59.28 72.76 kHz VDD = 3.0V fOSC3 Resistor for oscillation = 100kΩ 5.04 5.993 7.04 kHz Kf1 RT0, RT0-1, RT1 = 1kHz 8.006 8.210 8.416  RS to RT oscillation frequency *1 ratio Kf2 RT0, RT0-1, RT1 = 10kHz 0.99 1 1.01  VDD = 3.0V Kf3 RT0, RT0-1, RT1 = 100kHz 0.100 0.108 0.115  1 * : Kfx is the ratio of the oscillation frequency by the sensor resistor to the oscillation frequency by the reference resistor on the same conditions. fOSCX(RT0-1−CS0 oscillation) fOSCX(RS0−CS0 oscillation) , IN0 CS0 RCT0 (*1) VIL *1: Input logic circuit to determine the specified measuring conditions. VDDL fOSCX(RT1−CS1 oscillation) fOSCX(RS1−CS1 oscillation) VDDX RT1 RT0, RT0-1, RT1: 1kΩ /10kΩ/100kΩ RS0, RS1: 10kΩ CS0, CT0, CS1: 560pF CVR0, CVR1: 820pF IN1 CS1 RS1 RT1 RCM VDD CV RT0 RS0 RS0 RT0 Input pins VIH , CVR1 RT0-1 CT0 CS0 CVR0 RS1 fOSCX(RT0−CS0 oscillation) fOSCX(RS0−CS0 oscillation) (x = 1, 2, 3) CS1 Kfx = Frequency measurement (fOSCX) AVDD VREFVSS AVSS CL1 CL0 CX Note: - Please have the shortest layout for the common node (wiring patterns which are connected to the external capacitors, resistors and IN0/IN1 pin), including CVR0/CVR1. Especially, do not have long wire between IN0/IN1 and RS0/RS1. The coupling capacitance on the wires may occur incorrect A/D conversion. Also, please do not have signals which may be a source of noise around the node. - When RT0/RT1 (Thermistor and etc.) requires long wiring due to the restricted placement, please have VSS(GND) trace next to the signal. - Please make wiring to components (capacitor, resisteor and etc.) necessory for objective measurement. Wiring to reserved components may affect to the A/D conversion operation by noise the components itself may have. 33/37 FEDL610Q421-03 ML610Q421/ML610Q422 Electrical Characteristics of Successive Approximation Type A/D Converter (VDD = 1.8 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, unless otherwise specified) Rating Parameter Symbol Condition Unit Min. Typ. Max. Resolution n    12 bit 2.7V ≤ VREF ≤ 3.6V −4  +4 Integral non-linearity error IDL 2.2V ≤ VREF ≤ 2.7V −6  +6 2.7V ≤ VREF ≤ 3.6V −3  +3 Differential non-linearity error LSB DNL 2.2V ≤ VREF ≤ 2.7V −5  +5 Zero-scale error VOFF  −6  +6 Full-scale error FSE  −6  +6 Reference voltage VREF  2.2  AVDD V SACK = 0  25  (HSCLK = 375kHz to 625kHz) Conversion time tCONV φ/CH SACK = 1  112  (HSCLK = 1.5MHz to 4.2MHz) φ: Period of high-speed clock (HSCLK) AVDD Reference voltage VREF VDD VDDL 10µF 1µF A 0.1µF − 1µF RI≤5kΩ + Analog input 0.1µF VDDX AIN0, AIN1 0.1µF VSS AVSS 34/37 FEDL610Q421-03 ML610Q421/ML610Q422 PACKAGE DIMENSIONS (Unit: mm) Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 35/37 FEDL610Q421-03 ML610Q421/ML610Q422 REVISION HISTORY Document No. FEDL610Q421-01 FEDL610Q421-02 FEDL610Q421-03 Date Jul. 29, 2009 Dec. 3, 2010 Feb. 9, 2015 Page Previous Current Edition Edition – – All 3,4 – – All 3,4 4 4 – 22 22 23 36 37 Description Final edition 1 Add to B version Change header Delete B version Change from "Shipment" to " Product name – Supported Function " Add CLOCK GENERATION CIRCUIT OPERATING CONDITIONS Change "RESET" to " Reset pulse width (PRST)" and " Power-on reset activation power rise time (TPOR )". Change description in Note. 36/37 FEDL610Q421-03 ML610Q421/ML610Q422 Notes 1) The information contained herein is subject to change without notice. 2) Although LAPIS Semiconductor is continuously working to improve product reliability and quality, semiconductors can break down and malfunction due to various factors. Therefore, in order to prevent personal injury or fire arising from failure, please take safety measures such as complying with the derating characteristics, implementing redundant and fire prevention designs, and utilizing backups and fail-safe procedures. LAPIS Semiconductor shall have no responsibility for any damages arising out of the use of our Products beyond the rating specified by LAPIS Semiconductor. 3) Examples of application circuits, circuit constants and any other information contained herein are provided only to illustrate the standard usage and operations of the Products.The peripheral conditions must be taken into account when designing circuits for mass production. 4) The technical information specified herein is intended only to show the typical functions of the Products and examples of application circuits for the Products. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of LAPIS Semiconductor or any third party with respect to the information contained in this document; therefore LAPIS Semiconductor shall have no responsibility whatsoever for any dispute, concerning such rights owned by third parties, arising out of the use of such technical information. 5) The Products are intended for use in general electronic equipment (i.e. AV/OA devices, communication, consumer systems, gaming/entertainment sets) as well as the applications indicated in this document. 6) The Products specified in this document are not designed to be radiation tolerant. 7) For use of our Products in applications requiring a high degree of reliability (as exemplified below), please contact and consult with a LAPIS Semiconductor representative: transportation equipment (i.e. cars, ships, trains), primary communication equipment, traffic lights, fire/crime prevention, safety equipment, medical systems, servers, solar cells, and power transmission systems. 8) Do not use our Products in applications requiring extremely high reliability, such as aerospace equipment, nuclear power control systems, and submarine repeaters. 9) LAPIS Semiconductor shall have no responsibility for any damages or injury arising from non-compliance with the recommended usage conditions and specifications contained herein. 10) LAPIS Semiconductor has used reasonable care to ensure the accuracy of the information contained in this document. However, LAPIS Semiconductor does not warrant that such information is error-free and LAPIS Semiconductor shall have no responsibility for any damages arising from any inaccuracy or misprint of such information. 11) Please use the Products in accordance with any applicable environmental laws and regulations, such as the RoHS Directive. For more details, including RoHS compatibility, please contact a ROHM sales office. LAPIS Semiconductor shall have no responsibility for any damages or losses resulting non-compliance with any applicable laws or regulations. 12) When providing our Products and technologies contained in this document to other countries, you must abide by the procedures and provisions stipulated in all applicable export laws and regulations, including without limitation the US Export Administration Regulations and the Foreign Exchange and Foreign Trade Act. 13) This document, in part or in whole, may not be reprinted or reproduced without prior consent of LAPIS Semiconductor. Copyright 2008 - 2015 LAPIS Semiconductor Co., Ltd. 2-4-8 Shinyokohama, Kouhoku-ku, Yokohama 222-8575, Japan http://www.lapis-semi.com/en/ 37/37