ML610Q438REFBOARD

Dear customer LAPIS Semiconductor Co., Ltd. ("LAPIS Semiconductor"), on the 1st day of October, 2020, implemented the incorporation-type company split (shinsetsu-bunkatsu) in which LAPIS established a new company, LAPIS Technology Co., Ltd. (“LAPIS Technology”) and LAPIS Technology succeeded LAPIS Semiconductor’s LSI business. Therefore, all references to "LAPIS Semiconductor Co., Ltd.", "LAPIS Semiconductor" and/or "LAPIS" in this document shall be replaced with "LAPIS Technology Co., Ltd." Furthermore, there are no changes to the documents relating to our products other than the company name, the company trademark, logo, etc. Thank you for your understanding. LAPIS Technology Co., Ltd. October 1, 2020 FEUL610Q438-03 ML610Q438/ML610Q439 User’s Manual Issue Date: May. 08, 2015 ML610Q438/ML610Q439 User’s Manual Notes 1) The information contained herein is subject to change without notice. 2) Although LAPIS Semiconductor is continuously working to improve product reliability and quality, semiconductors can break down and malfunction due to various factors. Therefore, in order to prevent personal injury or fire arising from failure, please take safety measures such as complying with the derating characteristics, implementing redundant and fire prevention designs, and utilizing backups and fail-safe procedures. LAPIS Semiconductor shall have no responsibility for any damages arising out of the use of our Products beyond the rating specified by LAPIS Semiconductor. 3) Examples of application circuits, circuit constants and any other information contained herein are provided only to illustrate the standard usage and operations of the Products.The peripheral conditions must be taken into account when designing circuits for mass production. 4) The technical information specified herein is intended only to show the typical functions of the Products and examples of application circuits for the Products. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of LAPIS Semiconductor or any third party with respect to the information contained in this document; therefore LAPIS Semiconductor shall have no responsibility whatsoever for any dispute, concerning such rights owned by third parties, arising out of the use of such technical information. 5) The Products are intended for use in general electronic equipment (i.e. AV/OA devices, communication, consumer systems, gaming/entertainment sets) as well as the applications indicated in this document. 6) The Products specified in this document are not designed to be radiation tolerant. 7) For use of our Products in applications requiring a high degree of reliability (as exemplified below), please contact and consult with a LAPIS Semiconductor representative: transportation equipment (i.e. cars, ships, trains), primary communication equipment, traffic lights, fire/crime prevention, safety equipment, medical systems, servers, solar cells, and power transmission systems. 8) Do not use our Products in applications requiring extremely high reliability, such as aerospace equipment, nuclear power control systems, and submarine repeaters. 9) LAPIS Semiconductor shall have no responsibility for any damages or injury arising from non-compliance with the recommended usage conditions and specifications contained herein. 10) LAPIS Semiconductor has used reasonable care to ensure the accuracy of the information contained in this document. However, LAPIS Semiconductor does not warrant that such information is error-free and LAPIS Semiconductor shall have no responsibility for any damages arising from any inaccuracy or misprint of such information. 11) Please use the Products in accordance with any applicable environmental laws and regulations, such as the RoHS Directive. For more details, including RoHS compatibility, please contact a ROHM sales office. LAPIS Semiconductor shall have no responsibility for any damages or losses resulting non-compliance with any applicable laws or regulations. 12) When providing our Products and technologies contained in this document to other countries, you must abide by the procedures and provisions stipulated in all applicable export laws and regulations, including without limitation the US Export Administration Regulations and the Foreign Exchange and Foreign Trade Act. 13) This document, in part or in whole, may not be reprinted or reproduced without prior consent of LAPIS Semiconductor. Copyright 2010 – 2015 LAPIS Semiconductor Co., Ltd. 2-4-8 Shinyokohama, Kouhoku-ku, Yokohama 222-8575, Japan http://www.lapis-semi.com/en/ FEUL610Q438 i ML610Q438/ML610Q439 User’s Manual Preface This manual describes the operation of the hardware of the 8-bit microcontroller ML610Q438/ML610Q439. The following manuals are also available. Read them as necessary.  nX-U8/100 Core Instruction Manual Description on the basic architecture and the each instruction of the nX-U8/100 Core.  MACU8 Assembler Package User’s Manual Description on the method of operating the relocatable assembler, the linker, the librarian, and the object converter and also on the specifications of the assembler language.  CCU8 User’s Manual Description on the method of operating the compiler.  CCU8 Programming Guide Description on the method of programming.  CCU8 Language Reference Description on the language specifications.  DTU8 Debugger User’s Manual Description on the method of operating the debugger DTU8.  IDEU8 User’s Manual Description on the integrated development environment IDEU8.  uEASE User’s Manual Description on the on-chip debug tool uEASE.  uEASE connection Manual Description about the connection between uEASE and ML610Qxxx.  FWuEASE Flash Writer Host Program User’s Manual Description on the Flash Writer host program. FEUL610Q438 ii ML610Q438/ML610Q439 User’s Manual Notation Classification Notation Description ♦ Numeric value xxh, xxH xxb Indicates a hexadecimal number. x: Any value in the range of 0 to F Indicates a binary number; “b” may be omitted. x: A value 0 or 1 ♦ Unit word, W byte, B nibble, N mega-, M kilo-, K kilo-, k milli-, m micro-, µ nano-, n second, s (lower case) 1 word = 16 bits 1 byte = 8 bits 1 nibble = 4 bits 106 210 = 1024 103 = 1000 10-3 10-6 10-9 second ♦ Terminology “H” level, “1” level Indicates high voltage signal levels VIH and VOH as specified by the electrical characteristics. Indicates low voltage signal levels VIL and VOL as specified by the electrical characteristics. “L” level, “0” level ♦ Register description R/W: Indicates that Read/Write attribute. “R” indicates that data can be read and “W” indicates that data can be written. “R/W” indicates that data can be read or written. Invalid bit: This bit reads “0” when read. Write to this bit is ignored. Register name Bit name MSB LSB FCON0   OUTC1 OUTC0 OSCM1 OSCM0 SYSC1 SYSC0 R/W Initial value R/W 0 R/W 0 R/W 1 R/W 1 R/W 0 R/W 1 R/W 0 R/W 1 Initial value after reset FEUL610Q438 iii ML610Q438/ML610Q439 User’s Manual Contents Table of Contents Chapter 1 1. Overview......................................................................................................................................................... 1-1 1.1 Features ....................................................................................................................................................... 1-1 1.2 Configuration of Functional Blocks ............................................................................................................ 1-5 1.2.1 Block Diagram of ML610Q438 .......................................................................................................... 1-5 1.2.2 Block Diagram of ML610Q439 .......................................................................................................... 1-6 1.3 Pins ............................................................................................................................................................. 1-7 1.3.1 Pin Layout ........................................................................................................................................... 1-7 1.3.1.1 Pin Layout of ML610Q438 LQFP Package..................................................................................... 1-7 1.3.1.2 Pin Layout of ML610Q439P LQFP Package .................................................................................. 1-8 1.3.1.3 Pin Layout of ML610Q438 Chip ..................................................................................................... 1-9 1.3.1.4 Pin Layout of ML610Q439 Chip ................................................................................................... 1-10 1.3.1.5 Pad Coordinates of ML610Q438 Chip .......................................................................................... 1-11 1.3.1.6 Pad Coordinates of ML610Q439 Chip .......................................................................................... 1-12 1.3.2 List of Pins ........................................................................................................................................ 1-13 1.3.3 Description of Pins ............................................................................................................................ 1-17 1.3.4 Termination of Unused Pins ............................................................................................................. 1-21 1.3.5 The main difference points of ML610Q438 and ML610Q439 ......................................................... 1-21 Chapter 2 2. CPU and Memory Space ................................................................................................................................. 2-1 2.1 Overview..................................................................................................................................................... 2-1 2.2 Program Memory Space ............................................................................................................................. 2-1 2.3 Data Memory Space.................................................................................................................................... 2-2 2.4 Instruction Length ....................................................................................................................................... 2-2 2.5 Data Type.................................................................................................................................................... 2-2 2.6 Description of Registers .............................................................................................................................. 2-3 2.6.1 List of Registers .................................................................................................................................. 2-3 2.6.2 Data Segment Register (DSR) ............................................................................................................ 2-4 Chapter 3 3. Reset Function ................................................................................................................................................ 3-1 3.1 Overview..................................................................................................................................................... 3-1 3.1.1 Features ............................................................................................................................................... 3-1 3.1.2 Configuration ...................................................................................................................................... 3-1 3.1.3 List of Pin............................................................................................................................................ 3-1 3.2 Description of Registers .............................................................................................................................. 3-2 3.2.1 List of Registers .................................................................................................................................. 3-2 3.2.2 Reset Status Register (RSTAT) .......................................................................................................... 3-2 3.3 Description of Operation............................................................................................................................. 3-3 3.3.1 Operation of System Reset Mode ....................................................................................................... 3-3 Chapter 4 4. MCU Control Function ................................................................................................................................... 4-1 4.1 Overview..................................................................................................................................................... 4-1 4.1.1 Features ............................................................................................................................................... 4-1 4.1.2 Configuration ...................................................................................................................................... 4-1 4.2 Description of Registers .............................................................................................................................. 4-2 4.2.1 List of Registers .................................................................................................................................. 4-2 4.2.2 Stop Code Acceptor (STPACP) .......................................................................................................... 4-3 4.2.3 Standby Control Register (SBYCON) ................................................................................................ 4-4 4.2.4 Block Control Register 0 (BLKCON0)............................................................................................... 4-5 4.2.5 Block Control Register 1 (BLKCON1)............................................................................................... 4-6 FEUL610Q438 Contents-1 ML610Q438/ML610Q439 User’s Manual Contents 4.2.6 4.2.7 4.2.8 Block Control Register 2 (BLKCON2)............................................................................................... 4-7 Block Control Register 3 (BLKCON3)............................................................................................... 4-8 Block Control Register 4 (BLKCON4)............................................................................................... 4-9 4.3 Description of Operation........................................................................................................................... 4-11 4.3.1 Program Run Mode ........................................................................................................................... 4-11 4.3.2 HALT Mode ..................................................................................................................................... 4-11 4.3.3 STOP Mode ...................................................................................................................................... 4-12 4.3.3.1 STOP Mode When CPU Operates with Low-Speed Clock ........................................................... 4-12 4.3.3.2 STOP Mode When CPU Operates with High-Speed Clock .......................................................... 4-13 4.3.3.3 Note on Return Operation from STOP/HALT Mode .................................................................... 4-14 4.3.4 Block Control Function..................................................................................................................... 4-15 Chapter 5 5. Interrupts (INTs) ............................................................................................................................................. 5-1 5.1 Overview..................................................................................................................................................... 5-1 5.1.1 Features ............................................................................................................................................... 5-1 5.2 Description of Registers .............................................................................................................................. 5-2 5.2.1 List of Registers .................................................................................................................................. 5-2 5.2.2 Interrupt Enable Register 1 (IE1) ........................................................................................................ 5-3 5.2.3 Interrupt Enable Register 2 (IE2) ........................................................................................................ 5-5 5.2.4 Interrupt Enable Register 3 (IE3) ........................................................................................................ 5-6 5.2.5 Interrupt Enable Register 4 (IE4) ........................................................................................................ 5-7 5.2.6 Interrupt Enable Register 5 (IE5) ........................................................................................................ 5-8 5.2.7 Interrupt Enable Register 6 (IE6) ........................................................................................................ 5-9 5.2.8 Interrupt Enable Register 7 (IE7) ...................................................................................................... 5-11 5.2.9 Interrupt Request Register 0 (IRQ0) ................................................................................................. 5-12 5.2.10 Interrupt Request Register 1 (IRQ1) ................................................................................................. 5-13 5.2.11 Interrupt Request Register 2 (IRQ2) ................................................................................................. 5-15 5.2.12 Interrupt Request Register 3 (IRQ3) ................................................................................................. 5-16 5.2.13 Interrupt Request Register 4 (IRQ4) ................................................................................................. 5-17 5.2.14 Interrupt Request Register 5 (IRQ5) ................................................................................................. 5-18 5.2.15 Interrupt Request Register 6 (IRQ6) ................................................................................................. 5-19 5.2.16 Interrupt Request Register 7 (IRQ7) ................................................................................................. 5-21 5.3 Description of Operation........................................................................................................................... 5-23 5.3.1 Maskable Interrupt Processing .......................................................................................................... 5-24 5.3.2 Non-Maskable Interrupt Processing .................................................................................................. 5-24 5.3.3 Software Interrupt Processing ........................................................................................................... 5-24 5.3.4 Notes on Interrupt Routine ................................................................................................................ 5-25 5.3.5 Interrupt Disable State ...................................................................................................................... 5-28 Chapter 6 6. Clock Generation Circuit ................................................................................................................................ 6-1 6.1 Overview..................................................................................................................................................... 6-1 6.1.1 Features ............................................................................................................................................... 6-1 6.1.2 Configuration ...................................................................................................................................... 6-1 6.1.3 List of Pins .......................................................................................................................................... 6-2 6.2 Description of Registers .............................................................................................................................. 6-2 6.2.1 List of Registers .................................................................................................................................. 6-2 6.2.2 Frequency Control Register 0 (FCON0) ............................................................................................. 6-3 6.2.3 Frequency Control Register 1 (FCON1) ............................................................................................. 6-5 6.3 Description of Operation............................................................................................................................. 6-6 6.3.1 Low-Speed Clock................................................................................................................................ 6-6 6.3.1.1 Low-Speed Clock Generation Circuit.............................................................................................. 6-6 6.3.1.2 Operation of Low-Speed Clock Generation Circuit ........................................................................ 6-7 6.3.2 High-Speed Clock ............................................................................................................................... 6-8 6.3.2.1 500 kHz RC Oscillation ................................................................................................................... 6-8 FEUL610Q438 Contents-2 ML610Q438/ML610Q439 User’s Manual Contents 6.3.2.2 Crystal/Ceramic Oscillation Mode .................................................................................................. 6-9 6.3.2.3 Built-in PLL Oscillation Mode ...................................................................................................... 6-10 6.3.2.4 External Clock Input Mode ........................................................................................................... 6-10 6.3.2.5 2 MHz RC Oscillation ................................................................................................................. 6-11 6.3.2.6 Operation of High-Speed Clock Generation Circuit...................................................................... 6-12 6.3.3 Switching of System Clock ............................................................................................................... 6-14 6.4 Specifying port registers ........................................................................................................................... 6-16 6.4.1 Functioning P21 (OUTCLK) as the high speed clock output ........................................................... 6-16 6.4.2 Functioning P22 (LSCLK) as the low speed clock output ................................................................ 6-16 Chapter 7 7. Time Base Counter ......................................................................................................................................... 7-1 7.1 Overview..................................................................................................................................................... 7-1 7.1.1 Features ............................................................................................................................................... 7-1 7.1.2 Configuration ...................................................................................................................................... 7-1 7.2 Description of Registers .............................................................................................................................. 7-3 7.2.1 List of Registers .................................................................................................................................. 7-3 7.2.2 Low-Speed Time Base Counter (LTBR) ............................................................................................ 7-4 7.2.3 High-Speed Time Base Counter Divide Register (HTBDR) .............................................................. 7-5 7.2.4 Low-Speed Time Base Counter Frequency Adjustment Registers L and H (LTBADJL, LTBADJH) ..................................................................................................................... 7-6 7.3 Description of Operation............................................................................................................................. 7-7 7.3.1 Low-Speed Time Base Counter .......................................................................................................... 7-7 7.3.2 High-Speed Time Base Counter ......................................................................................................... 7-8 7.3.3 Low-Speed Time Base Counter Frequency Adjustment Function ...................................................... 7-9 Chapter 8 8. Capture ............................................................................................................................................................ 8-1 8.1 Overview..................................................................................................................................................... 8-1 8.1.1 Features ............................................................................................................................................... 8-1 8.1.2 Configuration ...................................................................................................................................... 8-1 8.1.3 List of Pins .......................................................................................................................................... 8-1 8.2 Description of Registers .............................................................................................................................. 8-2 8.2.1 List of Registers ........................................................................................................................................ 8-2 8.2.2 Capture Control Register (CAPCON) ................................................................................................. 8-3 8.2.3 Capture Status Register (CAPSTAT).................................................................................................. 8-4 8.2.4 Capture Data Register 0 (CAPR0) ...................................................................................................... 8-5 8.2.5 Capture Data Register 1 (CAPR1) ...................................................................................................... 8-6 8.3 Description of Operation............................................................................................................................. 8-7 Chapter 9 9. 1 kHz Timer (1kHzTM) .................................................................................................................................. 9-1 9.1 Overview..................................................................................................................................................... 9-1 9.1.1 Features ............................................................................................................................................... 9-1 9.1.2 Configuration ...................................................................................................................................... 9-1 9.2 Description of Registers .............................................................................................................................. 9-2 9.2.1 List of Registers .................................................................................................................................. 9-2 9.2.2 1 kHz Timer Count Registers (T1KCRL, T1KCRH).......................................................................... 9-3 9.2.3 1 kHz Timer Control Register (T1KCON) ......................................................................................... 9-4 9.3 Description of Operation............................................................................................................................. 9-5 Chapter 10 10. Timers ........................................................................................................................................................... 10-1 10.1 Overview................................................................................................................................................... 10-1 10.1.1 Features ............................................................................................................................................. 10-1 10.1.2 Configuration .................................................................................................................................... 10-1 FEUL610Q438 Contents-3 ML610Q438/ML610Q439 User’s Manual Contents 10.2 Description of Registers ............................................................................................................................ 10-2 10.2.1 List of Registers ................................................................................................................................ 10-2 10.2.2 Timer 0 Data Register (TM0D) ........................................................................................................ 10-3 10.2.3 Timer 1 Data Register (TM1D) ........................................................................................................ 10-4 10.2.4 Timer 2 Data Register (TM2D) ........................................................................................................ 10-5 10.2.5 Timer 3 Data Register (TM3D) ........................................................................................................ 10-6 10.2.6 Timer 0 Counter Register (TM0C) ................................................................................................... 10-7 10.2.7 Timer 1 Counter Register (TM1C) ................................................................................................... 10-8 10.2.8 Timer 2 Counter Register (TM2C) ................................................................................................... 10-9 10.2.9 Timer 3 Counter Register (TM3C) ................................................................................................. 10-10 10.2.10 Timer 0 Control Register 0 (TM0CON0) ....................................................................................... 10-11 10.2.11 Timer 1 Control Register 0 (TM1CON0) ....................................................................................... 10-13 10.2.12 Timer 2 Control Register 0 (TM2CON0) ....................................................................................... 10-14 10.2.13 Timer 3 Control Register 0 (TM3CON0) ....................................................................................... 10-16 10.2.14 Timer 0 Control Register 1 (TM0CON1) ....................................................................................... 10-17 10.2.15 Timer 1 Control Register 1 (TM1CON1) ....................................................................................... 10-18 10.2.16 Timer 2 Control Register 1 (TM2CON1) ....................................................................................... 10-19 10.2.17 Timer 3 Control Register 1 (TM3CON1) ....................................................................................... 10-19 10.3 Description of Operation......................................................................................................................... 10-20 Chapter 11 11. PWM ............................................................................................................................................................. 11-1 11.1 Overview................................................................................................................................................... 11-1 11.1.1 Features ............................................................................................................................................. 11-1 11.1.2 Configuration .................................................................................................................................... 11-1 11.1.3 List of Pins ........................................................................................................................................ 11-2 11.2 Description of Registers ............................................................................................................................ 11-2 11.2.1 List of Registers ................................................................................................................................ 11-2 11.2.2 PWM0 Period Registers (PW0PL, PW0PH) .................................................................................... 11-3 11.2.3 PWM1 Period Registers (PW1PL, PW1PH) .................................................................................... 11-4 11.2.4 PWM2 Period Registers (PW2PL, PW2PH) .................................................................................... 11-5 11.2.5 PWM0 Duty Registers (PW0DL, PW0DH)...................................................................................... 11-6 11.2.6 PWM1 Duty Registers (PW1DL, PW1DH)...................................................................................... 11-7 11.2.7 PWM2 Duty Registers (PW2DL, PW2DH)...................................................................................... 11-8 11.2.8 PWM0 Counter Registers (PW0CH, PW0CL) ................................................................................. 11-9 11.2.9 PWM1 Counter Registers (PW1CH, PW1CL) ............................................................................... 11-10 11.2.10 PWM2 Counter Registers (PW2CH, PW2CL) ............................................................................... 11-11 11.2.11 PWM0 Control Register 0 (PW0CON0)......................................................................................... 11-12 11.2.12 PWM1 Control Register 0 (PW1CON0)......................................................................................... 11-13 11.2.13 PWM2 Control Register 0 (PW2CON0)......................................................................................... 11-14 11.2.14 PWM0 Control Register 1 (PW0CON1)......................................................................................... 11-15 11.2.15 PWM1 Control Register 1 (PW1CON1)......................................................................................... 11-16 11.2.16 PWM2 Control Register 1 (PW2CON1)......................................................................................... 11-17 11.3 Description of Operation......................................................................................................................... 11-18 11.4 Specifying port registers ......................................................................................................................... 11-20 11.4.1 Functioning P43 (PWM0) as the PWM0 output ............................................................................. 11-20 11.4.2 Functioning P34 (PWM0) as the PWM0 output ............................................................................. 11-21 11.4.3 Functioning P47 (PWM1) as the PWM1 output ............................................................................. 11-22 11.4.4 Functioning P35 (PWM1) as the PWM1 output ............................................................................. 11-23 11.4.5 Functioning P20 (PWM2) as the PWM2 output ............................................................................. 11-24 11.4.6 Functioning P30 (PWM2) as the PWM2 output ............................................................................. 11-25 Chapter 12 12. Watchdog Timer ........................................................................................................................................... 12-1 12.1 Overview................................................................................................................................................... 12-1 12.1.1 Features ............................................................................................................................................. 12-1 12.1.2 Configuration .................................................................................................................................... 12-1 FEUL610Q438 Contents-4 ML610Q438/ML610Q439 User’s Manual Contents 12.2 Description of Registers ............................................................................................................................ 12-2 12.2.1 List of Registers ................................................................................................................................ 12-2 12.2.2 Watchdog Timer Control Register (WDTCON) ............................................................................... 12-3 12.2.3 Watchdog Timer Mode Register (WDTMOD) ................................................................................. 12-4 12.3 Description of Operation........................................................................................................................... 12-5 Chapter 13 13. Synchronous Serial Port................................................................................................................................ 13-1 13.1 Overview................................................................................................................................................... 13-1 13.1.1 Features ............................................................................................................................................. 13-1 13.1.2 Configuration .................................................................................................................................... 13-1 13.1.3 List of Pins ........................................................................................................................................ 13-2 13.2 Description of Registers ............................................................................................................................ 13-3 13.2.1 List of Registers ................................................................................................................................ 13-3 13.2.2 Serial Port Transmit/Receive Buffers (SIO0BUFL, SIO0BUFH) .................................................... 13-4 13.2.3 Serial Port Control Register (SIO0CON) .......................................................................................... 13-5 13.2.4 Serial Port Mode Register 0 (SIO0MOD0) ....................................................................................... 13-6 13.2.5 Serial Port Mode Register 1 (SIO0MOD1) ....................................................................................... 13-7 13.3 Description of Operation........................................................................................................................... 13-8 13.3.1 Transmit Operation ........................................................................................................................... 13-8 13.3.2 Receive Operation............................................................................................................................. 13-9 13.3.3 Transmit/Receive Operation ........................................................................................................... 13-10 13.4 Specifying port registers ......................................................................................................................... 13-11 13.4.1 Functioning P42 (SOUT0), P41 (SCK0) and P40 (SIN0) as the SSIO/ “Master mode” ................ 13-11 13.4.2 Functioning P42 (SOUT0), P41 (SCK0) and P40 (SIN0) as the SSIO/ ”Slave mode”................... 13-12 13.4.3 Functioning P46 (SOUT0), P45 (SCK0) and P44 (SIN0) as the SSIO/ ”Master mode” ................ 13-13 13.4.4 Functioning P46 (SOUT0), P45 (SCK0) and P44 (SIN0) as the SSIO/ ”Slave mode”................... 13-14 13.5 About timer0/1 int clock for the transfer clock of the synchronous serial port ...................................... 13-15 Chapter 14 14. UART ........................................................................................................................................................... 14-1 14.1 Overview................................................................................................................................................... 14-1 14.1.1 Features ............................................................................................................................................. 14-1 14.1.2 Configuration .................................................................................................................................... 14-1 14.1.3 List of Pins ........................................................................................................................................ 14-1 14.2 Description of Registers ............................................................................................................................ 14-2 14.2.1 List of Registers ................................................................................................................................ 14-2 14.2.2 UART0 Transmit/Receive Buffer (UA0BUF) .................................................................................. 14-3 14.2.3 UART0 Control Register (UA0CON) .............................................................................................. 14-4 14.2.4 UART0 Mode Register 0 (UA0MOD0) ........................................................................................... 14-5 14.2.5 UART0 Mode Register 1 (UA0MOD1) ........................................................................................... 14-6 14.2.6 UART0 Baud Rate Registers L, H (UA0BRTL, UA0BRTH) .......................................................... 14-8 14.2.7 UART0 Status Register (UA0STAT) ............................................................................................... 14-9 14.3 Description of Operation......................................................................................................................... 14-11 14.3.1 Transfer Data Format ...................................................................................................................... 14-11 14.3.2 Baud Rate ........................................................................................................................................ 14-12 14.3.3 Transmit Data Direction ................................................................................................................. 14-13 14.3.4 Transmit Operation ......................................................................................................................... 14-14 14.3.5 Receive Operation........................................................................................................................... 14-16 14.4 Specifying port registers ......................................................................................................................... 14-18 14.4.1 Functioning P43(TXD0) and P42(RXD0) as the UART ................................................................ 14-18 14.4.2 Functioning P43(TXD0) and P02(RXD0) as the UART ................................................................ 14-19 Chapter 15 15. I2C Bus Interface ........................................................................................................................................... 15-1 15.1 Overview................................................................................................................................................... 15-1 15.1.1 Features ............................................................................................................................................. 15-1 FEUL610Q438 Contents-5 ML610Q438/ML610Q439 User’s Manual Contents 15.1.2 Configuration .................................................................................................................................... 15-1 15.1.3 List of Pins ........................................................................................................................................ 15-1 15.2 Description of Registers ............................................................................................................................ 15-2 15.2.1 List of Registers ................................................................................................................................ 15-2 15.2.2 I2C Bus 0 Receive Register (I2C0RD) .............................................................................................. 15-3 15.2.3 I2C Bus 0 Slave Address Register (I2C0SA) .................................................................................... 15-4 15.2.4 I2C Bus 0 Transmit Data Register (I2C0TD) .................................................................................... 15-5 15.2.5 I2C Bus 0 Control Register (I2C0CON)............................................................................................ 15-6 15.2.6 I2C Bus 0 Mode Register (I2C0MOD).............................................................................................. 15-7 15.2.7 I2C Bus 0 Status Register (I2C0STAT) ............................................................................................ 15-8 15.3 Description of Operation........................................................................................................................... 15-9 15.3.1 Communication Operating Mode...................................................................................................... 15-9 15.3.1.1 Start Condition............................................................................................................................... 15-9 15.3.1.2 Repeated Condition ....................................................................................................................... 15-9 15.3.1.3 Slave Address Transmit Mode....................................................................................................... 15-9 15.3.1.4 Data Transmit Mode ...................................................................................................................... 15-9 15.3.1.5 Data Receive Mode ....................................................................................................................... 15-9 15.3.1.6 Control Register Setting Wait State ............................................................................................... 15-9 15.3.1.7 Stop Condition ............................................................................................................................... 15-9 15.3.2 Communication Operation Timing ................................................................................................. 15-10 15.3.3 Operation Waveforms ..................................................................................................................... 15-12 15.4 Specifying port registers ........................................................................................................................ 15-13 15.4.1 Functioning P41(SCL) and P40(SDA) as the I2C .......................................................................... 15-13 Chapter 16 16. NMI Pin ........................................................................................................................................................ 16-1 16.1 Overview................................................................................................................................................... 16-1 16.1.1 Features ............................................................................................................................................. 16-1 16.1.2 Configuration .................................................................................................................................... 16-1 16.1.3 List of Pins ........................................................................................................................................ 16-1 16.2 Description of Registers ............................................................................................................................ 16-2 16.2.1 List of Registers ................................................................................................................................ 16-2 16.2.2 NMI Data Register (NMID) .............................................................................................................. 16-3 16.2.3 NMI Control Register (NMICON).................................................................................................... 16-4 16.3 Description of Operation........................................................................................................................... 16-5 16.3.1 Interrupt Request ............................................................................................................................... 16-5 Chapter 17 17. Port 0............................................................................................................................................................. 17-1 17.1 Overview................................................................................................................................................... 17-1 17.1.1 Features ............................................................................................................................................. 17-1 17.1.2 Configuration .................................................................................................................................... 17-1 17.1.3 List of Pins ........................................................................................................................................ 17-2 17.2 Description of Registers ............................................................................................................................ 17-3 17.2.1 List of Registers ................................................................................................................................ 17-3 17.2.2 Port 0 Data Register (P0D) ............................................................................................................... 17-4 17.2.3 Port 0 Control Registers 0, 1 (P0CON0, P0CON1) .......................................................................... 17-5 17.2.4 External Interrupt Control Registers 0, 1 (EXICON0, EXICON1)................................................... 17-6 17.2.5 External Interrupt Control Register 2 (EXICON2) ........................................................................... 17-7 17.3 Description of Operation........................................................................................................................... 17-9 17.3.1 External Interrupt .............................................................................................................................. 17-9 17.3.2 Interrupt Request ............................................................................................................................... 17-9 Chapter 18 18. Port 1............................................................................................................................................................. 18-1 18.1 Overview................................................................................................................................................... 18-1 18.1.1 Features ............................................................................................................................................. 18-1 FEUL610Q438 Contents-6 ML610Q438/ML610Q439 User’s Manual Contents 18.1.2 Configuration .................................................................................................................................... 18-1 18.1.3 List of Pins ........................................................................................................................................ 18-1 18.2 Description of Registers ............................................................................................................................ 18-2 18.2.1 List of Registers ................................................................................................................................ 18-2 18.2.2 Port 1 Data Register (P1D) ............................................................................................................... 18-3 18.2.3 Port 1 Control Registers 0, 1 (P1CON0, P1CON1) .......................................................................... 18-4 18.3 Description of Operation........................................................................................................................... 18-5 18.3.1 Input Port Function ........................................................................................................................... 18-5 18.3.2 Secondary Function .......................................................................................................................... 18-5 Chapter 19 19. Port 2............................................................................................................................................................. 19-1 19.1 Overview................................................................................................................................................... 19-1 19.1.1 Features ............................................................................................................................................. 19-1 19.1.2 Configuration .................................................................................................................................... 19-1 19.1.3 List of Pins ........................................................................................................................................ 19-1 19.2 Description of Registers ............................................................................................................................ 19-2 19.2.1 List of Registers ................................................................................................................................ 19-2 19.2.2 Port 2 Data Register (P2D) ............................................................................................................... 19-3 19.2.3 Port 2 control registers 0, 1 (P2CON0, P2CON1) ............................................................................ 19-4 19.2.4 Port 2 Mode Register , Port 2 Mode Register1 (P2MOD0, P2MOD1 ) ............................................ 19-5 19.2.5 Port 2 Mode Register 2 (P2MOD2) .................................................................................................. 19-6 19.3 Description of Operation........................................................................................................................... 19-8 19.3.1 Output Port Function......................................................................................................................... 19-8 19.3.2 Secondary and Tertiary Function ...................................................................................................... 19-8 Chapter 20 20. Port 3............................................................................................................................................................. 20-1 20.1 Overview................................................................................................................................................... 20-1 20.1.1 Features ............................................................................................................................................. 20-1 20.1.2 Configuration .................................................................................................................................... 20-1 20.1.3 List of Pins ........................................................................................................................................ 20-2 20.2 Description of Registers ............................................................................................................................ 20-3 20.2.1 List of Registers ................................................................................................................................ 20-3 20.2.2 Port 3 data register (P3D).................................................................................................................. 20-4 20.2.3 Port 3 Direction Register (P3DIR) .................................................................................................... 20-5 20.2.4 Port 3 control registers 0, 1 (P3CON0, P3CON1) ............................................................................ 20-6 20.2.5 Port 3 mode registers 0, 1 (P3MOD0, P3MOD1) ............................................................................. 20-8 20.3 Description of Operation......................................................................................................................... 20-10 20.3.1 Input/Output Port Functions............................................................................................................ 20-10 20.3.2 Secondary and Tertiary Functions .................................................................................................. 20-10 Chapter 21 21. Port 4............................................................................................................................................................. 21-1 21.1 Overview................................................................................................................................................... 21-1 21.1.1 Features ............................................................................................................................................. 21-1 21.1.2 Configuration .................................................................................................................................... 21-1 21.1.3 List of Pins ........................................................................................................................................ 21-2 21.2 Description of Registers ............................................................................................................................ 21-3 21.2.1 List of Registers ................................................................................................................................ 21-3 21.2.2 Port 4 Data Register (P4D) ............................................................................................................... 21-4 21.2.3 Port 4 Direction Register (P4DIR) .................................................................................................... 21-5 21.2.4 Port 4 Control Registers 0, 1 (P4CON0, P4CON1) .......................................................................... 21-6 21.2.5 Port 4 Mode Registers 0, 1 (P4MOD0, P4MOD1) ........................................................................... 21-8 21.3 Description of Operation......................................................................................................................... 21-11 21.3.1 Input/Output Port Functions............................................................................................................ 21-11 21.3.2 Secondary and Tertiary Functions .................................................................................................. 21-11 FEUL610Q438 Contents-7 ML610Q438/ML610Q439 User’s Manual Contents Chapter 22 22. Port A ............................................................................................................................................................ 22-1 22.1 Overview................................................................................................................................................... 22-1 22.1.1 Features ............................................................................................................................................. 22-1 22.1.2 Configuration .................................................................................................................................... 22-1 22.1.3 List of Pins ........................................................................................................................................ 22-1 22.2 Description of Registers ............................................................................................................................ 22-2 22.2.1 List of Registers ................................................................................................................................ 22-2 22.2.2 Port A Data Register (PAD).............................................................................................................. 22-3 22.2.3 Port A Direction Register (PADIR) .................................................................................................. 22-4 22.2.4 Port A Control Registers 0, 1 (PACON0, PACON1) ....................................................................... 22-5 22.3 Description of Operation........................................................................................................................... 22-7 22.3.1 Input/Output Port Functions.............................................................................................................. 22-7 Chapter 23 23. Melody Driver .............................................................................................................................................. 23-1 23.1 Overview................................................................................................................................................... 23-1 23.1.1 Features ............................................................................................................................................. 23-1 23.1.2 Configuration .................................................................................................................................... 23-1 23.1.3 List of Pins ........................................................................................................................................ 23-1 23.2 Description of Registers ............................................................................................................................ 23-2 23.2.1 List of Registers ................................................................................................................................ 23-2 23.2.2 Melody 0 Control Register (MD0CON) ........................................................................................... 23-3 23.2.3 Melody 0 Tempo Code Register (MD0TMP) ................................................................................... 23-4 23.2.4 Melody 0 Scale Code Register (MD0TON)...................................................................................... 23-5 23.2.5 Melody 0 Tone Length Code Register (MD0LEN) .......................................................................... 23-6 23.3 Description of Operation........................................................................................................................... 23-7 23.3.1 Operation of Melody Output ............................................................................................................. 23-7 23.3.2 Tempo Codes .................................................................................................................................... 23-8 23.3.3 Tone Length Codes ........................................................................................................................... 23-9 23.3.4 Scale Codes ..................................................................................................................................... 23-10 23.3.5 Example of Using Melody Circuit .................................................................................................. 23-11 23.3.6 Operations of Buzzer Output .......................................................................................................... 23-12 23.4 Specifying port registers ......................................................................................................................... 23-13 23.4.1 Functioning P22 (MD0) as the Melody or Buzzer output ............................................................... 23-13 Chapter 24 24. RC Oscillation Type A/D Converter ............................................................................................................. 24-1 24.1 Overview................................................................................................................................................... 24-1 24.1.1 Features ............................................................................................................................................. 24-1 24.1.2 Configuration .................................................................................................................................... 24-1 24.1.3 List of Pins ........................................................................................................................................ 24-2 24.2 Description of Registers ............................................................................................................................ 24-3 24.2.1 List of Registers ................................................................................................................................ 24-3 24.2.2 RC-ADC Counter A Registers (RADCA0–2) .................................................................................. 24-4 24.2.3 RC-ADC Counter B Registers (RADCB0–2) ................................................................................... 24-5 24.2.4 RC-ADC Mode Register (RADMOD).............................................................................................. 24-6 24.2.5 RC-ADC Control Register (RADCON)............................................................................................ 24-7 24.3 Description of Operation........................................................................................................................... 24-8 24.3.1 RC Oscillator Circuits ....................................................................................................................... 24-8 24.3.2 Counter A/Counter B Reference Modes ......................................................................................... 24-11 24.3.3 Example of Use of RC Oscillation Type A/D Converter ................................................................ 24-15 24.3.4 Monitoring RC Oscillation.............................................................................................................. 24-20 24.4 Specifying port registers ......................................................................................................................... 24-21 24.4.1 Functioning P35(RCM), P34(RCT0), P33(RT0), P32(RS0), P31(CS0) and P30(IN0) as the RC-ADC(Ch0) ................................................................................................................................ 24-21 FEUL610Q438 Contents-8 ML610Q438/ML610Q439 User’s Manual Contents 24.4.2 Functioning P47(RT1), P46(RS1), P45(CS1) and P44(IN1) as the RC-ADC(Ch1) ....................... 24-22 Chapter 25 25. Successive Approximation Type A/D Converter .......................................................................................... 25-1 25.1 Overview................................................................................................................................................... 25-1 25.1.1 Features ............................................................................................................................................. 25-1 25.1.2 Configuration .................................................................................................................................... 25-1 25.1.3 List of Pins ........................................................................................................................................ 25-2 25.2 Description of Registers ............................................................................................................................ 25-3 25.2.1 List of Registers ................................................................................................................................ 25-3 25.2.2 SA-ADC Result Register 0L (SADR0L) .......................................................................................... 25-4 25.2.3 SA-ADC Result Register 0H (SADR0H) ......................................................................................... 25-4 25.2.4 SA-ADC Result Register 1L (SADR1L) .......................................................................................... 25-5 25.2.5 SA-ADC Result Register 1H (SADR1H) ......................................................................................... 25-5 25.2.6 SA-ADC Control Register 0 (SADCON0) ....................................................................................... 25-6 25.2.7 SA-ADC Control Register 1 (SADCON1) ....................................................................................... 25-7 25.2.8 SA-ADC Mode Register 0 (SADMOD0) ......................................................................................... 25-8 25.2.9 Amplifier Offset Register (AMPOFFS) ............................................................................................ 25-9 25.2.10 Amplifier Gain Register (AMPGAIN)............................................................................................ 25-10 25.2.11 Amplifier Control Register 0 (AMPCON0) .................................................................................... 25-11 25.3 Description of Operation......................................................................................................................... 25-13 25.3.1 Analog Input Settings ..................................................................................................................... 25-13 25.3.2 Settings of A/D Conversion Channels .............................................................................................. 25-15 25.3.3 Operation of the Successive Approximation A/D Converter in Direct Input.................................. 25-16 25.3.4 Operation of the Successive Approximation A/D Converter in Amplification Input ..................... 25-17 25.3.5 Operation of the Successive Approximation A/D Converter in Differential Amplification Input .. 25-18 Chapter 26 26. LCD Drivers ................................................................................................................................................. 26-1 26.1 Overview................................................................................................................................................... 26-1 26.1.1 Features ............................................................................................................................................. 26-3 26.1.2 Configuration of the LCD Drivers .................................................................................................... 26-4 26.1.3 Configuration of the Bias Generation Circuit ................................................................................... 26-5 26.1.4 List of Pins ........................................................................................................................................ 26-6 26.2 Description of Registers ............................................................................................................................ 26-9 26.2.1 List of Registers ................................................................................................................................ 26-9 26.2.2 Bias Circuit Control Register 0 (BIASCON) .................................................................................. 26-10 26.2.3 Display Control Register (DSPCNT) .............................................................................................. 26-11 26.2.4 Display Mode Register 0 (DSPMOD0) .......................................................................................... 26-12 26.2.5 Display Mode Register 1 (DSPMOD1) .......................................................................................... 26-14 26.2.6 Display Control Register (DSPCON) ............................................................................................. 26-15 26.2.7 Display Allocation Register A (DS0C0A to DS63C7A) ................................................................ 26-16 26.2.8 Display Allocation Register B (DS0C0B to DS63C7B) ................................................................. 26-18 26.2.9 Display Registers (DSPR00 to DSPRFE) ....................................................................................... 26-20 26.2.10 Segout Data Registers 0 (SEGOUT0) ............................................................................................. 26-35 26.2.11 Segout Data Registers 1 (SEGOUT1) ............................................................................................. 26-36 26.2.12 Segout Data Registers 2 (SEGOUT2) ............................................................................................. 26-37 26.2.13 Segout Data Registers 3 (SEGOUT3) ............................................................................................. 26-38 26.3 Description of Operation......................................................................................................................... 26-39 26.3.1 Operation of LCD Drivers and Bias Generation Circuit ................................................................. 26-39 26.3.2 Segment Mapping When the Programmable Display Allocation Function is Not Used ................ 26-40 26.3.3 Segment Mapping When the Programmable Display Allocation Function is Used ....................... 26-41 26.3.4 Common Output Waveforms .......................................................................................................... 26-43 26.3.5 Segment Output Waveform ............................................................................................................ 26-45 Chapter 27 27. Battery Level Detector .................................................................................................................................. 27-1 FEUL610Q438 Contents-9 ML610Q438/ML610Q439 User’s Manual Contents 27.1 Overview................................................................................................................................................... 27-1 27.1.1 Features ............................................................................................................................................. 27-1 27.1.2 Configuration .................................................................................................................................... 27-1 27.2 Description of Registers ............................................................................................................................ 27-2 27.2.1 List of Registers ................................................................................................................................ 27-2 27.2.2 Battery Level Detector Control Register 0 (BLDCON0) .................................................................. 27-3 27.2.3 Battery Level Detector Control Register 1 (BLDCON1) .................................................................. 27-4 27.3 Description of Operation........................................................................................................................... 27-5 27.3.1 Threshold Voltage ............................................................................................................................. 27-5 27.3.2 Operation of Battery Level Detector ................................................................................................. 27-6 Chapter 28 28. Power Supply Circuit .................................................................................................................................... 28-1 28.1 Overview................................................................................................................................................... 28-1 28.1.1 Features ............................................................................................................................................. 28-1 28.1.2 Configuration .................................................................................................................................... 28-1 28.1.3 List of Pins ........................................................................................................................................ 28-1 28.2 Description of Operation........................................................................................................................... 28-2 Chapter 29 29. On-Chip Debug Function .............................................................................................................................. 29-1 29.1 Overview................................................................................................................................................... 29-1 29.2 Method of Connecting to On-Chip Debug Emulator ................................................................................ 29-1 29.3 Flash Memory Rewrite Function .............................................................................................................. 29-2 Appendixes Appendix A Appendix B Appendix C Appendix D Appendix E Registers ......................................................................................................................................... A-1 Package Dimensions ........................................................................................................................B-1 Electrical Characteristics .................................................................................................................C-1 Application Circuit Example .......................................................................................................... D-1 Check List ........................................................................................................................................ E-1 Revision History Revision History .....................................................................................................................................................R-1 FEUL610Q438 Contents-10 Chapter 1 Overview ML610Q438/ML610Q439 User’s Manual Chapter 1 Overview 1. Overview 1.1 Features This LSI is a high-performance 8-bit CMOS microcontroller into which rich peripheral circuits, such as synchronous serial port, UART, I2C bus interface (master), melody driver, battery level detect circuit, RC oscillation type A/D converter, and LCD driver, are incorporated around 8-bit CPU nX-U8/100. The CPU nX-U8/100 is capable of efficient instruction execution in 1-instruction 1-clock mode by 3-stage pipe line architecture parallel procesing. The Flash ROM that is installed as program memory achieves low-voltage low-power consumption operation (read operation) equivalent to mask ROM and is most suitable for battery-driven applications. The on-chip debug function that is installed enables program debugging and programming. • CPU − 8-bit RISC CPU (CPU name: nX-U8/100) − Instruction system: 16-bit instructions − Instruction set: Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on − On-Chip debug function − Minimum instruction execution time 30.5 µs (@32.768 kHz system clock) 0.24 4µs (@4.096 MHz system clock) • Internal memory − Internal 128KByte Flash ROM (64K×16 bits) (including unusable 1KByte TEST area) − Internal 6KByte Data RAM (6144×8 bits), 1KByte Display Allocation RAM (1024 x 8bit) − Internal 192-byte RAM for display • Interrupt controller − 2 non-maskable interrupt sources (Internal source: 1, External source: 1) − 27 maskable interrupt sources (Internal sources: 19, External sources: 8) • Time base counter − Low-speed time base counter ×1 channel Frequency compensation (Compensation range: Approx. −488ppm to +488ppm. Compensation accuracy: Approx. 0.48ppm) − High-speed time base counter ×1 channel • Watchdog timer − Non-maskable interrupt and reset − Free running − Overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s) • Timers − 8 bits × 4 channels (16-bit configuration available) • 1 kHz timer − 10 Hz/1 Hz interrupt function FEUL610Q438 1-1 ML610Q438/ML610Q439 User’s Manual Chapter 1 Overview • Capture − Time base capture × 2 channels (4096 Hz to 32 Hz) • PWM − Resolution 16 bits × 3 channel • Synchronous serial port − Master/slave selectable − LSB first/MSB first selectable − 8-bit length/16-bit length selectable − Timer interrupt is used as a serial clock and selection is possible • UART − TXD/RXD × 1 channel − Bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits − Positive logic/negative logic selectable − Built-in baud rate generator • I2C bus interface − Master function only − Fast mode (400 kbps@4MHｚ), standard mode (100 kbps@4MHｚ, 50kbps@500kHz) • Melody driver − Scale: 29 types (Melody sound frequency: 508 Hz to 32.768 kHz) − Tone length: 63 types − Tempo: 15 types − Buzzer output mode (4 output modes, 8 frequencies, 16 duty levels) • RC oscillation type A/D converter − 24-bit counter − Time division × 2 channels • Successive approximation type A/D converter − 12-bit A/D converter − Input × 2 channels • General-purpose ports − Non-maskable interrupt input port × 1 channel − Input-only port × 10 channels (including secondary functions) − Output-only port × 3 channels (including secondary functions) − Input/output port 20 channels (including secondary functions) FEUL610Q438 1-2 ML610Q438/ML610Q439 User’s Manual Chapter 1 Overview • LCD driver − Dot matrix can be supported. ML610Q438: 1344 dots max. (56 seg × 24 com) ML610Q439: 1024 dots max. (64 seg × 16 com) − 1/1 to 1/24 duty − 1/3 or 1/4 bias (built-in bias generation circuit) − Frame frequency selecable (approx. 64 Hz, 73 Hz, 85 Hz, and 102 Hz) − Bias voltage multiplying clock selectable (8 types) − Contrast adjustment (1/3 bias: 32 steps, 1/4 bias: 20 steps) − LCD drive stop mode, LCD display mode, all LCDs on mode, and all LCDs off mode selectable − Programmable display allocation function (available only when 1/1~1/8 duty is selected) • Reset − Reset through the RESET_N pin − Power-on reset generation when powered on − Reset when oscillation stop of the low-speed clock is detected − Reset by the watchdog timer (WDT) overflow • Power supply voltage detect function − Judgment voltages: One of 16 levels − Judgment accuracy: ±2% (Typ.) • Clock − Low-speed clock: (This LSI can not guarantee the operation withoug low-speed clock) Crystal oscillation (32.768 kHz) − High-speed clock: Built-in RC oscillation (2M/500kHz) Built-in PLL oscillation (8.192 MHz ±2.5%), crystal/ceramic oscillation (4.096 MHz), external clock − Selection of high-speed clock mode by software: Built-in RC oscillation, built-in PLL oscillation, crystal/ceramic oscillation, external clock • Power management − HALT mode: Instruction execution by CPU is suspended (peripheral circuits are in operating states). − STOP mode: Stop of low-speed oscillation and high-speed oscillation (Operations of CPU and peripheral circuits are stopped.) − Clock gear: The frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, or 1/8 of the oscillation clock) − Block Control Function: Power down (reset registers and stop clock supply) the circuits of unused peripherals. • Guaranteed operating range − Operating temperature: −20°C to +70°C (non-P version) −40°C to +85°C (P version) − Operating voltage: VDD = 1.1V to 3.6V, AVDD = 2.2V to 3.6V FEUL610Q438 1-3 ML610Q438/ML610Q439 User’s Manual Chapter 1 Overview • Product name – Supported Function The line-up of the ML610Q438 and ML610Q439 is below. ROM type Operating temperature Product availability ML610Q438-xxxWA Flash ROM -20°C to +70°C Yes ML610Q439-xxxWA Flash ROM -20°C to +70°C Yes ROM type Operating temperature Product availability ML610Q438-xxxTC Flash ROM -20°C to +70°C Yes ML610Q439P-xxxTC Flash ROM -40°C to +85°C Yes - Chip (Die) - -144-pin plastic LQFP - xxx: ROM code number (xxx of the blank product is NNN) Q:Flash ROM version P: Wide range temperature version WA: Chip TC: LQFP FEUL610Q438 1-4 ML610Q438/ML610Q439 User’s Manual Chapter 1 Overview 1.2 Configuration of Functional Blocks 1.2.1 Block Diagram of ML610Q438 CPU (nX-U8/100) EPSW1～3 GREG 0～15 PSW Timing Controller On-Chip ICE TEST ECSR1～3 LR DSR/CSR EA PC ALU SP Instruction Decoder Instruction Register Data-bus VDD VSS RESET_N ELR1～3 RESET & TEST XT0 XT1 INT 1 OSC VDDL VDDX I UART RXD0* TXD0* INT 1 TBC PWM ×3 Capture ×2 INT 4 RC-ADC ×2 1kHzTC 8bit Timer ×4 SDA* SCL* INT 3 PWM0* to PWM2* INT 1 Melody INT 1 INT 5 MD0* NMI P00 to P03 P10 to P11 GPIO P20 to P22 P30 to P35 P40 to P47 AVDD AVSS INT 1 Display Allocation RAM 1KByte 12bit-ADC AIN0, AIN1 Display RAM 192Byte BLD Figure 1-1 FEUL610Q438 SCK0* SIN0* SOUT0* INT 1 INT Power VREF WDT VPP SSIO I2C INT 4 LSCLK* OUTCLK* IN0* CS0* RS0* RT0* CRT0* RCM* IN1* CS1* RS1* RT1* INT 1 RAM 6144byte Interrupt Controller OSC0* OSC1* Program Memory (Flash) 128Kbyte BUS Controller LCD Driver COM0 to COM23 LCD BIAS VL1, VL2, VL3, VL4 SEG0 to SEG55 C1, C2, C3, C4 Block Diagram of ML610Q438 1-5 ML610Q438/ML610Q439 User’s Manual Chapter 1 Overview 1.2.2 Block Diagram of ML610Q439 CPU (nX-U8/100) EPSW1～3 GREG 0～15 PSW Timing Controller On-Chip ICE TEST ECSR1～3 LR DSR/CSR EA PC ALU SP Instruction Decoder Instruction Register Data-bus VDD VSS RESET_N ELR1～3 RESET & TEST XT0 XT1 INT 1 OSC INT 4 VDDL VDDX INT 1 Power SCK0* SIN0* SOUT0* UART RXD0* TXD0* INT 1 INT 1 1kHzTC 8bit Timer ×4 PWM0* to PWM2* INT 1 INT 5 MD0* NMI P00 to P03 P10 to P11 GPIO P20 to P22 P30 to P35 P40 to P47 INT 1 Display Allocation RAM 1KByte 12bit-ADC AIN0, AIN1 LCD Driver COM0 to COM15 LCD BIAS VL1, VL2, VL3, VL4 Display RAM 192Byte BLD Figure 1-2 FEUL610Q438 SDA* SCL* INT 3 PWM ×3 Capture ×2 INT 4 RC-ADC ×2 TBC Melody INT 1 AVDD AVSS VREF WDT VPP SSIO I2C LSCLK* OUTCLK* IN0* CS0* RS0* RT0* CRT0* RCM* IN1* CS1* RS1* RT1* INT 1 RAM 6144byte Interrupt Controller OSC0* OSC1* Program Memory (Flash) 128Kbyte BUS Controller SEG0 to SEG63 C1, C2, C3, C4 Block Diagram of ML610Q439 1-6 ML610Q438/ML610Q439 User’s Manual Chapter 1 Overview 1.3 Pins 1.3.1 Pin Layout 108pin 109pin VREF AVSS VSS P20 P21 P22 P40 P41 VPP RESET_N P44 P45 P46 P47 P30 P31 P34 P32 P33 P35 TEST VDD VDDL VSS VDDX XT0 (NC) XT1 P42 P43 VL1 VL2 VL3 VL4 C1 C2 L610Q438 73pin 72pin 7 7 7 6 68 67 66 65 64 63 62 61 6 5 58 57 56 55 54 53 52 51 5 4 4 4 4 4 4 4 4 4 4 3 3 3 144pin 1pin C3 C4 P00/EXI0 P01/EXI1 P02/EXI2 P03/EXI3 NMI VSS P10 (NC) P11 VDD COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 109 11 11 11 11 11 11 11 11 11 11 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 AVDD (NC) AIN1 AIN0 VSS P07 P06 P05 P04 PA5 PA4 PA3 PA2 PA1 PA0 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 SEG55 SEG54 SEG53 SEG52 SEG51 1.3.1.1 Pin Layout of ML610Q438 LQFP Package SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 (NC) SEG16 37pin 36pin (NC): No Connection Figure 1-3 FEUL610Q438 Pin Layout of ML610Q438 Package 1-7 ML610Q438/ML610Q439 User’s Manual Chapter 1 Overview 108pin 109pin VREF AVSS VSS P20 P21 P22 P40 P41 VPP RESET_N P44 P45 P46 P47 P30 P31 P34 P32 P33 P35 TEST VDD VDDL VSS VDDX XT0 (NC) XT1 P42 P43 VL1 VL2 VL3 VL4 C1 C2 L610Q439P 73pin 72pin 7 7 7 6 68 67 66 65 64 63 62 61 6 5 58 57 56 55 54 53 52 51 5 4 4 4 4 4 4 4 4 4 4 3 3 3 144pin 1pin C3 C4 P00/EXI0 P01/EXI1 P02/EXI2 P03/EXI3 NMI VSS P10 (NC) P11 VDD COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 109 11 11 11 11 11 11 11 11 11 11 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 AVDD (NC) AIN1 AIN0 VSS P07 P06 P05 P04 PA5 PA4 PA3 PA2 PA1 PA0 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 1.3.1.2 Pin Layout of ML610Q439P LQFP Package SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 (NC) SEG16 37pin 36pin (NC): No Connection Figure 1-4 FEUL610Q438 Pin Layout of ML610Q439P Package 1-8 ML610Q438/ML610Q439 User’s Manual Chapter 1 Overview AVDD AIN1 AIN0 VSS P07 P06 P05 P04 PA5 PA4 PA3 PA2 PA1 PA0 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 SEG55 SEG54 SEG53 SEG52 SEG51 83 82 81 80 79 78 77 76 75 74 73 72 71 □□□□□□□□□□□□□□□□□□□□□□ □□□□□□□□ □□□□□ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 3.46m □□□□□□□□□□□□□□□□□□□□□□□□ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 □□ 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 □□□□□□□□□ P11 10 VDD 11 □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ 1 2 3 4 5 6 7 8 9 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 C3 C4 P00/EXI P01/EXI P02/EXI P03/EXI NMI VSS P10 VREF AVSS VSS P20 P21 P22 P40 P41 VPP RESET_N P44 P45 P46 P47 P30 P31 P34 P32 P33 P35 TEST VDD VDDL VSS VDDX XT0 XT1 P42 P43 VL1 VL2 VL3 VL4 C1 C2 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 1.3.1.3 Pin Layout of ML610Q438 Chip 3.51mm Chip size: PAD count: Minimum PAD pitch: PAD aperture: Chip thickness: Voltage of the rear side of chip: Figure 1-5 FEUL610Q438 TBD mm × TBD mm 138 pins 80 µm 70 µm × 70 µm 350 µm VSS level Dimensions of ML610Q438 Chip 1-9 ML610Q438/ML610Q439 User’s Manual Chapter 1 Overview AVDD AIN1 AIN0 VSS P07 P06 P05 P04 PA5 PA4 PA3 PA2 PA1 PA0 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 83 82 81 80 79 78 77 76 75 74 73 72 71 □□□□□□□□□□□□□□□□□□□□□□ □□□□□□□□ □□□□□ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 3.46mm □□□□□□□□□□□□□□□□□□□□□□□□ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 □□ 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 □□□□□□□□□ P11 10 VDD 11 □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ □ 1 2 3 4 5 6 7 8 9 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 C3 C4 P00/EXI P01/EXI P02/EXI P03/EXI NMI VSS P10 VREF AVSS VSS P20 P21 P22 P40 P41 VPP RESET_N P44 P45 P46 P47 P30 P31 P34 P32 P33 P35 TEST VDD VDDL VSS VDDX XT0 XT1 P42 P43 VL1 VL2 VL3 VL4 C1 C2 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 1.3.1.4 Pin Layout of ML610Q439 Chip 3.51mm Chip size: PAD count: Minimum PAD pitch: PAD aperture: Chip thickness: Voltage of the rear side of chip: Figure 1-6 FEUL610Q438 TBD mm × TBD mm 138 pins 80 µm 70 µm × 70 µm 350 µm VSS level Dimensions of ML610Q439 Chip 1-10 ML610Q438/ML610Q439 User’s Manual Chapter 1 Overview 1.3.1.5 Pad Coordinates of ML610Q438 Chip Table 1-1 Pad Coordinates of ML610Q438 Chip Center: X=0,Y=0 PAD No. 1 Pad Name C3 X (μm) -1485 Y (μm) -1624 PAD No. 48 Pad Name SEG28 X (μm) 1649 Y (μm) -400 PAD No. 95 Pad Name PA3 X (μm) -525 Y (μm) 1624 2 C4 -1405 -1624 49 SEG29 1649 -320 96 PA4 -605 1624 3 P00/EXI0 -1315 -1624 50 SEG30 1649 -240 97 PA5 -685 1624 4 P01/EXI1 -1235 -1624 51 SEG31 1649 -160 98 P04 -765 1624 -1155 -1624 52 SEG32 1649 -80 99 P05 -845 1624 6 P02/EXI2 /RXD0/P2 CK P03/EXI3 -1075 -1624 53 SEG33 1649 0 100 P06 -925 1624 7 NMI -995 -1624 54 SEG34 1649 80 101 P07 -1005 1624 8 VSS -865 -1624 55 SEG35 1649 160 102 VSS -1106 1624 9 P10 -785 -1624 56 SEG36 1649 240 103 AIN0 -1186 1624 10 P11 -625 -1624 57 SEG37 1649 320 104 AIN1 -1366 1624 11 VDD -545 -1624 58 SEG38 1649 400 105 AVDD -1446 1624 12 COM0 -445 -1624 59 SEG39 1649 480 106 VREF -1649 1430 13 COM1 -365 -1624 60 SEG40 1649 560 107 AVSS -1649 1270 14 COM2 -285 -1624 61 SEG41 1649 640 108 VSS -1649 1190 15 COM3 -205 -1624 62 SEG42 1649 720 109 P20 -1649 1095 16 COM4 -125 -1624 63 SEG43 1649 800 110 P21 -1649 1015 17 COM5 -45 -1624 64 SEG44 1649 880 111 P22 -1649 935 18 COM6 35 -1624 65 SEG45 1649 960 112 P40 -1649 855 19 COM7 115 -1624 66 SEG46 1649 1040 113 P41 -1649 775 20 SEG0 235 -1624 67 SEG47 1649 1120 114 VPP -1649 695 21 SEG1 315 -1624 68 SEG48 1649 1200 115 RESET_N -1649 615 22 SEG2 395 -1624 69 SEG49 1649 1280 116 P44 -1649 535 23 SEG3 475 -1624 70 SEG50 1649 1360 117 P45 -1649 455 24 SEG4 555 -1624 71 SEG51 1515 1624 118 P46 -1649 375 25 SEG5 635 -1624 72 SEG52 1435 1624 119 P47 -1649 295 26 SEG6 715 -1624 73 SEG53 1355 1624 120 P30 -1649 215 27 SEG7 795 -1624 74 SEG54 1275 1624 121 P31 -1649 135 28 SEG8 875 -1624 75 SEG55 1195 1624 122 P34 -1649 55 29 SEG9 955 -1624 76 COM23 1095 1624 123 P32 -1649 -25 30 SEG10 1035 -1624 77 COM22 1015 1624 124 P33 -1649 -105 31 SEG11 1115 -1624 78 COM21 935 1624 125 P35 -1649 -185 32 SEG12 1195 -1624 79 COM20 855 1624 126 TEST -1649 -265 33 SEG13 1275 -1624 80 COM19 775 1624 127 VDD -1649 -345 34 SEG14 1355 -1624 81 COM18 695 1624 128 VDDL -1649 -425 35 SEG15 1435 -1624 82 COM17 615 1624 129 VSS -1649 -505 36 SEG16 1649 -1360 83 COM16 535 1624 130 VDDX -1649 -585 37 SEG17 1649 -1280 84 COM15 375 1624 131 XT0 -1649 -665 38 SEG18 1649 -1200 85 COM14 295 1624 132 XT1 -1649 -825 39 SEG19 1649 -1120 86 COM13 215 1624 133 P42 -1649 -905 40 SEG20 1649 -1040 87 COM12 135 1624 134 P43 -1649 -985 41 SEG21 1649 -960 88 COM11 55 1624 135 VL1 -1649 -1080 42 SEG22 1649 -880 89 COM10 -25 1624 136 VL2 -1649 -1160 43 SEG23 1649 -800 90 COM9 -105 1624 137 VL3 -1649 -1240 44 SEG24 1649 -720 91 COM8 -185 1624 138 VL4 -1649 -1320 45 SEG25 1649 -640 92 PA0 -285 1624 139 C1 -1649 -1400 46 SEG26 1649 -560 93 PA1 -365 1624 140 C2 -1649 -1480 47 SEG27 1649 -480 94 PA2 -445 1624 5 FEUL610Q438 1-11 ML610Q438/ML610Q439 User’s Manual Chapter 1 Overview 1.3.1.6 Pad Coordinates of ML610Q439 Chip Table 1-2 PAD No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 Pad Name C3 C4 P00/EXI0 P01/EXI1 P02/EXI2 /RXD0/P2 CK P03/EXI3 NMI VSS P10 P11 VDD COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 FEUL610Q438 Pad Coordinates of ML610Q439 Chip Center: X=0,Y=0 Pad X Y Name (μm) (μm) PA3 -525 1624 PA4 -605 1624 PA5 -685 1624 P04 -765 1624 X (μm) -1485 -1405 -1315 -1235 Y (μm) -1624 -1624 -1624 -1624 PAD No. 48 49 50 51 Pad Name SEG28 SEG29 SEG30 SEG31 X (μm) 1649 1649 1649 1649 Y (μm) -400 -320 -240 -160 PAD No. 95 96 97 98 -1155 -1624 52 SEG32 1649 -80 99 P05 -845 1624 -1075 -995 -865 -785 -625 -545 -445 -365 -285 -205 -125 -45 35 115 235 315 395 475 555 635 715 795 875 955 1035 1115 1195 1275 1355 1435 1649 1649 1649 1649 1649 1649 1649 1649 1649 1649 1649 1649 -1624 -1624 -1624 -1624 -1624 -1624 -1624 -1624 -1624 -1624 -1624 -1624 -1624 -1624 -1624 -1624 -1624 -1624 -1624 -1624 -1624 -1624 -1624 -1624 -1624 -1624 -1624 -1624 -1624 -1624 -1360 -1280 -1200 -1120 -1040 -960 -880 -800 -720 -640 -560 -480 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 PA0 PA1 PA2 1649 1649 1649 1649 1649 1649 1649 1649 1649 1649 1649 1649 1649 1649 1649 1649 1649 1649 1515 1435 1355 1275 1195 1095 1015 935 855 775 695 615 535 375 295 215 135 55 -25 -105 -185 -285 -365 -445 0 80 160 240 320 400 480 560 640 720 800 880 960 1040 1120 1200 1280 1360 1624 1624 1624 1624 1624 1624 1624 1624 1624 1624 1624 1624 1624 1624 1624 1624 1624 1624 1624 1624 1624 1624 1624 1624 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 P06 P07 VSS AIN0 AIN1 AVDD VREF AVSS VSS P20 P21 P22 P40 P41 VPP RESET_N P44 P45 P46 P47 P30 P31 P34 P32 P33 P35 TEST VDD VDDL VSS VDDX XT0 XT1 P42 P43 VL1 VL2 VL3 VL4 C1 C2 -925 -1005 -1106 -1186 -1366 -1446 -1649 -1649 -1649 -1649 -1649 -1649 -1649 -1649 -1649 -1649 -1649 -1649 -1649 -1649 -1649 -1649 -1649 -1649 -1649 -1649 -1649 -1649 -1649 -1649 -1649 -1649 -1649 -1649 -1649 -1649 -1649 -1649 -1649 -1649 -1649 1624 1624 1624 1624 1624 1624 1430 1270 1190 1095 1015 935 855 775 695 615 535 455 375 295 215 135 55 -25 -105 -185 -265 -345 -425 -505 -585 -665 -825 -905 -985 -1080 -1160 -1240 -1320 -1400 -1480 1-12 ML610Q438/ML610Q439 User’s Manual Chapter 1 Overview 1.3.2 List of Pins PAD No. Q439 Q438 8,102, 108,129 Primary function Pin name I/O Function Tertiary function Pin name I/O Function Vss  Negative power supply pin       Positive power supply pin Power supply pin for  internal logic (internally generated) Power supply pin for  low-speed oscillation (internally generated) Power supply pin for  Flash ROM Negative power supply pin for successive  approximation type ADC Positive power supply pin for successive  approximation type ADC Power supply pin for  LCD bias (internally generated) Power supply pin for  LCD bias (internally generated) Power supply pin for  LCD bias (internally generated) Power supply pin for  LCD bias (internally generated) Capacitor connection  pin for LCD bias generation Capacitor connection  pin for LCD bias generation Capacitor connection  pin for LCD bias generation Capacitor connection  pin for LCD bias generation Input/output pin for I/O testing                                                                                           Reset input pin       Low-speed clock oscillation pin Low-speed clock oscillation pin Reference power supply pin for successive approximation type ADC Successive approximation type ADC input                         8,102, 108,12 Secondary function Pin name I/O Function 9 11,127 11,127 VDD  128 128 VDDL 130 130 VDDX 114 114 VPP 107 107 AVSS 105 105 AVDD 135 135 VL1 136 136 VL2 137 137 VL3 138 138 VL4 139 139 C1 140 140 C2 1 1 C3 2 2 C4 126 126 TEST 115 115 RESET_ N I 131 131 XT0 I 132 132 XT1 O 106 106 VREF  103 103 AIN0 I FEUL610Q438 1-13 ML610Q438/ML610Q439 User’s Manual Chapter 1 Overview PAD No. Q439 Q438 Primary function Pin name I/O 104 104 AIN1 I 7 7 NMI I 3 3 P00/EXI0/ CAP0 I 4 4 P01/EXI1/ CAP1 I 5 5 P02/EXI2 /RXD0 /P2CK I 6 6 P03/EXI3 I 98 98 P04/EXI4 I/O 99 99 P05/EXI5 I/O 100 100 P06/EXI6 I/O 101 101 P07/EXI7 I/O Function Successive approximation type ADC input Non-maskable interrupt pin Secondary function Pin name I/O                                                            9 9 P10 I 10 P11 I Input port 109 109 P20/LED0 O Output port 110 110 P21/LED1 O Output port 111 111 P22/LED2 O Output port 120 120 P30 I/O Input/output port 121 121 P31 I/O Input/output port 123 123 P32 I/O Input/output port 124 124 P33 I/O Input/output port 122 122 P34 I/O Input/output port 125 125 P35 I/O Input/output port 112 112 P40 I/O Input/output port 113 113 P41 I/O Input/output port SCL 133 133 P42 I/O Input/output port RXD0 I TXD0 O IN1 134 P43 116 116 P44/T02P 0CK 117 117 P45/T13P 1CK Input/output port, Timer I/O 1/Timer 3/PWM1 external clock input 118 118 P46/T46P 2CK 119 119 P47 FEUL610Q438 Input/output port, I/O PWM2 external clock input I/O Input/output port Function  10 134 Pin name I/O  Input port, External interrupt 0 input, Capture 0 input Input port, External interrupt 1 input, Capture 1 input Input port, External interrupt 2, UART0 receive, PWM2 external clock input Input port, External interrupt 3 Input port, External interrupt 4 Input port, External interrupt 5 Input port, External interrupt 6 Input port, External interrupt 7 Input port I/O Input/output port Input/output port, Timer I/O 0/Timer 2/PWM0 external clock input Function Tertiary function OSC0 I High-speed oscillation   OSC1 O High-speed oscillation   PWM2 O       PWM2 O PWM2 output          PWM0 O PWM0 output PWM1 O PWM1 output I SSIO data input Low-speed clock output High-speed clock OUTCLK O output MD0 O Melody output RC type ADC0 IN0 I oscillation input pin RC type ADC0 CS0 O reference capacitor connection pin RC type ADC0 RS0 O reference resistor connection pin RC type ADC0 resistor RT0 O sensor connection pin RC type ADC0 RCT0 O resistor/capacitor sensor connection pin RC type ADC oscillation RCM O monitor 2 SDA I/O I C data input/output LSCLK O SIN0  PWM2 output 2 I/O I C clock input/output SCK0 UART data input SOUT0 O UART data output PWM0 O PWM0 output I RC type ADC1 oscillation input pin SIN0 I SSIO0 data input CS1 O RC type ADC1 reference capacitor connection pin SCK0 I/O SSIO0 synchronous clock RS1 O RC type ADC1 reference resistor SOUT0 O SSIO0 data output RT1 O RC type ADC1 PWM1 O PWM1 output I/O SSIO synchronous clock SSIO data output 1-14 ML610Q438/ML610Q439 User’s Manual Chapter 1 Overview PAD No. Q439 Q438 Primary function Pin name I/O Function Secondary function Pin name I/O Function Tertiary function Pin name I/O Function resistor sensor connection pin                                        LCD common pin      LCD common pin      O LCD common pin      O LCD common pin               92 92 PA0 I/O Input/output port   93 93 PA1 I/O Input/output port   94 94 PA2 I/O Input/output port   95 95 PA3 I/O Input/output port   96 96 PA4 I/O Input/output port   97 97 PA5 I/O Input/output port   12 12 COM0 O LCD common pin   13 13 COM1 O LCD common pin  14 14 COM2 O LCD common pin 15 15 COM3 O 16 16 COM4 O 17 17 COM5 18 18 COM6 19 19 COM7 O LCD common pin   91 91 COM8 O LCD common pin   90 90 COM9 O LCD common pin          89 89 COM10 O LCD common pin                            84 84 COM15 O LCD common pin    83 COM16 O LCD common pin    82 COM17 O LCD common pin           81 COM18 O LCD common pin       88 88 COM11 O LCD common pin   87 87 COM12 O LCD common pin   86 86 COM13 O LCD common pin   85 85 COM14 O LCD common pin    80 COM19 O LCD common pin        79 COM20 O LCD common pin        78 COM21 O LCD common pin        77 COM22 O LCD common pin        76 COM23 O LCD common pin       20 20 SEG0 O LCD segment pin       21 21 SEG1 O LCD segment pin       22 22 SEG2 O LCD segment pin       23 23 SEG3 O LCD segment pin       24 24 SEG4 O LCD segment pin       25 25 SEG5 O LCD segment pin       26 26 SEG6 O LCD segment pin       27 27 SEG7 O LCD segment pin       28 28 SEG8 O LCD segment pin       29 29 SEG9 O LCD segment pin       30 30 SEG10 O LCD segment pin       31 31 SEG11 O LCD segment pin       32 32 SEG12 O LCD segment pin       33 33 SEG13 O LCD segment pin       34 34 SEG14 O LCD segment pin       35 35 SEG15 O LCD segment pin                   36 36 SEG16 O LCD segment pin 37 37 SEG17 O LCD segment pin FEUL610Q438 1-15 ML610Q438/ML610Q439 User’s Manual Chapter 1 Overview PAD No. Q439 Q438 Primary function Function Secondary function Pin name I/O Function Tertiary function Pin name I/O 38 38 SEG18 O LCD segment pin    Pin name I/O   Function  39 39 SEG19 O LCD segment pin       40 40 SEG20 O LCD segment pin       41 41 SEG21 O LCD segment pin       42 42 SEG22 O LCD segment pin       43 43 SEG23 O LCD segment pin       44 44 SEG24 O LCD segment pin       45 45 SEG25 O LCD segment pin       46 46 SEG26 O LCD segment pin       47 47 SEG27 O LCD segment pin       48 48 SEG28 O LCD segment pin       49 49 SEG29 O LCD segment pin       50 50 SEG30 O LCD segment pin       51 51 SEG31 O LCD segment pin       52 52 SEG32 O LCD segment pin       53 53 SEG33 O LCD segment pin       54 54 SEG34 O LCD segment pin       55 55 SEG35 O LCD segment pin       56 56 SEG36 O LCD segment pin       57 57 SEG37 O LCD segment pin       58 58 SEG38 O LCD segment pin       59 59 SEG39 O LCD segment pin       60 60 SEG40 O LCD segment pin       61 61 SEG41 O LCD segment pin       62 62 SEG42 O LCD segment pin       63 63 SEG43 O LCD segment pin       64 64 SEG44 O LCD segment pin       65 65 SEG45 O LCD segment pin       66 66 SEG46 O LCD segment pin       67 67 SEG47 O LCD segment pin       68 68 SEG48 O LCD segment pin       69 69 SEG49 O LCD segment pin       70 70 SEG50 O LCD segment pin       71 71 SEG51 O LCD segment pin       72 72 SEG52 O LCD segment pin       73 73 SEG53 O LCD segment pin       74 74 SEG54 O LCD segment pin       75 75 SEG55 O LCD segment pin       76  SEG56 O LCD segment pin       77  SEG57 O LCD segment pin       78  SEG58 O LCD segment pin       79  SEG59 O LCD segment pin       80  SEG60 O LCD segment pin       81  SEG61 O LCD segment pin       82  SEG62 O LCD segment pin       83  O LCD segment pin       SEG63 FEUL610Q438 1-16 ML610Q438/ML610Q439 User’s Manual Chapter 1 Overview 1.3.3 Description of Pins Pin name I/O Description Primary/ Secondary/ Tertiary Logic — Negative — — — — Secondary Secondary — — Secondary — Secondary — Primary Positive Primary Positive Primary Positive Primary Positive Primary Positive Primary Positive Secondary Positive Primary/Se condary Positive System Reset input pin. When this pin is set to a “L” level, system reset mode is set and the internal section is initialized. When this pin is set to a “H” level subsequently, program execution starts. A pull-up resistor is internally connected. XT0 I Crystal connection pin for low-speed clock. XT1 O A 32.768 kHz crystal oscillator (see measuring circuit 1) is connected to this pin. Capacitors CDL and CGL are connected across this pin and VSS as required. OSC0 I Crystal/ceramic connection pin for high-speed clock. OSC1 O A crystal or ceramic is connected to this pin (4.1 MHz max.). Capacitors CDH and CGH (see measuring circuit 1) are connected across this pin and VSS. This pin is used as the secondary function of the P10 pin(OSC0) and P11 pin(OSC1). LSCLK O Low-speed clock output pin. This pin is used as the secondary function of the P20 pin. OUTCLK O High-speed clock output pin. This pin is used as the secondary function of the P21 pin. General-purpose input port RESET_N I General-purpose input port. Since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. P10-P11 I General-purpose input port. Since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. General-purpose output port P20-P22 O General-purpose output port. Since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. General-purpose input/output port P30-P35 I/O General-purpose input/output port. Since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. P40-P47 I/O General-purpose input/output port. Since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. PA0-PA5 I/O General-purpose input/output port. P00-P07 I UART TXD0 O RXD0 I FEUL610Q438 UART data output pin. This pin is used as the secondary function of the P43 pin. UART data input pin. This pin is used as the secondary function of the P42 or the primary function of the P02 pin. 1-17 ML610Q438/ML610Q439 User’s Manual Chapter 1 Overview Pin name Primary/ Secondary/ Tertiary Logic Secondary Positive Secondary Positive I/O Synchronous serial clock input/output pin. This pin is used as the tertiary function of the P41 or P45 pin. I Synchronous serial data input pin. This pin is used as the tertiary function of the P40 or P44 pin. O Synchronous serial data output pin. This pin is used as the tertiary function of the P42 or P46 pin. Tertiary — Tertiary Positive Tertiary Positive PWM0 output pin. This pin is used as the tertiary function of the P43 or P34 pin. PWM0 external clock input pin. This pin is used as the primary function of the P44 pin. PWM1 output pin. This pin is used as the tertiary function of the P47 or P35 pin. PWM1 external clock input pin. This pin is used as the primary function of the P45 pin. PWM2 output pin. This pin is used as the tertiary function of the P20 or P30 pin. PWM2 external clock input pin. This pin is used as the primary function of the P02 pin. Tertiary Positive Primary — Tertiary Positive Primary — Tertiary Positive Primary — Primary Positive/ negative Positive/ negative I/O Description 2 I C bus interface 2 SDA I/O I C data input/output pin. This pin is used as the secondary function of the P40 pin. This pin has an NMOS open drain output. When using this pin as 2 a function of the I C, externally connect a pull-up resistor. 2 SCL O I C clock output pin. This pin is used as the secondary function of the P41 pin. This pin has an NMOS open drain output. When using this pin as a 2 function of the I C, externally connect a pull-up resistor. Synchronous serial (SSIO) SCK0 SIN0 SOUT0 PWM PWM0 O T0P0CK I PWM1 O T1P1CK I PWM2 O P2CK I External interrupt NMI I EXI0-7 I External non-maskable interrupt input pin. An interrupt is generated on both edges. External maskable interrupt input pins. Interrupt enable and edge selection can be performed for each bit by software. These pins are used as the primary functions of the P00-P07 pins. Primary Capture CAP0 I CAP1 I Capture trigger input pins. The value of the time base counter is captured in the register synchronously with the interrupt edge selected by software. These pins are used as the primary functions of the P00 pin(CAP0) and P01 pin(CAP1). Primary Primary Positive/ negative Positive/ negative Timer T0P0CK I T1P1CK I External clock input pin used for Timer 0. This pin is used as the primary function of the P44 pin. External clock input pin used for Timer 1. This pin is used as the primary function of the P45 pin. Melody MD0 O Melody/buzzer signal output pin. This pin is used as the secondary function of the P22 pin. LED drive LED0-2 O Nch open drain output pins to drive LED. FEUL610Q438 Primary Primary — — Secondary Positive/ negative Primary Positive/ negative 1-18 ML610Q438/ML610Q439 User’s Manual Chapter 1 Overview Pin name I/O Description RC oscillation type A/D converter IN0 I Channel 0 oscillation input pin. This pin is used as the secondary function of the P30 pin. CS0 O Channel 0 reference capacitor connection pin. This pin is used as the secondary function of the P31 pin. RS0 O This pin is used as the secondary function of the P32 pin which is the reference resistor connection pin of Channel 0. RT0 O Resistor sensor connection pin of Channel 0 for measurement. This pin is used as the secondary function of the P34 pin. CRT0 O Resistor/capacitor sensor connection pin of Channel 0 for measurement. This pin is used as the secondary function of the P33 pin. RCM O RC oscillation monitor pin. This pin is used as the secondary function of the P35 pin. IN1 I Oscillation input pin of Channel 1. This pin is used as the secondary function of the P44 pin. CS1 O Reference capacitor connection pin of Channel 1. This pin is used as the secondary function of the P45 pin. RS1 O Reference resistor connection pin of Channel 1. This pin is used as the secondary function of the P46 pin. RT1 O Resistor sensor connection pin for measurement of Channel 1. This pin is used as the secondary function of the P47 pin. Successive approximation type A/D converter AVSS — Negative power supply pin for successive approximation type A/D converter. AVDD — Positive power supply pin for successive approximation type A/D converter. VREF — Reference power supply pin for successive approximation type A/D converter. AIN0 I Channel 0 analog input for successive approximation type A/D converter. AIN1 I Channel 1 analog input for successive approximation type A/D converter. LCD drive signal COM0-15 O COM8-23 O Common output pins. Common output pins. These pins are for the ML610Q438, but are not provided in the ML610Q439. SEG0-57 O Segment output pin. SEG58-63 O Segment output pins. These pins are for the ML610Q439, but are not provided in the ML610Q438. LCD driver power supply VL1 — Power supply pins for LCD bias (internally generated). Capacitors Ca, Cb, VL2 — Cc, and Cd (see measuring circuit 1) are connected between VSS and VL1, VL3 — VL2, VL3, and VL4, respectively. VL4 — C1 — Power supply pins for LCD bias (internally generated). Capacitors C12 C2 — and C34 (see measuring circuit 1) are connected between C1 and C2 and C3 — between C3 and C4, respectively. C4 For testing — TEST I/O Input/output pin for testing. A pull-down resistor is internally connected. Power supply VSS — Negative power supply pin. VDD — Positive power supply pin. FEUL610Q438 Primary/ Secondary/ Tertiary Secondary Secondary Secondary Secondary Secondary Secondary Secondary Secondary Secondary Secondary Logic — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 1-19 ML610Q438/ML610Q439 User’s Manual Chapter 1 Overview Pin name I/O Description VDDL — VDDX — VPP — Positive power supply pin (internally generated) for internal logic. Capacitors CL0 and CL1 (see measuring circuit 1) are connected between this pin and VSS. Plus-side power supply pin (internally generated) for low-speed oscillation. Capacitor Cx (see measuring circuit 1) is connected between this pin and VSS. Power supply pin for programming Flash ROM. A pull-up resistor is internally connected. FEUL610Q438 Primary/ Secondary/ Tertiary — Logic — — — — — 1-20 ML610Q438/ML610Q439 User’s Manual Chapter 1 Overview 1.3.4 Termination of Unused Pins Table 1-3 shows methods of terminating the unused pins. Table 1-3 Pin Termination of Unused Pins Recommended pin termination Open VPP AVDD VSS AVSS VSS VREF VSS AIN0, AIN1 Open VL1, VL2, VL3, VL4 Open C1, C2, C3, C4 RESET_N TEST NMI P00 to P07 P10 to P11 P20 to P22 P30 to P35 P40 to P47 PA0 to PA5 COM0 to 23 SEG0 to 63 Open Open Open Open VDD or VSS VDD Open Open Open Open Open Open Note: It is recommended to set the unused input ports and input/output ports to the inputs with pull-down resistors/pull-up resistors or the output mode since the supply current may become excessively large if the pins are left open in the high impedance input setting. 1.3.5 The main difference points of ML610Q438 and ML610Q439 Table 1-4 The main difference points of ML610Q438 and ML610Q439. Function LCD COM LCD SEG FEUL610Q438 ML610Q438 ML610Q439 COM23 to COM0 SEG55 to SEG0 COM15 to COM0 SEG63 to SEG0 1-21 Chapter 2 CPU and Memory Space ML610Q438/ML610Q439 User’s Manual Chapter 2 CPU and Memory Space 2. CPU and Memory Space 2.1 Overview This LSI includes 8-bit CPU nX-U8/100 and the memory model is “LARGE model” . For details of the CPU nX-U8/100, see “nX-U8/100 Core Instruction Manual”. 2.2 Program Memory Space The program memory space is used to store program codes, table data (ROM window), or vector tables. The program codes have a length of 16 bits and are specified by a 16-bit program counter (PC). The ROM window area data has a length of 8 bits and can be used as table data. The vector table, which has 16-bit long data, can be used as reset vectors, hardware interrupt vectors, and software interrupt vectors. The program memory space consists of 2 segments and has 128-Kbyte (64-Kword) capacity. Figure 2-1 shows the configuration of the program memory space. CSR:PC Segment 0 CSR:PC 0:0000H Vector Table Area or 1:0000H Segment 1 Program Code 0:00FFH ROM Window Area 0:0100H Program Code or ROM Window Area Program Code 0:D7FFH or 0:D800H ROM Window Area Program Code Area 0:FBFFH 0:FC00 H Test Data Area 0:FDFF H Write-able 0:FC00H Test Data Area 1:FFFF H 0:FFFFH 8bit Figure 2-1 8bit 8bit Configuration of Program Memory Space Notes: − Since test program data is stored in the 1024Byte (512Word) test data area (0:FC00H to 0:FFFFH) of Segment 0, this area cannot be used as a program code area. − The address “0: FC00H to 0: FDFFH” in the test area is write-able and erase-able. Fill the area with “0FFH”. If data in the area is uncertain or other data (i.e. not 0FFH), operating with the code can not be guranteed. − The area 0:E000H to 0:FDFFH of Segment 0 cannot be used as a ROM window area. − Set “0FFH” data (BRK instruction) in the unused area of the program memory space. FEUL610Q438 2-1 ML610Q438/ML610Q439 User’s Manual Chapter 2 CPU and Memory Space 2.3 Data Memory Space The data memory space of this LSI consists of the ROM window area, 6KByte RAM area and SFR area of Segment 0 and the ROM reference areas of the Segment 1 and Segment 8. The data memory stores 8-bit data and is specified by 20 bits consisting of higher 4 bits as DSR and lower 16 bits as addressing specified by each instruction. Figure 2-2 shows the configuration of the data memory space. DSR: Data address Segment 0 0:0000H DSR: Data address Segment 1 1:0000H DSR: Data address Segment 8 8:0000H ROM Window Area ROM Reference ROM Reference Area Area 0:0D7FFH 0:0D800H RAM Area 6KByte 0:0EFFFH 0:0F000H 8:0FDFFH SFR Area 0:0FFFFH 8:0FC00H 1:0FFFFH 8bit Figure 2-2 8:0FFFFH 8bit Test Data Area 8bit Configuration of Data Memory Space 2.4 Instruction Length The length of a instruction is 16 bits. 2.5 Data Type The data types supported include byte (8 bits) and word (16 bits). FEUL610Q438 2-2 ML610Q438/ML610Q439 User’s Manual Chapter 2 CPU and Memory Space 2.6 Description of Registers 2.6.1 List of Registers Address 0F000H Name Data segment register FEUL610Q438 Symbol (Byte) DSR Symbol (Word)  R/W R/W Size 8 Initial value 00H 2-3 ML610Q438/ML610Q439 User’s Manual Chapter 2 CPU and Memory Space 2.6.2 Data Segment Register (DSR) Address: 0F000H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 DSR     DSR3 DSR2 DSR1 DSR0 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 DSR is a special function register (SFR) to retain a data segment. Instruction Manual”. For details of DSR, see “nX-U8/100 Core [Description of Bits] • DSR3-DSR0 (bits 3-0) DSR3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FEUL610Q438 DSR2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 DSR1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 DSR0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Description Data segment 0 (initial value) Data segment 1 Prohibited Data segment 8 Prohibited 2-4 Chapter 3 Reset Function ML610Q438/ML610Q439 User’s Manual Chapter 3 Reset Function 3. Reset Function 3.1 Overview This LSI has the five reset functions shown below. If any of the five reset conditions is satisfied, this LSI enters system reset mode. • • • • • Reset by the RESET_N pin Reset by power-on detection Reset by the low-speed oscillation stop detection Reset by the 2nd watchdog timer (WDT) overflow Software reset by execution of the BRK instruction 3.1.1 Features • • • • • The RESER_N pin has an internal pull-up resistor The low-speeed oscillation stop deteciton time is 3 ms (typ.) 250 ms, 1 sec, 4 sec, or 16 sec can be selected as the watchdog timer (WDT) overflow period Built-in reset status register (RSTAT) indicating the reset generation causes Only the CPU is reset by the BRK instruction (neither the RAM area nor the SFR area are reset). 3.1.2 Configuration Figure 3-1 shows the configuration of the reset generation circuit. VDD RESET_N Reset signal Power-on reset Low-speed Oscillation stop detect reset RSTAT Data bus WDT reset RSTAT: Reset status register Figure 3-1 Configuration of Reset Generation Circuit 3.1.3 List of Pin Pin name RESET_N FEUL610Q438 I/O I Description Reset input pin 3-1 ML610Q438/ML610Q439 User’s Manual Chapter 3 Reset Function 3.2 Description of Registers 3.2.1 List of Registers Address Name Symbol (Byte) Symbol (Word) R/W Size Initial value 0F001H Reset status register RSTAT  R/W 8  3.2.2 Reset Status Register (RSTAT) Address: 0F001H Access: R/W Access size: 8 bits Initial value: Undefined 7 6 5 4 3 2 1 0 RSTAT ― ― ― ― ― WDTR XSTR POR R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W x R/W 1 RSTAT is a special function register (SFR) that indicates the causes by which the reset is generated. At the occurrence of reset, the contents of RSTAT are not initialized, while the bit indicating the cause of the reset is set to ”1”. When checking the reset cause using this function, perform write operation to RSTAT in advance and initialize the contents of RSTAT to “00H”. [Description of Bits] • POR (bit 0) The POR bit is a flag that indicates that the power-on reset is generated. This bit is set to “1” when powered on. POR 0 1 Description Power-on reset not generated Power-on reset generated • XSTR (bit 1) The XSTR bit is a flag that indicates the generation of low-speed oscillation stop detect reset. When low-speed oscillation stops for the period specified by the low-speed oscillation stop detection time (TSTOP) or more, this bit is set to “1”. XSTR 0 1 Description Low-speed oscillation stop detect reset not occurred Low-speed oscillation stop detect reset occurred • WDTR (bit 2) The WSDTR is a flag that indicates that the watchdog timer reset is generated. This bit is set to “1” when the reset by overflow of the watchdog timer is generated. WDTR 0 1 Description Watchdog timer reset not occurred Watchdog timer reset occurred Note: No flag is provided that indicates the occurrence of reset by the RESET_N pin. FEUL610Q438 3-2 ML610Q438/ML610Q439 User’s Manual Chapter 3 Reset Function 3.3 Description of Operation 3.3.1 Operation of System Reset Mode System reset has the highest priority among all the processings and any other processing being executed up to then is cancelled. The system reset mode is set by any of the following causes. • • • • • Reset by the RESET_N pin Reset by power-on detection Reset by low-speed oscillation stop detection Reset by watchdog timer (WDT) overflow Software reset by the BRK instruction (only the CPU is reset) In system reset mode, the following processing is performed. (1) The power circuit is initialized, but not initialized by the reset by the BRK instruction execution. For the details of the power circuit, refer to Chapter 28, “Power Circuit”. (2) All the special function registers (SFRs) whose initial value is not undefined are initialized. However, the initialization is not performed by software reset due to execution of the BRK instruction. See Appendix A “Registers” for the initial values of the SFRs. (3) CPU is initialized. • All the registers in CPU are initialized. • The contents of addresses 0000H and 0001H in the program memory are set to the stack pointer (SP). • The contents of addresses 0002H and 0003H in the program memory are set to the program counter (PC). However, when the interrupt level (ELEEVL) of the program status word (PSW) at reset by the BRK instruction is 1 or lower, the contents of addresses 0004H and 0005H of the program memory are set in the program counter (PC). For the BRK instruction, see “nX-U8/100 Core Instruction Manual”. Note: In system reset mode, the contents of data memory and those of any SFR whose initial value is undefined are not initialized and are undefined. Initialize them by software. In system reset mode by the BRK instruction, no special function register (SFR) that has a fixed initial value is initialized either. Therefore initialize such an SFR by software. FEUL610Q438 3-3 Chapter 4 MCU Control Function ML610Q438/ML610Q439 User’s Manual Chapter 4 MCU Control Function 4. MCU Control Function 4.1 Overview The operating states of this LSI are classified into the following 4 modes including system reset mode: System reset mode Program run mode HALT mode STOP mode For system reset mode, see Chapter 3, “Reset Function”. This LSI has a block control function, which power downs the circuits of unused peripherals (reset registers and stop clock supplies) to make even more reducing the current consumption. 4.1.1 Features • • • • HALT mode, where the CPU stops operating and only the peripheral circuit is operating STOP mode, where both low-speed oscillation and high-speed oscillation stop Stop code acceptor function, which controls transition to STOP mode Block control function, which power downs the circuits of unused peripherals (reset registers and stop clock supplies). 4.1.2 Configuration Figure 4-1 shows an operating state transition diagram. Release of reset Power on Program run mode System reset mode Reset or BRK instruction STP = “1” Reset Reset HLT = “1” Interrupt External interrupt STOP mode Figure 4-1 FEUL610Q438 HALT mode Operating State Transition Diagram 4-1 ML610Q438/ML610Q439 User’s Manual Chapter 4 MCU Control Function 4.2 Description of Registers 4.2.1 List of Registers Address 0F008H 0F009H 0F028H 0F029H 0F02AH 0F02BH 0F02CH FEUL610Q438 Name Stop code acceptor Standby control register Block control register 0 Block control register 1 Block control register 2 Block control register 3 Block control register 4 Symbol (Byte) Symbol (Word) R/W Size Initial value STPACP SBYCON BLKCON0 BLKCON1 BLKCON2 BLKCON3 BLKCON4        W W R/W R/W R/W R/W R/W 8 8 8 8 8 8 8  00H 00H 00H 00H 00H 00H 4-2 ML610Q438/ML610Q439 User’s Manual Chapter 4 MCU Control Function 4.2.2 Stop Code Acceptor (STPACP) Address: 0F008H Access: W Access size: 8 bits Initial value:  (Undefined) 7 6 5 4 3 2 1 0 STPACP ― ― ― ― ― ― ― ― W Initial value W ― W ― W ― W ― W ― W ― W ― W ― STPACP is a write-only special function register (SFR) that is used for setting a STOP mode. When STPACP is read, “00H” is read. When data is written to STPACP in the order of “5nH”(n: an arbitrary value) and “0AnH”(n: an arbitrary value), the stop code acceptor is enabled. When the STP bit of the standby control register (SBYCON) is set to “1” in this state, the mode is changed to the STOP mode. When the STOP mode is set, the STOP code acceptor is disabled. When another instruction is executed between the instruction that writes “5nH” to STPACP and the instruction that writes “0AnH”, the stop code acceptor is enabled after “0AnH” is written. However, if data other than “0AnH” is written to STPACP after “5nH” is written, the “5nH” write processing becomes invalid so that data must be written again starting from “5nH”. During a system reset, the stop code acceptor is disabled. Note: The STOP code acceptor can not be enabled on the condition of that both any interrupt enable flag and the corresponding interrupt request flag are “1”(An interrupt request occurrence with resetting MIE flag will have the condition). FEUL610Q438 4-3 ML610Q438/ML610Q439 User’s Manual Chapter 4 MCU Control Function 4.2.3 Standby Control Register (SBYCON) Address: 0F009H Access: W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 SBYCON ― ― ― ― ― ― STP HLT W Initial value W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 SBYCON is a special function register (SFR) to control operating mode of MCU. [Description of Bits] • STP (bit 1) The STP bit is used for setting the STOP mode. When the STP bit is set to “1” with the stop code adapter enabled by using STPACP, the mode is changed to the STOP mode. When the NMI interrupt request or the P00–P03 interrupt request enabled by the interrupt enable register 1 (IE1) is issued, the STP bit is set to “0” and the LSI returns to the program run mode. • HLT (bit 0) The HALT bit is used for setting a HALT mode. When the HALT bit is set to “1”, the mode is changed to the HALT mode. When the NMI interrupt request, WDT interrupt request, or enabled (the interrupt enable flag is “1”) interrupt request is issued, the HALT bit is set to “1” and the mode is returned to program run mode. STP 0 0 1 1 HLT 0 1 0 1 Description Program run mode (initial value) HALT mode STOP mode Prohibited Note: The mode can not be changed to HALT mode or STOP mode on the condition of that both any interrupt enable flag and the corresponding interrupt request flag are “1”(An interrupt request occurrence with resetting MIE flag will have the condition). When a maskable interrupt source (interrupt with enable bit) occurs while the MIE flag of the program status word (PSW) in the nX-U8/100 core is “0”, the STOP mode and the HALT mode are simply released and interrupt processing is not performed. Refer to the “nX-U8/100 Core Instruction Manual” for details of PSW. FEUL610Q438 4-4 ML610Q438/ML610Q439 User’s Manual Chapter 4 MCU Control Function 4.2.4 Block Control Register 0(BLKCON0) Address: 0F028H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 BLKCON0 ― ― ― ― DTM3 DTM2 DTM1 DTM0 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 BLKCON0 is a special function register (SFR) to make even more reducing current consumption by turning unused peripherals off. [Description of Bits] • DTM3 (bit 3) The DTM3 bit is used to control Timer3 operation. When the DTM3 bit is set to “1”, the circuits related to Timer 3 are reset and turned off. DTM3 0 1 Description Enable operating Timer 3 (initial value) Disable operating Timer 3 • DTM2 (bit 2) The DTM2 bit is used to control Timer2 operation. When the DTM2 bit is set to “1”, the circuits related to Timer 2 are reset and turned off. DTM2 0 1 Description Enable operating Timer 2 (initial value) Disable operating Timer 2 • DTM1 (bit 1) The DTM1 bit is used to control Timer1 operation. When the DTM1 bit is set to “1”, the circuits related to Timer 1 are reset and turned off. DTM1 0 1 Description Enable operating Timer 1 (initial value) Disable operating Timer 1 • DTM0 (bit 0) The DTM0 bit is used to control Timer0 operation. When the DTM0 bit is set to “1”, the circuits related to Timer 0 are reset and turned off. DTM0 0 1 Description Enable operating Timer 0 (initial value) Disable operating Timer 0 Note: When certain bits of block control registers are set to “1”, corresponding peripherals are reset (all registers are reset) and operating clocks for the peripherals stop. Writing to every SFR (special function register) in the corresponding peripherals is not valid while the bits of block control registers are set to “1” and returns the initial value for read. Ensure the bits are reset to “0” before using the peripherals to enable the operation. See Chapter 10, “Timers” for detail about operation of Timer 0, Timer 1, Timer 2 and Timer 3.. FEUL610Q438 4-5 ML610Q438/ML610Q439 User’s Manual Chapter 4 MCU Control Function 4.2.5 Block Control Register 1(BLKCON1) Address: 0F029H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 BLKCON1 ― ― ― DT1K ― DPW2 DPW1 DPW0 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 BLKCON1 is a special function register (SFR) to make even more reducing current consumption by turning unused peripherals off. [Description of Bits] • DT1K (bit 4) The DT1K bit is used to control 1kHz Timer operation. When the DT1K bit is set to “1”, the circuits related to 1kHz Timer are reset and turned off. DT1K 0 1 Description Enable operating 1kHz Timer (initial value) Disable operating 1kHz Timer • DPW2 (bit 2) The DPW2 bit is used to control PWM2 operation. When the DPW2 bit is set to “1”, the circuits related to PWM2 are reset and turned off. DPW2 0 1 Description Enable operating PWM2 (initial value) Disable operating PWM2 • DPW1 (bit 1) The DPW1 bit is used to control PWM1 operation. When the DPW1 bit is set to “1”, the circuits related to PWM1 are reset and turned off. DPW1 0 1 Description Enable operating PWM1 (initial value) Disable operating PWM1 • DPW0 (bit 0) The DPW0 bit is used to control PWM0 operation. When the DPW0 bit is set to “1”, the circuits related to PWM0 are reset and turned off. DPW0 0 1 Description Enable operating PWM0 (initial value) Disable operating PWM0 Note: When certain bits of block control registers are set to “1”, corresponding peripherals are reset (all registers are reset) and operating clocks for the peripherals stop. Writing to every SFR (special function register) in the corresponding peripherals is not valid while the bits of block control registers are set to “1” and returns the initial value for read. Ensure the bits are reset to “0” before using the peripherals to enable the operation. See Chapter 9, “1kHz Timer” for detail about operation of 1kHz Timer. See Chapter 11, “PWM” for detail about operation of PWM. FEUL610Q438 4-6 ML610Q438/ML610Q439 User’s Manual Chapter 4 MCU Control Function 4.2.6 Block Control Register 2(BLKCON2) Address: 0F02AH Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 BLKCON2 DI2C0 ― ― ― ― DUA0 ― DSIO0 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 BLKCON2 is a special function register (SFR) to make even more reducing current consumption by turning unused peripherals off. [Description of Bits] • DI2C0 (bit 7) The DI2C0 bit is used to control I2C bus interface operation. When the DI2C0 bit is set to “1”, the circuits related to I2C bus interface are reset and turned off. DI2C0 0 1 Description Enable operating I2C (initial value) Disable operating I2C • DUA0 (bit 2) The DUA0 bit is used to control UART operation. When the DUA0 bit is set to “1”, the circuits related to UART are reset and turned off. DUA0 0 1 Description Enable operating UART (initial value) Disable operating UART • DSIO0 (bit 0) The DSIO0 bit is used to control SSIO operation. When the DSIO0 bit is set to “1”, the circuits related to SSIO are reset and turned off. DSIO0 0 1 Description Enable operating SSIO (initial value) Disable operating SSIO Note: When certain bits of block control registers are set to “1”, corresponding peripherals are reset (all registers are reset) and operating clocks for the peripherals stop. Writing to every SFR (special function register) in the corresponding peripherals is not valid while the bits of block control registers are set to “1” and returns the initial value for read. Ensure the bits are reset to “0” before using the peripherals to enable the operation. See Chapter 15, “I2C Bus Interface” for detail about operation of I2C Bus Interface. See Chapter 14, “UART” for detail about operation of UART. See Chapter 13, “Synchronous Serial Port” for detail about operation of SSIO. FEUL610Q438 4-7 ML610Q438/ML610Q439 User’s Manual Chapter 4 MCU Control Function 4.2.7 Block Control Register 3(BLKCON3) Address: 0F02BH Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 BLKCON3 ― ― ― ― ― ― ― DMD0 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 BLKCON3 is a special function register (SFR) to make even more reducing current consumption by turning unused peripherals off. [Description of Bits] • DMD0 (bit 0) The DMD0 bit is used to control Melody/Buzzer operation. When the DMD0 bit is set to “1”, the circuits related to Melody/Buzzer are reset and turned off. DMD0 0 1 Description Enable operating Melody/Buzzer (initial value) Disable operating Melody/Buzzer Note: When certain bits of block control registers are set to “1”, corresponding peripherals are reset (all registers are reset) and operating clocks for the peripherals stop. Writing to every SFR (special function register) in the corresponding peripherals is not valid while the bits of block control registers are set to “1” and returns the initial value for read. Ensure the bits are reset to “0” before using the peripherals to enable the operation. See Chapter 23, “Melody Driver” for detail about operation of Melody/Buzzer. FEUL610Q438 4-8 ML610Q438/ML610Q439 User’s Manual Chapter 4 MCU Control Function 4.2.8 Block Control Register 4(BLKCON4) Address: 0F02CH Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 BLKCON4 ― DLCD DBLD DXTSP ― ― DRAD DSAD R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 BLKCON4 is a special function register (SFR) to make even more reducing current consumption by turning unused peripherals off. [Description of Bits] • DLCD (bit 6) The DLCD bit is used to control LCD driver operation. When the DLCD bit is set to “1”, the circuits related to LCD driver are reset and turned off. DLCD 0 1 Description Enable operating LCD driver (initial value) Disable operating LCD driver • DBLD (bit 5) The DBLD bit is used to control BLD (Battery Level Detector) operation. When the DBLD bit is set to “1”, the circuits related to BLD are reset and turned off. DBLD 0 1 Description Enable operating BLD (initial value) Disable operating BLD driver • DXTSP (bit 4) The DXTSP bit is used to control 32kHz oscillation stop detect operation. When the DXTSP bit is set to “1”, the circuits related to 32kHz oscillation stop detect are reset and turned off. DXTSP 0 1 Description Enable operating 32kHz oscillation stop detect (initial value) Disable operating 32kHz oscillation stop detect • DRAD (bit 1) The DRAD bit is used to control RC type A/D converter operation. When the DRAD bit is set to “1”, the circuits related to RC type A/D converter are reset and turned off. DRAD 0 1 Description Enable operating RC type A/D converter (initial value) Disable operating RC type A/D converter • DSAD (bit 1) The DSAD bit is used to control Successive approximation type A/D converter operation. When the DSAD bit is set to “1”, the circuits related to Successive approximation type A/D converter are reset and turned off. DSAD 0 1 Description Enable operating Successive approximation type A/D converter (initial value) Disable operating Successive approximation type A/D converter FEUL610Q438 4-9 ML610Q438/ML610Q439 User’s Manual Chapter 4 MCU Control Function Note: When certain bits of block control registers are set to “1”, corresponding peripherals are reset (all registers are reset) and operating clocks for the peripherals stop. Writing to every SFR (special function register) in the corresponding peripherals is not valid while the bits of block control registers are set to “1” and returns the initial value for read. Ensure the bits are reset to “0” before using the peripherals to enable the operation. See Chapter 26, “LCD Driver” for detail about operation of LCD driver. See Chapter 27, “Battery Level Detector” for detail about operation of BLD. See Chapter 3, “Reset Function” for detail about operation of 32kHz oscillation stop detector. See Chapter 24, “RC Oscillation Type A/D Converter” for detail about operation of RC oscillation type A/D converter. FEUL610Q438 4-10 ML610Q438/ML610Q439 User’s Manual Chapter 4 MCU Control Function 4.3 Description of Operation 4.3.1 Program Run Mode The program run mode is the state where the CPU executes instructions sequentially. At power-on reset, RESET_N pin reset, low-speed oscillation stop detect reset, or WDT overflow reset, the CPU executes instructions from the addresses that are set in addresses 0002H and 0003H of program memory (ROM) after the system reset mode is released. At reset by the BRK instruction, the CPU executes instructions from the addresses that are set in the addresses 0004H and 0005H of the program memory after the system reset mode is released. However, when the value of the interrupt level bit (ELEVEL) of the program status word (PSW) is 02H or higher at execution of the BRK instruction (after the occurrence of the WDT interrupt or NMI interrupt), the CPU executes instructions from the addresses that are set in the addresses 0002H and 0003H. For details of the BRK instruction and PSW, see the “nX-U8/100 Core Instruction Manual” and for the reset function, see Chapter 3, “Reset Function”. 4.3.2 HALT Mode The HALT mode is the state where the CPU interrupts execution of instructions and only the peripheral circuits are running. When the HLT bit of the standby control register (SBYCON) is set to “1”, the HALT mode is set. When a NMI interrupt request, a WDT interrupt request, or an interrupt request enabled by an interrupt enable register (IE1–IE7) is issued, the HLT bit is set to “0” on the falling edge of the next system clock (SYSCLK) and the HALT mode is returned to the program run mode released. Figure 4-2 shows the operation waveforms in HALT mode. System clock SYSCLK CPUCLK SBYCON.HLT Interrupt request Program operating mode Figure 4-2 HALT mode Program operating mode Operation Waveforms in HALT Mode Note: Since up to two instructions are executed during the period between HALT mode release and a transition to interrupt processing, place two NOP instructions next to the instruction that sets the HLT bit to “1”. FEUL610Q438 4-11 ML610Q438/ML610Q439 User’s Manual Chapter 4 MCU Control Function 4.3.3 STOP Mode The STOP mode is the state where low-speed oscillation and high-speed oscillation stop and the CPU and peripheral circuits stop the operation. When the stop code acceptor is enabled by writing “5nH”(n: an arbitrary value) and “0AnH”(n: an arbitrary value) to the stop code acceptor (STPACP) sequentially and the STP bit of the standby control register (SBYCON) is set to “1”, the STOP mode is entered. When the STOP mode is set, the stop code acceptor is disabled. When a NMI interrupt request or an interrupt-enabled (the interrupt enable flag is “1”) P00 to P07 interrupt request is issued, the STP bit is set to “0”, the STOP mode is released, and the mode is returned to the program run mode. 4.3.3.1 STOP Mode When CPU Operates with Low-Speed Clock When the stop code acceptor is in the enabled state and the STP bit of SBYCON is set to “1”, the STOP mode is entered, stopping low-speed oscillation and high-speed oscillation. When the NMI interrupt request or the interrupt-enabled (the interrupt enable flag is “1”) P00 to P07 interrupt request is issued, the STP bit is set to “0” and low-speed oscillation restarts. If the high-speed clock was oscillating before the STOP mode is entered, the high-speed oscillation restarts. When the high-speed clock was not oscillating before the STOP mode is entered, high-speed oscillation does not start. When an interrupt request occurs, the STOP mode is released after the elapse of the low-speed oscillation start time (TXTL) and the low-speed clock (LSCLK) oscillation settling time (8192-pulse count), the mode is returned to the program mode, and the low-speed clock (LSCLK) restarts supply to the peripheral circuits. If the high-speed clock already started oscillation at this time, the high-speed clocks (OSCLK and HSCLK) also restart supply to the peripheral circuits. For the low-speed oscillation start time (TXTL), see the “Electrical Characteristics” Section in Appendix C. Figure 4-3 shows the operation waveforms in STOP mode when CPU operates with the low-speed clock. Oscillation waveform Hiz Low-speed oscillation waveform TXTL LSCLK Low-speed oscillation 8192-pulse count SYSCLK High-speed oscillation waveform HSCLK Oscillation waveform Oscillation waveform HSCLK waveform HSCLK waveform SBYCON.STP bit Interrupt request Program operating mode Figure 4-3 FEUL610Q438 STOP mode Program operating mode Operation Waveforms in STOP Mode When CPU Operates with Low-Speed Clock 4-12 ML610Q438/ML610Q439 User’s Manual Chapter 4 MCU Control Function 4.3.3.2 STOP Mode When CPU Operates with High-Speed Clock When the CPU is operating with a high-speed clock and the STP bit of SBYCON is set to “1” with the stop code acceptor enabled, the STOP mode is entered and high-speed oscillation and low-speed oscillation stop. When the NMI interrupt request or the interrupt-enabled (the interrupt enable flag is “1”) P00 to P07 interrupt request is issued, the STP bit is set to “0” and the low-speed and high-speed oscillation restart. When an interrupt request is issued, the STOP mode is released after the elapse of the high-speed oscillation start time (TXTH/TRC) and the high-speed clock (OSCLK) oscillation stabilization time (8192-pulse count), the mode is returned to the program run mode, and the high-speed clocks (OSCLK and HSCLK) restart supply to the peripheral circuits. The low-speed clock (LSCLK) restarts supply to the peripheral circuits after the elapse of the low-speed oscillation start time (TXTL) and low-speed clock (LSCLK) oscillation settling time (8192 count). For the high-speed oscillation start time (TXTH) and low-speed oscillation start time (TXTL), see the “Electrical Characteristics” Section in Appendix C. Figure 4-4 shows the operation waveforms in STOP mode when CPU operates with the high-speed clock. High-speed oscillation waveform High-speed oscillation waveform OSCLK, HSCLK OSCLK and HSCLK waveforms High-speed oscillation waveform TXTH/TRC OSCLK and HSCLK waveforms High-speed oscillation 8192-pulse count SYSCLK HSCLK waveform Low-speed oscillation waveform HSCLK waveform Low-speed oscillation waveform Hiz TXTL 8192-pulse count LSCLK SBYCON.STP bit Interrupt request Program operating mode Figure 4-4 STOP mode Program operating mode Operation Waveforms in STOP Mode When CPU Operates with High-Speed Clock Note: The STOP mode is entered two cycles after the instruction that sets the STP bit to “1” and up to two instructions are executed during the period between STOP mode release and a transition to interrupt processing. Therefore, place two NOP instructions next to the instruction that set the STP bit to “1”. FEUL610Q438 4-13 ML610Q438/ML610Q439 User’s Manual Chapter 4 MCU Control Function 4.3.3.3 Note on Return Operation from STOP/HALT Mode The operation of returning from the STOP mode and HALT mode varies according to the interrupt level (ELEVEL) of the program status word (PSW), master interrupt enable flag (MIE), the contents of the interrupt enable register (IE0 to IE3), and whether the interrupt is a non-maskable interrupt or a maskable interrupt. For details of PSW and the IE and IRQ registers, see “nX-U8/100 Core Instruction Manual” and Chapter 5, “Interrupt”, respectively. Table 4-1 and Table 4-2 show the return operations from STOP/HALT mode. Table 4-1 Return Operation from STOP/HALT Mode (Non-Maskable Interrupt) ELEVEL * MIE * IEn.m − IRQn.m 0 3 * − 1 0, 1, 2 * − 1 Table 4-2 Return operation from STOP/HALT mode Not returned from STOP/HALT mode. After the mode is returned from STOP/HALT mode, the program operation restarts from the instruction following the instruction that sets the STP/HLT bit to “1”. The program operation does not go to the interrupt routine. After the mode is returned from the STOP/HALT mode, program operation restarts from the instruction following the instruction that sets the STP/HLT bit to “1”, then goes to the interrupt routine. Return Operation from STOP/HALT Mode (Maskable Interrupt) ELEVEL * * * MIE * * 0 IEn.m * 0 1 IRQn.m 0 1 1 2,3 1 1 1 0, 1 1 1 1 Return operation from STOP/HALT mode Not returned from STOP/HALT mode. After the mode is returned from STOP/HALT mode, the program operation restarts from the instruction following the instruction that sets the STP/HLT bit to “1”. The program operation does not go to the interrupt routine. After the mode is returned from the STOP/HALT mode, program operation restarts from the instruction following the instruction that sets the STP/HLT bit to “1”, then goes to the interrupt routine. Notes: • If the ELEVEL bit is 0H, it indicates that the CPU is performing neither nonmaskable interrupt processing nor maskable interrupt processing nor software interrupt processing. • If the ELEVEL bit is 1H, it indicates that the CPU is performing maskable interrupt processing or software interrupt processing. (ELEVEL is set during interrupt transition cycle.) • If the ELEVEL bit is 2H, it indicates that the CPU is performing non-maskable interrupt processing. (ELEVEL is set during interrupt transition cycle.) • If the ELEVEL bit is 3H, it indicates that the CPU is performing interrupt processing specific to the emulator. This setting is not allowed in normal applications. FEUL610Q438 4-14 ML610Q438/ML610Q439 User’s Manual Chapter 4 MCU Control Function 4.3.4 Block Control Function This LSI has a block control function, which resets and completely turns operating circuits of unused peripherals off to make even more reducing current consumption. When certain bits of block control registers are set to “1”, corresponding peripherals are reset (all registers are reset) and operating clocks for the peripherals stop. Writing to every SFR (special function register) in the corresponding peripherals is not valid while the bits of block control registers are set to “1” and returns the initial value for read. Ensure the bits are reset to “0” before using the peripherals to enable the operation. BLKCON0 register controls(disables/enables) operation of Timer 0, Timer 1, Timer 2 and Timer 3. BLKCON1 register controls(disables/enables) operation of 1kHz Timer, PWM0, PWM1 and PWM2. BLKCON2 register controls(disables/enables) operation of I2C, UART and SSIO. BLKCON3 register controls(disables/enables) operation of Melody/Buzzer. BLKCON4 register controls(disables/enables) operation of LCD driver, Battery Level Detector, 32kHz oscillation stop detector and RC type A/D converter. Note: See the each chapter for detail about the opeation of each peripheral and relevant notes. FEUL610Q438 4-15 Chapter 5 Interrupts (INTs) ML610Q438/ML610Q439 User’s Manual Chapter 5 Interrupts (INTs) 5. Interrupts (INTs) 5.1 Overview This LSI has 32 interrupt sources (External interrupts: 9 sources, Internal interrupts: 23 sources) and a software interrupt (SWI). For details of each interrupt, see the following chapters: Chapter 7, “Time Base Counter” Chapter 9, “1 kHz Timer” Chapter 10, “Timer” Chapter 11, “PWM” Chapter 12, “Watchdog Timer” Chapter 13 “Synchronous Serial Port” Chapter 14, “UART” Chapter 15, “I2C Bus Interface” Chapter 16, “NMI” Chapter 17, “Port0” Chapter 23, “Melody Driver” Chapter 24, “RC Oscillation Type A/D Converter” 5.1.1 Features • • • • 2 non-maskable interrupt sources (Internal source: 1, External source: 1) 30 maskable interrupt sources (Internal sources: 22, External sources: 8) Software interrupt (SWI): 64 sources max. External interrupts allow edge selection and sampling selection. FEUL610Q438 5-1 ML610Q438/ML610Q439 User’s Manual Chapter 5 Interrupts (INTs) 5.2 Description of Registers 5.2.1 List of Registers Address 0F011H 0F012H 0F013H 0F014H 0F015H 0F016H 0F017H 0F018H 0F019H 0F01AH 0F01BH 0F01CH 0F01DH 0F01EH 0F01FH Name Interrupt enable register 1 Interrupt enable register 2 Interrupt enable register 3 Interrupt enable register 4 Interrupt enable register 5 Interrupt enable register 6 Interrupt enable register 7 Interrupt request register 0 Interrupt request register 1 Interrupt request register 2 Interrupt request register 3 Interrupt request register 4 Interrupt request register 5 Interrupt request register 6 Interrupt request register 7 FEUL610Q438 Symbol (Byte) Symbol (Word) R/W Size Initial value IE1 IE2 IE3 IE4 IE5 IE6 IE7 IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7                R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 5-2 ML610Q438/ML610Q439 User’s Manual Chapter 5 Interrupts (INTs) 5.2.2 Interrupt Enable Register 1 (IE1) Address: 0F011H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 IE1 EP07 EP06 EP05 EP04 EP03 EP02 EP01 EP00 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 IE1 is a special function register (SFR) to control enable/disable for each interrupt request. When an interrupt is accepted, the master interrupt enable flag (MIE) is set to “0”, but the corresponding flag of IE1 is not reset. [Description of Bits] • EP00 (bit 0) EP00 is the enable flag for the input port P00 pin interrupt (P00INT). EP00 0 1 Description Disabled (initial value) Enabled • EP01 (bit 1) EP01 is the enable flag for the input port P01 pin interrupt (P01INT). EP01 0 1 Description Disabled (initial value) Enabled • EP02 (bit 2) EP02 is the enable flag for the input port P02 pin interrupt (P02INT). EP02 0 1 Description Disabled (initial value) Enabled • EP03 (bit 3) EP03 is the enable flag for the input port P03 pin interrupt (P03INT). EP03 0 1 Description Disabled (initial value) Enabled • EP04 (bit 4) EP04 is the enable flag for the input port P04 pin interrupt (P04INT). EP04 0 1 FEUL610Q438 Description Disabled (initial value) Enabled 5-3 ML610Q438/ML610Q439 User’s Manual Chapter 5 Interrupts (INTs) • EP05 (bit 5) EP05 is the enable flag for the input port P05 pin interrupt (P05INT). EP05 0 1 Description Disabled (initial value) Enabled • EP06 (bit 6) EP06 is the enable flag for the input port P06 pin interrupt (P06INT). EP06 0 1 Description Disabled (initial value) Enabled • EP07 (bit 7) EP07 is the enable flag for the input port P07 pin interrupt (P07INT). EP07 0 1 FEUL610Q438 Description Disabled (initial value) Enabled 5-4 ML610Q438/ML610Q439 User’s Manual Chapter 5 Interrupts (INTs) 5.2.3 Interrupt Enable Register 2 (IE2) Address: 0F012H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 IE2 EI2C0     ESAD  ESIO0 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 IE2 is a special function register (SFR) to control enable/disable for each interrupt request. When an interrupt is accepted, the master interrupt enable flag (MIE) is set to “0”, but the corresponding flag of IE2 is not reset. [Description of Bits] • ESIO0 (bit 0) ESIO0 is the enable flag for the synchronous serial port 0 interrupt (SIO0INT). ESIO0 0 1 Description Disabled (initial value) Enabled • ESAD (bit 2) ESAD is the enable flag for the successive approximation type A/D converter interrupt (SADINT). ESAD 0 1 Description Disabled (initial value) Enabled • EI2C0 (bit 7) EI2C0 is the enable flag for the I2C bus 0 interrupt (I2C0INT). EI2C0 0 1 FEUL610Q438 Description Disabled (initial value) Enabled 5-5 ML610Q438/ML610Q439 User’s Manual Chapter 5 Interrupts (INTs) 5.2.4 Interrupt Enable Register 3 (IE3) Address: 0F013H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 IE3       ETM1 ETM0 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 IE3 is a special function register (SFR) to control enable/disable for each interrupt request. When an interrupt is accepted, the master interrupt enable flag (MIE) is set to “0”, but the corresponding flag of IE3 is not reset. [Description of Bits] • ETM0 (bit 0) ETM0 is the enable flag for the timer 0 interrupt (TM0INT). ETM0 0 1 Description Disabled (initial value) Enabled • ETM1 (bit 1) ETM1 is the enable flag for the timer 1 interrupt (TM1INT). ETM1 0 1 FEUL610Q438 Description Disabled (initial value) Enabled 5-6 ML610Q438/ML610Q439 User’s Manual Chapter 5 Interrupts (INTs) 5.2.5 Interrupt Enable Register 4 (IE4) Address: 0F014H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 IE4   ERAD   EMD0  EUA0 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 IE4 is a special function register (SFR) to control enable/disable for each interrupt request. When an interrupt is accepted, the master interrupt enable flag (MIE) is set to “0”, but the corresponding flag of IE4 is not reset. [Description of Bits] • EUA0 (bit 0) EUA0 is the enable flag for the UART0 interrupt (UA0INT). EUA0 0 1 Description Disabled (initial value) Enabled • EMD0 (bit 2) EMD0 is the enable flag for the melody 0 interrupt (MD0INT). EMD0 0 1 Description Disabled (initial value) Enabled • ERAD (bit 5) ERAD is the enable flag for the RC oscillation type A/D converter interrupt (RADINT). ERAD 0 1 FEUL610Q438 Description Disabled (initial value) Enabled 5-7 ML610Q438/ML610Q439 User’s Manual Chapter 5 Interrupts (INTs) 5.2.6 Interrupt Enable Register 5 (IE5) Address: 0F015H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 IE5   ETM3 ETM2     R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 IE5 is a special function register (SFR) to control enable/disable for each interrupt request. When an interrupt is accepted, the master interrupt enable flag (MIE) is set to “0”, but the corresponding flag of IE5 is not reset. [Description of Bits] • ETM2 (bit 4) ETM2 the enable flag for the timer 2 interrupt (TM2INT). ETM2 0 1 Description Disabled (initial value) Enabled • ETM3 (bit 5) ETM3 the enable flag for the timer 3 interrupt (TM3INT) ETM3 0 1 FEUL610Q438 Description Disabled (initial value) Enabled 5-8 ML610Q438/ML610Q439 User’s Manual Chapter 5 Interrupts (INTs) 5.2.7 Interrupt Enable Register 6 (IE6) Address: 0F016H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 IE6 E32H E64H E128H ET1K  EPW2 EPW1 EPW0 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 IE6 is a special function register (SFR) to control enable/disable for each interrupt request. When an interrupt is accepted, the master interrupt enable flag (MIE) is set to “0”, but the corresponding flag of IE6 is not reset. [Description of Bits] • EPW0 (bit 0) EPW0 is the enable flag for the PWM0 interrupt (PW0INT) EPW0 0 1 Description Disabled (initial value) Enabled • EPW1 (bit 1) EPW1 is the enable flag for the PWM1 interrupt (PW1INT) EPW1 0 1 Description Disabled (initial value) Enabled • EPW2 (bit 2) EPW2 is the enable flag for the PWM2 interrupt (PW2INT) EPW2 0 1 Description Disabled (initial value) Enabled • ET1K (bit 4) ET1K is the enable flag for the 1 kHz timer interrupt (T1KINT). ET1K 0 1 Description Disabled (initial value) Enabled • E128H (bit 5) E128H is the enable flag for the time base counter 128 Hz interrupt (T128HINT). E128H 0 1 FEUL610Q438 Description Disabled (initial value) Enabled 5-9 ML610Q438/ML610Q439 User’s Manual Chapter 5 Interrupts (INTs) • E64H (bit 6) E64H is the enable flag for the time base counter 64 Hz interrupt (T64HINT). E64H 0 1 Description Disabled (initial value) Enabled • E32H (bit 7) E32H is the enable flag for the time base counter 32 Hz interrupt (T32HINT). E32H 0 1 FEUL610Q438 Description Disabled (initial value) Enabled 5-10 ML610Q438/ML610Q439 User’s Manual Chapter 5 Interrupts (INTs) 5.2.8 Interrupt Enable Register 7 (IE7) Address: 0F017H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 IE7    E1H E2H E4H E8H E16H R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 IE7 is a special function register (SFR) to control enable/disable for each interrupt request. When an interrupt is accepted, the master interrupt enable flag (MIE) is set to “0”, but the corresponding flag of IE7 is not reset. [Description of Bits] • E16H (bit 0) E16H is the enable flag for the time base counter 16 Hz interrupt (T16HINT). E16H 0 1 Description Disabled (initial value) Enabled • E8H (bit 1) E8H is the enable flag for the time base counter 8 Hz interrupt (T8HINT). E8H 0 1 Description Disabled (initial value) Enabled • E4H (bit 2) E4H is the enable flag for the time base counter 4 Hz interrupt (T4HINT). E4H 0 1 Description Disabled (initial value) Enabled • E2H (bit 3) E2H is the enable flag for the time base counter 2 Hz interrupt (T2HINT). E2H 0 1 Description Disabled (initial value) Enabled • E1H (bit 4) E1H is the enable flag for the time base counter 1 Hz interrupt (T1HINT). E1H 0 1 FEUL610Q438 Description Disabled (initial value) Enabled 5-11 ML610Q438/ML610Q439 User’s Manual Chapter 5 Interrupts (INTs) 5.2.9 Interrupt Request Register 0 (IRQ0) Address: 0F018H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 IRQ0       QNMI QWDT R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 IRQ0 is a special function register (SFR) to request an interrupt for each interrupt source. The watchdog timer interrupt (WDTINT) and the NMI interrupt (NMINT) are non-maskable interrupts that do not depend on MIE. In this case, an interrupt is requested to the CPU regardless of the value of the Mask Interrupt Enable flag (MIE). Each IRQ0 request flag is set to “1” regardless of the MIE value when an interrupt is generated. By setting the IRQ0 request flag to “1” by software, an interrupt can be generated. The corresponding flag of IRQ0 is set to “0” by hardware when the interrupt request is accepted by the CPU. [Description of Bits] • QWDT (bit 0) QWDT is the request flag for the watchdog timer interrupt (WDTINT). QWDT 0 1 Description No request (initial value) Request • QNMI (bit 1) QNMI is the request flag for the NMI interrupt (NMINT). QNMI 0 1 Description No request (initial value) Request Note: When an interrupt is generated by the write instruction to the interrupt request register (IRQ0), the interrupt shift cycle starts after the next 1 instruction is executed. FEUL610Q438 5-12 ML610Q438/ML610Q439 User’s Manual Chapter 5 Interrupts (INTs) 5.2.10 Interrupt Request Register 1 (IRQ1) Address: 0F019H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 IRQ1 QP07 QP06 QP05 QP04 QP03 QP02 QP01 QP00 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 IRQ1 is a special function register (SFR) to request an interrupt for each interrupt source. Each IRQ1 request flag is set to “1” regardless of the IE1 and MIE values when an interrupt is generated. In this case, an interrupt is requested to the CPU when the related flag of the interrupt enable register (IE1) is set to “1” and the master interrupt enable flag (MIE) is set to “1”. By setting the IRQ1 request flag to “1” by software, an interrupt can be generated. The corresponding flag of IRQ1 is set to “0” by hardware when the interrupt request is accepted by the CPU. [Description of Bits] • QP00 (bit 0) QP00 is the request flag for the input port P00 pin interrupt (P00INT). QP00 0 1 Description No request (initial value) Request • QP01 (bit 1) QP01 is the request flag for the input port P01 pin interrupt (P01INT). QP01 0 1 Description No request (initial value) Request • QP02 (bit 2) QP02 is the request flag for the input port P02 pin interrupt (P02INT). QP02 0 1 Description No request (initial value) Request • QP03 (bit 3) QP03 is the request flag for the input port P03 pin interrupt (P03INT). QP03 0 1 Description No request (initial value) Request • QP04 (bit 4) QP04 is the request flag for the input port P04 pin interrupt (P04INT). QP04 0 1 Description No request (initial value) Request • QP05 (bit 5) QP05 is the request flag for the input port P05 pin interrupt (P05INT). FEUL610Q438 5-13 ML610Q438/ML610Q439 User’s Manual Chapter 5 Interrupts (INTs) QP05 0 1 Description No request (initial value) Request • QP06 (bit 6) QP06 is the request flag for the input port P06 pin interrupt (P06INT). QP06 0 1 Description No request (initial value) Request • QP07 (bit 7) QP07 is the request flag for the input port P07 pin interrupt (P07INT). QP03 0 1 Description No request (initial value) Request Note: When an interrupt is generated by the write instruction to the interrupt request register (IRQ1) or to the interrupt enable register (IE1), the interrupt shift cycle starts after the next 1 instruction is executed. FEUL610Q438 5-14 ML610Q438/ML610Q439 User’s Manual Chapter 5 Interrupts (INTs) 5.2.11 Interrupt Request Register 2 (IRQ2) Address: 0F01AH Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 IRQ2 QI2C0     QSAD  QSIO0 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 IRQ2 is a special function register (SFR) to request an interrupt for each interrupt source. Each IRQ2 request flag is set to “1” regardless of the IE2 and MIE values when an interrupt is generated. In this case, an interrupt is requested to the CPU when the related flag of the interrupt enable register (IE2) is set to “1” and the master interrupt enable flag (MIE) is set to “1”. By setting the IRQ2 request flag to “1” by software, an interrupt can be generated. The corresponding flag of IRQ2 is set to “0” by hardware when the interrupt request is accepted by the CPU. [Description of Bits] • QSIO0 (bit 0) QSIO0 is the request flag for the synchronous serial port 0 interrupt (SIO0INT). QSIO0 0 1 Description No request (initial value) Request • QSAD (bit 2) QSAD is the request flag for the successive approximation type A/D converter interrupt (SADINT) QSAD 0 1 Description No request (initial value) Request • QI2C0 (bit 7) QI2C0 is the request flag for the I2C bus 0 interrupt (I2C0INT). QI2C0 0 1 Description No request (initial value) Request Note: When an interrupt is generated by the write instruction to the interrupt request register (IRQ2) or to the interrupt enable register (IE2), the interrupt shift cycle starts after the next 1 instruction is executed. FEUL610Q438 5-15 ML610Q438/ML610Q439 User’s Manual Chapter 5 Interrupts (INTs) 5.2.12 Interrupt Request Register 3 (IRQ3) Address: 0F01BH Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 IRQ3       QTM1 QTM0 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 IRQ3 is a special function register (SFR) to request an interrupt for each interrupt source. Each IRQ3 request flag is set to “1” regardless of the IE3 and MIE values when an interrupt is generated. In this case, an interrupt is requested to the CPU when the related flag of the interrupt enable register (IE3) is set to “1” and the master interrupt enable flag (MIE) is set to “1”. By setting the IRQ3 request flag to “1” by software, an interrupt can be generated. The corresponding flag of IRQ3 is set to “0” by hardware when the interrupt request is accepted by the CPU. [Description of Bits] • QTM0 (bit 0) QTM0 is the request flag for the timer 0 interrupt (TM0INT). QTM0 0 1 Description No request (initial value) Request • QTM1 (bit 1) QTM1 is the request flag for the timer 1 interrupt (TM1INT). QTM1 0 1 Description No request (initial value) Request Note: When an interrupt is generated by the write instruction to the interrupt request register (IRQ3) or to the interrupt enable register (IE3), the interrupt shift cycle starts after the next 1 instruction is executed. FEUL610Q438 5-16 ML610Q438/ML610Q439 User’s Manual Chapter 5 Interrupts (INTs) 5.2.13 Interrupt Request Register 4 (IRQ4) Address: 0F01CH Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 IRQ4   QRAD   QMD0  QUA0 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 IRQ4 is a special function register (SFR) to request an interrupt for each interrupt source. Each IRQ4 request flag is set to “1” regardless of the IE4 and MIE values when an interrupt is generated. In this case, an interrupt is requested to the CPU when the related flag of the interrupt enable register (IE4) is set to “1” and the master interrupt enable flag (MIE) is set to “1”. By setting the IRQ4 request flag to “1” by software, an interrupt can be generated. The corresponding flag of IRQ4 is set to “0” by hardware when the interrupt request is accepted by the CPU. [Description of Bits] • QUA0 (bit 0) QUA0 is the request flag for the UART0 interrupt (UA0INT). QUA0 0 1 Description No request (initial value) Request • QMD0 (bit 2) QMD0 is the request flag for the melody 0 interrupt (MD0INT). QMD0 0 1 Description No request (initial value) Request • QRAD (bit 5) QRAD is the request flag for the RC oscillation type A/D converter interrupt (RADINT). QRAD 0 1 Description No request (initial value) Request Note: When an interrupt is generated by the write instruction to the interrupt request register (IRQ4) or to the interrupt enable register (IE4), the interrupt shift cycle starts after the next 1 instruction is executed. FEUL610Q438 5-17 ML610Q438/ML610Q439 User’s Manual Chapter 5 Interrupts (INTs) 5.2.14 Interrupt Request Register 5 (IRQ5) Address: 0F01DH Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 IRQ5   QTM3 QTM2     R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 IRQ5 is a special function register (SFR) to request an interrupt for each interrupt source. Each IRQ5 request flag is set to “1” regardless of the IE5 and MIE values when an interrupt is generated. In this case, an interrupt is requested to the CPU when the related flag of the interrupt enable register (IE5) is set to “1” and the master interrupt enable flag (MIE) is set to “1”. By setting the IRQ5 request flag to “1” by software, an interrupt can be generated. The corresponding flag of IRQ5 is set to “0” by hardware when the interrupt request is accepted by the CPU. [Description of Bits] • QTM2 (bit ４) QTM2 is the request flag for the timer 2 interrupt (TM2INT). QTM2 0 1 Description No request (initial value) Request • QTM3 (bit ５) QTM3 is the request flag for the timer 3 interrupt (TM3INT). QTM3 0 1 Description No request (initial value) Request Note: When an interrupt is generated by the write instruction to the interrupt request register (IRQ5) or to the interrupt enable register (IE5), the interrupt shift cycle starts after the next 1 instruction is executed. FEUL610Q438 5-18 ML610Q438/ML610Q439 User’s Manual Chapter 5 Interrupts (INTs) 5.2.15 Interrupt Request Register 6 (IRQ6) Address: 0F01EH Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 IRQ6 Q32H Q64H Q128H QT1K  QPW2 QPW1 QPW0 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 IRQ6 is a special function register (SFR) to request an interrupt for each interrupt source. Each IRQ6 request flag is set to “1” regardless of the IE6 and MIE values when an interrupt is generated. In this case, an interrupt is requested to the CPU when the related flag of the interrupt enable register (IE6) is set to “1” and the master interrupt enable flag (MIE) is set to “1”. By setting the IRQ6 request flag to “1” by software, an interrupt can be generated. The corresponding flag of IRQ6 is set to “0” by hardware when the interrupt request is accepted by the CPU. [Description of Bits] • QPW0 (bit 0) QPW0 is the request flag for the PWM0 interrupt (PW0INT). QPW0 0 1 Description No request (initial value) Request • QPW1 (bit 1) QPW1 is the request flag for the PWM1 interrupt (PW1INT). QPW1 0 1 Description No request (initial value) Request • QPW2 (bit 2) QPW2 is the request flag for the PWM2 interrupt (PW2INT). QPW2 0 1 Description No request (initial value) Request • QT1K (bit 4) QT1K is the request flag for the 1 kHz timer interrupt (T1KINT). QT1K 0 1 Description No request (initial value) Request • Q128H (bit 5) Q128H is the request flag for the time base counter 128 Hz interrupt (T128HINT). Q128H 0 1 Description No request (initial value) Request • Q64H (bit 6) Q64H is the request flag for the time base counter 64 Hz interrupt (T64HINT). FEUL610Q438 5-19 ML610Q438/ML610Q439 User’s Manual Chapter 5 Interrupts (INTs) Q64H 0 1 Description No request (initial value) Request • Q32H (bit 7) Q32H is the request flag for the time base counter 32 Hz interrupt (T32HINT). Q32H 0 1 Description No request (initial value) Request Note: When an interrupt is generated by the write instruction to the interrupt request register (IRQ6) or to the interrupt enable register (IE6), the interrupt shift cycle starts after the next 1 instruction is executed. FEUL610Q438 5-20 ML610Q438/ML610Q439 User’s Manual Chapter 5 Interrupts (INTs) 5.2.16 Interrupt Request Register 7 (IRQ7) Address: 0F01FH Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 IRQ7    Q1H Q2H Q4H Q8H Q16H R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 IRQ7 is a special function register (SFR) to request an interrupt for each interrupt source. Each IRQ7 request flag is set to “1” regardless of the IE7 and MIE values when an interrupt is generated. In this case, an interrupt is requested to the CPU when the related flag of the interrupt enable register (IE7) is set to “1” and the master interrupt enable flag (MIE) is set to “1”. By setting the IRQ7 request flag to “1” by software, an interrupt can be generated. The corresponding flag of IRQ7 is set to “0” by hardware when the interrupt request is accepted by the CPU. [Description of Bits] • Q16H (bit 0) Q16H is the request flag for the time base counter 8 Hz interrupt (T16HINT). Q16H 0 1 Description No request (initial value) Request • Q8H (bit 1) Q8H is the request flag for the time base counter 8 Hz interrupt (T8HINT). Q8H 0 1 Description No request (initial value) Request • Q4H (bit 2) Q4H is the request flag for the time base counter 4 Hz interrupt (T4HINT). Q4H 0 1 Description No request (initial value) Request • Q2H (bit 3) Q2H is the request flag for the time base counter 2 Hz interrupt (T2HINT). Q2H 0 1 FEUL610Q438 Description No request (initial value) Request 5-21 ML610Q438/ML610Q439 User’s Manual Chapter 5 Interrupts (INTs) • Q1H (bit 5) Q1H is the request flag for the time base counter 1 Hz interrupt (T1HINT). Q1H 0 1 Description No request (initial value) Request Note: When an interrupt is generated by the instruction to write to the interrupt request register (IRQ7) or to the interrupt enable register (IE7), the the interrupt shift cycle starts after the next 1 instruction is executed. FEUL610Q438 5-22 ML610Q438/ML610Q439 User’s Manual Chapter 5 Interrupts (INTs) 5.3 Description of Operation With the exception of the watchdog timer interrupt (WDTINT) and the NMI interrupt (NMINT), interrupt enable/disable for 30 sources is controlled by the master interrupt enable flag (MIE) and the individual interrupt enable registers (IE1 to 7). WDTINT and NMIINT are non-maskable interrupts. When the interrupt conditions are satisfied, the CPU calls a branching destination address from the vector table determined for each interrupt source and the interrupt shift cycle starts to branch to the interrupt processing routine. Table 5-1 lists the interrupt sources. Table 5-1 Priority Interrupt Sources Interrupt source Symbol Vector table address 1 Watchdog timer interrupt WDTINT 0008H 2 NMI interrupt NMINT 000AH 3 P00 interrupt P00INT 0010H 4 P01 interrupt P01INT 0012H 5 P02 interrupt P02INT 0014H 6 P03 interrupt P03INT 0016H 7 P04 interrupt P04INT 0018H 6 P05 interrupt P05INT 001AH 9 P06 interrupt P06INT 001CH 10 P07 interrupt P07INT 001EH 11 SIO0INT 0020H SADINT 0024H 13 Synchronous serial port 0 interrupt Successive approximation type A/D converter interrupt 2 I C bus 0 interrupt I2C0INT 002EH 14 Timer 0 interrupt TM0INT 0030H 15 Timer 1 interrupt TM1INT 0032H 16 UART 0 interrupt UA0INT 0040H 17 MD0INT 0044H RADINT 004AH 19 Melody 0 interrupt RC oscillation type A/D converter interrupt Timer 2 interrupt TM2INT 0058H 20 Timer 3 interrupt TM3INT 005AH 21 PWM0 interrupt PW0INT 0060H 22 PWM1 interrupt PW1INT 0062H 23 PWM2 interrupt PW2INT 0064H 12 18 24 1 kHz timer interrupt T1KINT 0068H 25 TBC128Hz interrupt T128HINT 006AH 26 TBC64Hz interrupt T64HINT 006CH 27 TBC32Hz interrupt T32HINT 006EH 28 TBC16Hz interrupt T16HINT 0070H 29 TBC8Hz interrupt T8HINT 0072H 30 TBC4Hz interrupt T4HINT 0074H 31 TBC2Hz interrupt T2HINT 0076H 32 TBC1Hz interrupt T1HINT 0078H Note: - When multiple interrupts are generated concurrently, the interrupts are serviced according to this priority and processing of low-priority interrupts is pending. - Please define vector tables for all unused interrupts for fail safe. FEUL610Q438 5-23 ML610Q438/ML610Q439 User’s Manual Chapter 5 Interrupts (INTs) 5.3.1 Maskable Interrupt Processing When an interrupt is generated with the MIE flag set to “1”, the following processing is executed by hardware and the processing of program shifts to the interrupt destination. (1) (2) (3) (4) (5) (6) Transfer the program counter (PC) to ELR1. Transfer CSR to ECSR1. Transfer PSW toEPSW1. Set the MIE flag to “0”. Set the ELEVEL field to“1”. Load the interrupt start address into PC. 5.3.2 Non-Maskable Interrupt Processing When an interrupt is generated regardless of the state of MIE flag, the following processing is performed by hardware and the processing of program shifts to the interrupt destination. (1) (2) (3) (4) (5) Transfer PC to ELR2. Transfer CSR to ECSR2. Transfer PSW to EPSW2. Set the ELEVEL field to “2”. Load the interrupt start address into PC. 5.3.3 Software Interrupt Processing A software interrupt is generated as required within an application program. When the SWI instruction is performed within the program, a software interrupt is generated, the following processing is performed by hardware, and the processing program shifts to the interrupt destination. The vector table is specified by the SWI instruction. (1) (2) (3) (4) (5) (6) Transfer PC to ELR1. Transfer CSR to ECSR1. Transfer PSW to EPSW1. Set the MIE flag to “0”. Set the ELEVEL field to “1”. Load the interrupt start address into PC. Reference: For the MIE flag, Program Counter (PC), CSR, PSW, and ELEVEL, see “nX-U8/100 Core Instruction Manual”. FEUL610Q438 5-24 ML610Q438/ML610Q439 User’s Manual Chapter 5 Interrupts (INTs) 5.3.4 Notes on Interrupt Routine Notes are different in programming depending on whether a subroutine is called or not by the program in executing an interrupt routine, whether multiple interrupts are enabled or disabled, and whether such interrupts are maskable or non-maskable. State A: Maskable interrupt is being processed A-1: When a subroutine is not called by the program in executing an interrupt routine A-1-1: When multiple interrupts are disabled • Processing immediately after the start of interrupt routine execution No specific notes. • Processing at the end of interrupt routine execution Specify the RTI instruction to return the contents of the ELR register to the PC and those of the EPSW register to PSW. A-1-2: When multiple interrupts are enabled • Processing immediately after the start of interrupt routine execution Specify “PUSH ELR, EPSW” to save the interrupt return address and the PSW status in the stack. • Processing at the end of interrupt routine execution Specify “POP PC, PSW” instead of the RTI instruction to return the contents of the stack to PC and PSW. Example of description: State A-1-1 Example of description: State A-1-2 Intrpt_A-1-1; Intrpt_A-1-2; DI : : : RTI FEUL610Q438 ; A-1-1 state ; Disable interrupt PUSH ELR, EPSW ; Return PC from ELR ; Return PSW form EPSW ; End EI : : : : : POP PC, PSW ; Start ; Save ELR and EPSW at the beginning ; Enable interrupt ; Return PC from the stack ; Return PSW from the stack ; End 5-25 ML610Q438/ML610Q439 User’s Manual Chapter 5 Interrupts (INTs) A-2: When a subroutine is called by the program in executing an interrupt routine A-2-1: When multiple interrupts are disabled • Processing immediately after the start of interrupt routine execution Specify the “PUSH LR” instruction to save the subroutine return address in the stack. • Processing at the end of interrupt routine execution Specify “POP LR” immediately before the RTI instruction to return from the interrupt processing after returning the subroutine return address to LR. A-2-2: When multiple interrupts are enabled • Processing immediately after the start of interrupt routine execution Specify “PUSH LR, ELR, EPSW” to save the interrupt return address, the subroutine return address, and the EPSW status in the stack. • Processing at the end of interrupt routine execution Specify “POP PC, PSW, LR” instead of the RTI instruction to return the saved data of the interrupt return address to PC, the saved data of EPSW to PSW, and the saved data of LR to LR. Example of description: A-2-2 Intrpt_A-2-2; PUSH ELR, EPSW, LR ; Start ; Save ELR, EPSW, LR at the beginning EI : : : ; Enable interrupt BL Sub_1 : POP PC, PSW, LR ; Call subroutine Sub_1 FEUL610Q438 Sub_1; DI RT ; Return PC from the stack ; Return PSW from the stack ; Return LR from the stack ; End ; ; Disable interrupt : : : ; Return PC from LR ; End of subroutine 5-26 ML610Q438/ML610Q439 User’s Manual Chapter 5 Interrupts (INTs) State B: Non-maskable interrupt is being processed B-1: When no instruction is executed in an interrupt routine • Processing immediately after the start of interrupt routine execution Specify the RTI instruction to return the contents of the ELR register to the PC and those of the EPSW register to PSW. B-2: When one or more instructions are executed in an interrupt routine B-2-1: When a subroutine is not called by the program in executing an interrupt routine • Processing immediately after the start of interrupt routine execution Specify “PUSH ELR, EPSW” to save the interrupt return address and the PSW status in the stack. • Processing at the end of interrupt routine execution Specify “POP PC, PSW” instead of the RTI instruction to return the contents of the stack to PC and PSW. B-2-2: When a subroutine is called by the program in executing an interrupt routine • Processing immediately after the start of interrupt routine execution Specify “PUSH LR, ELR, EPSW” to save the interrupt return address, the subroutine return address, and the EPSW status in the stack. • Processing at the end of interrupt routine execution Specify “POP PC, PSW, LR” instead of the RTI instruction to return the saved data of the interrupt return address to PC, the saved data of EPSW to PSW, and the saved data of LR to LR.. Example of description: B-1 Intrpt_B-1: RTI Example of description: B-2-1 ; B-1 state ; Return PC from ELR Intrpt_B-2-1: ; Start PUSH ELR，EPSW ; Save ELR, EPSW at the beginning ; Return PSW form EPSW ; End : : : POP PC，PSW ; Return PC from the stack ; Return PSW from the stack ; End Example of description: B-2-2 Intrpt_B-2-2: PUSH ELR,EPSW,LR ; Start ; Save ELR, EPSW, LR at the beginning : Sub_1: : : : : ； : BL Sub_1 ; Call subroutine Sub_1 : POP PC，PSW，LR : RT ; Return PC from the stack ; Return PC from LR ; End of subroutine ; Return PSW from the stack ; Return LR from the stack ; End FEUL610Q438 5-27 ML610Q438/ML610Q439 User’s Manual Chapter 5 Interrupts (INTs) 5.3.5 Interrupt Disable State Even if the interrupt conditions are satisfied, an interrupt may not be accepted depending on the operating state. This is called an interrupt disabled state. See below for the interrupt disabled state and the handling of interrupts in this state. Interrupt disabled state 1: Between the interrupt shift cycle and the instruction at the beginning of the interrupt routine When the interrupt conditions are satisfied in this section, an interrupt is generated immediately following the execution of the instruction at the beginning of the interrupt routine corresponding to the interrupt that has already been enabled. Interrupt disabled state 2: Between the DSR prefix instruction and the next instruction When the interrupt conditions are satisfied in this section, an interrupt is generated immediately after execution of the instruction following the DSR prefix instruction. Reference: For the DSR prefix instruction, see “nX-U8/100 Core Instruction Manual”. FEUL610Q438 5-28 Chapter 6 Clock Generation Circuit ML610Q438/ML610Q439 User’s Manual Chapter 6 Clock Generation Circuit 6. Clock Generation Circuit 6.1 Overview The clock generation circuit generates and provides a low-speed clock (LSCLK), 2× low-speed clock (LSCLK2), a high-speed clock (HSCLK), a system clock (SYSCLK), and a high-speed output clock (OUTCLK). LSCLK, LSCLK×2, and HSCLK are time base clocks for the peripheral circuits, SYSCLK is a basic operation clock of CPU, and OUTCLK is a clock that is output from a port. For the OUTCLK output port, see Chapter 19, “Port 2”. Additionally, for the STOP mode described in this chapter, see Chapter 4, “MCU Control Function”, and for BLD, see Chapter 27, “Battery Level Detection Circuit”. 6.1.1 Features • Low-speed clock: 32.768 kHz crystal oscillation mode − Capable of generating LSCLK × 2 (64 kHz) to be used for some peripherals. • High-speed clock: Software selection − 500 kHz RC oscillation mode − Crytal/ceramic oscillation mode − Built-in PLL oscillation mode − External clock input mode − 2 MHz RC oscillation mode 6.1.2 Configuration Figure 6-1 shows the configuration of the clock generation circuit. 2× low-speed clock (LSCLK×2) XT0 Low-speed clock (LSCLK) MPX XT1 Low-speed clock generation circuit P10/OSC0 P11/OSC1 High-speed clock generation circuit OSCLK System clock (SYSCLK) Divide ratio selection 1/1, 1/2, 1/4, 1/8 High-speed clock (HSCLK) Divide ratio selection 1/1, 1/2, 1/4, 1/8 High-speed output clock (OUTCLK) FCON0, FCON1 Data bus FCON0 FCON1 : Frequency control register 0 : Frequency control register 1 Figure 6-1 Configuration of Clock Generation Circuit Note: This LSI starts operation with a clock generated by dividing the 500 kHz RC oscillation frequency by 8 after power-on or a system reset. At initialization by software, set the FCON0 or FCON1 register to switch the clock to a required one. Operation of this LSI is not guaranteed under a condition where a low-speed clock is not supplied. FEUL610Q438 6 -1 ML610Q438/ML610Q439 User’s Manual Chapter 6 Clock Generation Circuit 6.1.3 List of Pins Pin name XT0 XT1 I/O I O P10/OSC0 I P11/OSC1 O Description Pin for connecting a crystal for low-speed clock Pin for connecting a crystal for low-speed clock Pin for connecting a crystal/ceramic resonator for high-speed clock Used for the secondary function of the P10 pin Pin for connecting a crystal/ceramic resonator for high-speed clock Used for the secondary function of the P11 pin 6.2 Description of Registers 6.2.1 List of Registers Address 0F002H 0F003H FEUL610Q438 Name Frequency control register 0 Frequency control register 1 Symbol (Byte) Symbol (Word) R/W Size FCON0 FCON1 FCON R/W R/W 8/16 8 Initial value 33H 03H 6 -2 ML610Q438/ML610Q439 User’s Manual Chapter 6 Clock Generation Circuit 6.2.2 Frequency Control Register 0 (FCON0) Address: 0F002H Access: R/W Access size: 8/16 bits Initial value: 33H 7 6 5 4 3 2 1 0 FCON0  OSCM2 OUTC1 OUTC0 OSCM1 OSCM0 SYSC1 SYSC0 R/W Initial value R/W 0 R/W 0 R/W 1 R/W 1 R/W 0 R/W 0 R/W 1 R/W 1 FCON0 is a special function register (SFR) to control the high-speed clock generation circuit and to select system clock. [Description of Bits] • SYSC1, SYSC0 (bits 1, 0) The SYSC1 and SYSC0 bits are used to select the frequency of the high-speed clock (HSCLK) used for system clock and periphera1 circuits (including high-speed time base counter). OSCLK, 1/2OSCLK, 1/4OSCLK, or 1/8OSCLK can be selected. The maximum operating frequency guaranteed for the system clock (SYSCLK) of this LSI is 4.2 MHz. At system reset, 1/8OSCLK is selected. SYSC1 0 0 1 1 SYSC0 0 1 0 1 Description OSCLK (1/2OSCLK in built-in PLL oscillation mode) 1/2OSCLK 1/4OSCLK 1/8OSCLK (initial value) • OSCM2, OSCM1, OSCM0 (bits 6, 3, 2) The OSCM2, OSCM1 and OSCM0 bits are used to select the mode of the high-speed clock generation circuit. 500kHz RC oscillation mode, crystal/ceramic oscillation mode, PLL oscillation mode, external clock input mode, or 2MHz RC oscillation mode can be selected. The setting of OSCM1 and OSCM0 can be changed only when high-speed oscillation is being stopped (ENOSC bit of FCON1 is “0”). At system reset, RC oscillation mode is selected. − When switching the high-speed oscillation mode, please first switch back to low speed clock before switching to other high-speed clock (set the ENOSC bit and SYSCLK bit of FCON1 to “0”). OSCM2 0 0 0 0 1 OSCM1 0 0 1 1 X OSCM0 0 1 0 1 X Description 500kHz RC oscillation mode (initial value) Crystal/ceramic oscillation mode Built-in PLL oscillation mode External clock input mode 2MHz RC oscillation mode • OUTC1, OUTC0 (bits 5, 4) The OUTC1 and OUTC0 bits are used to select the frequency of the high-speed output clock which is output when the secondary function of the port is used. OSCLK, 1/2OSCLK, 1/4OSCLK, or 1/8OSCLK can be selected. At system reset, 1/8OSCLK is selected. OUTC1 0 0 1 1 FEUL610Q438 OUTC0 0 1 0 1 Description OSCLK 1/2OSCLK 1/4OSCLK 1/8OSCLK (initial value) 6 -3 ML610Q438/ML610Q439 User’s Manual Chapter 6 Clock Generation Circuit Note: − To switch the mode of the high-speed clock generation circuit using the OSCM2, OSCM1 and OSCM0 bits, stop the high-speed oscillation and set the system clock to the low-speed clock (set the ENOSC bit and SYSCLK of FCON1 to “0”). − The oscillators that are connected to the P10/OSC0 and P11/OSC1 pins must not exceed 4.2 MHz. In external clock mode, input a clock that does not exceed 4.2 MHz. When a built-in PLL oscillation mode is selected (OSCM2 = “0”, OSCM1 = “1”, OSCM0 = “0”), 1/2OSCLK (about 4.096 MHz) is output as HSCLK even if OSCLK (SYSC0 = “0”, SYSC1 = “1”) is selected. − When built-in PLL (about 8.192 MHz) oscillation mode is selected (OSCM2 = “0”, OSCM1 = “1”, OSCM0 = “0”), 1/2OSCLK (about 4.096 MHz) is output as HSCLK even if OSCLK (SYSC0 = “0”, SYSC1 = “1”) is selected. FEUL610Q438 6 -4 ML610Q438/ML610Q439 User’s Manual Chapter 6 Clock Generation Circuit 6.2.3 Frequency Control Register 1 (FCON1) Address: 0F003H Access: R/W Access size: 8 bits Initial value: 03H 7 6 5 4 3 2 1 0 FCON1 LPLL     ENMLT ENOSC SYSCLK R/W Initial value R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 1 R/W 1 FCON1 is a special function register (SFR) to control the high-speed clock generation circuit and to select system clock. [Description of Bits] • SYSCLK (bit 0) The SYSCLK bit is used to select system clock. It allows selection of the low-speed clock (LSCLK) or HSCLK (1/nOSCLK: n = 1, 2, 4, 8) selected by using the high-speed clock frequency select bit (SYSC1, 0) of FCON0. When the oscillation of high-speed clock is stopped (ENOSC bit = “0”), the SYSCLK bit is fixed to “0” and the low-speed clock (LSCLK) is selected for system clock. SYSCLK 0 1 Description LSCLK HSCLK (initial value) • ENOSC (bit 1) The ENOSC bit is used to select enable/disable of the oscillation of the high-speed clock oscillator. ENOSC 0 1 Description Disables high-speed oscillation Enables high-speed oscillation (initial value) • ENMLT (bit 2) The ENMLT bit is used to select enable/disable of the operation of the 2× low-speed clock (LSCLK×2). ENMLT 0 1 Description Disables 2× low-speed clock operation (initial value) Enables 2× low-speed clock operation • LPLL (bit 7) The LPLL bit is used as a flag to indicate the oscillation state of PLL oscillation. When the LPLL bit is set to “1”, this indicates that the PLL oscillation frequency is locked within 8.192 MHz±2.5%. When the LPLL bit is set to “0”, this indicates that the PLL oscillation is inactive or the PLL oscillation frequency is not within 8.192 MHz±2.5%. LPLL is a read-only bit. LPLL 0 1 FEUL610Q438 Description Disables the use of PLL oscillation (initial value) Enables the use of PLL oscillation 6 -5 ML610Q438/ML610Q439 User’s Manual Chapter 6 Clock Generation Circuit 6.3 Description of Operation 6.3.1 Low-Speed Clock 6.3.1.1 Low-Speed Clock Generation Circuit Figure 6-2 shows the configuration of the low-speed clock generation circuit. A low-speed clock generation circuit is provided with an external 32.768 kHz crystal. To match the oscillation frequency by using a trimmer capacitor, connect external capacitors (CGL and CDL) as required. In STOP mode, VDDX is powered off to stop low-speed oscillation, and the XT0 and XT1 pins become Hiz (Hi Impedance state). When the ENMLT bit of FCON1 is set to “1”, the 2× low-speed clock circuit starts to generate the LSCLK×2(64kHz) VDDX 32.768 kHz crystal Control Circuit CGL STOP mode XT0 Low-speed clock (LSCLK) CG RF VSS CDL XT1 CD VSS 2× clock circuit 2× low-speed clock (LSCLK×2) ENMLT VSS Figure 6-2 Circuit Configuration of 32.768 kHz Crystal Oscillation Mode Notes: − Install a crystal as close to the LSI as possible and make sure that signals causing noise and power supply wiring are not near the crystal and its wiring. − Note that oscillation may stop due to condensation. − The internal loading capacitance CG=CD=12pF (Typ.) exist in the low-speed clock generation circuit. This value does not include parasitic bond and package capacitance. FEUL610Q438 6 -6 ML610Q438/ML610Q439 User’s Manual Chapter 6 Clock Generation Circuit 6.3.1.2 Operation of Low-Speed Clock Generation Circuit The low-speed clock generation circuit is activated by the occurrence of power ON reset. A low-speed clock (LSCLK) is supplied to the peripheral circuits after the elapse of the low-speed oscillation start period (TXTL ) and oscillation stabilization period (8192 counts) after powered on. The low-speed clock generation circuit stops the oscillation in STOP mode. When oscillation is resumed by releasing of the STOP mode by external interrupt, LSCLK is supplied to the peripheral circuits after the elapse of the low-speed oscillation start period (TXTL) and low-speed clock (LSCLK) oscillation stabilization period. For STOP mode, see Chapter 4, “MCU Control Function”. Figure 6-3 shows the waveforms of the low-speed clock generation circuit. For the low-speed oscillation start time (TXTL), see Appendix C, “Electrical Characteristics”. Power supply VDD RESET TXTL: Oscillation start time Low-speed clock oscillation waveform TXTL: Oscillation start time Low-speed clock oscillation waveform Reset of voltage regulator for low-speed oscillation RESET_VRX Low-speed oscillation Count: 4096 Low-speed oscillation Count: 8192 Low-speed clock LSCLK Low-speed clock oscillation waveform Low-speed oscillation Count: 4096 LSCLK waveform Start of LSCLK supply Low-speed oscillation Count: 8192 STOP mode LSCLK waveform Start of LSCLK supply Occurrence of external interrupt Figure 6-3 Operation of Low-Speed Clock Generation Circuit Note: After the power supply is turned on, CPU starts operation with a high-speed clock (500 kHz RC oscillation). It is recommended to switch to the low-speed clock after confirming that the low-speed clock is oscillating by checking that the 128 Hz interrupt request bit (Q128H) of the low-speed time base counter is “1”. If the clock is switched before the low-speed clock oscillates, the CPU stops operation until oscillation of the low-speed clock starts. FEUL610Q438 6 -7 ML610Q438/ML610Q439 User’s Manual Chapter 6 Clock Generation Circuit 6.3.2 High-Speed Clock Setting of the OSCM2, OSCM1 and OSCM0 bits of the frequency control register 0 (FCON0) allows selection of the 500 kHz RC oscillation mode, crysta/ceramic oscillation mode, built-in PLL (Phase Locked Loop) oscillation mode, or external clock input mode for the high-speed clock generation circuit. 6.3.2.1 500 kHz RC Oscillation In 500kHz RC oscillation mode (OSCM2 = “0”, OSCM0 = “0”, OSCM1 = “0”), supply of OSCLK (high-speed oscillation clock) is started when 500kHz RC oscillation clock pulse count reaches 128 after oscillation is enabled (ENOSC is set to “1”). In 500 kHz RC oscillation mode, both the P10/OSC0 pin and the P11/OSC1 pin can be used as general-purpose input ports. Figure 6-4 shows the circuit configuration in 500kHz RC oscillation mode. VDDL STOP mode RC oscillation circuit Figure 6-4 ENOSC (Enables oscillation) Count: 128 OSCLK (High-speed oscillation clock) Circuit Configuration in RC Oscillation Mode Notes: − The 500kHz-RC oscillation mode is allowed within the range of VDD = 1.3 V to 3.6 V. − After system reset mode is released, supply of OSCLK starts after the RC oscillation clock pulse count reaches 8192. After release of a STOP mode, supply of OSCLK starts. FEUL610Q438 6 -8 ML610Q438/ML610Q439 User’s Manual Chapter 6 Clock Generation Circuit 6.3.2.2 Crystal/Ceramic Oscillation Mode In crystal/ceramic oscillation mode, both the P10/OSC0 pin and the P11/OSC1 pin are used for crystal ceramic oscillation. In crystal/ceramic oscillation mode, a crystal or a ceramic resonator is externally connected to the P10/OSC0 and P11/OSC1 pins. If the high-speed oscillation clock pulse count reaches 4096 after oscillation enable, the clock is output to OSCLK (high-speed oscillation clock). Figure 6-5 shows the circuit configuration in crystal/ceramic oscillation mode. VDD 4.096 MHz crystal/ceramic oscillator CGH STOP mode ENOSC (Enables oscillation) P10/OSC0 Count: 4096 OSCLK (High-speed oscillation clock) RFH CDH P11/OSC1 VSS Figure 6-5 Circuit Configuration in Crystal/Ceramic Oscillation Mode Notes: − The crystal/ceramic oscillation mode can be used within a VDD range of 1.8 V to 3.6 V. Select a frequency according to the operating voltage range by using the power supply voltage detection circuit (BLD). See Chapter 27, “Battery Level Detection Circuit” for details of BLD. − Install a crystal or a ceramic resonator as close to the LSI as possible and make sure that signals causing noise and power supply wiring are not near the crystal or the ceramic resonator and their wiring. − Note that oscillation may stop due to condensation. − The crystal or the ceramic resonator connected to the P10/OSC0 and P11/OSC1 pins should not exceed the guaranteed maximum operation frequency of 4.2 MHz of the system clock (SYSCLK) of this LSI. FEUL610Q438 6 -9 ML610Q438/ML610Q439 User’s Manual Chapter 6 Clock Generation Circuit 6.3.2.3 Built-in PLL Oscillation Mode The PLL oscillation circuit generates a clock of 8.192 MHz (= 32.768 kHz × 250) ±2.5%. When the PLL oscillation clock (OSCLK) reaches within 8.192 MHz±2.5%, the LPLL flag of FCON1 is set. In built-in PLL oscillation mode (OSCM2 = “0”, OSCM0 = “0”, OSCM1 = “1”), supply of OSCLK (high-speed oscillation clock) is started when PLL oscillation clock pulse count reaches 4096 after oscillation is enabled (ENOSC is set to “1”). In PLL oscillation mode, both the P10/OSC0 pin and the P11/OSC1 pin can be used as general-purpose input ports. Figure 6-6 shows the circuit configuration in PLL oscillation mode. VDDL STOP mode PLL oscillation circuit 32.768 kHz ENOSC (Enables oscillation) Count: 4096 Figure 6-6 OSCLK (High-speed oscillation clock) Circuit Configuration in PLL Oscillation Mode Note: The PLL oscillation mode can be used within a VDD range of 1.8 V to 3.6 V. Select a frequency according to the operating voltage range by using the power supply voltage detection circuit (BLD). When OSCLK is selected through SYSC1 or SYSC0 of FCON0 in PLL oscillation mode, about 4.096MHz, which is the same as 1/2OSCLK, is selected. To use a PLL oscillation mode, a frequency of low-speed crystal oscillation 32.768kHz is necessary. The frequency of 32.768kHz is not adjusted by the frequency adjustment circuit of the time base counter. 6.3.2.4 External Clock Input Mode In external clock input mode, external clock is input from the P10/OSC0 pin. The P11/OSC1 pin can be used as a general-purpose input port. Figure 6-7 shows the circuit configuration in external clock input mode. VDD STOP mode ENOSC (Enables oscillation) External clock input P10/OSC0 Figure 6-7 High-speed oscillation clock (OSCLK) Circuit Configuration in External Clock Input Mode Notes: − The external clock input mode can be used within a VDD range of 1.8 V to 3.6 V. Select a frequency according to the operation voltage range by using the power supply voltage detection circuit (BLD). − Since the diodes are included between the P10/OSC0 pin and VDD and between the P10/OSC0 pin and VSS, do not apply voltages higher than VDD and lower than VSS to the P10/OSC0 pin. − If the P10/OSC0 pin is left open in external clock input mode, excessive current can flow. Therefore, make sure that the “H” level (VDD) or the “L” level (VSS) is input. − The clock that is input should not exceed the guaranteed maximum operating frequency 4.2 MHz of the system clock (SYSCLK) of this LSI. FEUL610Q438 6 -10 ML610Q438/ML610Q439 User’s Manual Chapter 6 Clock Generation Circuit 6.3.2.5 2 MHz RC Oscillation In 2Mhz RC oscillation mode (OSCM2 = “1”, OSCM0 = “X”, OSCM1 = “X”), supply of OSCLK (high-speed oscillation clock) is started when 2MHz RC oscillation clock pulse count reaches 2048 after oscillation is enabled (ENOSC is set to “1”). In 2 MHz RC oscillation mode, both the P10/OSC0 pin and the P11/OSC1 pin can be used as general-purpose input ports. Figure 6-8 shows the circuit configuration in 2MHz RC oscillation mode. VDDL STOP mode RC oscillation ENOSC (Enables oscillation) circuit Count: 2048 Figure 6-8 OSCLK (High-speed oscillation clock) Circuit Configuration in 2MHz RC Oscillation Mode Notes: − The 2MHz RC osillation mode can be used within a VDD range of 1.8 V to 3.6 V. Select a frequency according to the operation voltage range by using the power supply voltage detection circuit (BLD). FEUL610Q438 6 -11 ML610Q438/ML610Q439 User’s Manual Chapter 6 Clock Generation Circuit 6.3.2.6 Operation of High-Speed Clock Generation Circuit The high-speed clock generation circuit is activated in 500Hz RC oscillation mode by power-on reset generation. As a result of the occurrence of power-on reset, the circuit goes into system reset mode and then shifts to program operating mode after the elapse of the high-speed RC oscillation start time (TRC) and the oscillation stabilization time (Count: 8192) of the high-speed oscillation clock (OSCLK) and at the same time, a high-speed clock (HSCLK) is supplied to the peripheral circuits. Figure 6-9 shows the waveforms of the high-speed clock generation circuit at power on. For the high-speed RC oscillation start time (TRC), see Appendix C, “Electrical Characteristics”. Power supply VDD RESET TRC: Oscillation start time High-speed oscillation clock waveform High-speed clock HSCLK System clock SYSCLK High-speed oscillation clock waveform High-speed oscillation Count: 8192 HSCLK waveform SYSCLK waveform CPU start Figure 6-9 Operation of High-Speed Clock Generation Circuit at Power-On The high-speed clock generation circuit allows selection of an oscillation mode and start/stop of oscillation by using the frequency control registers 0 and 1 (FCON0 and FCON1). Oscillation can be started by setting the ENOSC bit to “1” after selecting a high-speed oscillation mode in FCON0 and a high-speed oscillation frequency. After the start of oscillation, HSCLK starts supply of a clock to the peripheral circuits following the elapse of the high-speed oscillation start period (TRC/TXTH/TPLL) in each mode and the oscillation stabilization period of the high-speed oscillation clock (OSCLK). The high-speed clock generation circuit stops oscillation when it shifts to a STOP mode by the software. When the STOP mode is released by external interrupt, HSCLK supplies clocks to peripheral circuits following the elapse of the high-speed oscillation start period (TRC/TXTH/TPLL) in each mode and the oscillation stabilization period of the high-speed clock (OSCLK). The oscillation stabilization period is the duration of 128 clock pulses in 500 kHz RC oscillation mode and external clock input mode and the duration of 4096 clock pulses in the crystal/ceramic oscillation mode and PLL oscillation mode. FEUL610Q438 6 -12 ML610Q438/ML610Q439 User’s Manual Chapter 6 Clock Generation Circuit Figure 6-10 shows the waveforms of the high-speed clock generation circuit in crystal/ceramic oscillation mode. High-speed oscillation enable ENOSC TXTH/TPLL: High-speed/PLL oscillation start time High-speed oscillation waveform High-speed clock HSCLK High-speed oscillation waveform TXTH/TPLL: High-speed/PLL oscillation start time High-speed oscillation waveform High-speed oscillation Count: 4096 HSCLK waveform High-speed oscillation Count: 4096 HSCLK waveform TXTL: Low-speed/PLL oscillation start time Low-speed clock oscillation waveform Low-speed clock oscillation waveform Start of high-speed oscillation Low-speed clock oscillation waveform Generation of external interrupt Figure 6-10 Stop of high-speed oscillation STOP mode Restart of program Operation of High-Speed Clock Generation Circuit in Crystal/Ceramic Oscillation Mode FEUL610Q438 6 -13 ML610Q438/ML610Q439 User’s Manual Chapter 6 Clock Generation Circuit 6.3.3 Switching of System Clock The system clock can be switched between high-speed clock (HSCLK) and low-speed clock (LSCLK) by using the frequency control registers (FCON0, FCON1). Figure 6-11 shows a flow of system clock switching processing (HSCLK→LSCLK) and Figure 6-12 shows a flow of system clock switching processing (LSCLK→HSCLK). System clock switching SYSCLK←”0” System clock switching (High-speed clock→Low-speed clock) Stop of high-speed oscillation (* do not need to stop the oscillation if the high-speed clock is used for any peripheral) ENOSC←”0” Low-speed operation mode Figure 6-11 Flow of System Clock Switching Processing (HSCLK→LSCLK) Note: After the power is turned on or if the system clock is switched from HSCLK to LSCLK immediately following return from the STOP mode, the CPU becomes inactive until LSCLK starts clock supply to the peripheral circuits. Therefore, It is recommended to switch to LSCLK after confirming that the LSCLK is oscillating by checking that the time base counter interrupt request bit (Q128H) is “1”. FEUL610Q438 6 -14 ML610Q438/ML610Q439 User’s Manual Chapter 6 Clock Generation Circuit Set high-speed oscillation mode before switching the system clock. System clock switching 500 kHz RC used? Yes No When using crystal/ceramic oscillation, PLL oscillation, an external clock mode, or 2 MHz RC oscillation mode check that VDD is 1.8V or higher by using BLD. Voltage detection by BLD VDD ≥ 1.8V? Yes ENOSC←”1” Wait until oscillation stabilizes (TWAIT) SYSCLK←”1” No Crystal/ceramic oscillation, PLL oscillation, external clock input mode, and 2 MHz RC oscillation mode cannot be used. Use 500 kHz RC oscillation mode or low-speed clock (LSCLK). As necessary, check VDD 1.3V or higher for using the 500kHz RC oscillation clock. Start of high-speed oscillation TWAIT = 500 µs @500 kHz RC oscillation mode TWAIT = 20 ms @Crystal/ceramic oscillation mode TWAIT = 10 ms @PLL oscillation mode TWAIT = 1 ms @Internal clock input mode TWAIT = 3 ms @2 MHz RC oscillation mode System clock switching (Low-speed clock→High-speed clock) High-speed operation mode Figure 6-12 Flow of System Clock Switching Processing (LSCLK→HSCLK) Note: If the system clock is switched from a low-speed clock to a high-speed clock before the high-speed clock (HSCLK) starts oscillation, the CPU becomes inactive until HSCLK starts clock supply to the peripheral circuits. FEUL610Q438 6 -15 ML610Q438/ML610Q439 User’s Manual Chapter 6 Clock Generation Circuit 6.4 Specifying port registers When you want to make sure clock output functions are working, please check related port registers are specified. See Chapter 19, “Port2” for detail about the port registers. 6.4.1 Functioning P21 (OUTCLK) as the high speed clock output Set P21MD bit (bit1 of P2MOD register) to “1” for specifying the high speed clock output as the secondary function of P21. Reg. name P2MOD register (Address: 0F214H) Bit 7 6 5 4 3 2 1 0 Bit name - - - - - P22MD P21MD P20MD Data - - - - - * 1 * Set P21C1 bit (bit1 of P2CON1 register) to “1” and set P21C0 bit(bit1 of P2CON0 register) to “1”, for specifying the P21 as CMOS output. Reg. name P2CON1 register (Address: 0F213H) Bit 7 6 5 4 3 2 1 0 Bit name - - - - - P22C1 P21C1 P20C1 Data - - - - - * 1 * Bit 7 6 5 4 3 2 1 0 Bit name - - - - - P22C0 P21C0 P20C0 Data - - - - - * 1 * Reg. name P2CON0 register (Address: 0F212H) Data of P21D bit (bit1 of P2D register) does not affect to the high speed clock output function, so don’t care the data for the function. Reg. name P2D register (Address: 0F210H) Bit 7 6 5 4 3 2 1 0 Bit name - - - - - P22D P21D P20D Data - - - - - * ** * - : Bit does not exist. * : Bit not related to the high speed clock function ** : Don’t care the data. Note: P21(Port2) is an output-only port, does not have an register to select the data direction(input or output). FEUL610Q438 6 -16 ML610Q438/ML610Q439 User’s Manual Chapter 6 Clock Generation Circuit 6.4.2 Functioning P20 (LSCLK) as the low speed clock output Set P20MD bit (bit0 of P2MOD register) to “1” for specifying the low speed clock output as the secondary function of P22. Reg. name P2MOD register (Address: 0F214H) Bit 7 6 5 4 3 2 1 0 Bit name - - - - - P22MD P21MD P20MD Data - - - - - * * 1 Set P20C1 bit (bit0 of P2CON1 register) to “1” and P20C0 bit (bit0 of P2CON0 register), for specifying P20 as CMOS output. Reg. name P2CON1 register (Address: 0F213H) Bit 7 6 5 4 3 2 1 0 Bit name - - - - - P22C1 P21C1 P20C1 Data - - - - - * * 1 Reg. name P2CON0 register (Address: 0F212H) Bit 7 6 5 4 3 2 1 0 Bit name - - - - - P22C0 P21C0 P20C0 Data - - - - - * * 1 Data of P20D bit (bit0 of P2D register) does not affect to the low speed clock output function, so don’t care the data for the function. Reg. name P2D register (Address: 0F210H) Bit 7 6 5 4 3 2 1 0 Bit name - - - - - P22D P21D P20D Data - - - - - * * ** - : Bit does not exist. * : Bit not related to the low speed clock function ** : Don’t care the data. Note: P20(Port2) is an output-only port, does not have an register to select the data direction(i.e. input or output). FEUL610Q438 6 -17 Chapter 7 Time Base Counter ML610Q438/ML610Q439 User’s Manual Chapter 7 Time Base Counter 7. Time Base Counter 7.1 Overview This LSI includes a low-speed time base counter (LTBC) and a high-speed time base counter (HTBC) that generate base clocks for peripheral circuits. By using the time base counter, it is possible to generate events periodically. For input clocks, see Chapter 6, “Clock Generation Circuit”. For interrupt permission, interrupt request flags, etc., described in this chapter, see Chapter 5, “Interrupts”. 7.1.1 Features • LTBC generates T32KHZ to T1HZ signals by dividing the low-speed clock (LSCLK) frequency. • LTBC allows frequency adjustment (Adjustment range: Approx. −488ppm to +488ppm. Adjustment accuracy: Approx. 0.48ppm) by using the low-speed time base counter frequency adjustment registers (LTBADJH and LTBADJL). • HTBC generates HTB1 to HTB32 signals by dividing the high-speed clock (HSCLK) frequency. • Capable of generating 128Hz , 64Hz , 32Hz , 16Hz , 8Hz , 4Hz , 2Hz, and 1Hz interrupts. 7.1.2 Configuration Figure 7-1 and Figure 7-2 show the configuration of a low-speed time base counter and a high-speed time base counter, respectively. T32KHZ T16KHZ T8KHZ T4KHZ T2KHZ T1KHZ T512HZ T256HZ T128HZ T64HZ T32HZ T16HZ T8HZ T4HZ T2HZ T1HZ 7-bit Counter LSCLK (32.768 kHz) R LTBR 8-bit Counter R LTBADJL LTBDJH RESET (Internal signal) 8 Data bus LTBR Write LTBR LTBADJL LTBADJH Figure 7-1 FEUL610Q438 8 : Low-speed time base counter register : Low-speed time base counter frequency adjust register : Low-speed time base counter frequency adjust register Configuration of Low-Speed Time Base Counter (LTBC) 7-1 ML610Q438/ML610Q439 User’s Manual Chapter 7 Time Base Counter HSCLK (4.096 MHz) RESET (Internal signal) HTBDR 1/n-Counter R HTBCLK 4.096 MHz to 256 Hz 8 Data bus HTBDR: High-speed time base counter frequency divide register Figure 7-2 Configuration of High-Speed Time Base Counter Note: The frequency of HSCLK changes according to specified data in SYSC1 bit and SYSC0 bit of Frequency control register 0 (FON0) FEUL610Q438 7-2 ML610Q438/ML610Q439 User’s Manual Chapter 7 Time Base Counter 7.2 Description of Registers 7.2.1 List of Registers Address 0F00AH 0F00BH 0F00CH 0F00DH Name Low-speed time base counter register High-speed time base counter frequency divide register Low-speed time base counter frequency adjustment register L Low-speed time base counter frequency adjustment register H FEUL610Q438 Symbol (Byte) Symbol (Word) R/W Size Initial value LTBR  R/W 8 00H HTBDR  R/W 8 00H R/W 8/16 00H R/W 8 00H LTBADJL LTBADJ LTBADJH 7-3 ML610Q438/ML610Q439 User’s Manual Chapter 7 Time Base Counter 7.2.2 Low-Speed Time Base Counter (LTBR) Address: 0F00AH Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 LTBR T1HZ T2HZ T4HZ T8HZ T16HZ T32HZ T64HZ T128HZ R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 LTBR is a special function register (SFR) to read the T128HZ-T1HZ outputs of the low-speed time base counter. The T128HZ-T1HZ outputs are set to “0” when write operation is performed for LTBR. Note: A TBC interrupt (128Hz interrupt, 64Hz interrupt, 32Hz interrupt, 16Hz interrupt, 8Hz interrupt, 4Hz interrupt, 2Hz interrupt, or 1Hz interrupt) may occur depending on the LTBR write timing (see Figure 7-4, “Interrupt Timing and Reset Timing by Writing to LTBR”). Therefore, take care in software programming. FEUL610Q438 7-4 ML610Q438/ML610Q439 User’s Manual Chapter 7 Time Base Counter 7.2.3 High-Speed Time Base Counter Divide Register (HTBDR) Address: 0F00BH Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 HTBDR     HTD3 HTD2 HTD1 HTD0 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 HTBDR is a special function register (SFR) to set the divide ratio of the 4-bit, 1/n counter. [Description of Bits] • HTD3-HTD0 (bits 3-0) The HTD3-HTD0 bits are used to set the frequency divide ratio of the 4-bit, 1/n counter. The frequency divide ratios selectable include 1/1 to 1/16. HTD3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 HTD2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 HTD1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 HTD0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Description Divide ratio × 1/16 (initial value) × 1/15 × 1/14 × 1/13 × 1/12 × 1/11 × 1/10 × 1/9 × 1/8 × 1/7 × 1/6 × 1/5 × 1/4 × 1/3 × 1/2 × 1/1 Frequency of HTBCLK (*1) 256 kHz 273 kHz 293 kHz 315 kHz 341 kHz 372 kHz 410 kHz 455 kHz 512 kHz 585 kHz 683 kHz 819 kHz 1024 kHz 1365 kHz 2048 kHz 4096 kHz *1: Indicates the frequency when the high-speed oscillation clock, HSCLK, is 4096 kHz. FEUL610Q438 7-5 ML610Q438/ML610Q439 User’s Manual Chapter 7 Time Base Counter 7.2.4 Low-Speed Time Base Counter Frequency Adjustment Registers L and H (LTBADJL, LTBADJH) Address: 0F00CH Access: R/W Access size: 8/16 bits Initial value: 00H 7 6 5 4 3 2 1 0 LTBADJL LADJ7 LADJ6 LADJ5 LADJ4 LADJ3 LADJ2 LADJ1 LADJ0 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 LTBADJH      LADJS LADJ9 LADJ8 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Address: 0F00DH Access: R/W Access size: 8 bits Initial value: 00H LTBADJL and LTBADJH are special function registers (SFRs) to set the frequency adjustment values of the low-speed time base clock. [Description of Bits] • LADJS, LADJ9-LADJ8 (bits 2-0) LADJ7-LADJ0 (bits 7-0) The LADJS and LADJ9 to LADJ0 bits are used to adjust frequency. Adjustment range: Approx. −488ppm to +488ppm. Adjustment accuracy: Approx. 0.48ppm See Section 7.3.3, “Low-Speed Time Base Counter Frequency Adjustment Function” for the correspondence between the frequency adjustment values (LTBADJH, LTBADJL) and adjustment ratio. FEUL610Q438 7-6 ML610Q438/ML610Q439 User’s Manual Chapter 7 Time Base Counter 7.3 Description of Operation 7.3.1 Low-Speed Time Base Counter The low-speed time base counter (LTBC) starts counting from 0000H on the LSCLK falling edge after system reset. The T128HZ, T64HZ, T32HZ, T16HZ, T8HZ, T4HZ, T2HZ, and T1HZ outputs of LTBC are used as time base interrupts and an interrupt is requested on the falling edge of each output. Each of LTBC outputs is also used as an operation clock for peripheral circuits. The output data of T128HZ to T1HZ of LTBC can be read from the low-speed time base counter register (LTBR). When reading the data, read LTBR twice and check that the two values coincide to prevent reading of undefined data during counting. Figure 7-3 shows an example of program to read LTBR. LEA offset LTBR ; EA←LTBR address L L R0, R1, [EA] [EA] ; 1st read ; 2nd read CMP BNE R0, MARK R1 ; Comparison for LTBR ; To MARK when the values do not coincide MARK: ; ; : Figure 7-3 Programming Example for Reading LTBR LTBR is reset when write operation is performed and the T128HZ to T1HZ outputs are set to “0”. Write data is invalid. Since an interrupt occurs if a falling edge occurs in the T128Hz to T1Hz outputs during writing to LTBR, take care in software programming. Figure 7-4 shows interrupt generation timing and reset timing of the time base counter output by writing to LTBR. LTBR Write T256HZ T128HZ T64HZ T32HZ T16HZ T16HZ T8HZ T4HZ T2HZ T1HZ Indicates interrupt timing Figure 7-4 FEUL610Q438 Interrupt Timing and Reset Timing by Writing to LTBR 7-7 ML610Q438/ML610Q439 User’s Manual Chapter 7 Time Base Counter 7.3.2 High-Speed Time Base Counter The high-speed time base counter is configured as a 4-bit 1/n counter (n = 1 to 16). In the 4-bit 1/n counter, the divided clock (1/16×HSCLK to 1/1×HSCLK) selected by the high-speed time base counter divide register (HTBDR) is generated as HTBCLK. HTBCLK is used as a timer and also as an operation clock of PWM. Figure 7-5 shows the output waveform of HTBCLK. High-speed clock HSCLK 1/n counter output HTBCLK × 1/1 High-speed time base counter Divide register HTBDR 0FH Figure 7-5 FEUL610Q438 × 1/2 0EH × 1/3 0DH Output Waveform of HTBCLK 7-8 ML610Q438/ML610Q439 User’s Manual Chapter 7 Time Base Counter 7.3.3 Low-Speed Time Base Counter Frequency Adjustment Function Frequency adjustment (Adjustment range: Approx. −488ppm to +488ppm. Adjustment accuracy: Approx. 0.48ppm) is possible for outputs of T8KHZ to T1HZ of LTBC by using the low-speed time base counter frequency adjust registers (LTBADJH and LTBADJL). Table7-1 shows correspondence between the frequency adjustment values (LTBADJH, LTBADJL) and adjustment ratio. Table 7-1 0 0 : 0 0 0 0 1 1 : 1 1 1 1 : 0 0 0 0 1 1 : 0 0 1 1 : 0 0 0 0 1 1 : 0 0 Correspondence between Frequency Adjustment Values (LTBADJH, LTBADJL) and Adjustment Ratio 1 1 : 0 0 0 0 1 1 : 0 0 LADJ10 to 0 1 1 1 1 1 1 : : : 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 : : : 0 0 0 0 0 0 1 1 : 0 0 0 0 1 1 : 0 0 1 1 : 0 0 0 0 1 1 : 0 0 1 1 : 1 1 0 0 1 1 : 0 0 1 0 : 1 0 1 0 1 0 : 1 0 Hexadecimal Frequency adjustment ratio (ppm) 3FFH +487.80 3FEH +487.33 : : 003H +1.43 002H +0.95 001H +0.48 000H 0 7FFH −0.48 7FEH −0.95 : : 401H −487.80 400H −488.28 The adjustment values (LADJ10 to LADJ0) to be set in LTBADJH and LTBADJL can be obtained by using the following equations: Adjustment value = Frequency adjustment ratio × 2097152 (decimal) = Frequency adjustment ratio × 200000h (hexadecimal) Example 1: When adjusting +15.0ppm (gaining time) Adjustment value = +15.0ppm × 2097152 (decimal) = +15.0 × 10−6 × 2097152 = +31.45728 (decimal) ≅ 01Fh (hexadecimal) Example 2: When adjusting −25.5ppm (losing time) Adjustment value = −25.5ppm × 2097152 (decimal) = −25.5 × 10−6 × 2097152 = −53.477376 (decimal) ≅ 7CCh (hexadecimal) Note: The low-speed clock (LSCLK) and the outputs of T32KHZ and T16KHZ of LTBC are not adjusted by the frequency adjust function. The frequency adjustment accuracy does not guarantee the accuracy including the frequency variation of the crystal oscillation (32.768kHz) due to temperature variations. FEUL610Q438 7-9 Chapter 8 Capture ML610Q438/ML610Q439 User’s Manual Chapter 8 Capture 8. Capture 8.1 Overview This LSI has two channels of capture circuits that capture the T4KHZ to T32HZ signals of the low-speed base counter (LTBC) to the capture register at the occurrence of P00 and P01 interrupts. The circuits capture timings at which each interrupt occurred, based on the time from the time base counter. For the external interrupt (P00INT, P01INT) from the P00 or P01 pin, see Chapter 5, "Interrupt" and Chapter 17, "Port 0". 8.1.1 Features • Time base capture×2ch (4096Hz to 32Hz) 8.1.2 Configuration Figure 8-1 shows the configuration of the capture circuit. T4KHZ T2KHZ T1KHZ T512HZ T256HZ T128HZ T64HZ T32HZ LSCLK (32.768kHz) LTBC P01INT P00INT Interrupt request signal Capture Controller CAPR1 CAPR0 CAPSTAT CAPCON CP1F R CP0F R 8 Write CAPR1 Write CAPR0 Data bus CAPCON CAPSTAT CAPR0 CAPR1 8 : Capture control register : Capture status register : Capture data register 0 : Capture data register 1 Figure 8-1 Configuration of Capture Circuit 8.1.3 List of Pins Pin name I/O P00/CAP0 I P01/CAP1 I FEUL610Q438 Description Capture 0 input pin Used as the secondary function of the P00 pin. Capture 1 input pin Used as the secondary function of the P01 pin. 8-1 ML610Q438/ML610Q439 User’s Manual Chapter 8 Capture 8.2 Description of Registers 8.2.1 List of Registers Address 0F090H 0F091H 0F092H 0F093H Name Capture control register Capture status register Capture data register 0 Capture data register 1 FEUL610Q438 Symbol (Byte) CAPCON CAPSTAT CAPR0 CAPR1 Symbol (Word)     R/W R/W R/W R/W R/W Size 8 8 8 8 Initial value 00H 00H 00H 00H 8-2 ML610Q438/ML610Q439 User’s Manual Chapter 8 Capture 8.2.2 Capture Control Register (CAPCON) Address: 0F090H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 CAPCON       ECAP1 ECAP0 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 CAPCON is a special function register (SFR) to control the capture circuit. [Description of Bits] • ECAP0 (bit 0) The ECAP0 bit is used to start or stop the operation of capture 0. ECAP0 0 1 Description Stops the capture 0 operation. (initial value) Starts the capture 0 operation. • ECAP1 (bit 1) The ECAP1 bit is used to start or stop the operation of capture 1. ECAP1 0 1 FEUL610Q438 Description Stops the capture 1 operation. (initial value) Starts the capture 1 operation. 8-3 ML610Q438/ML610Q439 User’s Manual Chapter 8 Capture 8.2.3 Capture Status Register (CAPSTAT) Address: 0F091H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 CAPSTAT       CAPF1 CAPF0 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 CAPSTAT is a special function register (SFR) to indicate a state of the capture circuit. [Description of Bits] • CAPF0 (bit 0) The CAPF0 bit is the flag to indicate whether data is captured in capture data register 0 (CARP0) or not. When the CAPF0 bit is set to "1", it indicates that data is captured in capture data register 0 (CAPR0). When the CAPF0 bit is set to "1", the next capture operation is stopped. So perform the write operation to capture data register 0 (CAPR0) to clear the CAPF0 bit to "0". CAPF0 0 1 Description No capture 0 latch (initial value) Capture 0 latch • CAPF1 (bit 1) The CAPF1 bit is the flag to indicate whether data is captured in capture data register 0 (CARP1) or not. When the CAPF0 bit is set to "1", it indicates that data is captured in capture data register 0 (CAPR1). When the CAPF1 bit is set to "1", the next capture operation is stopped. So perform the write operation to capture data register 1 (CAPR1) to clear theCAPF0 bit to "0". CAPF1 0 1 FEUL610Q438 Description No capture 1 latch (initial value) Capture 1 latch 8-4 ML610Q438/ML610Q439 User’s Manual Chapter 8 Capture 8.2.4 Capture Data Register 0 (CAPR0) Address: 0F092H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 CAPR0 CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 CAPR0 is a register in which capture data is stored. The T4KHZ to T32HZ signals of the low-speed time base counter (LTBC) are captured when the P00 interrupt request is generated with the CAPF0 flag (bit 0 of the CAPSTAT register) set to "0". Writing to CAPR0 sets the CAPF0 flag of CAPSTAT to "0". The value of CAPR0 does not change even if data is written to it. FEUL610Q438 8-5 ML610Q438/ML610Q439 User’s Manual Chapter 8 Capture 8.2.5 Capture Data Register 1 (CAPR1) Address: 0F093H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 CAPR1 CP17 CP16 CP15 CP14 CP13 CP12 CP11 CP10 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 CAPR1 is a register in which capture data is stored. The T4KHZ to T32HZ signals of the low-speed time base counter (LTBC) are captured when the P01 interrupt request is generated with the CAPF1 flag (bit 1 of the CAPSTAT register) set to "0". Writing to CAPR1 sets the CAPF1 flag of CAPSTAT to "0". The value of CAPR1 does not change even if data is written to it. FEUL610Q438 8-6 ML610Q438/ML610Q439 User’s Manual Chapter 8 Capture 8.3 Description of Operation The capture circuit starts the capture operation by setting the ECAP0 or ECAP1 bit of the capture control register (CAPCON). When the input trigger from the P00 or P01 pin selected by the external interrupt control register 0 or 1 (EXICON0 or EXICON1) is generated and the P00 or P01 interrupt request flag (QP00 or QP01) is set to “1”, the T4KHZ to T32HZ signals of the low-speed time base counter (LTBC) are captured in the capture register 0 or 1 (CAPR0 or CAPR1) on the next low-speed clock (LSCLK) falling edge and the at the same time, the capture flag (CAPF0 or CAPF1) of the capture status register (CAPSTAT) is set to “1”. When the capture flag (CAPF0, CAPF1) is “1”, the following capture operation stops. After reading the value captured in the capture register 0 or 1 (CAPR0, CAPR1), perform write operation (write data is meaningless) for the capture register 0 or 1 (CAPR0, CAPR1), clear the capture flag (CAPF0, CAPF1) to “0”, and wait for the next P00 or P01 interrupt. Figure 8-2 shows the timing of the capture operation. System clock SYSCLK LSCLK (32.768 kHz) LTBC (T4KHZ to T32HZ) N N+1 P00 and P01 pins QP00, QP01 Interrupt request flag CAPR0, CAPR1 XX N+1 N+1 CAPF0, CAPF1 Write CAPR0, 1 Figure 8-2 Timing Diagram of Capture Operation Note: When CPU is operating at the high speed (HSCLK), check that the capture flag (CAPF0, CAPF1) is set to "1" after the P00 or P01 interrupt request is generated and then read capture data register 0 or 1 (CAPR0, CAPR1). FEUL610Q438 8-7 Chapter 9 1 kHz Timer (1kHzTM) ML610Q438/ML610Q439 User’s Manual Chapter 9 1 kHz Timer (1kHzTM) 9. 1 kHz Timer (1kHzTM) 9.1 Overview This LSI includes a 1 kHz timer to measure 1/1000 seconds. The 1 kHz timer counts the 1 kHz signal created by dividing the T2KHZ output frequency (2.048 kHz) of the low-speed time base counter (LTBC) and generates a 10 Hz or 1 Hz interrupt (1 kHz timer interrupt). With the 1 kHz timer, 1/1000 second, which is difficult to generate on a time-base-counter basis, represented by a decimal number can be obtained easily. The timer can be applied to period measurement for stopwatches. For the timer base counter, see Chapter 7, “Time Base Counter”. 9.1.1 Features • 10 Hz/1 Hz interrupt select function 9.1.2 Configuration Figure 9-1 shows the configuration of the 1 kHz timer. Interrupt control T1KINT 1 kHz signal 10 Hz Binary/ternary counter T2KHZ (2.048 kHz) R T1KCRL Decimal×1 digit 1 Hz T1KCRH Decimal×2 digits R R Write T1KCRH Write T1KCRL T1KCON Data bus T1KCON T1KCRL T1KCRH : 1 kHz timer control register : 1 kHz timer count register L : 1 kHz timer count register H Figure 9-1 FEUL610Q438 Configuration of 1 kHz Timer 9-1 ML610Q438/ML610Q439 User’s Manual Chapter 9 1 kHz Timer (1kHzTM) 9.2 Description of Registers 9.2.1 List of Registers Address 0F080H 0F081H 0F082H Name 1 kHz timer count register L 1 kHz timer count register H 1 kHz timer control register FEUL610Q438 Symbol (Byte) T1KCRL T1KCRH T1KCON Symbol (Word) T1KCR  R/W R/W R/W R/W Size 8/16 8 8 Initial value 00H 00H 00H 9-2 ML610Q438/ML610Q439 User’s Manual Chapter 9 1 kHz Timer (1kHzTM) 9.2.2 1 kHz Timer Count Registers (T1KCRL, T1KCRH) Address: 0F080H Access: R/W Access size: 8/16 bits Initial value: 00H 7 6 5 4 3 2 1 0 T1KCRL T1KC3 T1K02 T1KC1 T1KC0     R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Address: 0F081H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 T1KCRH T1KC11 T1K010 T1KC9 T1KC8 T1KC7 T1K06 T1KC5 T1KC4 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 T1KCRL and T1KCRH are special function registers (SFRs) to read the decimal count values of the 1 kHz timer. When the write operation to T1KCRL or T1KCRH, the valid bit of T1KCRL or T1KCRH is "0" respectively. [Description of Bits] • T1KC11 to T1KC0 (T1KCRH: bits 7 to 0, T1KCRL: bits 7 to 4) T1KC11 to T1KC0 indicate the count values of the 1 kHz timer. FEUL610Q438 9-3 ML610Q438/ML610Q439 User’s Manual Chapter 9 1 kHz Timer (1kHzTM) 9.2.3 1 kHz Timer Control Register (T1KCON) Address: 0F082H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 T1KCON       T1KSEL T1KRUN R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 T1KCON is a special function register (SFR) to control the 1 kHz timer. [Description of Bits] • T1KRUN (bit 0) The T1KRUN bit is used to control start/stop of the count operation of the 1 kHz timer counter. T1KRUN 0 1 Description Stops 1 kHz timer operation (initial value). Starts 1 kHz operation. • T1KSEL (bit 1) The T1LSEL bit is used to select the interrupt period of the 1 kHz timer. The 10 Hz or 1 Hz interrupt can be selected. T1KSEL 0 1 FEUL610Q438 Description 10 Hz interrupt (initial value) 1 Hz interrupt 9-4 ML610Q438/ML610Q439 User’s Manual Chapter 9 1 kHz Timer (1kHzTM) 9.3 Description of Operation By setting the T1KRUN bit of the 1kHz timer control register (T1KCON) to “1”, the 1kHz timer starts counting of the 1kHz timer counter registers L or H (T1KCRL, T1KCRH). By dividing the T2KHz signal frequency (2.048kHz) of the low-speed timer base counter (LTBC) by the binary/ternary counter, the timer generates a 1kHz signal. Based on the 1kHz signal, a 1kHz timer interrupt request signal (T1KINT) is generated by the decimal counters of T1KCRL and T1KCRH. The period of the 1kHz timer interrupt can be selected between the 10Hz interrupt or 1Hz interrupt using the T1KSEL bit of T1KCON. When write operation is performed for T1KCRL or T1KCRH, the value of the binary/ternary counter and the value of T1KCRL or T1KCRH is cleared to “0”. Data can be read from T1KCRL and T1KCRH. When reading data from T1KCRL or T1KCRH in the 1kHz timer operation start state, read T1KCRL or T1KCRH twice and check that the values match to prevent the reading of undefined data during counting. Figure 9-2 shows an example of the program for reading T1KCL and T1LCRH. LEA offset T1KCRL ; EA←T1KCRL address MARK: L ER0, [EA] L ER2, [EA] ; First read ; Second read CMP ER0, ER1 BNE MARK ; Comparison of T1KCRL and T1CKRH ; To MARK when not matched. ; ; : Figure 9-2 FEUL610Q438 Example of Program for Reading T1KCRL and T1KCRH 9-5 Chapter 10 Timers ML610Q438/ML610Q439 User’s Manual Chapter 10 Timers 10. Timers 10.1 Overview This LSI includes 2 channels of 8-bit timers. For the input clock, see Chapter 6, “Clock Generation Circuit”. 10.1.1 Features • The timer interrupt (TMnINT) is generated when the values of timer counter register (TMnC, n=0 to 3) and timer data register (TMnD) coincide. • A timer configured by combining timer 0 and timer 1 or timer 2 and timer 3can be used as a 16-bit timer. • For the timer clock, the low-speed clock (LSCLK/256, LSCLK/128, LSCLK/64, LSCLK/32, LSCLK/16, LSCLK/8, LSCLK/4, LSCLK/2, LSCLK), high-speed time base clock (HTBCLK), or external clock can be selected. • Selection of one shot timer mode is possible. 10.1.2 Configuration Figure 10-1 shows the configuration of the timers. TMnINT Match Write TMnC LSCLK HTBCLK Comparator TMnCON0 TnCK TMnCON1 External clock P44/T02P0CK P45/T13P1CK 8 R 8 TMnC TMnD 8 8 n = 0 to 3 Data bus (a) In 8-bit Timer Mode (Timers 0 to 3) TMmINT Match Write TMnC Write TMmC n = 0,2, m = 1,3 Comparator 16 16 8 LSCLK HTBCLK External clock P44/T02P0CK P45/T13P1CK TMnCON0 TnCK TMnCON1 R TMnC 8 R TMmC 8 8 TMnD TMmD 8 8 8 Read TMnC TMmC latch 8 Data bus (b) 16-bit Timer Mode (Timers 0 to 3) TMnCON0: TMnCON1: TMmD, TMnD: TMmC, TMnC: Timer control register 0 Timer control register 1 Timer data registers Timer counter registers Figure 10-1 FEUL610Q438 Configuration of Timers 10-1 ML610Q438/ML610Q439 User’s Manual Chapter 10 Timers 10.2 Description of Registers 10.2.1 List of Registers Address 0F030H 0F031H 0F032H 0F033H 0F034H 0F035H 0F036H 0F037H 0F038H 0F039H 0F03AH 0F03BH 0F03CH 0F03DH 0F03EH 0F03FH FEUL610Q438 Name Timer 0 data register Timer 0 counter register Timer 0 control register 0 Timer 0 control register 1 Timer 1 data register Timer 1 counter register Timer 1 control register 0 Timer 1 control register 1 Timer 2 data register Timer 2 counter register Timer 2 control register 0 Timer 2 control register 1 Timer 3 data register Timer 3 counter register Timer 3 control register 0 Timer 3 control register 1 Symbol (Byte) TM0D TM0C TM0CON0 TM0CON1 TM1D TM1C TM1CON0 TM1CON1 TM2D TM2C TM2CON0 TM2CON1 TM3D TM3C TM3CON0 TM3CON1 Symbol (Word) TM0DC TM0CON TM1DC TM1CON TM2DC TM2CON TM3DC TM3CON R/W Size Initial value R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8/16 8 8/16 8 8/16 8 8/16 8 8/16 8 8/16 8 8/16 8 8/16 8 0FFH 00H 00H 00H 0FFH 00H 00H 00H 0FFH 00H 00H 00H 0FFH 00H 00H 00H 10-2 ML610Q438/ML610Q439 User’s Manual Chapter 10 Timers 10.2.2 Timer 0 Data Register (TM0D) Address: 0F030H Access: R/W Access size: 8 bits Initial value: 0FFH 7 6 5 4 3 2 1 0 TM0D T0D7 T0D6 T0D5 T0D4 T0D3 T0D2 T0D1 T0D0 R/W Initial value R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 TM0D is a special function register (SFR) to set the value to be compared with the timer 0 counter register (TM0C) value. Note: Set TM0D when the timer stops. When “00H” is written in TM0D, TM0D is set to “01H”. FEUL610Q438 10-3 ML610Q438/ML610Q439 User’s Manual Chapter 10 Timers 10.2.3 Timer 1 Data Register (TM1D) Address: 0F034H Access: R/W Access size: 8 bits Initial value: 0FFH 7 6 5 4 3 2 1 0 TM1D T1D7 T1D6 T1D5 T1D4 T1D3 T1D2 T1D1 T1D0 R/W Initial value R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 TM1D is a special function register (SFR) to set the value to be compared with the value of the timer 1 counter register (TM1C). Note: Set TM1D when the timer stops. When “00H” is written in TM1D, TM1D is set to “01H”. FEUL610Q438 10-4 ML610Q438/ML610Q439 User’s Manual Chapter 10 Timers 10.2.4 Timer 2 Data Register (TM2D) Address: 0F038H Access: R/W Access size: 8 bits Initial value: 0FFH 7 6 5 4 3 2 1 0 TM2D T2D7 T2D6 T2D5 T2D4 T2D3 T2D2 T2D1 T2D0 R/W Initial value R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 TM2D is a special function register (SFR) to set the value to be compared with the value of the timer 2 counter register (TM2C). Note: Set TM2D when the timer stops. When “00H” is written in TM2D, TM2D is set to “01H”. FEUL610Q438 10-5 ML610Q438/ML610Q439 User’s Manual Chapter 10 Timers 10.2.5 Timer 3 Data Register (TM3D) Address: 0F03CH Access: R/W Access size: 8 bits Initial value: 0FFH 7 6 5 4 3 2 1 0 TM3D T3D7 T3D6 T3D5 T3D4 T3D3 T3D2 T3D1 T3D0 R/W Initial value R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 TM3D is a special function register (SFR) to set the value to be compared with the value of the timer 3 counter register (TM3C). Note: Set TM3D when the timer stops. When “00H” is written in TM3D, TM3D is set to “01H”. FEUL610Q438 10-6 ML610Q438/ML610Q439 User’s Manual Chapter 10 Timers 10.2.6 Timer 0 Counter Register (TM0C) Address: 0F031H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 TM0C T0C7 T0C6 T0C5 T0C4 T0C3 T0C2 T0C1 T0C0 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 TM0C is a special function register (SFR) that functions as an 8-bit binary counter. When write operation to TM0C is performed, TM0C is set to “00H”. The data that is written is meaningless. In 16-bit timer mode, if write operation is performed to either the low-order TM0C or high-order TM1C, both the low-order and the high-order are set to “0000H”. During timer operation, the contents of TM0C may not be read depending on the conditions of the timer clock and the system clock. Table 10-1 shows whether a TM0C read is enabled or disabled during timer operation for each condition of the timer clock and system clock. Table 10-1 TM0C Read Enable/Disable during Timer Operation Timer clock T0CK LSCLK System clock SYSCLK 1/1～1/256LSCLK LSCLK HSCLK HTBCLK HTBCLK 1/1～1/256LSCLK HSCLK 1/1～1/256LSCLK HSCLK External clock FEUL610Q438 TM0C read enable/disable Read enabled Read enabled. However, to prevent the reading of undefined data during incremental counting, read consecutively TM0C twice until the last data coincides the previous data. Read disabled Read enabled Read disabled 10-7 ML610Q438/ML610Q439 User’s Manual Chapter 10 Timers 10.2.7 Timer 1 Counter Register (TM1C) Address: 0F035H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 TM1C T1C7 T1C6 T1C5 T1C4 T1C3 T1C2 T1C1 T1C0 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 TM1C is a special function register (SFR) that functions as an 8-bit binary counter. When write operation to TM1C is performed, TM1C is set to “00H”. The data that is written is meaningless. In 16-bit timer mode, if write operation is performed to either the low-order TM0C or high-order TM1C, both the low order and the high order are set to “0000H”. When reading TM1C in 16-bit timer mode, be sure to read TM0C first since the count value of TM1C is stored in the TM1C latch when TM0C is read. During timer operation, the contents of TM1C may not be read depending on the conditions of the timer clock and the system clock. Table 10-2 shows whether a TM1C read is enabled or disabled during timer operation for each condition of the timer clock and system clock. Table 10-2 TM1C Read Enable/Disable during Timer Operation Timer clock T1CK LSCLK System clock SYSCLK 1/1～1/256LSCLK LSCLK HSCLK HTBCLK HTBCLK 1/1～1/256LSCLK HSCLK 1/1～1/256LSCLK HSCLK External clock FEUL610Q438 TM1C read enable/disable Read enabled Read enabled. However, to prevent the reading of undefined data during incremental counting, read consecutively TM1C twice until the last data coincides the previous data Read disabled Read enabled Read disabled 10-8 ML610Q438/ML610Q439 User’s Manual Chapter 10 Timers 10.2.8 Timer 2 Counter Register (TM2C) Address: 0F039H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 TM2C T2C7 T2C6 T2C5 T2C4 T2C3 T2C2 T2C1 T2C0 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 TM2C is a special function register (SFR) that functions as an 8-bit binary counter. When write operation to TM2C is performed, TM2C is set to “00H”. The data that is written is meaningless. In 16-bit timer mode, if write operation is performed to either the low-order TM2C or high-order TM3C, both the low order and the high order are set to “0000H”. During timer operation, the contents of TM2C may not be read depending on the conditions of the timer clock and the system clock. Table 10-3 shows whether a TM2C read is enabled or disabled during timer operation for each condition of the timer clock and system clock. Table 10-3 TM2C Read Enable/Disable during Timer Operation Timer clock T2CK LSCLK System clock SYSCLK 1/1～1/256LSCLK LSCLK HSCLK HTBCLK HTBCLK 1/1～1/256LSCLK HSCLK 1/1～1/256LSCLK HSCLK External clock FEUL610Q438 TM2C read enable/disable Read enabled Read enabled. However, to prevent the reading of undefined data during incremental counting, read consecutively TM2C twice until the last data coincides the previous data. Read disabled Read enabled Read disabled 10-9 ML610Q438/ML610Q439 User’s Manual Chapter 10 Timers 10.2.9 Timer 3 Counter Register (TM3C) Address: 0F03DH Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 TM3C T3C7 T3C6 T3C5 T3C4 T3C3 T3C2 T3C1 T3C0 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 TM3C is a special function register (SFR) that functions as an 8-bit binary counter. When write operation to TM3C is performed, TM3C is set to “00H”. The data that is written is meaningless. In 16-bit timer mode, if write operation is performed to either the low-order (TM2C) or high-order (TM3C), both the low order and the high order are set to “0000H”. When reading TM3C in 16-bit timer mode, be sure to read TM2C first since the count value of TM3C is stored in the TM3C latch when TM2C is read. During timer operation, the contents of TM3C may not be read depending on the conditions of the timer clock and the system clock. Table 10-4 shows whether a TM3C read is enabled or disabled during timer operation for each condition of the timer clock and system clock. Table 10-4 TM3C Read Enable/Disable during Timer Operation Timer clock T3CK LSCLK System clock SYSCLK 1/1～1/256LSCLK LSCLK HSCLK HTBCLK HTBCLK 1/1～1/256LSCLK HSCLK 1/1～1/256LSCLK HSCLK External clock FEUL610Q438 TM3C read enable/disable Read enabled Read enabled. However, to prevent the reading of undefined data during incremental counting, read consecutively TM3C twice until the last data coincides the previous data. Read disabled Read enabled Read disabled 10-10 ML610Q438/ML610Q439 User’s Manual Chapter 10 Timers 10.2.10 Timer 0 Control Register 0 (TM0CON0) Address: 0F032H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 TM0CON0   T01M16 T0OST T0CS3 T0CS2 T0CS1 T0CS0 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 TM0CON0 is a special function (SFR) to control a timer 0. Rewrite TM0CON0 while the timer 0 is stopped (T0STAT of the TM0CON1 register is “0”). [Description of Bits] • T0CS3～T0CS0 (bits 3, 2, 1, 0) The T0CS3 ～ T0CS0 bits are used for selecting the operation clock of timer 0. 1/1～1/256 LSCLK, HTBCLK, or the external clock (P44/T02P0CK) can be selected by these bits. T0CS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 T0CS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 T0CS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 T0CS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Description LSCLK (initial value) 1/2 LSCLK 1/4 LSCLK 1/8 LSCLK 1/16 LSCLK 1/32 LSCLK 1/64 LSCLK 1/128 LSCLK 1/256 LSCLK HTBCLK Prohibited (timer 0 does not operate) Prohibited (timer 0 does not operate) Prohibited (timer 0 does not operate) Prohibited (timer 0 does not operate) Prohibited (timer 0 does not operate) External clock (P44/T02P0CK) • T0OST (bit 4) The T0OST bit is used for selecting a normal timer mode or a one-shot timer mode. When the T0OST bit is set to “1”, timer 0 is selected a one-shot timer mode. T0OST 0 1 FEUL610Q438 Description normal timer mode (initial value) one-shot timer mode 10-11 ML610Q438/ML610Q439 User’s Manual Chapter 10 Timers • T01M16 (bit 5) The T01M16 bit is used for selecting a 8-bit timer mode or a 16-bit timer mode. When the T01M16 bit is set to “1”, timer 0 and timer 1 are connected and they operate as a 16-bit timer. In 16-bit timer mode, timer 1 is incremented by a timer 0 overflow signal. A timer 0 interrupt (TM0INT) is not generated. T01M16 0 1 FEUL610Q438 Description 8-bit timer mode (initial value) 16-bit timer mode 10-12 ML610Q438/ML610Q439 User’s Manual Chapter 10 Timers 10.2.11 Timer 1 Control Register 0 (TM1CON0) Address: 0F036H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 TM1CON0    T1OST T1CS3 T1CS2 T1CS1 T1CS0 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 TM1CON0 is a special function (SFR) to control a timer 1. Rewrite TM1CON0 while the timer 1 is stopped (T1STAT of the TM1CON1 register is “0”). [Description of Bits] • T1CS3～T1CS0 (bits 3, 2, 1, 0) The T1CS3 ～ T1CS0 bits are used for selecting the operation clock of timer 1. 1/1～1/256 LSCLK, HTBCLK, or the external clock (P45/T13P0CK) can be selected by these bits. In cases where the 16-bit timer mode has been selected by setting T01M16 of TM0CON to “1”, the values of T1CS1 and T1CS0 are invalid. T1CS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 T1CS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 T1CS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 T1CS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Description LSCLK (initial value) 1/2 LSCLK 1/4 LSCLK 1/8 LSCLK 1/16 LSCLK 1/32 LSCLK 1/64 LSCLK 1/128 LSCLK 1/256 LSCLK HTBCLK Prohibited (timer 0 does not operate) Prohibited (timer 0 does not operate) Prohibited (timer 0 does not operate) Prohibited (timer 0 does not operate) Prohibited (timer 0 does not operate) External clock (P44/T02P0CK) • T1OST (bit 4) The T1OST bit is used for selecting a normal timer mode or a one-shot timer mode. When the T1OST bit is set to “1”, timer 1 is selected a one-shot timer mode. T0OST 0 1 FEUL610Q438 Description normal timer mode (initial value) one-shot timer mode 10-13 ML610Q438/ML610Q439 User’s Manual Chapter 10 Timers 10.2.12 Timer 2 Control Register 0 (TM2CON0) Address: 0F03AH Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 TM2CON0   T23M16 T2OST T2CS3 T2CS2 T2CS1 T2CS0 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 TM2CON0 is a special function (SFR) to control a timer 0. Rewrite TM2CON0 while the timer 2 is stopped (T2STAT of the TM2CON1 register is “0”). [Description of Bits] • T2CS3～T2CS0 (bits 3, 2, 1, 0) The T2CS3 ～ T2CS0 bits are used for selecting the operation clock of timer 2. 1/1～1/256 LSCLK, HTBCLK, or the external clock (P44/T02P0CK) can be selected by these bits. T2CS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 T2CS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 T2CS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 T2CS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Description LSCLK (initial value) 1/2 LSCLK 1/4 LSCLK 1/8 LSCLK 1/16 LSCLK 1/32 LSCLK 1/64 LSCLK 1/128 LSCLK 1/256 LSCLK HTBCLK Prohibited (timer 0 does not operate) Prohibited (timer 0 does not operate) Prohibited (timer 0 does not operate) Prohibited (timer 0 does not operate) Prohibited (timer 0 does not operate) External clock (P44/T02P0CK) • T2OST (bit 4) The T2OST bit is used for selecting a normal timer mode or a one-shot timer mode. When the T2OST bit is set to “1”, timer 2 is selected a one-shot timer mode. T2OST 0 1 FEUL610Q438 Description normal timer mode (initial value) one-shot timer mode 10-14 ML610Q438/ML610Q439 User’s Manual Chapter 10 Timers • T23M16 (bit 5) The T23M16 bit is used for selecting a 8-bit timer mode or a 16-bit timer mode. When the T23M16 bit is set to “1”, timer 2 and timer 3 are connected and they operate as a 16-bit timer. In 16-bit timer mode, timer 3 is incremented by a timer 2 overflow signal. A timer 2 interrupt (TM2INT) is not generated. T23M16 0 1 FEUL610Q438 Description 8-bit timer mode (initial value) 16-bit timer mode 10-15 ML610Q438/ML610Q439 User’s Manual Chapter 10 Timers 10.2.13 Timer 3 Control Register 0 (TM3CON0) Address: 0F03EH Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 TM3CON0    T3OST T3CS3 T3CS2 T3CS1 T3CS0 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 TM3CON0 is a special function (SFR) to control a timer 3. Rewrite TM3CON0 while the timer 3 is stopped (T3STAT of the TM3CON1 register is “0”). [Description of Bits] • T3CS3～T3CS0 (bits 3, 2, 1, 0) The T3CS3 ～ T3CS0 bits are used for selecting the operation clock of timer 1. 1/1～1/256 LSCLK, HTBCLK, or the external clock (P45/T13P0CK) can be selected by these bits. In cases where the 16-bit timer mode has been selected by setting T23M16 of TM2CON to “1”, the values of T3CS3 ～T3CS0 are invalid. T3CS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 T3CS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 T3CS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 T3CS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Description LSCLK (initial value) 1/2 LSCLK 1/4 LSCLK 1/8 LSCLK 1/16 LSCLK 1/32 LSCLK 1/64 LSCLK 1/128 LSCLK 1/256 LSCLK HTBCLK Prohibited (timer 0 does not operate) Prohibited (timer 0 does not operate) Prohibited (timer 0 does not operate) Prohibited (timer 0 does not operate) Prohibited (timer 0 does not operate) External clock (P44/T02P0CK) • T3OST (bit 4) The T3OST bit is used for selecting a normal timer mode or a one-shot timer mode. When the T3OST bit is set to “1”, timer 3 is selected a one-shot timer mode. T3OST 0 1 FEUL610Q438 Description normal timer mode (initial value) one-shot timer mode 10-16 ML610Q438/ML610Q439 User’s Manual Chapter 10 Timers 10.2.14 Timer 0 Control Register 1 (TM0CON1) Address: 0F033 Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 TM0CON1 T0STAT       T0RUN R/W Initial value R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 TM0CON1 is a special function register (SFR) to control a timer 0. [Description of Bits] • T0RUN (bit 0) The T0RUN bit is used for controlling count stop/start of timer 0. T0RUN 0 1 Description Stops counting. Starts counting. • T0STAT (bit 7) The T0STAT bit is used for indicating “counting stopped”/”counting in progress” of timer 0. T0STAT 0 1 Description Counting stopped. Counting in progress. FEUL610Q438 10-17 ML610Q438/ML610Q439 User’s Manual Chapter 10 Timers 10.2.15 Timer 1 Control Register 1 (TM1CON1) Address: 0F037H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 TM1CON1 T1STAT       T1RUN R/W Initial value R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 TM1CON1 is a special function register (SFR) to control a timer 1. [Description of Bits] • T1RUN (bit 0) The T1RUN bit is used for controlling count stop/start of timer 1. In 16-bit timer mode, be sure to set this bit to “0”. Timer 1 is incremented caused by a timer 0 overflow signal regardless of the value of T1RUN. T1RUN 0 1 Description Stops counting. Starts counting. • T1STAT (bit 7) The T1STAT bit is used for indicating “counting stopped”/”counting in progress” of timer 1. In 16-bit timer mode, this bit will read “0”. T1STAT 0 1 Description Counting stopped. Counting in progress. FEUL610Q438 10-18 ML610Q438/ML610Q439 User’s Manual Chapter 10 Timers 10.2.16 Timer 2 Control Register 1 (TM2CON1) Address: 0F03BH Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 TM2CON1 T2STAT       T2RUN R/W Initial value R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 TM2CON1 is a special function register (SFR) to control a timer 2. [Description of Bits] • T2RUN (bit 0) The T2RUN bit is used for controlling count stop/start of timer 2. T2RUN 0 1 Description Stops counting. Starts counting. • T2STAT (bit 7) The T2STAT bit is used for indicating “counting stopped”/”counting in progress” of timer 2. T2STAT 0 1 Description Counting stopped. Counting in progress. FEUL610Q438 10-19 ML610Q438/ML610Q439 User’s Manual Chapter 10 Timers 10.2.17 Timer 3 Control Register 1 (TM3CON1) Address: 0F03FH Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 TM3CON1 T3STAT       T3RUN R/W Initial value R 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 TM3CON1 is a special function register (SFR) to control a timer 3. [Description of Bits] • T3RUN (bit 0) The T3RUN bit is used for controlling count stop/start of timer 3. In 16-bit timer mode, be sure to set this bit to “0”. Timer 3 is incremented caused by a timer 2 overflow signal regardless of the value of T3RUN. T3RUN 0 1 Description Stops counting. Starts counting. • T3STAT (bit 7) The T3STAT bit is used for indicating “counting stopped”/”counting in progress” of timer 3. In 16-bit timer mode, this bit will read “0”. T3STAT 0 1 Description Counting stopped. Counting in progress. FEUL610Q438 10-20 ML610Q438/ML610Q439 User’s Manual Chapter 10 Timers 10.3 Description of Operation The timer counters (TMnC) are set to an operating state (TnSTAT are set to “1”) on the first falling edge of the timer clocks (TnCK) that are selected by the Timer 0 to 3 control register 0 (TMnCON0) when the TnRUN bits of timer 0 to 3control register 1 (TMnCON1) are set to “1” and increment the count value on the 2nd falling. When the count value of TM0C to TM3C and the timer 0 to 3 data register (TMnD) coincide, timer 0 to 3 interrupt (TMnINT) occurs on the next timer clock falling edge, TMnC are reset to “00H” and incremental counting continues. When the TnRUN bits are set to “0”, TMnC stop counting after counting once the falling of the timer clock (TnCK). Confirm that TMnC has been stopped by checking that the TnSTAT bit of the Timer 0–3 control register 1 (TMnCON1) is “0”. When the TnRUN bits are set to “1” again, TMn restart incremental counting from the previous values. To initialize TMnC to “00H”, perform write operation in TMnC. The timer interrupt period (TTMI) is expressed by the following equation. TMnD + 1 TnCK (Hz) TTMI = TMnD: TnCK: (n = 0 to 3) Timer 0 to 3 data register (TMnD) setting value (01H to 0FFH) Clock frequency selected by the Timer 0 to 3 control register 0 (TMnCON0) After the TnRUN bits are set to “1”, timers are synchronized by the timer clock and counting starts so that an error of a maximum of 1 clock period occurs until the first timer interrupt. The timer interrupt periods from the second time are constant. Figure 10-2 shows the normal timer mode operation timing diagram of Timer 0 to 3. TnCK TnRUN TnSTAT Write TMnC TMnC XX TMnD 00 01 02 88 87 88 88 00 01 5F 60 61 62 88 TMnINT (n = 0 to 1) Figure 10-2 TTMI Normal Timer Mode Operation Timing Diagram of Timer 0 to 3 Note: Even if “0” is written to the TnRUN bits, counting operation continues up to the falling edge (the timer 0 to 3 status flag (TnSTA) is in a “1” state) of the next timer clock pulse. Therefore, the timer 0 to 3 interrupt (TMnINT) may occur. FEUL610Q438 10-21 ML610Q438/ML610Q439 User’s Manual Chapter 10 Timers Figure 10-3 shows the one-shot timer mode operation timing diagram of Timer 0 to 3. TnCK TnRUN TnSTAT Write TMnC TMnC XX TMnD 00 01 02 88 87 88 88 01 00 88 TMnINT (n = 0 to 1) Figure 10-3 TTMI One-Shot Timer Mode Operation Timing Diagram of Timer 0 to 3 Note: In one-shot timer mode, When the count value of TM0C to TM3C and the timer 0 to 3 data register (TMnD) coincide, TnRUN bits are cleared automatically . FEUL610Q438 10-22 Chapter 11 PWM ML610Q438/ML610Q439 User’s Manual Chapter 11 PWM 11. PWM 11.1 Overview This LSI includes 3 channels of 16-bit PWM (Pulse Width Modulation). The PWMn(n=0 to 2) output function is assigned to P43(Port 4) and P34(Port 3) as the tertiary function. For the functions of port0, port 4 and port3, see Chapter 16, “Port0”, Chapter 20, “Port 4” and Chapter 19, “Port 3”. 11.1.1 Features • The PWMn signals with the periods of approximately 488 ns (HTBCLK=4.096MHz) to 2s (@LSCLK=32.768kHz) can be generated and output outside of the LSI. • The output logic of the PWMn signal can be switched to the positive or negative logic. • At the coincidence of PWMn signal period, duties, and period & duty, a PWM interrupt (PWnINT) occurs. • For the PWMn clock, a low-speed clock (LSCLK), a high-speed time base clock (HTBCLK), and an external clock are available. 11.1.2 Configuration Figure 11 - 1 shows the configuration of the PWMn circuit. PnNEG PnFLG Write PWnCH Write PWnCL Period match Comparator External clock P44/T02P0CK/PWM0 P45/T13P1CK/PWM1 16 LSCLK HTBCLK PWnCON0 PWnCON1 P02/EXI2/RXD0/PWM2 Read PWnCL PnCK Comparator PWnCH latch 8 16 PWnPBUF PWnDBUF PWnPH/L PWnDH/L 8 8 8 8 n = 0 to 2 Data bus PWMn period register L PWMn period register H PWMn period buffer PWMn duty register L PWMn duty register H PWMn duty buffer PWMn counter register L PWMn counter register H PWMn control register 0 PWMn control register 1 Figure 11-1 FEUL610Q438 Duty match 16 R PWnCH/L 8 PWnPL: PWnPH: PWnPBUF: PWnDL: PWnDH: PWnDBUF: PWnCL: PWnCH: PWnCON0: PWnCON1: PWnINT Output control circuit P43/PWM0 or P34/PWM0 P47/PWM1 or P35/PWM1 P30/PWM2 or P20/PWM2 Configuration of PWMn Circuit 11-1 ML610Q438/ML610Q439 User’s Manual Chapter 11 PWM 11.1.3 List of Pins Pin name I/O P43/PWM0 O P34/PWM0 O P47/PWM1 O P35/PWM1 O P30/PWM2 O P20/PWM2 O Description PWM0 output pin Used for the secondary function of the P43 pin. PWM0 output pin Used for the secondary function of the P34 pin. PWM1 output pin Used for the secondary function of the P47 pin. PWM1 output pin Used for the secondary function of the P35 pin. PWM2 output pin Used for the secondary function of the P30 pin. PWM2 output pin Used for the secondary function of the P20 pin. 11.2 Description of Registers 11.2.1 List of Registers Address 0F0A0H 0F0A1H 0F0A2H 0F0A3H 0F0A4H 0F0A5H 0F0A6H 0F0A7H 0F0A8H 0F0A9H 0F0AAH 0F0ABH 0F0ACH 0F0ADH 0F0AEH 0F0AFH 0F0B0H 0F0B1H 0F0B2H 0F0B3H 0F0B4H 0F0B5H 0F0B6H 0F0B7H FEUL610Q438 Name PWM0 period register L PWM0 period register H PWM0 duty register L PWM0 duty register H PWM0 counter register L PWM0 counter register H PWM0 control register 0 PWM0 control register 1 PWM1 period register L PWM1 period register H PWM1 duty register L PWM1 duty register H PWM1 counter register L PWM1 counter register H PWM1 control register 0 PWM1 control register 1 PWM2 period register L PWM2 period register H PWM2 duty register L PWM2 duty register H PWM2 counter register L PWM2 counter register H PWM2 control register 0 PWM2 control register 1 Symbol (Byte) PW0PL PW0PH PW0DL PW0DH PW0CL PW0CH PW0CON0 PW0CON1 PW1PL PW1PH PW1DL PW1DH PW1CL PW1CH PW1CON0 PW1CON1 PW2PL PW2PH PW2DL PW2DH PW2CL PW2CH PW2CON0 PW2CON1 Symbol (Word) PW0P PW0D PW0C PW0CON PW1P PW1D PW1C PW1CON PW2P PW2D PW2C PW2CON R/W Size Initial value R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8/16 8 8/16 8 8/16 8 8/16 8 8/16 8 8/16 8 8/16 8 8/16 8 8/16 8 8/16 8 8/16 8 8/16 8 0FFH 0FFH 00H 00H 00H 00H 00H 40H 0FFH 0FFH 00H 00H 00H 00H 00H 40H 0FFH 0FFH 00H 00H 00H 00H 00H 40H 11-2 ML610Q438/ML610Q439 User’s Manual Chapter 11 PWM 11.2.2 PWM0 Period Registers (PW0PL, PW0PH) Address: 0F0A0H Access: R/W Access size: 8 bits Initial value: 0FFH 7 6 5 4 3 2 1 0 PW0PL P0P7 P0P6 P0P5 P0P4 P0P3 P0P2 P0P1 P0P0 R/W R/W R/W R/W R/W R/W R/W R/W R/W At reset 1 1 1 1 1 1 1 1 7 6 5 4 3 2 1 0 PW0PH P0P15 P0P14 P0P13 P0P12 P0P11 P0P10 P0P9 P0P8 R/W R/W R/W R/W R/W R/W R/W R/W R/W At reset 1 1 1 1 1 1 1 1 Address: 0F0A1H Access: R/W Access size: 8 bits Initial value: 0FFH PW0PH and PW0PL are special function registers (SFRs) to set the PWM0 periods. Note: When PW0PH or PW0PL is set to “0000H”, the PWM0 period buffer (PW0PBUF) is set to “0001H”. FEUL610Q438 11-3 ML610Q438/ML610Q439 User’s Manual Chapter 11 PWM 11.2.3 PWM1 Period Registers (PW1PL, PW1PH) Address: 0F0A8H Access: R/W Access size: 8 bits Initial value: 0FFH 7 6 5 4 3 2 1 0 PW1PL P1P7 P1P6 P1P5 P1P4 P1P3 P1P2 P1P1 P1P0 R/W R/W R/W R/W R/W R/W R/W R/W R/W At reset 1 1 1 1 1 1 1 1 7 6 5 4 3 2 1 0 PW1PH P1P15 P1P14 P1P13 P1P12 P1P11 P1P10 P1P9 P1P8 R/W R/W R/W R/W R/W R/W R/W R/W R/W At reset 1 1 1 1 1 1 1 1 Address: 0F0A9H Access: R/W Access size: 8 bits Initial value: 0FFH PW1PH and PW1PL are special function registers (SFRs) to set the PWM1 periods. Note: When PW1PH or PW1PL is set to “0000H”, the PWM1 period buffer (PW1PBUF) is set to “0001H”. FEUL610Q438 11-4 ML610Q438/ML610Q439 User’s Manual Chapter 11 PWM 11.2.4 PWM2 Period Registers (PW2PL, PW2PH) Address: 0F0B0H Access: R/W Access size: 8 bits Initial value: 0FFH 7 6 5 4 3 2 1 0 PW2PL P2P7 P2P6 P2P5 P2P4 P2P3 P2P2 P2P1 P2P0 R/W R/W R/W R/W R/W R/W R/W R/W R/W At reset 1 1 1 1 1 1 1 1 7 6 5 4 3 2 1 0 PW2PH P2P15 P2P14 P2P13 P2P12 P2P11 P2P10 P2P9 P2P8 R/W R/W R/W R/W R/W R/W R/W R/W R/W At reset 1 1 1 1 1 1 1 1 Address: 0F0B1H Access: R/W Access size: 8 bits Initial value: 0FFH PW2PH and PW2PL are special function registers (SFRs) to set the PWM2 periods. Note: When PW2PH or PW2PL is set to “0000H”, the PWM2 period buffer (PW2PBUF) is set to “0001H”. FEUL610Q438 11-5 ML610Q438/ML610Q439 User’s Manual Chapter 11 PWM 11.2.5 PWM0 Duty Registers (PW0DL, PW0DH) 7 6 5 4 3 2 1 0 PW0DL P0D7 P0D6 P0D5 P0D4 P0D3 P0D2 P0D1 P0D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W At reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 PW0DH P0D15 P0D14 P0D13 P0D12 P0D11 P0D10 P0D9 P0D8 R/W R/W R/W R/W R/W R/W R/W R/W R/W At reset 0 0 0 0 0 0 0 0 Address: 0F0A2H Access: R/W Access size: 8 bits Initial value: 00H Address: 0F0A3H Access: R/W Access size: 8 bits Initial value: 00H PW0DH and PW0DL are special function registers (SFRs) to set the duties of PWM0. Note: Set PW0DH and PW0DL to values smaller than those to which PW0PH and PW0PL are set. FEUL610Q438 11-6 ML610Q438/ML610Q439 User’s Manual Chapter 11 PWM 11.2.6 PWM1 Duty Registers (PW1DL, PW1DH) 7 6 5 4 3 2 1 0 PW1DL P1D7 P1D6 P1D5 P1D4 P1D3 P1D2 P1D1 P1D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W At reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 PW1DH P1D15 P1D14 P1D13 P1D12 P1D11 P1D10 P1D9 P1D8 R/W R/W R/W R/W R/W R/W R/W R/W R/W At reset 0 0 0 0 0 0 0 0 Address: 0F0AAH Access: R/W Access size: 8 bits Initial value: 00H Address: 0F0ABH Access: R/W Access size: 8 bits Initial value: 00H PW1DH and PW1DL are special function registers (SFRs) to set the duties of PWM1. Note: Set PW1DH and PW1DL to values smaller than those to which PW1PH and PW1PL are set. FEUL610Q438 11-7 ML610Q438/ML610Q439 User’s Manual Chapter 11 PWM 11.2.7 PWM2 Duty Registers (PW2DL, PW2DH) 7 6 5 4 3 2 1 0 PW2DL P2D7 P2D6 P2D5 P2D4 P2D3 P2D2 P2D1 P2D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W At reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 PW2DH P2D15 P2D14 P2D13 P2D12 P2D11 P2D10 P2D9 P2D8 R/W R/W R/W R/W R/W R/W R/W R/W R/W At reset 0 0 0 0 0 0 0 0 Address: 0F0B2H Access: R/W Access size: 8 bits Initial value: 00H Address: 0F0B3H Access: R/W Access size: 8 bits Initial value: 00H PW2DH and PW2DL are special function registers (SFRs) to set the duties of PWM2. Note: Set PW2DH and PW2DL to values smaller than those to which PW2PH and PW2PL are set. FEUL610Q438 11-8 ML610Q438/ML610Q439 User’s Manual Chapter 11 PWM 11.2.8 PWM0 Counter Registers (PW0CH, PW0CL) 7 6 5 4 3 2 1 0 PW0CL P0C7 P0C6 P0C5 P0C4 P0C3 P0C2 P0C1 P0C0 R/W R/W R/W R/W R/W R/W R/W R/W R/W At reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 PW0DH P0C15 P0C14 P0C13 P0C12 P0C11 P0C10 P0C9 P0C8 R/W R/W R/W R/W R/W R/W R/W R/W R/W At reset 0 0 0 0 0 0 0 0 Address: 0F0A4H Access: R/W Access size: 8 bits Initial value: 00H Address: 0F0A5H Access: R/W Access size: 8 bits Initial value: 00H PW0CL and PW0CH are special function registers (SFRs) that function as 16-bit binary counters. When data is written to either PW0CL or PW0CH, PW0CL and PW0CH is set to “0000H”. The data that is written is meaningless. When data is read from PW0CL, the value of PW0CH is latched. When reading PW0CH and PW0CL, use a word type instruction or pre-read PW0CL. The contents of PW0CH and PW0CL during PWM operation cannot be read depending on the combination of the PWM clock and system clock. Table 11-1 shows PW0CH and PW0CL read enable/disable for each combination of the PWM clock and system clock. Table 11-1 PW0CH and PW0CL Read Enable/Disable during PWM0 Operation PWM clock P0CK LSCLK System clock SYSCLK LSCLK LSCLK HSCLK HTBCLK HTBCLK LSCLK HSCLK LSCLK HSCLK External clock FEUL610Q438 PW0CH and PW0CL read enable/disable Read enabled Read enabled. However, to prevent the reading of undefined data during counting, read consecutively PW0CH or PW0CL twice until the last data coincides the previous data. Read disabled Read enabled Read disabled 11-9 ML610Q438/ML610Q439 User’s Manual Chapter 11 PWM 11.2.9 PWM1 Counter Registers (PW1CH, PW1CL) 7 6 5 4 3 2 1 0 PW1CL P1C7 P1C6 P1C5 P1C4 P1C3 P1C2 P1C1 P1C0 R/W R/W R/W R/W R/W R/W R/W R/W R/W At reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 PW1DH P1C15 P1C14 P1C13 P1C12 P1C11 P1C10 P1C9 P1C8 R/W R/W R/W R/W R/W R/W R/W R/W R/W At reset 0 0 0 0 0 0 0 0 Address: 0F0ACH Access: R/W Access size: 8 bits Initial value: 00H Address: 0F0ADH Access: R/W Access size: 8 bits Initial value: 00H PW1CL and PW1CH are special function registers (SFRs) that function as 16-bit binary counters. When data is written to either PW1CL or PW1CH, PW1CL and PW1CH is set to “0000H”. The data that is written is meaningless. When data is read from PW1CL, the value of PW1CH is latched. When reading PW1CH and PW1CL, use a word type instruction or pre-read PW1CL. The contents of PW1CH and PW1CL during PWM operation cannot be read depending on the combination of the PWM clock and system clock. Table 10-2 shows PW1CH and PW1CL read enable/disable for each combination of the PWM clock and system clock. Table 11-2 PW1CH and PW1CL Read Enable/Disable during PWM1 Operation PWM clock P1CK LSCLK System clock SYSCLK LSCLK LSCLK HSCLK HTBCLK HTBCLK LSCLK HSCLK LSCLK HSCLK External clock FEUL610Q438 PW1CH and PW1CL read enable/disable Read enabled Read enabled. However, to prevent the reading of undefined data during counting, read consecutively PW1CH or PW1CL twice until the last data coincides the previous data. Read disabled Read enabled Read disabled 11-10 ML610Q438/ML610Q439 User’s Manual Chapter 11 PWM 11.2.10 PWM2 Counter Registers (PW2CH, PW2CL) 7 6 5 4 3 2 1 0 PW2CL P2C7 P2C6 P2C5 P2C4 P2C3 P2C2 P2C1 P2C0 R/W R/W R/W R/W R/W R/W R/W R/W R/W At reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 PW2DH P2C15 P2C14 P2C13 P2C12 P2C11 P2C10 P2C9 P2C8 R/W R/W R/W R/W R/W R/W R/W R/W R/W At reset 0 0 0 0 0 0 0 0 Address: 0F0B4H Access: R/W Access size: 8 bits Initial value: 00H Address: 0F0B5H Access: R/W Access size: 8 bits Initial value: 00H PW2CL and PW2CH are special function registers (SFRs) that function as 16-bit binary counters. When data is written to either PW2CL or PW2CH, PW2CL and PW2CH is set to “0000H”. The data that is written is meaningless. When data is read from PW2CL, the value of PW2CH is latched. When reading PW2CH and PW2CL, use a word type instruction or pre-read PW2CL. The contents of PW2CH and PW2CL during PWM operation cannot be read depending on the combination of the PWM clock and system clock. Table 10-3 shows PW2CH and PW2CL read enable/disable for each combination of the PWM clock and system clock. Table 11-3 PW2CH and PW2CL Read Enable/Disable during PWM2 Operation PWM clock P2CK LSCLK System clock SYSCLK LSCLK LSCLK HSCLK HTBCLK HTBCLK LSCLK HSCLK LSCLK HSCLK External clock FEUL610Q438 PW2CH and PW2CL read enable/disable Read enabled Read enabled. However, to prevent the reading of undefined data during counting, read consecutively PW2CH or PW2CL twice until the last data coincides the previous data. Read disabled Read enabled Read disabled 11-11 ML610Q438/ML610Q439 User’s Manual Chapter 11 PWM 11.2.11 PWM0 Control Register 0 (PW0CON0) 7 6 5 4 3 2 1 0 PW0CON0    P0NEG P0IS1 P0IS0 P0CS1 P0CS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W At reset 0 0 0 0 0 0 0 0 Address: 0F0A6H Access: R/W Access size: 8 bits Initial value: 00H PW0CON0 is a special function register (SFR) to control PWM0. [Description of Bits] • P0CS1, P0CS0 (bits 1, 0) The P0CS1 and P0CS0 bits are used to select the PWM0 operation clocks. LSCLK, HTBCLK, or the external clock (P44/T02P0CK) can be selected. P0CS1 0 0 1 1 P0CS0 0 1 0 1 Description LSCLK (initial value) HTBCLK Prohibited (the PWM circuit does not operate) External clock (P44/T02P0CK) • P0IS1, P0IS0 (bits 3, 2) The P0IS1 and P0IS0 bits are used to select the point at which the PWM0 interrupt occurs. “When the periods coincide”, “when the duties coincide”, or “when the periods and duties coincide” can be selected. P0IS1 0 0 1 P0IS0 0 1 * Description When the periods coincide. (Initial value) When the duties coincide. When the periods and duties coincide. • P0NEG (bit 4) The P0NEG bit is used to select the output logic. When the positive logic is selected, the initial value of PWM0 output is “1”, and when the negative logic is selected, the initial value of PWM0 output is “0”. P0NEG 0 1 Description Positive logic (initial value) Negative logic FEUL610Q438 11-12 ML610Q438/ML610Q439 User’s Manual Chapter 11 PWM 11.2.12 PWM1 Control Register 0 (PW1CON0) 7 6 5 4 3 2 1 0 PW1CON0    P1NEG P1IS1 P1IS0 P1CS1 P1CS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W At reset 0 0 0 0 0 0 0 0 Address: 0F0AEH Access: R/W Access size: 8 bits Initial value: 00H PW1CON0 is a special function register (SFR) to control PWM1. [Description of Bits] • P1CS1, P1CS0 (bits 1, 0) The P1CS1 and P1CS0 bits are used to select the PWM1 operation clocks. LSCLK, HTBCLK, or the external clock (P44/T02P0CK) can be selected. P1CS1 0 0 1 1 P1CS0 0 1 0 1 Description LSCLK (initial value) HTBCLK Prohibited (the PWM circuit does not operate) External clock (P44/T02P0CK) • P1IS1, P1IS0 (bits 3, 2) The P1IS1 and P1IS0 bits are used to select the point at which the PWM1 interrupt occurs. “When the periods coincide”, “when the duties coincide”, or “when the periods and duties coincide” can be selected. P1IS1 0 0 1 P1IS0 0 1 * Description When the periods coincide. (Initial value) When the duties coincide. When the periods and duties coincide. • P1NEG (bit 4) The P1NEG bit is used to select the output logic. When the positive logic is selected, the initial value of PWM1 output is “1”, and when the negative logic is selected, the initial value of PWM1 output is “0”. P1NEG 0 1 Description Positive logic (initial value) Negative logic FEUL610Q438 11-13 ML610Q438/ML610Q439 User’s Manual Chapter 11 PWM 11.2.13 PWM2 Control Register 0 (PW2CON0) 7 6 5 4 3 2 1 0 PW2CON0    P2NEG P2IS1 P2IS0 P2CS1 P2CS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W At reset 0 0 0 0 0 0 0 0 Address: 0F0B6H Access: R/W Access size: 8 bits Initial value: 00H PW2CON0 is a special function register (SFR) to control PWM2. [Description of Bits] • P2CS1, P2CS0 (bits 1, 0) The P2CS1 and P2CS0 bits are used to select the PWM2 operation clocks. LSCLK, HTBCLK, or the external clock (P44/T02P0CK) can be selected. P2CS1 0 0 1 1 P2CS0 0 1 0 1 Description LSCLK (initial value) HTBCLK Prohibited (the PWM circuit does not operate) External clock (P44/T02P0CK) • P2IS1, P2IS0 (bits 3, 2) The P2IS1 and P2IS0 bits are used to select the point at which the PWM2 interrupt occurs. “When the periods coincide”, “when the duties coincide”, or “when the periods and duties coincide” can be selected. P2IS1 0 0 1 P2IS0 0 1 * Description When the periods coincide. (Initial value) When the duties coincide. When the periods and duties coincide. • P2NEG (bit 4) The P2NEG bit is used to select the output logic. When the positive logic is selected, the initial value of PWM2 output is “1”, and when the negative logic is selected, the initial value of PWM2 output is “0”. P2NEG 0 1 Description Positive logic (initial value) Negative logic FEUL610Q438 11-14 ML610Q438/ML610Q439 User’s Manual Chapter 11 PWM 11.2.14 PWM0 Control Register 1 (PW0CON1) 7 6 5 4 3 2 1 0 PW0CON1 P0STAT P0FLG      P0RUN R/W R R/W R/W R/W R/W R/W R/W R/W At reset 0 1 0 0 0 0 0 0 Address: 0F0A7H Access: R/W Access size: 8 bits Initial value: 40H PW0CON1 is a special function register (SFR) to control PWM0. [Description of Bits] • P0RUN (bit 0) The P0RUN bit is used to control count stop/start of PWM0. P0RUN 0 1 Description Stops counting. (Initial value) Starts counting. • P0FLG (bit 6) The P0FLG bit is used to read the output flag of PWM0. This bit is set to “1” when write operation to PW0CH or PW0CL is performed, P0FLG 0 1 Description PWM0 output flag = “0” PWM0 output flag = “1” (initial value) • P0STAT (bit 7) The P0STAT bit indicates “counting stopped or “counting in progress” of PWM0. P0STAT 0 1 Description Counting stopped. (Initial value) Counting in progress. FEUL610Q438 11-15 ML610Q438/ML610Q439 User’s Manual Chapter 11 PWM 11.2.15 PWM1 Control Register 1 (PW1CON1) 7 6 5 4 3 2 1 0 PW1CON1 P1STAT P1FLG      P1RUN R/W R R/W R/W R/W R/W R/W R/W R/W At reset 0 1 0 0 0 0 0 0 Address: 0F0AFH Access: R/W Access size: 8 bits Initial value: 40H PW1CON1 is a special function register (SFR) to control PWM1. [Description of Bits] • P1RUN (bit 0) The P1RUN bit is used to control count stop/start of PWM1. P1RUN 0 1 Description Stops counting. (Initial value) Starts counting. • P1FLG (bit 6) The P1FLG bit is used to read the output flag of PWM1. This bit is set to “1” when write operation to PW1CH or PW1CL is performed, P1FLG 0 1 Description PWM1 output flag = “0” PWM1 output flag = “1” (initial value) • P1STAT (bit 7) The P1STAT bit indicates “counting stopped or “counting in progress” of PWM1. P1STAT 0 1 Description Counting stopped. (Initial value) Counting in progress. FEUL610Q438 11-16 ML610Q438/ML610Q439 User’s Manual Chapter 11 PWM 11.2.16 PWM2 Control Register 1 (PW2CON1) 7 6 5 4 3 2 1 0 PW2CON1 P2STAT P2FLG      P2RUN R/W R R/W R/W R/W R/W R/W R/W R/W At reset 0 1 0 0 0 0 0 0 Address: 0F0B7H Access: R/W Access size: 8 bits Initial value: 40H PW2CON1 is a special function register (SFR) to control PWM2. [Description of Bits] • P2RUN (bit 0) The P2RUN bit is used to control count stop/start of PWM2. P2RUN 0 1 Description Stops counting. (Initial value) Starts counting. • P2FLG (bit 6) The P2FLG bit is used to read the output flag of PWM2. This bit is set to “1” when write operation to PW2CH or PW2CL is performed, P2FLG 0 1 Description PWM2 output flag = “0” PWM2 output flag = “1” (initial value) • P2STAT (bit 7) The P2STAT bit indicates “counting stopped or “counting in progress” of PWM2. P2STAT 0 1 Description Counting stopped. (Initial value) Counting in progress. FEUL610Q438 11-17 ML610Q438/ML610Q439 User’s Manual Chapter 11 PWM 11.3 Description of Operation The PWMn(n=0 to 2) counter registers (PWnCH, PWnCL) are set to an operating state (PnSTAT is set to “1”) on the first falling edge of the PWMn clock (PnCK) that are selected by the PWMn control register 0 (PWnCON0) when the PnRUN bit of PWMn control register 1 (PWnCON1) is set to “1” and increment the count value on the 2nd falling edge. When the count value of PWMn counter registers and the value of the PWMn duty buffer (PWnDBUF) coincide, the PWMn flag (PnFLG) is set to “0” on the next timer clock falling edge of PnCK. When the count value of PWMn counter registers and the value of the PWMn period buffer (PWnPBUF) coincide, the PWMn flag (PnFLG) is set to “1” on the next falling edge of PnCK and PWMn counter registers is set to “0000H” and incremental counting continues. At the same time, the value of the PWMn duty register (PWnDH, PWnDL) is transferred to the PWMn duty buffer (PWnDBUF) and the value of PWMn period register (PWnPH, PWnPL) to the PWMn period buffer (PWnPBUF). When the PnRUN bit is set to “0”, PWMn counter registers stop counting after counting once the falling of the PWMn clock (PnCK). Confirm that PWnCH and PWnCL are stopped by checking that the PnSTAT bit of the PWMn control register 1 (PWnCON1) is “0”. When the PnRUN bit is set to “1” again, PWMn counter registers restarts incremental counting from the previous value on the falling edge of PnCK. To initialize PWMn counter registers to “0000H”, perform write operation in either of PWnCH or PWnCL. At that time, PnFLG is also set to “1”. When data is written in the PWMn duty register (PWnDH, PWnDL) during count stop (PnRUN is in a “1” state), the data is transferred to the PWMn duty buffer (PWnDBUF) and when data is written in the PWMn period register (PWnPH, PWnPL), the data is transferred to the PWMn period buffer (PWnPBUF). The PWMn clock, the point at which an interrupt of PWMn occurs, and the logic of the PWMn output are selected by PWMn control register 0 (PWnCN0). The period of the PWMn signal (TPWPn) and the first half duration (TPWDn) of the duty are expressed by the following equations. TPWPn = PWnP + 1 PnCK (Hz) TPWPn = PWnD + 1 PnCK (Hz) (n = 0 to 2) PWnP: PWnD: PnCK: FEUL610Q438 PWMn period registers (PWnPH, PWnPL) setting value (0001H to 0FFFFH) PWMn duty registers (PWnDH, PWnDL) setting value (0000H to 0FFFEH) Clock frequency selected by the PWMn control register 0 (PWnCON0) 11-18 ML610Q438/ML610Q439 User’s Manual Chapter 11 PWM After the PnRUN bit is set to “1”, counting starts in synchronization with the PWMn clock. This causes an error of up to 1 clock pulse to the time the first PWMn interrupt is issued. The PWMn interrupt period from the second time is fixed. Figure 11-2 shows the operation timing of PWMn. (n = 0 to 2) PnCK PnRUN PnSTAT Write PWnCH Write PWnCL PWnCH/L XXXX 0000 PWnDH/L 8000 PWnDBUF 8000 PWnPH/L A000 PWnPBUF A000 0001 0002 7FFF 8000 8001 8002 7777 BBBB A000 A000 0000 0001 7777 7777 8000 8000 BBBB BBBB A000 A000 7777 BBBB PWnINT PnFLG PWMn* (Positive logic) PWMn* (negative logic) TPWD TPWP Figure 11-2 (1/2) Operation Timing Diagram of PWMn PnCK PnRUN PnSTAT PWnCH/L 2000 2001 2002 2003 2004 2005 2006 2007 2008 PnFLG Figure 11-2 (2/2) Operation Timing Diagram of PWMn Note: Even if “0” is written to the PnRUN bit, counting operation continues up to the falling edge (the PWMn status flag (Pn0STAT) is in a “1” state) of the next PWMn clock pulse. Therefore, the PWMn interrupt (PWnINT) may occur. FEUL610Q438 11-19 ML610Q438/ML610Q439 User’s Manual Chapter 11 PWM 11.4 Specifying port registers When you want to make sure the PWM function is working, please check related port registers are specified. See Chapter16, “Port 0”, Chapter 20, “Port 4” and Chapter 19, “Port 3” for detail about the port registers. 11.4.1 Functioning P43 (PWM0) as the PWM0 output Set P43MD1 bit (bit3 of P4MOD1 register) to “1” and set P43MD0 bit (bit3 of P4MOD0 register) to “0”, for specifying the PWM output as the tertiary function of P43. Reg. name P4MOD1 register (Address: 0F225H) Bit 7 6 5 4 3 2 1 0 Bit name P47MD1 P46MD1 P45MD1 P44MD1 P43MD1 P42MD1 P41MD1 P40MD1 Data * * * * 1 * * * Reg. name P4MOD0 register (Address: 0F224H) Bit 7 6 5 4 3 2 1 0 Bit name P47MD0 P46MD0 P45MD0 P44MD0 P43MD0 P42MD0 P41MD0 P40MD0 Data * * * * 0 * * * Set P43C1 bit (bit3 of P4CON1 register) to “1”, set P43C0 bit(bit3 of P4CON0 register) to “1” and set P43DIR bit(bit3 of P4DIR register) to “0”, for specifying the P43 as CMOS output. Reg. name P4CON1 register (Address: 0F223H) Bit 7 6 5 4 3 2 1 0 Bit name P47C1 P46C1 P45C1 P44C1 P43C1 P42C1 P41C1 P40C1 Data * * * * 1 * * * Reg. name P4CON0 register (Address: 0F222H) Bit 7 6 5 4 3 2 1 0 Bit name P47C0 P46C0 P45C0 P44C0 P43C0 P42C0 P41C0 P40C0 Data * * * * 1 * * * Reg. name P4DIR register (Address: 0F221H) Bit 7 6 5 4 3 2 1 0 Bit name P47DIR P46DIR P45DIR P44DIR P43DIR P42DIR P41DIR P40DIR Data * * * * 0 * * * Data of P43D bit (bit3 of P4D register) does not affect to the PWM output function, so don’t care the data for the function. Reg. name P4D register (Address: 0F220H) Bit 7 6 5 4 3 2 1 0 Bit name P47D P46D P45D P44D P43D P42D P41D P40D Data * * * * ** * * * * : Bit not related to the PWM function ** : Don’t care the data. FEUL610Q438 11-20 ML610Q438/ML610Q439 User’s Manual Chapter 11 PWM 11.4.2 Functioning P34 (PWM0) as the PWM0 output Set P34MD1 bit (bit4 of P3MOD1 register) to “1” and set P34MD0 bit (bit4 of P3MOD0 register) to “0”, for specifying the PWM output as the tertiary function of P34. Reg. name P3MOD1 register (Address: 0F21DH) Bit 7 6 5 4 3 2 1 0 Bit name - - P35MD1 P34MD1 P33MD1 P32MD1 P31MD1 P30MD1 Data - - * 1 * * * * Bit 7 6 5 4 3 2 1 0 Bit name - - P35MD0 P34MD0 P33MD0 P32MD0 P31MD0 P30MD0 Data - - * 0 * * * * Reg. name P3MOD0 register (Address: 0F21CH) Set P34C1 bit (bit4 of P3CON1 register) to “1”, set P34C0 bit(bit4 of P3CON0 register) to “1” and set P34DIR bit(bit4 of P3DIR register) to “0”, for specifying the P34 as CMOS output. Reg. name P3CON1 register (Address: 0F21BH) Bit 7 6 5 4 3 2 1 0 Bit name - - P35C1 P34C1 P33C1 P32C1 P31C1 P30C1 Data - - * 1 * * * * Reg. name P3CON0 register (Address: 0F21AH) Bit 7 6 5 4 3 2 1 0 Bit name - - P35C0 P34C0 P33C0 P32C0 P31C0 P30C0 Data - - * 1 * * * * Reg. name P3DIR register (Address: 0F219H) Bit 7 6 5 4 3 2 1 0 Bit name - - P35DIR P34DIR P33DIR P32DIR P31DIR P30DIR Data - - * 0 * * * * Data of P34D bit (bit4 of P3D register) does not affect to the PWM output function, so don’t care the data for the function. Reg. name P3D register (Address: 0F218H) Bit 7 6 5 4 3 2 1 0 Bit name - - P35D P34D P33D P32D P31D P30D Data - - * ** * * * * - : Bit does not exist. * : Bit not related to the PWM function ** : Don’t care the data. FEUL610Q438 11-21 ML610Q438/ML610Q439 User’s Manual Chapter 11 PWM 11.4.3 Functioning P47 (PWM1) as the PWM1 output Set P47MD1 bit (bit7 of P4MOD1 register) to “1” and set P47MD0 bit (bit7 of P4MOD0 register) to “0”, for specifying the PWM output as the tertiary function of P47. Reg. name P4MOD1 register (Address: 0F225H) Bit 7 6 5 4 3 2 1 0 Bit name P47MD1 P46MD1 P45MD1 P44MD1 P43MD1 P42MD1 P41MD1 P40MD1 Data 1 * * * * * * * Bit 7 6 5 4 3 2 1 0 Bit name P47MD0 P46MD0 P45MD0 P44MD0 P43MD0 P42MD0 P41MD0 P40MD0 Data 0 * * * * * * * Reg. name P4MOD0 register (Address: 0F224H) Set P47C1 bit (bit7 of P4CON1 register) to “1”, set P47C0 bit (bit7 of P4CON0 register) to “1” and set P47DIR bit (bit7 of P4DIR register) to “0”, for specifying the P47 as CMOS output. Reg. name P4CON1 register (Address: 0F223H) Bit 7 6 5 4 3 2 1 0 Bit name P47C1 P46C1 P45C1 P44C1 P43C1 P42C1 P41C1 P40C1 Data 1 * * * * * * * Reg. name P4CON0 register (Address: 0F222H) Bit 7 6 5 4 3 2 1 0 Bit name P47C0 P46C0 P45C0 P44C0 P43C0 P42C0 P41C0 P40C0 Data 1 * * * * * * * Reg. name P4DIR register (Address: 0F221H) Bit 7 6 5 4 3 2 1 0 Bit name P47DIR P46DIR P45DIR P44DIR P43DIR P42DIR P41DIR P40DIR Data 0 * * * * * * * Data of P47D bit (bit7 of P4D register) does not affect to the PWM output function, so don’t care the data for the function. Reg. name P4D register (Address: 0F220H) Bit 7 6 5 4 3 2 1 0 Bit name P47D P46D P45D P44D P43D P42D P41D P40D Data ** * * * * * * * * : Bit not related to the PWM function ** : Don’t care the data. FEUL610Q438 11-22 ML610Q438/ML610Q439 User’s Manual Chapter 11 PWM 11.4.4 Functioning P35 (PWM1) as the PWM1 output Set P35MD1 bit (bit5 of P3MOD1 register) to “1” and set P35MD0 bit (bit5 of P3MOD0 register) to “0”, for specifying the PWM output as the tertiary function of P35. Reg. name P3MOD1 register (Address: 0F21DH) Bit 7 6 5 4 3 2 1 0 Bit name - - P35MD1 P34MD1 P33MD1 P32MD1 P31MD1 P30MD1 Data - - 1 * * * * * Bit 7 6 5 4 3 2 1 0 Bit name - - P35MD0 P34MD0 P33MD0 P32MD0 P31MD0 P30MD0 Data - - 0 * * * * * Reg. name P3MOD0 register (Address: 0F21CH) Set P35C1 bit (bit5 of P3CON1 register) to “1”, set P35C0 bit (bit5 of P3CON0 register) to “1” and set P35DIR bit (bit5 of P3DIR register) to “0”, for specifying the P35 as CMOS output. Reg. name P3CON1 register (Address: 0F21BH) Bit 7 6 5 4 3 2 1 0 Bit name - - P35C1 P34C1 P33C1 P32C1 P31C1 P30C1 Data - - 1 * * * * * Reg. name P3CON0 register (Address: 0F21AH) Bit 7 6 5 4 3 2 1 0 Bit name - - P35C0 P34C0 P33C0 P32C0 P31C0 P30C0 Data - - 1 * * * * * Reg. name P3DIR register (Address: 0F219H) Bit 7 6 5 4 3 2 1 0 Bit name - - P35DIR P34DIR P33DIR P32DIR P31DIR P30DIR Data - - 0 * * * * * Data of P35D bit (bit5 of P3D register) does not affect to the PWM output function, so don’t care the data for the function. Reg. name P3D register (Address: 0F218H) Bit 7 6 5 4 3 2 1 0 Bit name - - P35D P34D P33D P32D P31D P30D Data - - ** * * * * * - : Bit does not exist. * : Bit not related to the PWM function ** : Don’t care the data. FEUL610Q438 11-23 ML610Q438/ML610Q439 User’s Manual Chapter 11 PWM 11.4.5 Functioning P20 (PWM2) as the PWM2 output Set P20MD1 bit (bit0 of P2MOD1 register) to “1” and set P20MD0 bit (bit0 of P2MOD0 register) to “0”, for specifying the PWM output as the tertiary function of P20. Reg. name P2MOD1 register (Address: 0F215H) Bit 7 6 5 4 3 2 1 0 Bit name - - - - - P22MD1 P21MD1 P20MD1 Data - - - - - * * 1 Bit 7 6 5 4 3 2 1 0 Bit name - - - - - P22MD0 P21MD0 P20MD0 Data - - - - - * * 0 Reg. name P2MOD0 register (Address: 0F214H) Set P20C1 bit (bit0 of P2CON1 register) to “1”, and set P20C0 bit (bit0 of P2CON0 register) to “1”, for specifying the P20 as CMOS output. Reg. name P2CON1 register (Address: 0F213H) Bit 7 6 5 4 3 2 1 0 Bit name - - - - - P22C1 P21C1 P20C1 Data - - - - - * * 1 Reg. name P2CON0 register (Address: 0F212H) Bit 7 6 5 4 3 2 1 0 Bit name - - - - - P22C0 P21C0 P20C0 Data - - - - - * * 1 Data of P20D bit (bit0 of P2D register) does not affect to the PWM output function, so don’t care the data for the function. Reg. name P2D register (Address: 0F210H) Bit 7 6 5 4 3 2 1 0 Bit name - - - - - P22D P21D P20D Data - - - - - * * ** * : Bit not related to the PWM function ** : Don’t care the data. FEUL610Q438 11-24 ML610Q438/ML610Q439 User’s Manual Chapter 11 PWM 11.4.6 Functioning P30 (PWM2) as the PWM2 output Set P30MD1 bit (bit0 of P3MOD1 register) to “1” and set P30MD0 bit (bit0 of P3MOD0 register) to “0”, for specifying the PWM output as the tertiary function of P30. Reg. name P3MOD1 register (Address: 0F21DH) Bit 7 6 5 4 3 2 1 0 Bit name - - P35MD1 P34MD1 P33MD1 P32MD1 P31MD1 P30MD1 Data - - * * * * * 1 Bit 7 6 5 4 3 2 1 0 Bit name - - P35MD0 P34MD0 P33MD0 P32MD0 P31MD0 P30MD0 Data - - * * * * * 0 Reg. name P3MOD0 register (Address: 0F21CH) Set P30C1 bit (bit0 of P3CON1 register) to “1”, set P30C0 bit (bit0 of P3CON0 register) to “1” and set P30DIR bit (bit0 of P3DIR register) to “0”, for specifying the P30 as CMOS output. Reg. name P3CON1 register (Address: 0F21BH) Bit 7 6 5 4 3 2 1 0 Bit name - - P35C1 P34C1 P33C1 P32C1 P31C1 P30C1 Data - - * * * * * 1 Reg. name P3CON0 register (Address: 0F21AH) Bit 7 6 5 4 3 2 1 0 Bit name - - P35C0 P34C0 P33C0 P32C0 P31C0 P30C0 Data - - * * * * * 1 Reg. name P3DIR register (Address: 0F219H) Bit 7 6 5 4 3 2 1 0 Bit name - - P35DIR P34DIR P33DIR P32DIR P31DIR P30DIR Data - - * * * * * 0 Data of P30D bit (bit0 of P3D register) does not affect to the PWM output function, so don’t care the data for the function. Reg. name P3D register (Address: 0F218H) Bit 7 6 5 4 3 2 1 0 Bit name - - P35D P34D P33D P32D P31D P30D Data - - * * * * * ** - : Bit does not exist. * : Bit not related to the PWM function ** : Don’t care the data. FEUL610Q438 11-25 Chapter 12 Watchdog Timer ML610Q438/ML610Q439 User’s Manual Chapter 122 Watchdog Timer 12. Watchdog Timer 12.1 Overview This LSI incorporates a watchdog timer (WDT) that operates at a system reset unconditionally (free-run operation) in order to detect an undefined state of the MCU and return from that state. If the WDT counter overflows due to the failure of clearing of the WDT counter within the WDT overflow period, the watchdog timer requests a WDT interrupt (non-maskable interrupt). When the second overflow occurs, the watchdog timer generates a WDT reset signal and shifts the mode to a system reset mode. For interrupts see Chapter 5, “Interrupts,” and for WDT interrupt see Chapter 3, “Reset Function”. 12.1.1 Features • • • • Non-maskable interrupt Free running (cannot be stopped) One of four types of overflow periods (125ms, 500ms, 2s, and 8s) selectable by software Reset generated by the second overflow 12.1.2 Configuration Figure 12-1 shows the configuration of the watchdog timer. WDT counter T256HZ R Reset interrupt control WDT reset WDTINT Non-maskable interrupt WDT overflow RESET_S System reset WDTCON WDTMOD “5AH” detection “0A5H” detection D R Q WDP QN WDTCON Write Data bus WDTCON WDTMOD : Watchdog timer control register : Watchdog timer mode register Figure 12-1 FEUL610Q438 Configuration of Watchdog Timer 12-1 ML610Q438/ML610Q439 User’s Manual Chapter 122 Watchdog Timer 12.2 Description of Registers 12.2.1 List of Registers Address 0F00EH 0F00FH Name Watchdog timer control register Watchdog timer mode register FEUL610Q438 Symbol (Byte) WDTCON WDTMOD Symbol (Word)   R/W R/W R/W Size 8 8 Initial value 00H 02H 12-2 ML610Q438/ML610Q439 User’s Manual Chapter 122 Watchdog Timer 12.2.2 Watchdog Timer Control Register (WDTCON) Address: 0F00EH Access: W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 WDTCON d7 d6 d5 d4 d3 d2 d1 WDP/d0 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 WDTCON is a special function register (SFR) to clear the WDT counter. When WDTCON is read, the value of the internal pointer (WDP) is read from bit 0. [Description of Bits] • WDP/d0 (bit 0) The value of the internal pointer (WDP) is read from this bit. The WDP is reset to “0” at the system reset or Watch Dog Timer overflow and is inverted every writing to WDTCON. • d7-d0 (bits 7-0) This bit is used to write data to clear the WDT counter. Write “5AH” on the condition of WDP is “0” and write “0A5H” on the condition of WDP is “1”. Note: Writing to WDTCON becomes enable after the system reset or releasing STOP mode and then the low-speed clock (LSCLK) oscillation starts. Untill the low-speed clock oscillation start, the WDP will not be inverted even if writing to the WDTCON. Therefore, please check the WDP before writing to the WDTCON to determine writing “5AH” or “0A5H”. Program example if ( WDP == 1 ){ WDTCON = 0xa5; } WDTCON = 0x5a; WDTCON = 0xa5; FEUL610Q438 /* WDP : 1 -> 0 */ /* WDP : 0 -> 1 */ /* WDP : 1 -> 0 */ 12-3 ML610Q438/ML610Q439 User’s Manual Chapter 122 Watchdog Timer 12.2.3 Watchdog Timer Mode Register (WDTMOD) Address: 0F00FH Access: W Access size: 8 bits Initial value: 02H 7 6 5 4 3 2 1 0 WDTMOD       WDT1 WDT0 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 1 R/W 0 WDTMOD is a special function register to set the overflow period of the watchdog timer. [Description of Bits] • WDT1-0 (bits 1-0) These bits are used to select an overflow period of the watchdog timer. The WDT1 and WDT0 bits set a overflow period (TWOV) of the WDT counter. One of 125ms, 500ms, 2s, and 8s can be selected. WDT1 0 0 1 1 FEUL610Q438 WDT0 0 1 0 1 Description 125 ms 500 ms 2 s (initial value) 8s 12-4 ML610Q438/ML610Q439 User’s Manual Chapter 122 Watchdog Timer 12.3 Description of Operation The WDT counter starts counting after the system reset has been released and the low-speed clock oscillation start.. Write "5AH" when the internal pointer (WDP) is "0"and then the WDT counter is cleared by writing "0A5H" when WDP is "1". WDP is reset to “0” at the time of system reset or when the WDT counter overflows and is inverted whenever data is written to WDTCON. When the WDT counter cannot be cleared within the WDT counter overflow period (TWOV), a watchdog timer interrupt (WDTINT) occurs. If the WDT counter is not cleared even by the software processing performed following the watchdog timer interrupt and overflow occurs again, WDT reset occurs and the mode shifts to a system reset mode. For the overflow period (TWOV) of the WDT counter, one of 125ms, 500ms, 2s, and 8s can be selected by the watchdog mode register (WDTMOD). Clear the WDT counter within the clear period of the WDT counter shown in Table 12-1. Table 12-1 WDT1 0 0 1 1 FEUL610Q438 WDT0 0 1 0 1 Clear Period of WDT Counter TWOV 125 ms 500 ms 2000 ms 8000 ms TWCL Approx. 121 ms Approx. 496 ms Approx. 1996 ms Approx. 7996 ms 12-5 ML610Q438/ML610Q439 User’s Manual Chapter 122 Watchdog Timer Figure 12-2 shows an example of watchdog timer operation. Program start Occurrence of abnormality Low-speed oscillation start WDTMOD setting RESET_S System reset Data:  5A  A5 WDTMOD setting  5A  5A  A5 5A A5 WDTCON Write WDTP Internal pointer Overflow WDT counter Occurrence of WDTINT WDTINT WDT interrupt Occurrence of WDT reset WDT reset TWOV Overflow period Figure 12-2 TWOV Overflow period Example of Watchdog Timer Operation       The WDT counter starts counting after the system reset has been released and the low-speed clock oscillation start. The overflow period of the WDT counter (TWOV) is set to WDTMOD. “5AH” is written to WDTCON. (Internal pointer 0→1) “0A5H” is written to WDTCON and the WDT counter is cleared. (Internal pointer 1→0) “5AH” is written o WDTCON. (Internal pointer 0→1) When “5AH” is written to WDTCON after the occurrence of abnormality, it cannot be accepted as the internal pointer is set to “1”. (Internal pointer 1→0)  Although “0A5H” is written to WDTCON, the WDT counter is not cleared since the internal pointer is “0” and the writing of “5AH” is not accepted in . (Internal pointer 0→1)  The WDT counter overflows and a watchdog timer interrupt request (WDTINT) is generated. In this case, the internal pointer is cleared to “0”.  If the WDT counter is not cleared even by the software processing performed following a watchdog timer interrupt and the WDT counter overflows again, WDT reset occurs and the mode is shifted to a system reset mode. Note: • In STOP mode, the watchdog timer operation also stops. • In HALT mode, the watchdog timer operation does not stop. When the WDT interrupt occurs, the HALT mode is released. • The watchdog timer cannot detect all the abnormal operations. Even if the CPU loses control, the watchdog timer cannot detect the abnormality in the operation state in which the WDT counter is cleared. FEUL610Q438 12-6 Chapter 13 Synchronous Serial Port ML610Q438/ML610Q439 User’s Manual Chapter 13 Synchronous Serial Port 13. Synchronous Serial Port 13.1 Overview This LSI includes one channel of the 8/16-bit synchronous serial port (SSIO) and can also be used to control the device incorporated with the SPI interface by using one GPIO as the chip enable pin. For the input clock, see Chapter 6, “Clock Generation Circuit”. When the synchronous serial port is used, the tertiary functions of port 4 must be set. For the tertiary functions of port 4, see Chapter 21, “Port 4”. 13.1.1 Features • Master or slave selectable • MSB first or LSB first selectable • 8-bit length or 16-bit length selectable fro the data length 13.1.2 Configuration Figure 13-1 shows the configuration of the synchronous serial port. SIO0INT P41/SCK0 P45/SCK0 P40/SIN0 P44/SIN0 T32KHZ to T128HZ TBC 1/4 HSCLK to 1/64 HSCLK P41/SCK0 P45/SCK0 Shift register 8 bits/16 bits Transmit register SIO0TRH, L Control circuit SIO0CON SIO0MOD0 SIO0MOD1 P42/SOUT0 P46/SOUT0 Receive register SIO0RCH, L LSB/MSB control SIO0BUFH, SIO0BUFL Data bus SIO0BUFL: SIO0BUFH: SIO0CON: SIO0MOD0: SIO0MOD1: Serial port transmit/receive buffer L Serial port transmit/receive buffer H Serial port control register Serial port mode register 0 Serial port mode register 1 Figure 13-1 FEUL610Q438 Configuration of Synchronous Serial Port 13-1 ML610Q438/ML610Q439 User’s Manual Chapter 13 Synchronous Serial Port 13.1.3 List of Pins Pin name P40/SIN0 P44/SIN0 P41/SCK0 P45/SCK0 P42/SOUT0 P46/SOUT0 FEUL610Q438 I/O I Description Receive data input. Used for the tertiary function of the P40 and P44 pins. I/O Synchronous clock input/output. Used for the tertiary function of the P41 and P45 pins. O Transmit data output. Used for the tertiary function of the P42 and P46 pins. 13-2 ML610Q438/ML610Q439 User’s Manual Chapter 13 Synchronous Serial Port 13.2 Description of Registers 13.2.1 List of Registers Address 0F280H 0F281H 0F282H 0F284H 0F285H FEUL610Q438 Name Serial port 0 transmit/receive buffer L Serial port 0 transmit/receive buffer H Serial port 0 control register Serial port 0 mode register 0 Serial port 0 mode register 1 Symbol (Byte) Symbol (Word) SIO0BUFL R/W Size Initial value R/W 8/16 00H R/W 8 00H R/W R/W R/W 8 8/16 8 00H 00H 00H SIO0BUF SIO0BUFH SIO0CON SIO0MOD0 SIO0MOD1  SIO0MOD 13-3 ML610Q438/ML610Q439 User’s Manual Chapter 13 Synchronous Serial Port 13.2.2 Serial Port Transmit/Receive Buffers (SIO0BUFL, SIO0BUFH) Address: 0F280H Access: R/W Access size: 8 bits/16 bits Initial value: 00H 7 6 5 4 3 2 1 0 SIO0BUFL S0B7 S0B6 S0B5 S0B4 S0B3 S0B2 S0B1 S0B0 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 SIO0BUFH S0B15 S0B14 S0B13 S0B12 S0B11 S0B10 S0B9 S0B8 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Address: 0F281H Access: R/W Access size: 8 bits Initial value: 00H SIO0BUFL and SIO0BUFH are special function registers (SFRs) to write transmit data and to read receive data of the synchronous serial port. When data is written in SIO0BUFL and SIO0BUFH, the data is written in the transmit registers (SIO0TRL and SIO0TRH) and when data is read from SIO0BUFL and SIO0BUFH, the contents of the receive registers (SIO0RCL and SIO0RCH) are read. FEUL610Q438 13-4 ML610Q438/ML610Q439 User’s Manual Chapter 13 Synchronous Serial Port 13.2.3 Serial Port Control Register (SIO0CON) Address: 0F282H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 SIO0CON        S0EN R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 SIO0CON is a special function register (SFR) to control the synchronous serial port. [Description of Bits] • S0EN (bit 0) The S0EN bit is used to specify start of synchronous serial communication. Writing a “1” to this bit starts 8-/16-bit data communication. This bit is set to “0” automatically when 8-/16-bit data communication is terminated. The S0EN bit is set to “0” at a system reset. S0EN 0 1 FEUL610Q438 Description Stops communication. (Initial value) Starts communication 13-5 ML610Q438/ML610Q439 User’s Manual Chapter 13 Synchronous Serial Port 13.2.4 Serial Port Mode Register 0 (SIO0MOD0) Address: 0F284H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 SIO0MOD0     S0LG S0MD1 S0MD0 S0DIR R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 SIO0MOD0 is a special function register (SFR) to set mode of the synchronous serial port. [Description of Bits] • S0DIR (bit 0) The S0DIR is used to select LSB first or MSB first. S0DIR 0 1 Description LSB first (initial value) MSB first • S0MD1, S0MD0 (bits 2, 1) The S0MD1 and S0MD0 bits are used to select transmit, receive, or transmit/receive mode of the synchronous serial port. S0MD1 0 0 1 1 S0MD0 0 1 0 1 Description Stops transmission/reception (initial value) Receive mode Transmit mode Transmit/receive mode • S0LG (bit 3) The S0LG bit is used to specify the bit length of the transmit/receive buffer, 8-bit or 16-bit length. The S0LG bit is set to “0” at a system reset. S0LG 0 1 Description 8-bit length (initial value) 16-bit length Note: • Do not change any of the SIO0MOD0 register settings during transmission/reception. • When the synchronous serial port is used, the tertiary functions of GPIO must be set. For the tertiary functions of Port 4, see Chapter 21, “Port 4”. FEUL610Q438 13-6 ML610Q438/ML610Q439 User’s Manual Chapter 13 Synchronous Serial Port 13.2.5 Serial Port Mode Register 1 (SIO0MOD1) Address: 0F285H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 SIO0MOD1    S0CKT S0CK3 S0CK2 S0CK1 S0CK0 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 SIO0MOD1 is a special function register (SFR) to set mode of the synchronous serial port. [Description of Bits] • S0CK3 to S0CK0 (bits 3 to 0) The S0CK3 to S0CK0 bits are used to select the transfer clock of the synchronous serial port. When the internal clock is selected, this LSI is set to master mode and when the external clock is selected, it is set to slave mode. S0CK3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 S0CK2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 S0CK1 0 0 1 1 0 0 1 1 0 0 1 1 * * S0CK0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Description 32 KHz (initial value) 16 KHz 1/4 HSCLK 1/8 HSCLK 1/16 HSCLK 1/32 HSCLK External clock 0 (P41/SCK0) External clock 1 (P45/SCK0) timer0 int clock (1/1) timer1 int clock (1/1) timer0 int clock (1/2) timer1 int clock (1/2) HSCLK 1/2HSCLK • S0CKT (bit 4) The S0CKT bit is used to select a tansfer clock output phase. S0CKT 0 1 FEUL610Q438 Description Clock type 0: Clock is output with a “H” level being the default. (Initial value) Clock type 1: Clock is output with a “L” level being the default. 13-7 ML610Q438/ML610Q439 User’s Manual Chapter 13 Synchronous Serial Port 13.3 Description of Operation 13.3.1 Transmit Operation When “1” is written to the S0MD1 bit and “0” is written to the S0MD0 bit of the serial mode register (SIO0MOD0), this LSI is set to a transmit mode. When transmit data is written to the serial port transmit /receive buffer (SIO0BUFL and H) and the S0EN bit of the serial port control register (SIO0CON) is set to “1”, transmission starts. When transmission of 8/16-bit data terminates, a synchronous serial port interrupt (SIO0INT) occurs and the S0EN bit is set to “0”. Transmit data is output from the tertiary function pins (P42/SOUT0 or P46/SOUT0) of GPIO. When an internal clock is selected in the serial port mode register (SIO0MOD1), the LSI is set to a master mode and when an external clock (P41/SCK0 or P45/SCK0) is selected, the LSI is set to a slave mode. The serial port mode register (SIO0MOD0) enables selection of MSB first/LSB first. The transmit data output pin (P42/SOUT0 or P46/SOUT0) and transfer clock input/output pin (P41/SCK0 or P45/SCK0) must be set to the tertiary functions. Figures 13-2 and 13-3 show the transmit operation waveforms of the synchronous serial ports for clock type 0 and clock type 1, respectively (8-bit length, LSB first, clock types 0 and 1). S0EN SCK0 SIO0TRL SOUT0 Transmit data 0 1 2 3 4 5 6 7 SIO0INT Figure 13-2 Transmit Operation Waveforms of Synchronous Serial Port for Clock Type 0 (8-bit Length, LSB first) S0EN SCK0 SIO0TRL SOUT0 Transmit data 0 1 2 3 4 5 6 7 SIO0INT Figure 13-3 FEUL610Q438 Transmit Operation Waveforms of Synchronous Serial Port for Clock Type 1 (8-bit Length, LSB first) 13-8 ML610Q438/ML610Q439 User’s Manual Chapter 13 Synchronous Serial Port 13.3.2 Receive Operation When “0” is written to the S0MD1 bit and “1” is written to the S0MD0 bit of the serial mode register (SIO0MOD0), this LSI is set to a receive mode. When the S0EN bit of the serial port control register (SIO0CON) is set to “1”, reception starts. When reception of 8/16-bit data terminates, a synchronous serial port interrupt (SIO0INT) occurs and the S0EN bit is set to “0”. Receive data is input from the tertiary function pins (P40/SIN0 or P44/SIN0) of GPIO. When an internal clock is selected in the serial port mode register (SIO0MD1), the LSI is set to a master mode and when an external clock (P41/SCK0 or P45/SCK0) is selected, the LSI is set to a slave mode. The serial port mode register (SIO0MOD0) enables selection of MSB first or LSB first. The receive data input pin (P40/SIN0 or P44/SIN0) and transfer clock input/output pin (P41/SCK0 or P45/SCK0) must be set to the tertiary function. Figures 13-4 and 13-5 show the receive operation waveforms of the synchronous serial ports for clock type 0 and clock type 1, respectively (8-bit length, MSB first, clock types 0 and 1). S0EN SCK0 SIN0 7 Shift register 6 7 5 6 4 5 3 4 2 3 1 2 0 0 1 SIO0RCL Receive data SIO0INT Figure 13-4 Receive Operation Waveforms of Synchronous Serial Port for Clock Type 0 (8-bit Length, MSB first) S0EN SCK0 SIN0 Shift register SIO0RCL 6 7 7 5 6 4 5 3 4 2 3 1 2 0 1 0 Receive data SIO0INT Figure 13-5 Receive Operation Waveforms of Synchronous Serial Port for Clock Type 1 (8-bit Length, MSB first) Note: When the SOUT0 pin is set to the tertiary function output in receive mode, a “H” level is output from the SOUT0 output pin. FEUL610Q438 13-9 ML610Q438/ML610Q439 User’s Manual Chapter 13 Synchronous Serial Port 13.3.3 Transmit/Receive Operation When “1” is written to the S0MD1 bit and “1” is written to the S0MD0 bit of the serial mode register (SIO0MOD0), this LSI is set to a transmit/receive mode. When the S0EN bit of the serial port control register (SIO0CON) is set to “1”, transmission/reception starts. When transmission/reception of 8/16-bit data terminates, a synchronous serial port interrupt (SIO0INT) occurs and the S0EN bit is set to “0”. Receive data is input from the tertiary function pins (P40/SIN0 or P44/SIN0) of GPIO, and transmit data is output from the tertiary function pins (P42/SOUT0 or P46/SOUT0) of GPIO When an internal clock is selected in the serial port mode register (SIO0MD1), the LSI is set to a master mode and when an external clock (P41/SCK0 or P45/SCK0) is selected, the LSI is set ot a slave mode. The serial port mode register (SIO0MOD0) enables selection of MSB first or LSB first. The receive data input pin (P40/SIN0 or P44/SIN0), the transmit data output pin (P42/SOUT0 or P46/SOUT0), and transfer clock input/output pin (P41/SCK0 or P45/SCK0) must be set to the tertiary function. Figure 13-6 shows the transmit/receive operation waveforms of the synchronous serial port (16-bit length, LSB first, clock types 0). S0EN SCK0 SIO0TRH,L Transmit data SOUT0 0 1 2 3 12 13 14 15 SIN0 0 1 2 3 12 13 14 15 Shift register SIO0RCH, L 0 1 2 3 12 13 14 15 Receive data SIO0INT Figure 13-6 FEUL610Q438 Transmit/Receive Operation Waveforms of Synchronous Serial Port (16-bit Length, LSB first, Clock Type 0) 13-10 ML610Q438/ML610Q439 User’s Manual Chapter 13 Synchronous Serial Port 13.4 Specifying port registers When you want to make sure the SSIO function is working, please check related port registers are specified. See Chapter 21, “Port 4” for detail about the port registers. 13.4.1 Functioning P42 (SOUT0), P41 (SCK0) and P40 (SIN0) as the SSIO/ “Master mode” Set P42MD1-P40MD1 bits(bit2-bit0 of P4MOD1 register) to “1” and set P42MD0-P40MD0(bit2-bit0 of P4MOD0 register) to “0”, for specifying the SSIO as the secondary function of P42, P41 and P40. Reg. name P4MOD1 register (Address: 0F225H) Bit 7 6 5 4 3 2 1 0 Bit name P47MD1 P46MD1 P45MD1 P44MD1 P43MD1 P42MD1 P41MD1 P40MD1 Data * * * * * 1 1 1 Reg. name P4MOD0 register (Address: 0F224H) Bit 7 6 5 4 3 2 1 0 Bit name P47MD0 P46MD0 P45MD0 P44MD0 P43MD0 P42MD0 P41MD0 P40MD0 Data * * * * * 0 0 0 Set P42C1-P41MC1 bits(bit2-bit1 of P4CON1 register) to “1”, set P42C0-P41C0 bits(bit2-bit1 of P4CON0 register) to “1”, and set P42DIR-P41DIR bits(bit2-bit1 of P4DIR register) to “0”, for specifying the P42-P41 as CMOS output. Set P40DIR bit(bit0 of P4DIR register) to “1” for specifying the P40 as an input pin. Data setting to P40C1 bit and P40C0 bit depend on the application circuit connected to P40. Reg. name P4CON1 register (Address: 0F223H) Bit 7 6 5 4 3 2 1 0 Bit name P47C1 P46C1 P45C1 P44C1 P43C1 P42C1 P41C1 P40C1 Data * * * * * 1 1 $ Reg. name P4CON0 register (Address: 0F222H) Bit 7 6 5 4 3 2 1 0 Bit name P47C0 P46C0 P45C0 P44C0 P43C0 P42C0 P41C0 P40C0 Data * * * * * 1 1 $ Reg. name P4DIR register (Address: 0F221H) Bit 7 6 5 4 3 2 1 0 Bit name P47DIR P46DIR P45DIR P44DIR P43DIR P42DIR P41DIR P40DIR Data * * * * * 0 0 1 Data of P42D-P40D bits (bit2-0 of P4D register) do not affect to the SSIO function, so don’t care the data for the function. Reg. name P4D register (Address: 0F220H) Bit 7 6 5 4 3 2 1 0 Bit name P47D P46D P45D P44D P43D P42D P41D P40D Data * * * * * ** ** ** * : Bit not related to the SSIO function ** : Don’t care the data $ : Arbitrarily FEUL610Q438 13-11 ML610Q438/ML610Q439 User’s Manual Chapter 13 Synchronous Serial Port 13.4.2 Functioning P42 (SOUT0), P41 (SCK0) and P40 (SIN0) as the SSIO/ ”Slave mode” Set P42MD1-P40MD1 bits(bit2-bit0 of P4MOD1 register) to “1” and set P42MD0-P40MD0(bit2-bit0 of P4MOD0 register) to “0”, for specifying the SSIO as the secondary function of P42, P41 and P40. They are the same setting as those in the case of master mode. Reg. name P4MOD1 register (Address: 0F225H) Bit 7 6 5 4 3 2 1 0 Bit name P47MD1 P46MD1 P45MD1 P44MD1 P43MD1 P42MD1 P41MD1 P40MD1 Data * * * * * 1 1 1 Reg. name P4MOD0 register (Address: 0F224H) Bit 7 6 5 4 3 2 1 0 Bit name P47MD0 P46MD0 P45MD0 P44MD0 P43MD0 P42MD0 P41MD0 P40MD0 Data * * * * * 0 0 0 Set P42C1 bit(bit2 of P4CON1 register) to “1”, set P42C0 bit(bit2 of P4CON0 register) to “1”, and set P42DIR bit(bit2 of P4DIR register) to “0”, for specifying the P42 as CMOS output. Set P41DIR-P40DIR bits(bit1-0 of P4DIR register) to “1” for specifying the P41 and P40 as input pins. Data setting to P41C1 bit, P40C1 bit, P41C0 bit and P40C0 bit, depend on the application circuit connected to P41 and P40. Reg. name P4CON1 register (Address: 0F223H) Bit 7 6 5 4 3 2 1 0 Bit name P47C1 P46C1 P45C1 P44C1 P43C1 P42C1 P41C1 P40C1 Data * * * * * 1 $ $ Reg. name P4CON0 register (Address: 0F222H) Bit 7 6 5 4 3 2 1 0 Bit name P47C0 P46C0 P45C0 P44C0 P43C0 P42C0 P41C0 P40C0 Data * * * * * 1 $ $ Bit 7 6 5 4 3 2 1 0 Bit name P47DIR P46DIR P45DIR P44DIR P43DIR P42DIR P41DIR P40DIR Data * * * * * 0 1 1 Reg. name P4DIR register (Address: 0F221H) Data of P42D-P40D bits (bit2-0 of P4D register) do not affect to the SSIO function, so don’t care the data for the function. Reg. name P4D register (Address: 0F220H) Bit 7 6 5 4 3 2 1 0 Bit name P47D P46D P45D P44D P43D P42D P41D P40D Data * * * * * ** ** ** * : Bit not related to the SSIO(using P42, P41, and P40) function ** : Don’t care the data $ : Arbitrarily FEUL610Q438 13-12 ML610Q438/ML610Q439 User’s Manual Chapter 13 Synchronous Serial Port 13.4.3 Functioning P46 (SOUT0), P45 (SCK0) and P44 (SIN0) as the SSIO/ ”Master mode” Set P46MD1-P44MD1 bits(bit6-bit4 of P4MOD1 register) to “1” and set P46MD0-P44MD0(bit6-bit4 of P4MOD0 register) to “0”, for specifying the SSIO as the secondary function of P46, P45 and P44. Reg. name P4MOD1 register (Address: 0F225H) Bit 7 6 5 4 3 2 1 0 Bit name P47MD1 P46MD1 P45MD1 P44MD1 P43MD1 P42MD1 P41MD1 P40MD1 Data * 1 1 1 * * * : Bit 7 6 5 4 3 2 1 0 Bit name P47MD0 P46MD0 P45MD0 P44MD0 P43MD0 P42MD0 P41MD0 P40MD0 Data * 0 0 0 * * * * Reg. name P4MOD0 register (Address: 0F224H) Set P46C1-P45MC1 bits(bit6-bit5 of P4CON1 register) to “1”, set P46C0-P45C0 bits(bit6-bit5 of P4CON0 register) to “1”, and set P46DIR-P45DIR bits(bit6-bit5 of P4DIR register) to “0”, for specifying the P46-P45 as CMOS output. Set P44DIR bit(bit4 of P4DIR register) to “1” for specifying the P44 as an input pin. Data setting to P44C1 bit and P44C0 bit depend on the application circuit connected to P44. Reg. name P4CON1 register (Address: 0F223H) Bit 7 6 5 4 3 2 1 0 Bit name P47C1 P46C1 P45C1 P44C1 P43C1 P42C1 P41C1 P40C1 Data * 1 1 $ * * * * Reg. name P4CON0 register (Address: 0F222H) Bit 7 6 5 4 3 2 1 0 Bit name P47C0 P46C0 P45C0 P44C0 P43C0 P42C0 P41C0 P40C0 Data * 1 1 $ * * * * Reg. name P4DIR register (Address: 0F221H) Bit 7 6 5 4 3 2 1 0 Bit name P47DIR P46DIR P45DIR P44DIR P43DIR P42DIR P41DIR P40DIR Data * 0 0 1 * * * * Data of P46D-P44D bits (bit6-4 of P4D register) do not affect to the SSIO function, so don’t care the data for the function. Reg. name P4D register (Address: 0F220H) Bit 7 6 5 4 3 2 1 0 Bit name P47D P46D P45D P44D P43D P42D P41D P40D Data * ** ** ** * * * * - : Bit not related to the SSIO(using P46, P45, and P44) function ** : Don’t care the data $ : Arbitrarily FEUL610Q438 13-13 ML610Q438/ML610Q439 User’s Manual Chapter 13 Synchronous Serial Port 13.4.4 Functioning P46 (SOUT0), P45 (SCK0) and P44 (SIN0) as the SSIO/ ”Slave mode” Set P46MD1-P44MD1 bits(bit6-bit4 of P4MOD1 register) to “1” and set P46MD0-P44MD0(bit6-bit4 of P4MOD0 register) to “0”, for specifying the SSIO as the secondary function of P46, P45 and P44. They are the same setting as those in the case of master mode. Reg. name P4MOD1 register (Address: 0F225H) Bit 7 6 5 4 3 2 1 0 Bit name P47MD1 P46MD1 P45MD1 P44MD1 P43MD1 P42MD1 P41MD1 P40MD1 Data * 1 1 1 * * * : Reg. name P4MOD0 register (Address: 0F224H) Bit 7 6 5 4 3 2 1 0 Bit name P47MD0 P46MD0 P45MD0 P44MD0 P43MD0 P42MD0 P41MD0 P40MD0 Data * 0 0 0 * * * * Set P46C1 bit(bit6 of P4CON1 register) to “1”, set P46C0 bit(bit6 of P4CON0 register) to “1”, and set P46DIR bit(bit6 of P4DIR register) to “0”, for specifying the P46 as CMOS output. Set P45DIR-P44DIR bits(bit5-4 of P4DIR register) to “1” for specifying the P45 and P44 as input pins. Data setting to P45C1 bit, P44C1 bit, P45C0 bit and P44C0 bit, depend on the application circuit connected to P45 and P44. Reg. name P4CON1 register (Address: 0F223H) Bit 7 6 5 4 3 2 1 0 Bit name P47C1 P46C1 P45C1 P44C1 P43C1 P42C1 P41C1 P40C1 Data * 1 $ $ * * * * Reg. name P4CON0 register (Address: 0F222H) Bit 7 6 5 4 3 2 1 0 Bit name P47C0 P46C0 P45C0 P44C0 P43C0 P42C0 P41C0 P40C0 Data * 1 $ $ * * * * Reg. name P4DIR register (Address: 0F221H) Bit 7 6 5 4 3 2 1 0 Bit name P47DIR P46DIR P45DIR P44DIR P43DIR P42DIR P41DIR P40DIR Data * 0 1 1 * * * * Data of P46D-P44D bits (bit6-4 of P4D register) do not affect to the SSIO function, so don’t care the data for the function. Reg. name P4D register (Address: 0F220H) Bit 7 6 5 4 3 2 1 0 Bit name P47D P46D P45D P44D P43D P42D P41D P40D Data * ** ** ** * * * * - : Bit not related to the SSIO(using P46, P45, and P44) function ** : Don’t care the data $ : Arbitrarily FEUL610Q438 13-14 ML610Q438/ML610Q439 User’s Manual Chapter 13 Synchronous Serial Port 13.5 About timer0/1 int clock for the transfer clock of the synchronous serial port Fig. 12-7 shows waves of timer0/1 int clock which can be selected as a transfer clock of a synchronous system serial port. Timer0 int clock (1/2) is divided clock of timer0 int clock (1/1). Timer1 int clock (1/2) is divided clock of timer1 int clock (1/1). timer0 int clock (1/1) or timer1 int clock (1/1) timer0 int clock (1/2) or timer1 int clock (1/2) Figure 13-7 FEUL610Q438 Waves of timer0 int clock (1/1), timer1 int clock (1/1), timer0 int clock (1/2) and timer1 int clock (1/2). 13-15 Chapter 14 UART ML610Q438/ML610Q439 User’s Manual Chapter 14 UART 14. UART 14.1 Overview This LSI includes 1 channel of UART (Universal Asynchronous Receiver Transmitter) which is an asynchrnous serial interface. For the input clock, see Chapter 6, “Clock Generation Circuit”. The use of UART requires setting of the secondary functions of Port 4. For setting of the secondary functions of Port 4, see Chapter 21, “Port 4”. 14.1.1 Features • • • • • • • • 5-bit/6-bit/7-bit/8-bit data length selectable Odd parity, even parity, or no parity selectable 1 stop bit or 2 stop bits selectable Provided with parity error flag, overrun error flag, framing error flag, and transmit buffer status flag. Positive logic or negative logic selectable as communication logic LSB first or MSB first slectable as a communication direction Communication speed: Settable within the range of 200bps to 115200bps Built-in baud rate generator 14.1.2 Configuration Figure 14-1 shows the configuration of the UART. P02/RXD0 P42/RXD0 LSCLK LSCLK×2 HSCLK P43/TXD0 Shift Register Band Rate Generator UA0BRTH, L UA0INT UART Controller UA0CON UA0MOD0, 1 UA0BUF UA0STAT Data bus UA0BUF: UA0BRTH, L: UA0CON: UA0MOD0, 1: UA0STAT: UART0 transmit/receive buffer UART0 baud rate registers H, L UART0 control register UART0 mode registers 0, 1 UART0 status register Figure 14-1 Configuration of UART 14.1.3 List of Pins Pin name I/O P02/RXD0 I P42/RXD0 I P43/TXD0 O FEUL610Q438 Description UART0 data input pin Used for the secondary function of the P02 pin. UART0 data input pin Used for the secondary function of the P42 pin. UART0 data output pin Used for the secondary function of the P43 pin. 14-1 ML610Q438/ML610Q439 User’s Manual Chapter 14 UART 14.2 Description of Registers 14.2.1 List of Registers Address 0F290H 0F291H 0F292H 0F293H 0F294H 0F295H 0F296H Name UART0 transmit/receive buffer UART0 control register UART0 mode register 0 UART0 mode register 1 UART0 baud rate register L UART0 baud rate register H UART0 status register FEUL610Q438 Symbol (Byte) Symbol (Word) UA0BUF UA0CON UA0MOD0 UA0MOD1 UA0BRTL UA0BRTH UA0STAT   UA0MOD UA0BRT  R/W Size Initial value R/W R/W R/W R/W R/W R/W R/W 8 8 8/16 8 8/16 8 8 00H 00H 00H 00H 00H 00H 00H 14-2 ML610Q438/ML610Q439 User’s Manual Chapter 14 UART 14.2.2 UART0 Transmit/Receive Buffer (UA0BUF) Address: 0F290H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 UA0BUF U0B7 U0B6 U0B5 U0B4 U0B3 U0B2 U0B1 U0B0 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 UA0BUF is a special function register (SFR) to store the transmit/receive data of the UART. In transmit mode, write transmission data to UA0BUF. To tranmit data continuously, write the next data to UA0BUF after making sure that the U0FUL flag of the UART0 status register (UA0STAT) is “0”. Any value written to UA0BUF can be read. In receive mode, since data received at termination of reception is stored in UA0BUF, read the contents of UABUF using the UART0 interrupt at termination of reception. At continuous reception, BA0BUF is updated whenever reception terminates. Any write to BA0BUF is disabled in receive mode. The bits not required when 5-bit, 6-bit, 7-bit, or 8-bit data length is slected become invalid in transmit mode and are set to “0” in receive mode. Note: For operation in transmit mode, be sure to set the transmit mode (UA0MOD0 and UA0MOD1) before setting transmit data in UAOBUF. FEUL610Q438 14-3 ML610Q438/ML610Q439 User’s Manual Chapter 14 UART 14.2.3 UART0 Control Register (UA0CON) Address: 0F291H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 UA0CON        U0EN R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 UA0CON is a special function register (SFR) to start/stop communication of the UART. [Description of Bits] • U0EN (bit 0) The U0EN bit is used to specify the UART communication operation start. When U0EN is set to “1”, UART communication starts. In transmit mode, this bit is automatically set to “0” at termination of transmission. In receive mode, receive operation is continued. To terminate reception, set the bit to “0” by software. U0EN 0 1 FEUL610Q438 Description Stops communication. (Initial value) Starts communication. 14-4 ML610Q438/ML610Q439 User’s Manual Chapter 14 UART 14.2.4 UART0 Mode Register 0 (UA0MOD0) Address: 0F292H Access: R/W Access size: 8/16 bits Initial value: 00H 7 6 5 4 3 2 1 0 UA0MOD0 — — — U0RSEL — U0CK1 U0CK0 U0IO R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 UA0MOD0 is a special function register (SFR) to set the transfer mode of the UART. [Description of Bits] • U0IO (bit 0) The U0IO bit is used to select transmit or receive mode. U0IO 0 1 Description Transmit mode (initial value) Receive mode • U0CK1, U0CK0 (bits 2, 1) The U0CK1 and U0CK0 bits are used to select the clock to be input to the baud rate generator of the UART0. U0CK1 0 0 1 U0CK0 0 1 * Description LSCLK (initial value) LSCLK×2 HSCLK • U0RSEL (bit 4) The U0RSEL bit is used to select the receive data input pin for the UART0. U0RSEL 0 1 Description Selects the P02 pin. (Initial value) Selects the P42 pin. Notes: - Always set the UA0MOD0 register while communication is stopped, and do not rewrite it during communication. - When specifying LSCLK×2 for the clock, enable the operation of the 2×low-speed clock by setting bit 2 (ENMLT) of the frequency control register 1 (FCON1) to “1”. - When selecting the P42 pin as the receive data input pin, it is necessary to configure settings for the Port 4 secondary functions. For the details of the Port 4 secondary function settings, see Chapter 21, “Port 4”. FEUL610Q438 14-5 ML610Q438/ML610Q439 User’s Manual Chapter 14 UART 14.2.5 UART0 Mode Register 1 (UA0MOD1) Address: 0F293H Access: R/W Access size: 8/16 bits Initial value: 00H 7 6 5 4 3 2 1 0 UA0MOD1 — U0DIR U0NEG U0STP U0PT1 U0PT0 U0LG1 U0LG0 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 UA0MOD1 is a special function register (SFR) to set the transfer mode of the UART. [Description of Bits] • U0LG1, U0LG0 (bits 1, 0) The U0LG1 and U0LG0 bits are used to specify the data length in the communication of the UART. U0LG1 0 0 1 1 U0LG0 0 1 0 1 Description 8-bit length (initial value) 7-bit length 6-bit length 5-bit length • U0PT1, U0PT0 (bits 3, 2) The U0PT1 and U0PT0 bits are used to select “even parity”, odd parith”, or “no parity” in the communication of the UART. U0PT1 0 0 1 U0PT0 0 1 * Description Even parity (initial value) Odd parity No parity bit • U0STP (bit 4) The U0STP bit is used to select the stop bit length in the communication of the UART. U0STP 0 1 Description 1 stop bit (initial value) 2 stop bits • U0NEG (bit 5) The U0NEG bit is used to select positive logic or negative logic in the communication of the UART. U0NEG 0 1 FEUL610Q438 Description Positive logic (initial value) Negative logic 14-6 ML610Q438/ML610Q439 User’s Manual Chapter 14 UART • U0DIR (bit 6) The U0DIR bit is used to select LSB first or MSB first in the communication of the UART. U0DIR 0 1 Description LSB first (initial value) MSB first Note: Always set the UA0MOD1 register while communication is stopped, and do not rewrite it during communication. FEUL610Q438 14-7 ML610Q438/ML610Q439 User’s Manual Chapter 14 UART 14.2.6 UART0 Baud Rate Registers L, H (UA0BRTL, UA0BRTH) Address: 0F294H Access: R/W Access size: 8/16 bits Initial value: 0FFH 7 6 5 4 3 2 1 0 UA0BRTL U0BR7 U0BR6 U0BR5 U0BR4 U0BR3 U0BR2 U0BR1 U0BR0 R/W Initial value R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Address: 0F295H Access: R/W Access size: 8 bits Initial value: 0FH 7 6 5 4 3 2 1 0 UA0BRTH — — — — U0BR11 U0BR10 U0BR9 U0BR8 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 1 R/W 1 R/W 1 R/W 1 UA0BRTL and UA0BRTH are special function registers (SFRs) to set the count value of the baud rate generator which generates baud rate clocks. For the relationship between the count value of the baud rate generator and baud rate, see Section 15.3.2, “Baud Rate”. Note: Always set the UA0BRTL and UA0BRTH registers while communication is stopped, and do not rewrite them during communication. FEUL610Q438 14-8 ML610Q438/ML610Q439 User’s Manual Chapter 14 UART 14.2.7 UART0 Status Register (UA0STAT) Address: 0F296H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 UA0STAT — — — — U0FUL U0PER U0OER U0FER R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 UA0STAT is a special function register (SFR) to indicate the state of transmit or receive operation of the UART. When any data is written to UA0STAT, all the flags are initialized to “0”. [Description of Bits] • U0FER (bit 0) The U0FER bit is used to indicate occurrence of a framing error of the UART. When an error occurs in the start or stop bit, the U0FER bit is set to “1”. This bit is updated each time reception is completed. The U0FER bit is fixed to “0” in transmit mode. U0FER 0 1 Description No framing error (initial value) Framing error • U0OER (bit 1) The U0OER bit is used to indicate occurrence of an overrun error of the UART. If the received data in the transmit/receive buffer (UA0BUF) is received again before it is read, this bit is set to “1”. Even if reception is stopped by the U0EN bit and then reception is restarted, this bit is set to “1” unless the previous receive data is not read. Therefore, make sure that data is always read from the transmit/receive buffer even if the data is not required. The U0OER bit is fixed to “0” in transmit mode. U0OER 0 1 Description No overrun error (initial value) Overrun error • U0PER (bit 2) The U0PER bit is used to indicate occurrence of a parity error of the UART. When the parity of the received data and the parity bit attached to the data do not coincide, this bit is set to “1”. U0PER is updated whenever data is received. The U0PER bit is fixed to “0” in transmit mode. U0PER 0 1 FEUL610Q438 Description No parity error (initial value) Parity error 14-9 ML610Q438/ML610Q439 User’s Manual Chapter 14 UART • U0FUL (bit 3) The U0FUL bit is used to indicate the state of the transmit/receive buffer of the UART. When transmit data is written in UA0BUF in transmit mode, this bit is set to “1” and when transmit data is transferred to the shift register, this bit is set to “0”. To transmit data consecutively, write the next transmit data to UA0BUF after checking that the U0FUL flag has been set to “0”. The U0FUL bit is fixed to “0” in receive mode. U0FUL 0 1 FEUL610Q438 Description There is no data in the transmit/receive buffer. (Initial value) There is data in the transmit/receive buffer. 14-10 ML610Q438/ML610Q439 User’s Manual Chapter 14 UART 14.3 Description of Operation 14.3.1 Transfer Data Format In the transfer data format, one frame contains a start bit, a data bit, a parity bit, and a stop bit. In this format, 5 to 8 bits can be selected as data bit. For the parity bit, “with parity bit”, “without parity bit”, “even parity”, or “odd parity” can be selected. For the stop bit, “1 stop bit” or “2 stop bits” are available and for the transfer direction, “LSB first” or “MSB first” are available for selection. For serial input/output logic, positive logic or negative logic can be selected. All these options are set with the UART0 mode register (UA0MOD1). Figure 14-2 and Figure 14-3 show the positive logicc input/output format and negative logic input/output format, respectively. 1 frame Start bit 1 2 3 4 6 5 7 8 Parity Stop bit bit Stop bit Data bit • 1 frame Max. ……… . 12 bits Min. ……… .. 7 bits Figure 14-2 • Data bit length……… . 8 to 5 bits variable • Parity bit……… .......... With or without parity bit selectable Odd or even parity selectable • Stop bit……… ............ 1 or 2 stop bits selectable Positive Logic Input/Output Format 1 frame Start bit 1 2 3 4 5 6 7 8 Parity Stop Stop bit bit bit Data bit • 1 frame Max. ……… 12 bits Min. ……… 7 bits Figure 14-3 FEUL610Q438 • Data bit length………..8 to 5 bits variable • Parity bit……… ...........With or without parity bit selectable Odd or even parity selectable • Stop bit……….............1 or 2 stop bits selectable Negative Logic Input/Output Format 14-11 ML610Q438/ML610Q439 User’s Manual Chapter 14 UART 14.3.2 Baud Rate Baud rates are generated by the baud generator. The baud rate generator generates a baud rate by counting the clock selected by the baud rate clock selection bits (U0CK1, U0CK0) of the UART0 mode register 0 (UA0MOD0). The count value of the baud rate generator can be set by writing it in the UART0 baud rate register H or L (UA0BRTH, UA0BRTL). The maximum count is 4096. The setting values of UA0BRTH and UA0BRTL are expressed by the following equation. UA0BRTH, L = Clock frequency (Hz) Baud rate (bps) –1 Table 14-2 lists the count values for typical baud rates. Table 14-2 Baud rate Count Values for Typical Baud Rates Baud rate generator clock selection Count value of the baud rate generator Baud rate clock U0CK1 U0CK0 Count value Period of 1 bit UA0BRTH UA0BRTL 1200 bps 32.768 kHz 0 0 27 Approx. 824 µs 00H 1AH 2400 bps 65.536 kHz 0 1 27 Approx. 412 µs 00H 1AH 4800 bps 4.096 MHz 1 * 853 Approx. 208 µs 03H 054H 9600 bps 4.096 MHz 1 * 427 Approx. 104 µs 01H 0AAH 19200 bps 4.096 MHz 1 * 213 Approx. 52 µs 00H 0D4H 38400 bps 4.096 MHz 1 * 107 Approx. 26 µs 00H 06AH 57600 bps 4.096 MHz 1 * 71 Approx. 17.3 µs 00H 046H 115200 bps 4.096 MHz 1 * 36 Approx. 8.8 µs 00H 023H Note: When UA0BRTH or UA0BRTL is set to a value equal to less than “0007H”, the value set is read from UA0BRTH or UA0BRTL but the value of the baud rate clock counter is the same as the value when UA0BRTH or UA0BRTL is set to “0008H”. When specifying 65.536 kHz (LSCLK×2) for the clock, enable the operation of the 2×low-speed clock by setting bit 2 (ENMLT) of the frequency control register 1 (FCON1) to “1”. FEUL610Q438 14-12 ML610Q438/ML610Q439 User’s Manual Chapter 14 UART 14.3.3 Transmit Data Direction Figure 14-4 shows the relationship between the transmit/receive buffer and the transmit/receive data. • Data length: 8 bits LSB reception MSB reception U0B7 U0B6 U0B5 U0B4 U0B3 U0B2 U0B1 U0B0 LSB reception MSB reception U0B6 U0B5 U0B4 U0B3 U0B2 U0B1 U0B0 LSB reception MSB reception U0B1 U0B0 LSB reception MSB reception • Data length: 7 bits LSB reception MSB reception U0B7 is “0” at completion of reception. • Data length: 6 bits LSB reception MSB reception U0B5 U0B4 U0B3 U0B2 U0B7 and U0B6 are “0” at completion of reception. • Data length: 5 bits LSB reception MSB reception U0B4 U0B3 U0B2 U0B1 U0B0 LSB reception MSB reception U0B7, U0B6, and U0B5 are “0” at completion of reception. Figure 14-4 Relationship between Transmit/Receive Buffer and Transmit/Receive Data Note: When the TXD0 pin is set to serve the secondary function output in receive mode, “H” level is output from the TXD0 pin. FEUL610Q438 14-13 ML610Q438/ML610Q439 User’s Manual Chapter 14 UART 14.3.4 Transmit Operation Transmission is started by setting the U0IO bit of the UART0 mode register 0 (UA0MOD0) to “0” to select transmit mode and setting the U0EN bit of the UART0 control register (UA0CON) to “1”. Figure 14-5 shows the operation timing for transmission. When the U0EN bit is set to “1” (), the baud rate generator generates an internal transfer clock of the baud rate set and starts transmission. The start bit is output to the TXD0 pin by the falling edge of the internal transfer clock (). Subsequently, transmit data, a parity bit, and a stop bit are output. When the start bit is output (), a UART0 interrupt is requested. In the UART0 interrupt routine, the next data to be transmitted is written to the transmit/receive buffer (UA0BUF). When the next data to be transmitted is written to the transmit/receive buffer (UA0OBUF), the transmit buffer status flag (U0FUL) is set to “1” () and a UART0 interrupt is requested on the falling edge of the internal transfer clock () after transmission of the stop bit. If the UART0 interrupt routine is terminated without writing the next data to the transmit/receive buffer, the U0FUL bit is not set to “1” () and transmission continues up to the transmission of the stop bit, then the U0EN bit is reset to “0” and a UART0 interrupt is requested. The valid period for the next transmit data to be written to the transmit/receive buffer is from the generation of an interrupt to the termination of stop bit transmission. () FEUL610Q438 14-14 FEUL610Q438 Figure 14-5 U0FUL UA0INT TXD0 output Internal transfer clock U0EN U0EN set signal UA0BUF System clock SYSCLK ↑ ↑  Start BRT U0EN set instruction 1st data UA0BUF write instruction ↑  0 BRT 2 7 Parity  Transmit/receive buffer write enable period 1 2nd data Stop ↑  Start 0 2 7 Parity  Transmit/receive buffer write enable period 1 Stop ↑  ML610Q438/ML610Q439 User’s Manual Chapter 14 UART Operation Timing in Transmission 14-15 ML610Q438/ML610Q439 User’s Manual Chapter 14 UART 14.3.5 Receive Operation Reception is started by selecting a receive data input pin using the U0RSEL bit of the UART0 mode register 0 (UA0MOD0), then setting the U0IO bit of UA0MOD0 to “0” to select receive mode, and then setting the U0EN bit of the UART0 control register (UA0CON) to “1”. Figure 14-6 shows the operation timing for reception. When receive operation starts, the LSI checks the data sent to the input pin RXD0 and waits for the arrival of a start bit. When detecting a start bit (), the LSI generates the internal transfer clock of the baud rate set with the start bit detect point as a reference and performs receive operation. The shift register shifts in the data input to RXD on the rising edge of the internal transfer clock. The data and parity bit are shifted into the shift register and 5- to 8- bit receive data is transferred to the transmit/receive buffer (UA0BUF) concurrently with the fall of the internal transfer clock of . The LSI requests a UART0 interrupt on the rising edge of the internal transfer clock subsequent to the internal transfer clock by which the receive data was fetched () and checks for a stop bit error and a parity bit error. When an error is detected, the LSI sets the corresponding bit of the UART0 status register (UA0STAT) to “1”. Parity error Overrun error Framing error : S0PER = “1” : S0OER = “1” : S0FER = “1” As shown in Figure 14-6, the rise of the internal transfer clock is set so that it may fall into the middle of the bit interval of the receive data. Reception continues until the U0EN bit is reset to “0” by the program. When the U0EN bit is reset to “0” during reception, the data received may be destroyed. When the U0EN bit is reset to “0” during the “U0EN reset enable period” in Figure 14.6, the data received is protected. FEUL610Q438 14-16 FEUL610Q438 Figure 14-6 U0OER U0PER Transmit/receive buffer UA0INT Shift register (input stage) Internal transfer clock RXD U0EN ↑  Start 0 BRT 0 1 ↑  Detection of start bit BRT Start 1 2 2 7 7 ↑  Stop Start 0 1st data Start ↑  0 1 1 6 6 7 7 Detection of Parity error, overrun error, and framing error Request for UART0 interrupt ↓ : Overrun error ↓ : Parity error Stop Parity Parity ↑  2nd data Stop Reception is stopped since the start bit is not fetched Parity Parity Stop U0EN reset enable period ML610Q438/ML610Q439 User’s Manual Chapter 14 UART Operation Timing in Reception 14-17 ML610Q438/ML610Q439 User’s Manual Chapter 14 UART 14.4 Specifying port registers When you want to make sure the UART function is working, please check related port registers are specified. See Chapter 21, “Port 4” and Chapter 17, “Port 0” for detail about the port registers. 14.4.1 Functioning P43(TXD0) and P42(RXD0) as the UART. Set P43MD1-P42MD1 bits(bit3-bit2 of P4MOD1 register) to “0” and set P43MD0-P42MD0(bit3-bit2 of P4MOD0 register) to “1”, for specifying the UART as the secondary function of P43 and P42. Reg. name P4MOD1 register (Address: 0F225H) Bit 7 6 5 4 3 2 1 0 Bit name P47MD1 P46MD1 P45MD1 P44MD1 P43MD1 P42MD1 P41MD1 P40MD1 Data * * * * 0 0 * * Reg. name P4MOD0 register (Address: 0F224H) Bit 7 6 5 4 3 2 1 0 Bit name P47MD0 P46MD0 P45MD0 P44MD0 P43MD0 P42MD0 P41MD0 P40MD0 Data * * * * 1 1 * * Set P43C1 bit(bit3 of P4CON1 register) to “1”, set P43C0 bit(bit3 of P4CON0 register) to “1”, and set P43DIR bit(bit3 of P4DIR register) to “0”, for specifying the P43 as CMOS output. Set P42DIR bit(bit2 of P4DIR register) to “1” for specifying the P42 as an input pin. Data setting to P42C1 bit and P42C0 bit, depend on the application circuit connected to P42. Reg. name P4CON1 register (Address: 0F223H) Bit 7 6 5 4 3 2 1 0 Bit name P47C1 P46C1 P45C1 P44C1 P43C1 P42C1 P41C1 P40C1 Data * * * * 1 $ * * Reg. name P4CON0 register (Address: 0F222H) Bit 7 6 5 4 3 2 1 0 Bit name P47C0 P46C0 P45C0 P44C0 P43C0 P42C0 P41C0 P40C0 Data * * * * 1 $ * * Bit 7 6 5 4 3 2 1 0 Bit name P47DIR P46DIR P45DIR P44DIR P43DIR P42DIR P41DIR P40DIR Data * * * * 0 1 * * Reg. name P4DIR register (Address: 0F221H) Data of P43D-P42D bits (bit3-2 of P4D register) do not affect to the UART function, so don’t care the data for the function. Reg. name P4D register (Address: 0F220H) Bit 7 6 5 4 3 2 1 0 Bit name P47D P46D P45D P44D P43D P42D P41D P40D Data * * * * ** ** * * * : Bit not related to the UART(using P43 and P42) function ** : Don’t care the data $ : Arbitrarily FEUL610Q438 14-18 ML610Q438/ML610Q439 User’s Manual Chapter 14 UART Note: The receive pin (RXD) is selected by U0RSEL bit(bit4 of UA0MOD0 register). Reseting the bit to “0” (initial value) selects P02 pin and setting the bit to “1” selects P43 pin. 14.4.2 Functioning P43(TXD0) and P02(RXD0) as the UART. Set P43MD1 bit(bit3 of P4MOD1 register) to “0” and set P43MD0(bit3 of P4MOD0 register) to “1”, for specifying the UART as the secondary function of P43. Reg. name P4MOD1 register (Address: 0F225H) Bit 7 6 5 4 3 2 1 0 Bit name P47MD1 P46MD1 P45MD1 P44MD1 P43MD1 P42MD1 P41MD1 P40MD1 Data * * * * 0 $ * * Bit 7 6 5 4 3 2 1 0 Bit name P47MD0 P46MD0 P45MD0 P44MD0 P43MD0 P42MD0 P41MD0 P40MD0 Data * * * * 1 $ * * Reg. name P4MOD0 register (Address: 0F224H) Set P43C1 bit(bit3 of P4CON1 register) to “1”, set P43C0 bit(bit3 of P4CON0 register) to “1”, and set P43DIR bit(bit3 of P4DIR register) to “0”, for specifying the P43 as CMOS output. Reg. name P4CON1 register (Address: 0F223H) Bit 7 6 5 4 3 2 1 0 Bit name P47C1 P46C1 P45C1 P44C1 P43C1 P42C1 P41C1 P40C1 Data * * * * 1 * * * Reg. name P4CON0 register (Address: 0F222H) Bit 7 6 5 4 3 2 1 0 Bit name P47C0 P46C0 P45C0 P44C0 P43C0 P42C0 P41C0 P40C0 Data * * * * 1 * * * Reg. name P4DIR register (Address: 0F221H) Bit 7 6 5 4 3 2 1 0 Bit name P47DIR P46DIR P45DIR P44DIR P43DIR P42DIR P41DIR P40DIR Data * * * * 0 * * * Data of P43D bit (bit3 of P4D register) do not affect to the UART function, so don’t care the data for the function. Reg. name P4D register (Address: 0F220H) Bit 7 6 5 4 3 2 1 0 Bit name P47D P46D P45D P44D P43D P42D P41D P40D Data * * * * ** * * * FEUL610Q438 14-19 ML610Q438/ML610Q439 User’s Manual Chapter 14 UART P02 is an input-only port, so there is no need to specify data direction (i.e. input or output). Data setting to P02C1 bit and P02C0 bit, depend on the application circuit connected to P02. Reg. name P0CON1 register (Address: 0F207H) Bit 7 6 5 4 3 2 1 0 Bit name - - - - P03C1 P02C1 P01C1 P00C1 Data - - - - * $ * * Reg. name P0CON0 register (Address: 0F206H) Bit 7 6 5 4 3 2 1 0 Bit name - - - - P03C0 P02C0 P01C0 P00C0 Data - - - - * $ * * Data of P02D bit (bit2 of P0D register) do not affect to the UART function, so don’t care the data for the function. Reg. name P0D register (Address: 0F204H) Bit 7 6 5 4 3 2 1 0 Bit name - - - - P03D P02D P01D P00D Data - - - - * ** * * * : Bit not related to the UART(using P43 and P02) function ** : Don’t care the data $ : Arbitrarily Note: The receive pin (RXD0) is selected by U0RSEL bit(bit4 of UA0MOD0 register). Setting the bit to “0” (initial value) selects P02 pin and setting the bit to “1” selects P43 pin. Even if P42 is specified as RXD0 by P42MD1 bit, P42MD0 bit, P42C1 bit, P42C0 bit and P42IDR bit, setting “0” to U0RSEL bit has priority to select P02 pin as the RXD0. P02(Port 0) is an input-only port, does not have registers that can select data direction(input or output) or mode(primary or secondary function). FEUL610Q438 14-20 Chapter 15 I2C Bus Interface ML610Q438/ML610Q439 User’s Manual Chapter 15 I2C Bus Interface 15. I2C Bus Interface 15.1 Overview This LSI includes 1 channel of I2C bus interface (master). The secondary functions of Port 4 are assigned to the I2C bus interface data input/output pin and the I2C bus interface clock input/output pin. For Port4, see Chapter 21, “Port 4”. 15.1.1 Features • Master function • Communication speeds supported include standard mode (100 kbps@4MHz HSCLK, 50kbps@500kHz HSCLK) and fast mode (400kbps@4MHｚ HSCLK). • 7-bit address format (10-bit address can be supported) 15.1.2 Configuration Figure 15-1 shows the configuration of the I2C bus interface. I2C0RD, I2C0STAT Shift Register Clock Generator HSCLK SCL SDA Controller I2C Controller I2C0SA I2C0MOD I2C0TD P41/SCL P40/SDA I2C0INT I2C0CON Data bus I2C0RD I2C0SA I2C0TD I2C0CON I2C0MOD I2C0STAT 2 : I C bus 0 receive register 2 : I C bus 0 slave address register 2 : I C bus 0 transmit data register 2 : I C bus 0 control register 2 : I C bus 0 mode register 2 : I C bus 0 status register Figure 15-1 2 Configuration of I C Bus Interface 15.1.3 List of Pins Pin name I/O Description 2 P40/SDA I/O P41/SCL I/O FEUL610Q438 I C bus interface data input/output pin. Used for the secondary function of the P40 pin. 2 I C bus interface clock input/output pin. Used for the secondary function of the P41 pin. 15-1 ML610Q438/ML610Q439 User’s Manual Chapter 15 I2C Bus Interface 15.2 Description of Registers 15.2.1 List of Registers Address 0F2A0H 0F2A1H 0F2A2H 0F2A3H 0F2A4H 0F2A5H Name 2 I C bus 0 receive register 2 I C bus 0 slave address register 2 I C bus 0 transmit data register 2 I C bus 0 control register 2 I C bus 0 mode register 2 I C bus 0 status register FEUL610Q438 Symbol (Byte) Symbol (Word) I2C0RD I2C0SA I2C0TD I2C0CON I2C0MOD I2C0STAT — — — — — — R/W Size Initial value R R/W R/W R/W R/W R 8 8 8 8 8 8 00H 00H 00H 00H 00H 00H 15-2 ML610Q438/ML610Q439 User’s Manual Chapter 15 I2C Bus Interface 2 15.2.2 I C Bus 0 Receive Register (I2C0RD) Address: 0F2A0H Access: R Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 I2C0RD I20R7 I20R6 I20R5 I20R4 I20R3 I20R2 I20R1 I20R0 R Initial value R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 I2C0RD is a read-only special function register (SFR) to store receive data. I2C0RD is updataed after completion of each reception. [Description of Bits] • I20R7-I20R0 (bits 7-0) The I20R7 to I20R0 bits are used to store receive data. The signal input to the SDA pin is received at transmission of a slave address and at data transmission/reception in sync with the rising edge of the signal on the SCL pin. Since data that has been output to the SDA and SCL pins is received not only at data reception but also at slave address data transmission and data transmission, it is possible to check whether transmit data has certainly been transmitted. FEUL610Q438 15-3 ML610Q438/ML610Q439 User’s Manual Chapter 15 I2C Bus Interface 15.2.3 I2C Bus 0 Slave Address Register (I2C0SA) Address: 0F2A1H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 I2C0SA I20A6 I20A5 I20A4 I20A3 I20A2 I20A1 I20A0 I20RW R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 I2C0SA is a special function register (SFR) to set the address and the transmit/receive mode of the slave device. [Description of Bits] • I20RW (bit 0) The I20RW bit is used to select the data transmit mode (write) or data receive mode (read). I20RW 0 1 Description Data transmit mode (initial value) Data receive mode • I20A6-I20A0 (bits 7-1) The I20A6 to I20A0 bits are used to set the address of the communication destination. FEUL610Q438 15-4 ML610Q438/ML610Q439 User’s Manual Chapter 15 I2C Bus Interface 2 15.2.4 I C Bus 0 Transmit Data Register (I2C0TD) Address: 0F2A2H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 I2C0TD I20T7 I20T6 I20T5 I20T4 I20T3 I20T2 I20T1 I20T0 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 I2C0TD is a special function register (SFR) to set transmit data. [Description of Bits] • I20T7-0 (bits 7-0) The I20T7 to 0 bits are used to set transmit data. FEUL610Q438 15-5 ML610Q438/ML610Q439 User’s Manual Chapter 15 I2C Bus Interface 15.2.5 I2C Bus 0 Control Register (I2C0CON) Address: 0F2A3H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 I2C0CON I20ACT — — — — I20RS I20SP I20ST R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 W 0 W 0 R/W 0 I2C0CON is a special function register (SFR) to control transmit and receive operations. [Description of Bits] • I20ST (bit 0) The I20ST bit is used to control the communication operation of the I2C bus interface. When the I20ST bit is set to “1”, communication starts. When “1” is overwritten to the I20ST bit in a control register setting wait state after transmission/reception of acknowledgment, communication starts again. When the I20ST bit is set to “0”, communication is stopped forcibly. The I20ST bit can be set to “1” only when the I2C bus interface is in an operation enable state (I20EN = “1”). When the I20SP bit is set to “1”, the I20ST bit is set to “0”. I20ST 0 1 Description Stops communication (initial value) Starts communication • I20SP (bit 1) The I20SP bit is a write-only bit used to request a stop condition. When the I20SP bit is set to “1”, the I2C bus shifts to the stop condition and communication stops. When the I20SP bit is read, “0” is always read. I20SP 0 1 Description No stop condition request (initial value) Stop condition request • I20RS (bit 2) The I20RS bit is a write-only bit used to request a restart. When this bit is set to “1” during data communication, the I2C bus shifts to the restart condition and communication restarts from the slave address. I20RS can be set to “1” only while communication is active (I20ST =“1”). When the I20RS bit is read, “0” is always read. I20RS 0 1 Description No restart request (initial value) Restart request • I20ACT (bit 7) The I20ACT bit is used to set the acknowledge signal to be output at completion of reception. I20ACT 0 1 FEUL610Q438 Description Acknowledgment data “0” (initial value) Acknowledgment data “1” 15-6 ML610Q438/ML610Q439 User’s Manual Chapter 15 I2C Bus Interface 2 15.2.6 I C Bus 0 Mode Register (I2C0MOD) Address: 0F2A4H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 I2C0MOD — — — I20SYN I20DW1 I20DW0 I20MD I20EN R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 I2C0MOD is a special function register (SFR) to set operating mode. [Description of Bits] • I20EN (bit 0) The I20EN bit is used to enable the operation of the I2C bus interface. Only when the I20EN bit is set to “1”, the I20ST bit can be set and the I20BB flag starts operation. When the I20EN bit is set to “0”, all the SFRs related to the I2C bus 0 are initialized. I20EN 0 1 Description 2 Stops I C operation. (Initial value) 2 Enables I C operation. • I20MD (bit 1) The I20MD bit is used to set the communication speed of the I2C bus interface. selected. I20MD 0 1 Standard mode or fast mode can be Description Standard mode (initial value)/ 100kbps@4MHz HSCLK Fast mode / Max. 400kbps@4MHz HSCLK • I20DW1, I20DW0 (bits 3, 2) The I20DW1 and I20DW0 bits are used to set the communication speed reduction rate of the I2C bus interface. this bit so that the communication speed does not exceed 100kpbs/400kpbs. I20DW1 0 0 1 1 I20DW0 0 1 0 1 Set Description No communication speed reduction (initial value) 10% communication speed reduction 20% communication speed reduction 30% communication speed reduction • I20SYN (bit 4) Always set the I20SYN bit to 0. Note: The I2C bus is set so that the communication speed may become 100kbps/400kbps when HSCLK is 4 MHz. Therefore, when using PLL oscillation (approx. 8.192 MHz) for high-speed oscillation, select 1/2HSCLK at selection of the HSCLK frequency of FCON0 and select 10% communication speed reduction at selection of I2C0MOD communication speed reduction. When 500 kHz RC oscillation is used, communication in standard mode (50kbps) is available with the fast mode by setting I20MD bit to “1”. FEUL610Q438 15-7 ML610Q438/ML610Q439 User’s Manual Chapter 15 I2C Bus Interface 2 15.2.7 I C Bus 0 Status Register (I2C0STAT) Address: 0F2A5H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 I2C0STAT — — — — — I20ER I20ACR I20BB R Initial value: R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 I2C0STAT is a read-only special function register (SFR) to indicate the state of the I2C bus interface. [Description of Bits] • I20BB (bit 0) The I20BB bit is used to indicate the state of use of the I2C bus interface. When the start condition is generated on the I2C bus, this bit is set to “1” and when the stop condition is generated, the bit is set to “0”. The I20BB bit is set to “0” when the I20EN bit of I2C0MOD is “0”. I20BB 0 1 Description 2 I C bus-free state (Initial value) 2 I C bus-busy state • I20ACR (bit 1) The I20ACR bit is used to store the acknowledgment signal received. Acknowledgment signals are received each time the slave address is received and data transmission or reception is completed. The I20ACR bit is set to “0” when the I20EN bit of I2C0MOD is “0”. I20ACR 0 1 Description Receives acknowledgment “0”. (Initial value) Receives acknowledgment “1”. • I20ER (bit 2) The I20ER bit is a flag to indicate a transmit error. When the value of the bit transmitted and the value of the SDA pin do not coincide, this bit is set to “1”. The SDA remains the output until the subsequent byte data communication terminates even if I20ER is set to “1”. The I20ER bit is set to “0” when a write operation to I2C0CON is performed. The I20ER bit is set to “0” when the I20EN bit of I2C0MOD is set to “0”. I20ER 0 1 FEUL610Q438 Description No transmit error (initial value) Transmit error 15-8 ML610Q438/ML610Q439 User’s Manual Chapter 15 I2C Bus Interface 15.3 Description of Operation 15.3.1 Communication Operating Mode Communication is started when communication mode is selected by using the I2C bus 0 mode register (I2C0MOD), the I2C function is enabled by using the I20EN bit, a slave address and a data communication direction are set in the I2C bus 0 slave address register, and “1” is written to the I20ST bit of the I2C bus 0 control register (I2C0CON). 15.3.1.1 Start Condition When “1” is written to the I20ST bit of the I2C bus 0 control register ((I2C0CON) while communication is stopped (the I20ST bit is “0”), communication is started and the start condition waveform is output to the SDA and SCL pins. After execution of the start condition, the LSI shifts to slave address transmit mode. 15.3.1.2 Repeated Start Condition When “1” is written to the I20RS and I20ST bits of the I2C bus 0 control register ((I2C0CON) during communication (the I20ST bit is “0”), the repeated start condition waveform is output to the SDA and SCL pins. After execution of the repeated start condition, the LSI shifts to slave address transmit mode. 15.3.1.3 Slave Address Transmit Mode In slave address transmit mode, the values (slave address and data communication direction) of the I2C bus 0 slave address register (I2C0SA) are transmitted in MSB first, and finally, the acknowledgment signal is received in the I20ACR bit of the I2C bus 0 status register (I2CSTAT). At completion of acknowledgment reception, the LSI shifts to the I2C bus 0 control register (I2C0CON) setting wait state (control register setting wait state). The value of I2C0SA output from the SDA pin is stored in I2C0RD. 15.3.1.4 Data Transmit Mode In data transmit mode, the value of I2C0TD is transmitted in MSB first, and finally, the acknowledgment signal is received in the I20ACR bit of the I2C bus 0 status register (I2CSTAT). At completion of acknowledgment reception, the LSI shifts to the I2C bus 0 control register (I2C0CON) setting wait state (control register setting wait state). The value of I2C0TD output from the SDA pin is stored in I2C0RD. 15.3.1.5 Data Receive Mode In data receive mode, the value input in the SDA pin is received synchronously with the rising edge of the serial clock output to the SCL pin, and finally, the value of the I20ACT bit of the I2C bus 0 control register (I2C0CON) is output. At completion of acknowledgment transmission, the LSI shifts to the I2C bus 0 control register (I2C0CON) setting wait state (control register setting wait state). The data received is stored in I2C0RD after the acknowledgment signal is output. The acknowledgment signal output is received in the I20ACR bit of the I2C bus 0 status register (I2CSTAT). 15.3.1.6 Control Register Setting Wait State When the LSI shifts to the control register setting wait state, an I2C bus interface interrupt (I2C0INT) is generated. In the control register setting wait state, the transmit flag (I20ER) of the I2C bus 0 status register (I2C0STAT) and acknowledgment receive data (I20ACR) are confirmed and at data reception, the contents of I2C0RD are read in the CPU and the next operation mode is selected. When “1” is written to the I20ST bit in the control register setting wait state, the LSI shifts to the data transmit or receive mode. When “1” is written to the I20SP bit, the LSI shifts to the stop condition. When “1” is written to the I20RS bit, the operation shifts to the repeated start condition. 15.3.1.7 Stop Condition In the stop condition, the stop condition waveform is output to the SDA and SCL pins. waveform is output, an I2C bus interface interrupt (I2C0INT) is generated. FEUL610Q438 After the stop condition 15-9 ML610Q438/ML610Q439 User’s Manual Chapter 15 I2C Bus Interface 15.3.2 Communication Operation Timing Figures 15-2 to 15-4 show the operation timing and control method for each communication mode. Transmission Reception S P S r Start condition Stop condition Restart condition Register I20CSA=”xxxxxxx0B” setting I2C0CON=”01H” SDA S I2C0TD=”xxH” I2C0CON=”01H” A A A A A A A R A 6 5 4 3 2 1 0 W D D 7 6 A A Reception of Transmission of Transmission of acknowledgment acknowledgment non-acknowledgment I2C0TD = ”xxH” I2C0TD=”xxH” I2C0CON=”01H” I2C0CON=”01H” I2C0CON=”02H” D A 0 Value of I2C0TD  Value of I2C0SA A D D 7 6 D A 0 D D 7 6 D A 0 P Value of I2C0TD  Value of I2C0TD  I2C0INT I20ST I2C0RD Figure 15-2 Value of I2C0TD  Value of I2C0TD  Operation Timing in Data Transmit Mode (Write) Register I2C0SA=”xxxxxxx1B” setting I2C0CON=”01H” SDA Value of I2C0TD  Value of I2C0SA I2C0CON=”01H” I2C0CON=”01H” I2C0CON=”81H” I2C0CON=”02H” R A S A A A A A A A 6 5 4 3 2 1 0 W Value of I2C0SA D D 7 6 D A 0 D D 7 6 D A 0 D D 7 6 D A 0 Receive data  Receive data  Receive data  Value of I2C0SA Receive data  Receive data  P I2C0INT I20ST I2C0RD Figure 15-3 Register I2C0SA=”xxxxxxx0B” setting I2C0CON=”01H” SDA S A A 6 5 A R A 0 W Value of I2C0SA Receive data  Operation Timing in Data Receive Mode (Read) I2C0TD=”xxH” I2C0SA=”xxxxxxx1B” I2C0CON=”01H” I2C0CON=”05H” D D 7 6 D A 0 Value of I2C0TD  S A A r 6 5 A R A 0 W Value of I2C0SA I2C0CON=”81H” I2C0CON=”02H” D D 7 6 D A 0 P Receive data  I2C0INT I20ST I2C0RD Figure 15-4 FEUL610Q438 Value of I2C0SA Value of I2C0TD  Value of I2C0SA Receive data  Operation Timing at Data Transmit/Receive Mode (Write/Read) Switching 15-10 ML610Q438/ML610Q439 User’s Manual Chapter 15 I2C Bus Interface Figure 15-5 shows the operation timing and control method when an acknowledgment error occurs. Register setting SDA I2C0SA=”xxxxxxx0B” I2C0CON=”01H” S Acknowledgment error I2C0CON=”02H” A A A A A A A R A 6 5 4 3 2 1 0 W Value of I2C0SA P I2C0INT I20ST I2C0RD Value of I2C0SA I20ACR Figure 15-5 Operation Suspend Timing at Occurrence of Acknowledgment Error When the values of the transmitted bit and the SDA pin do not coincide, the I20ER bit of the I2C bus 0 status register (I2C0STAT) is set to “1” and SDA pin remains the output until termination of the subsequent byte data communication I20ER bit is initialized to “0” by writing I2C Bus 0 Control Register (I2C0COCON). Figure 15-6 shows the operation timing and control method when transmission fails. Register setting I2C0SA=”xxxxxxx0B” I2C0CON=”01H” I2C0CON=”00H” Transmission failure SDA S A A A A 6 5 4 3 A I2C0INT I20ST I2C0RD Undefined data I20ER Figure 15-6 FEUL610Q438 Operation Timing When Transmission Fails 15-11 ML610Q438/ML610Q439 User’s Manual Chapter 15 I2C Bus Interface 15.3.3 Operation Waveforms Figure 15-7 shows the operation waveforms of the SDA and SCL signals and the I20BB flag. relationship between communication speeds and HSCLK clock counts. Start condition Restart condition Table 15-1 shows the Stop condition SDA SCL I20BB tCYC tHD:STA tLOW Figure 15-7 Table 15-1 tHD:DAT tSU:DAT tSU:STO tBUF Operation Waveforms of SDA and SCL Signals and I20BB Flag Relationship between Communication Speeds and HSCLK Clock Counts Speed reduction (I20DW1, 0) No reduction 10% reduction Standard mode 100 kｂｐｓ 20% reduction 30% reduction No reduction 10% reduction Fast mode 400 kｂｐｓ 20% reduction 30% reduction φ: Period of high-speed clock (HSCLK) Communication speed (I20SP) tSU:STA tHIGH tCYC tHD:STA tLOW tHD:DAT tHIGH tSU:STA tSU:DAT tSU:STO tBUF 40φ 44φ 48φ 52φ 10φ 11φ 12φ 13φ 18φ 20φ 22φ 24φ 4φ 4φ 5φ 5φ 22φ 24φ 26φ 28φ 6φ 7φ 7φ 8φ 4φ 4φ 4φ 4φ 2φ 2φ 2φ 2φ 18φ 20φ 22φ 24φ 4φ 4φ 5φ 5φ 22φ 24φ 26φ 28φ 6φ 7φ 7φ 8φ 18φ 20φ 22φ 24φ 4φ 5φ 5φ 6φ 18φ 20φ 22φ 24φ 4φ 4φ 5φ 5φ 22φ 24φ 26φ 28φ 6φ 7φ 7φ 8φ Note The HSCLK clock count is set so that the communication speed may be set to 100kbps/400kbps when HSCLK is 4 MHz. When the high-speed clock frequency is not 4 MHz, select an I2C0MOD communication speed reduction rate and an FCON0 HSCLK frequency so that the communication speed may not exceed 100kbps/400kbps. FEUL610Q438 15-12 ML610Q438/ML610Q439 User’s Manual Chapter 15 I2C Bus Interface 15.4 Specifying port registers When you want to make sure the I2C function is working, please check related port registers are specified. See Chapter 21, “Port 4” for detail about the port registers. 15.4.1 Functioning P41(SCL) and P40(SDA) as the I2C Set P41MD1-P40MD1 bits(bit1-bit0 of P4MOD1 register) to “0” and set P41MD0-P40MD0(bit1-bit0 of P4MOD0 register) to “1”, for specifying the I2C as the secondary function of P41 and P40. Reg. name P4MOD1 register (Address: 0F225H) Bit 7 6 5 4 3 2 1 0 Bit name P47MD1 P46MD1 P45MD1 P44MD1 P43MD1 P42MD1 P41MD1 P40MD1 Data * * * * * * 0 0 Reg. name P4MOD0 register (Address: 0F224H) Bit 7 6 5 4 3 2 1 0 Bit name P47MD0 P46MD0 P45MD0 P44MD0 P43MD0 P42MD0 P41MD0 P40MD0 Data * * * * * * 1 1 Set P41C1-P40C1 bit(bit1-0 of P4CON1 register) to “1”, set P41C0-P40C0 bit(bit1-0 of P4CON0 register) to “0”, and set P41DIR-P40DIR bit(bit1-0 of P4DIR register) to “0”, for specifying the P41 and P40 as Nch open-drain output. The open-drain/open-collector outputs are required on the I2C bus line to avoid collision between H level and L level. Reg. name P4CON1 register (Address: 0F223H) Bit 7 6 5 4 3 2 1 0 Bit name P47C1 P46C1 P45C1 P44C1 P43C1 P42C1 P41C1 P40C1 Data * * * * * * 1 1 Bit 7 6 5 4 3 2 1 0 Bit name P47C0 P46C0 P45C0 P44C0 P43C0 P42C0 P41C0 P40C0 Data * * * * * * 0 0 Reg. name P4CON0 register (Address: 0F222H) Reg. name P4DIR register (Address: 0F221H) Bit 7 6 5 4 3 2 1 0 Bit name P47DIR P46DIR P45DIR P44DIR P43DIR P42DIR P41DIR P40DIR Data * * * * * * 0 0 Data of P41D-P40D bits (bit1-0 of P4D register) do not affect to the I2C function, so don’t care the data for the function. Reg. name P4D register (Address: 0F220H) Bit 7 6 5 4 3 2 1 0 Bit name P47D P46D P45D P44D P43D P42D P41D P40D Data * * * * * * ** ** * : Bit not related to the I2C(using P41 and P40) function ** : Don’t care the data FEUL610Q438 15-13 Chapter 16 NMI Pin ML610Q438/ML610Q439 User’s Manual Chapter 16 NMI Pin 16. NMI Pin 16.1 Overview This LSI includes an input port (NMI) which generates a non-maskable interrupt. For interrupts see Chapter 5, “Interrupts”. 16.1.1 Features • Non-maskable interrupt pin. • Allows selection of an input with a pull-up resistor or a high-impedance input. • Applies a noise filter to NMI interrupt (NMINT). 16.1.2 Configuration Figure 16-1 shows the configuration of the NMI pin. Data bus VDD Pull-up Controller VDD NMI NMICON 1 NMID Noise Filter VSS NMID: NMICON: 1 NMINT NMI data register NMI control register Figure 16-1 Configuration of NMI Pin 16.1.3 List of Pins Pin name Input/output NMI I/O FEUL610Q438 Description Non-maskable interrupt input port 16-1 ML610Q438/ML610Q439 User’s Manual Chapter 16 NMI Pin 16.2 Description of Registers 16.2.1 List of Registers Address Name 0F200H NMI data register 0F201H NMI control register FEUL610Q438 Symbol (Byte) Symbol (Word) R/W Size NMID  R 8 NMICON  R/W 8 Initial value Depends on pin state 00H 16-2 ML610Q438/ML610Q439 User’s Manual Chapter 16 NMI Pin 16.2.2 NMI Data Register (NMID) Address: 0F200H Access: R Access size: 8 bits Initial value: Depends on the pin state 7 6 5 4 3 2 1 0 NMID        NMI R Initial value R 0 R 0 R 0 R 0 R 0 R 0 R 0 R x NMID is a read-only special function register (SFR) for reading the NMI pin level. [Description of Bits] • NMI (bit 0) The NMI bit is used to read the level of the NMI pin. NMI 0 1 FEUL610Q438 Description “0” level “1” level 16-3 ML610Q438/ML610Q439 User’s Manual Chapter 16 NMI Pin 16.2.3 NMI Control Register (NMICON) Address: 0F201H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 NMICON        NMIC R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 NMICON is a special function register (SFR) to select the input mode of the NMI pin. [Description of Bits] • NMIC (bit 0) The NMIC bit is used to select the input mode with or without a pull-up resistor. NMIC 0 1 FEUL610Q438 Description Input mode with a pull-up resistor (initial value) High-impedance input mode 16-4 ML610Q438/ML610Q439 User’s Manual Chapter 16 NMI Pin 16.3 Description of Operation The non-maskable NMI interrupt (NMIINT) is assigned to the NMI pin. The NMI pin allows selection of an input mode with a pull-up resistor or a high-impedance input mode by using the NMI control register (NMICON). At a system reset, the input mode with a pull-up resistor is selected. The level of the NMI pin can be read by reading the NMI data register (MMID). 16.3.1 Interrupt Request When a level change occurs at the NMI pin after the duration longer than the minimum NMI interrupt pulse width, a non-maskable interrupt which does not depend on the master interrupt enable flag (MIE) is generated. Figure 16-2 shows the NMI interrupt generation timing. SYSCLK NMI pin TNMI TNMI TNMI NMINT Interrupt request QNMI Figure 16-2 FEUL610Q438 NMI Interrupt Generation Timing 16-5 Chapter 17 Port 0 ML610Q438/ML610Q439 User’s Manual Chapter 17 Port 0 17. Port 0 17.1 Overview This LSI includes Port 0 (P00 to P07) which is a 8-bit input port. 17.1.1 Features • All bits support a maskable interrupt function. • Allows selection of interrupt disabled mode, falling-edge interrupt mode, rising-edge interrupt mode, or both-edge interrupt mode for each bit. • Allows selection of with/without interrupt sampling for each bit.(Sampling frequency: T16KHZ) • Allows selection of high-impedance input mode, input mode with a pull-down resistor, or input mode with a pull-up resistor for each bit. • The P02 pin can be used as the RXD0 input pin of UART0, or the external clock input pin for PWM2. 17.1.2 Configuration Figure 17-1 shows the configuration of Port 0. VDD Pull-up Pull-down Controller VDD P00 to P07 Data bus P0CON0 P0CON1 VSS 8 P0D EXICON0 EXICON1 EXICON2 VSS Interrupt Controller 8 1 1 P0D P0CON0 P0CON1 EXICON0 EXICON1 EXICON2 Sampling clock T16KHZ RXD0 P2CK : Port 0 data register : Port 0 control register 0 : Port 0 control register 1 : External interrupt control register 0 : External interrupt control register 1 : External interrupt control register 2 Figure 17-1 FEUL610Q438 P00INT to P07INT Configuration of Port 0 17-1 ML610Q438/ML610Q439 User’s Manual Chapter 17 Port 0 17.1.3 List of Pins Pin name P00/EXI0 P01/EXI1 P02/EXI2/RXD0/ P2CK P03/EXI3 P04/EXI4 P05/EXI5 P06/EXI6 P07/EXI7 FEUL610Q438 I/O I I I I I I I I Description Input port, External 0 interrupt Input port, External 1 interrupt Input port, External 2 interrupt, UART0 data input (RXD0), PWM2 external clock input (P2CK) Input port, External 3 interrupt Input port, External 4 interrupt Input port, External 5 interrupt Input port, External 6 interrupt Input port, External 7 interrupt 17-2 ML610Q438/ML610Q439 User’s Manual Chapter 17 Port 0 17.2 Description of Registers 17.2.1 List of Registers Address Name 0F204H Port 0 data register 0F206H 0F207H 0F020H 0F021H 0F022H Port 0 control register 0 Port 0 control register 1 External interrupt control register 0 External interrupt control register 1 External interrupt control register 2 FEUL610Q438 Symbol (Byte) Symbol (Word) R/W Size P0D  R 8 R/W R/W R/W R/W R/W 8/16 8 8 8 8 P0CON0 P0CON1 EXICON0 EXICON1 EXICON2 P0CON    Initial value Depends on pin status 00H 00H 00H 00H 00H 17-3 ML610Q438/ML610Q439 User’s Manual Chapter 17 Port 0 17.2.2 Port 0 Data Register (P0D) Address: 0F204H Access: R Access size: 8 bits Initial value: Depends on pin status 7 6 5 4 3 2 1 0 P0D P07D P06D P05D P04D P03D P02D P01D P00D R Initial value R x R x R x R x R x R x R x R x P0D is a special function register (SFR) to only read the pin level of Port 0. [Description of Bits] • P07D-P00D (bits 7-0) The P07D to P00D bits are used to read the pin level of Port 0. P00D 0 1 P00 pin input: “L” level P00 pin input: “H” level P01D 0 1 P01 pin input: “L” level P01 pin input: “H” level P02D 0 1 P02 pin input: “L” level P02 pin input: “H” level P03D 0 1 P03 pin input: “L” level P03 pin input: “H” level P04D 0 1 P04 pin input: “L” level P04 pin input: “H” level P05D 0 1 P05 pin input: “L” level P05 pin input: “H” level P06D 0 1 P06 pin input: “L” level P06 pin input: “H” level P07D 0 1 P07 pin input: “L” level P07 pin input: “H” level FEUL610Q438 Description Description Description Description Description Description Description Description 17-4 ML610Q438/ML610Q439 User’s Manual Chapter 17 Port 0 17.2.3 Port 0 Control Registers 0, 1 (P0CON0, P0CON1) Address: 0F206H Access: R/W Access size: 8/16 bits Initial value: 00H 7 6 5 4 3 2 1 0 P0CON0 P07C0 P06C0 P05C0 P04C0 P03C0 P02C0 P01C0 P00C0 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Address: 0F207H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 P0CON1 P07C1 P06C1 P05C1 P04C1 P03C1 P02C1 P01C1 P00C1 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 P0CON0 and P0CON1 are special function registers (SFRs) to select the input mode of Port 0. [Description of Bits] • P07C0-P00C0, P07C1-P00C1 (bits 7-0) The P07C0 to P00C0 bits and the P07C1 to P00C1 bits are used to select high-impedance input mode, input mode with a pull-down resistor, or input mode with a pull-up resistor. The P0nC0 bit and the P0nC1 bit determine the input mode of P0n (Example: When P02C0 = “0” and P02C1 = “1”, P02 is in input mode with a pull-up resistor). P07C1-P00C1 0 0 1 1 FEUL610Q438 P07C0-P00C0 0 1 0 1 Description High-impedance input mode (initial value) Input mode with a pull-down resistor Input mode with a pull-up resistor High-impedance input mode 17-5 ML610Q438/ML610Q439 User’s Manual Chapter 17 Port 0 17.2.4 External Interrupt Control Registers 0, 1 (EXICON0, EXICON1) Address: 0F020H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 EXICON0 P07E0 P06E0 P05E0 P04E0 P03E0 P02E0 P01E0 P00E0 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Address: 0F021H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 EXICON1 P07E1 P06E1 P05E1 P04E1 P03E1 P02E1 P01E1 P00E1 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 EXICON0 and EXICON1 are special function registers (SFRs) to select an interrupt edge of Port 0. [Description of Bits] • P07E0-P00E0, P07E1-P00E1 (bits 7-0) The P07E0 to P00E0 bits and the P07E1 to P00E1 bits are used to select interrupt disabled mode, falling-edge interrupt mode, rising-edge interrupt mode, or both-edge interrupt mode. The P0nE0 bit and the P0nE1 bit determine the interrupt mode of P0n (Example: When P02E0 = “0” and P02E1 = “1”, P02 is in rising-edge interrupt mode). P07E1-P00E1 0 0 1 1 FEUL610Q438 P07E0-P00E0 0 1 0 1 Description Interrupt disabled mode (initial value) Falling-edge interrupt mode Rising-edge interrupt mode Both-edge interrupt mode 17-6 ML610Q438/ML610Q439 User’s Manual Chapter 17 Port 0 17.2.5 External Interrupt Control Register 2 (EXICON2) Address: 0F022H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 EXICON2 P07SM P06SM P05SM P04SM P03SM P02SM P01SM P00SM R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 EXICON2 is a special function register (SFR) to select detection of signal edge for interrupts with or without sampling. [Description of Bits] • P07SM-P00SM (bits 7-0) The P07SM to P00SM bits are used to select detection of signal edge for Port 0 interrupts with or without sampling. The sampling clock is T16KHZ of the low-speed time base counter (LTBC). P00SM 0 1 P01SM 0 1 P02SM 0 1 P03SM 0 1 FEUL610Q438 Description Detects the input signal edge for a P00 interrupt without sampling (initial value). Detects the input signal edge for a P00 interrupt with sampling. Description Detects the input signal edge for a P01 interrupt without sampling (initial value). Detects the input signal edge for a P01 interrupt with sampling. Description Detects the input signal edge for a P02 interrupt without sampling (initial value). Detects the input signal edge for a P02 interrupt with sampling. Description Detects the input signal edge for a P03 interrupt without sampling (initial value). Detects the input signal edge for a P03 interrupt with sampling. 17-7 ML610Q438/ML610Q439 User’s Manual Chapter 17 Port 0 P04SM 0 1 P05SM 0 1 P06SM 0 1 P07SM 0 1 Description Detects the input signal edge for a P04 interrupt without sampling (initial value). Detects the input signal edge for a P04 interrupt with sampling. Description Detects the input signal edge for a P05 interrupt without sampling (initial value). Detects the input signal edge for a P05 interrupt with sampling. Description Detects the input signal edge for a P06 interrupt without sampling (initial value). Detects the input signal edge for a P06 interrupt with sampling. Description Detects the input signal edge for a P07 interrupt without sampling (initial value). Detects the input signal edge for a P07 interrupt with sampling. Note: In STOP mode, since the 16 kHz sampling clock stops, no sampling is performed regardless of the values set in P00SM to P07SM. FEUL610Q438 17-8 ML610Q438/ML610Q439 User’s Manual Chapter 17 Port 0 17.3 Description of Operation For each pin of Port 0, the setting of the Port 0 control registers 0 and 1 (P0CON0 and P0CON1) allows selection of high-impedance input mode, input mode with a pull-down resistor, or input mode with a pull-up resistor. High-impedance input mode is selected at system reset. The pin level of Port 0 can be read by reading the Port 0 data register (P0D) 17.3.1 External Interrupt The Port 0 pins (P00 to P07) can be used for P00 to P07 interrupts (P00INT to P07INT). The P00 to P07 interrupts are maskable and interrupt enable or disable can be selected. For details of interrupts, see Chapter 5, “Interrupts”. The P02 pin can be used as the RXD0 input pin of UART0, or the external clock input pin for PWM2. For the UART function and the PWM function, see Chapter 14, “UART,” and Chapter 11, “PWM,” respectively. 17.3.2 Interrupt Request When an interrupt edge selected with the external interrupt control register 0, 1, or 2 (EXICON0, EXICON1, or EXICON2) occurs at a Port 0 pin, a maskable P00 (P01, P02, P03, P04, P05, P06, or P07) interrupt (P00INT, P01INT, P02INT, P03INT, P04INT, P05INT, P06INT, or P07INT). Figure 17-2 shows the P00 to P07 interrupt generation timing in rising-edge interrupt mode, in falling-edge interrupt mode, and in both-edge interrupt mode without sampling and the P00 to P07 interrupt generation timing in rising-edge interrupt mode with sampling. SYSCLK P0n pin P0nINT Interrupt request QP0n (a) When Falling-Edge Interrupt Mode without Sampling is Selected SYSCLK P0n pin P0nINT Interrupt request QP0n (b) When Rising-Edge Interrupt Mode without Sampling is Selected FEUL610Q438 17-9 ML610Q438/ML610Q439 User’s Manual Chapter 17 Port 0 SYSCLK P0n pin P0nINT Interrupt request QP0n (c) When Both-Edge Interrupt Mode without Sampling is Selected T16KHZ SYSCLK P0n pin P0nINT Interrupt request QP0n n = 0 to 7 (d) When Rising-Edge Interrupt Mode with Sampling is Selected Figure 17-2 FEUL610Q438 P00 to P07 Interrupt Generation Timing 17-10 Chapter 18 Port 1 ML610Q438/ML610Q439 User’s Manual Chapter 18 Port 1 18. Port 1 18.1 Overview This LSI incorporates a 2-bit input port, Port 1 (P10, P11). Port 1 can have a high-speed oscillation pin or an external clock input pin as a secondary function. When the port is used as a high-speed oscillation pin, the P11 pin functions as an output pin if crystal/ceramic oscillation mode is selected with the OSCM1–0 bits of the FCON0 register. For high-speed oscillation and external clock input, see Chapter 6, “Clock Generation Circuit”. 18.1.1 Features • Allows selection of high-impedance input mode, input mode with a pull-down resistor, or input mode with a pull-up resistor for each bit. • Allows selection of a high-speed crystal/ceramic resonator pin or an external clock input pin as a secondary function. 18.1.2 Configuration Figure 18-1 shows the configuration of Port 1. VDD Data bus Pull-up Pull-down Controller VDD VSS 2 P1CON0 P1CON1 2 P10, P11 P1D 2 High-speed oscillation circuit 2 VSS FCON0 (OSCM1, OSCM0) 1 OSCLK STOP mode ENOSC (oscillation enable) P1D P1CON0 P1CON1 : Port 1 data register : Port 1 control register 0 : Port 1 control register 1 Figure 18-1 Configuration of Port 1 18.1.3 List of Pins Pin name I/O P10/OSC0 I Input port P11/OSC1 I/O Input port FEUL610Q438 Primary function Secondary function High-speed crystal/ceramic oscillation pin, external clock input pin High-speed crystal/ceramic oscillation pin 18-1 ML610Q438/ML610Q439 User’s Manual Chapter 18 Port 1 18.2 Description of Registers 18.2.1 List of Registers Address Name 0F208H Port 1 data register 0F20AH 0F20BH Port 1 control register 0 Port 1 control register 1 FEUL610Q438 Symbol (Byte) Symbol (Word) R/W Size P1D  R 8 P1CON0 P1CON1 P1CON R/W R/W 8/16 8 Initial value Depends on pin status 00H 00H 18-2 ML610Q438/ML610Q439 User’s Manual Chapter 18 Port 1 18.2.2 Port 1 Data Register (P1D) Address: 0F208H Access: R Access size: 8 bits Initial value: Depends on pin status 7 6 5 4 3 2 1 0 P1D       P11D P10D R Initial value R 0 R 0 R 0 R 0 R 0 R 0 R x R x P1D is a special function register (SFR) dedicated to read the input level of the Port 1 pin. [Description of Bits] • P11D, P10D (bits 1, 0) The P11D and P10D bits are used to read the input level of the Port 1 pin. P11D 0 1 Input level of the P11 pin: ”L” Input level of the P11 pin: ”H” P10D 0 1 Input level of the P10 pin: ”L” Input level of the P10 pin: ”H” FEUL610Q438 Description Description 18-3 ML610Q438/ML610Q439 User’s Manual Chapter 18 Port 1 18.2.3 Port 1 Control Registers 0, 1 (P1CON0, P1CON1) Address: 0F20AH Access: R/W Access size: 8/16 bits Initial value: 00H 7 6 5 4 3 2 1 0 P1CON0       P11C0 P10C0 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Address: 0F20BH Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 P0CON1       P11C1 P10C1 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 P1CON0 and P1CON1 are special function registers (SFRs) to select the input mode of Port 1. [Description of Bits] • P11C0, P10C0, P11C1, P00C1 (bits 1-0) The P11C0, P10C0, P11C1 and P00C1 bits are used to select high-impedance input mode, input mode with a pull-down resistor, or input mode with a pull-up resistor. P11C1 0 0 1 1 P11C0 0 1 0 1 Description P11 pin: high-impedance input mode (initial value) P11 pin: input mode with a pull-down resistor P11 pin: input mode with a pull-up resistor P11 pin: high-impedance input mode P10C1 0 0 1 1 P10C0 0 1 0 1 Description P10 pin: high-impedance input mode (initial value) P10 pin: input mode with a pull-down resistor P10 pin: input mode with a pull-up resistor P10 pin: high-impedance input mode Note: When using P10 and P11 as crystal/ceramic oscillation pins, be sure to set the P10 and P11 pins to high-impedance input mode. When using the P10 pin as an external clock input pin, set the P10 pin to high-impedance input mode so that the pull-up or pull-down resistor will not carry current. FEUL610Q438 18-4 ML610Q438/ML610Q439 User’s Manual Chapter 18 Port 1 18.3 Description of Operation 18.3.1 Input Port Function For each pin of Port 1, one of high-impedance input mode, input mode with a pull-down resistor, and input mode with a pull-up resistor can be selected by setting the Port 1 control registers 0 and 1 (P1CON0 and P1CON1). At system reset, high-impedance input mode is selected as the initial state. The input level of the Port 1 pin can be read by reading the Port 1 data register (P1D). 18.3.2 Secondary Function A high-speed crystal/ceramic oscillation pin or an external clock input pin is assigned to Port 1 as a secondary function. Select high-speed crystal/ceramic oscillation mode or external clock input mode by using the high-speed clock mode select function of the OSCM1 and 0 bits of the frequency control register 0 (FCON0). In crystal/ceramic oscillation mode, both P10 and P11 pins are used as the pins for crystal/ceramic oscillation. In external clock input mode, the P10 pin is used as the input pin of external clock and the P11 pin can be used as a general-purpose input port. Note: No port mode register is provided for switching between the primary function and the secondary function of Port 1. When using the Port 1 pins as high-speed oscillation pins, pin mode is switched according to the values set in the OSCM1 and OSCM0 bits of the FCON0 register. See Chapter 6, “Clock Generation Circuit,” for the details of the FCON0 register, high-speed oscillation, and external clock input. FEUL610Q438 18-5 Chapter 19 Port 2 ML610Q438/ML610Q439 User’s Manual Chapter 19 Port 2 19. Port 2 19.1 Overview This LSI includes 3-bit Port 2 (P20 to P22) dedicated to output. Port 2 can output low-speed clock (LSCLK), high-speed output clock (OUTCLK), and melody as a secondary function. For clock output and melody 0 (MD0) output, see Chapter 6, “Clock Generation Circuit” and Chapter 23, “Melody Driver”, respectively. 19.1.1 Features • Allows direct LED drive. • Allows selection of high-impedance output mode, P-channel open drain output mode, N-channel open drain output mode, or CMOS output mode for each bit. • Allows output of low-speed clock (LSCLK), high-speed clock (OUTCLK), melody 0 (MD0), or PWM2 (PWM2) as a secondary function. 19.1.2 Configuration Figure 19-1 shows the configuration of Port 2. VDD VDD P20 to P22 Port2 Output Controller 3 Data bus P2MOD P2MOD1 P2CON0 P2CON1 P2D 4 VSS VSS P2D P2CON0 P2CON1 P2MOD Ｐ２ＭＯＤ１ LSCLK OUTCLK MD0 PWM2 : Port 2 data register : Port 2 control register 0 : Port 2 control register 1 : Port 2 mode register : Port 2 mode register1 Figure 19-1 Configuration of Port 2 19.1.3 List of Pins Pin name P20/LED0 /LSCLK/PWM2 P21/LED1 /OUTCLK P22/LED2 /MD0 FEUL610Q438 I/O O O O Primary function Output port, Direct LED drive Output port, Direct LED drive Output port, Direct LED drive Secondary function Low-speed clock output (LSCLK) High-speed clock output (OUTCLK) Melody 0 output (MD0) Tertiary function PWM2 output   19-1 ML610Q438/ML610Q439 User’s Manual Chapter 19 Port 2 19.2 Description of Registers 19.2.1 List of Registers Address Name 0F210H Port 2 data register 0F212H 0F213H 0F214H 0F215H Port 2 control register 0 Port 2 control register 1 Port 2 mode register 0 Port 2 mode register 1 FEUL610Q438 Symbol (Byte) Symbol (Word) R/W Size P2D  R/W 8 R/W R/W R/W R/W 8/16 8 8/16 8 P2CON0 P2CON1 P2MOD P2MOD1 P2CON P2MODW Initial value Depends on pin status 00H 00H 00H 00H 19-2 ML610Q438/ML610Q439 User’s Manual Chapter 19 Port 2 19.2.2 Port 2 Data Register (P2D) Address: 0F210H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 P2D      P22D P21D P20D R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 P2D is a special function register (SFR) to set the output value of Port 2. The value of this register is output to Port 2. The value written to P2D is readable. [Description of Bits] • P22D-P20D (bits 2-0) The P22D to P20D bits are used to set the output value of the Port 2 pin. P22D 0 1 Output level of the P22 pin: ”L” Output level of the P22 pin: ”H” P21D 0 1 Output level of the P21 pin: ”L” Output level of the P21 pin: ”H” P20D 0 1 Output level of the P20 pin: ”L” Output level of the P20 pin: ”H” FEUL610Q438 Description Description Description 19-3 ML610Q438/ML610Q439 User’s Manual Chapter 19 Port 2 19.2.3 Port 2 control registers 0, 1 (P2CON0, P2CON1) Address: 0F212H Access: R/W Access size: 8/16 bits Initial value: 00H 7 6 5 4 3 2 1 0 P2CON0      P22C0 P21C0 P20C0 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Address: 0F213H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 P2CON1      P22C1 P21C1 P20C1 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 P2CON0 and P2CON1 are special function registers (SFRs) to select the output state of the output pin Port 2. [Description of Bits] • P22C0-P20C0, P22C1-P20C1 (bits 3-0) The P22C0 to P20C0 and P22C1 to P20C1 bits are used to select high-impedance output mode, P-channel open drain output mode, N-channel open drain output mode, or CMOS output mode. To directly drive LEDs, select N-channel open drain output mode. P22C1 0 0 1 1 P22C0 0 1 0 1 Description P22 pin: In high-impedance output mode (initial value) P22 pin: In P-channel open drain output mode P22 pin: In N-channel open drain output mode P22 pin: In CMOS output mode P21C1 0 0 1 1 P21C0 0 1 0 1 Description P21 pin: In high-impedance output mode (initial value) P21 pin: In P-channel open drain output mode P21 pin: In N-channel open drain output mode P21 pin: In CMOS output mode P20C1 0 0 1 1 P20C0 0 1 0 1 Description P20 pin: In high-impedance output mode (initial value) P20 pin: In P-channel open drain output mode P20 pin: In N-channel open drain output mode P20 pin: In CMOS output mode FEUL610Q438 19-4 ML610Q438/ML610Q439 User’s Manual Chapter 19 Port 2 19.2.4 Port 2 Mode Register, Port 2 Mode Register1 (P2MOD, P2MOD1) Address: 0F214H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 P2MOD0      P22MD P21MD P20MD R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Address: 0F215H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 P2MOD1      P22MD1 P21MD1 P20MD1 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 P2MOD0 and P2MOD1 is a special function register (SFR) to select the primary function or the secondary function of Port 2 [Description of Bits] • P22MD1, P22MD (bit 2) The P22MD1 and P22MD bit is used to select the primary function or the secondary function of the P22 pin. P22MD1 0 0 1 1 P22MD 0 1 0 1 Description General-purpose output port function (initial value) Melody 0 (MD0) output function Prohibited Prohibited • P21MD1, P21MD (bit 1) The P21MD1 and P21MD bit is used to select the primary function or the secondary function of the P21 pin. P21MD1 0 0 P21MD 0 1 Description General-purpose output port function (initial value) High-speed output clock (OUTCLK) output function 1 0 Prohibited 1 1 Prohibited • P20MD1, P20MD (bit 0) The P20MD1 and P20MD bit is used to select the primary function or the secondary function of the P20 pin. P20MD1 0 0 1 1 FEUL610Q438 P20MD 0 1 0 1 Description General-purpose output port function (initial value) Low-speed clock (LSCLK) output function PWM2 output function Prohibited 19-5 ML610Q438/ML610Q439 User’s Manual Chapter 19 Port 2 Note: The output characteristics of port2(P20, P21 and P22) corresponds to VOL1 and VOH1 when the secondary function is selected, and corresponds to VOL2 and VOH2 when the primary function is selected, which are shown in Appendix C, "Electrical Characteristics". If any bit combination out of the above is set to “Prohibited” and the corresponding bit of the port 2 is sepecified to output mode (selected in port2 control register), status of corresponding pin is fixed, regardless the contents of Port2 register (P2D) High-impedance output mode: High-impedance P-channel open drain output mode: High-impedance N-channel open drain output mode: Fixed to “L” CMOS output mode: High-impedance: Fixed to “L” FEUL610Q438 19-6 ML610Q438/ML610Q439 User’s Manual Chapter 19 Port 2 19.2.5 Port 2 Mode Register 2 (P2MOD2) Address: 0F216H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 P2MOD2       OCK1 OCK0 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 P2MOD2 is a special function register (SFR) to select low-speed clock, when P20 is the low-speed clock output function [Description of Bits] • OCK1, OCK0 (bits 1, 0) The OCK1 and OCK0 bits are used to select, or transmit/receive mode of the synchronous serial port. OCK1 0 0 1 1 FEUL610Q438 OCK0 0 1 0 1 Description LSCLK (initial value) T1KHZ(1/32LSCLK) T64HZ(1/512LSCLK) T2HZ(1/16384LSCLK) 19-7 ML610Q438/ML610Q439 User’s Manual Chapter 19 Port 2 19.3 Description of Operation 19.3.1 Output Port Function For each pin of Port 2, any one of high-impedance output mode, P-channel open drain output mode, N-channel open drain output mode, and CMOS output mode can be selected by setting the Port 2 control registers 0 and 1 (P2CON0 and P2CON1). At a system reset, high-impedance output mode is selected as the initial state. Depending of the value set in the Port 2 data register (P2D), a “L” level or “H” level signal is output to each pin of Port 2. 19.3.2 Secondary and Tertiary Function Low-speed clock (LSCLK) output, High-speed output clock (OUTCLK) output, melody 0 (MD0) output, or PWM2 (PWM2) output is assigned to Port 2 as a secondary and tertiary function. These pins can be used in a secondary or tertiary function mode by setting the P22MD to P20MD bits and the P22MD1 to P20MD1 bits of the Port 2 mode registers (P2MOD, P2MOD1). Low-speed clock (LSCLK) output can be set up by the OCK0 bit and the OCK1 bit of the Port2 mode register 2 (P2MOD2). FEUL610Q438 19-8 Chapter 20 Port 3 ML610Q438/ML610Q439 User’s Manual Chapter 20 Port 3 20. Port 3 20.1 Overview This LSI includes Port 3 (P30 to P35), which is a 6-bit input/output port. This port can also be used as the RC-ADC (channel 0) oscillation pins (IN0, CS0, RS0, RT0, CRT0, RCM) and the PWM output pin in secondary and tertiary modes. For RC-ADC and PWM, see Chapter 24, “RC Oscillation Type A/D converter”, and Chapter 11, “PWM”. 20.1.1 Features • Allows selection of high-impedance output, P-channel open drain output, N-channel open drain output, or CMOS output in output mode for each bit. • Allows selection of high-impedance input, input with a pull-down resistor, or input with a pull-up resistor in input mode for each bit. • The RC-ADC (channel 0) oscillation pins (IN0, CS0, RS0, RT0, CRT0, RCM), the PWM0 output pin (PWM0), the PWM0 output pin (PWM0), and the PWM2 output pin (PWM2) can be used as the secondary functions. 20.1.2 Configuration Figure 20-1 shows the configuration of Port 3. VDD Data bus Pull-up Pull-down Controller VDD P3DIR P3MOD0, 1 P3CON0, 1 VSS VDD P30 to P35 Port3 Output Controller 6 P3D 6 6 VSS VSS P3D P3DIR P3CON0 P3CON1 P3MOD0 P3MOD1 1 : Port 3 data register : Port 3 direction register : Port 3 control register 0 : Port 3 control register 1 : Port 3 mode register 0 : Port 3 mode register 1 Figure 20-1 FEUL610Q438 Outputs for RC-ADC (CS0, RS0, RT0, CRT0, RCM) Output for PWM0 (PWM0) Output for PWM1 (PWM1) Output for PWM2 (PWM2) Input for RC-ADC (IN0) Configuration of Port 3 20-1 ML610Q438/ML610Q439 User’s Manual Chapter 20 Port 3 20.1.3 List of Pins Pin name I/O Primary function P30/IN0/PWM2 I/O Input/output port P31/CS0 I/O Input/output port P32/RS0 I/O Input/output port P33/RT0 I/O Input/output port P34/CRT0/PWM0 I/O Input/output port P35/RCM/PWM1 I/O Input/output port FEUL610Q438 Secondary function Oscillation waveform input pin for RC-ADC Reference capacitor connection pin for RC-ADC Reference resistor connection pin for RC-ADC Resistor sensor connection pin for measurement for RC-ADC Resistor/capacitor sensor connection pin for measurement for RC-ADC RC oscillation monitor pin for RC-ADC Tertiary function PWM2 output pin    PWM0 output pin PWM1 output pin 20-2 ML610Q438/ML610Q439 User’s Manual Chapter 20 Port 3 20.2 Description of Registers 20.2.1 List of Registers Address 0F218H 0F219H 0F21AH 0F21BH 0F21CH 0F21DH Name Port 3 data register Port 3 direction register Port 3 control register 0 Port 3 control register 1 Port 3 mode register 0 Port 3 mode register 1 FEUL610Q438 Symbol (Byte) Symbol (Word) R/W Size Initial value P3D P3DIR P3CON0 P3CON1 P3MOD0 P3MOD1   R/W R/W R/W R/W R/W R/W 8 8 8/16 8 8/16 8 00H 00H 00H 00H 00H 00H P3CON P3MOD 20-3 ML610Q438/ML610Q439 User’s Manual Chapter 20 Port 3 20.2.2 Port 3 data register (P3D) Address: 0F218H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 P3D   P35D P34D P33D P32D P31D P30D R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 P3D is a special function register (SFR) to set the value to be output to the Port 3 pin or to read the input level of the Port 3. In output mode, the value of this register is output to the Port 3 pin. The value written to P3D is readable. In input mode, the input level of the Port 3 pin is read when P3D is read. Output mode or input mode is selected by using the port mode register (P3DIR) described later. [Description of Bits] • P35D-P30D (bits 5-0) The P35D to P30D bits are used to set the output value of the Port 3 pin in output mode and to read the pin level of the Port 3 pin in input mode. P35D 0 1 Description Output or input level of the P35 pin: ”L” Output or input level of the P35 pin: ”H” P34D 0 1 Description Output or input level of the P34 pin: ”L” Output or input level of the P34 pin: ”H” P33D 0 1 Description Output or input level of the P33 pin: ”L” Output or input level of the P33 pin: ”H” P32D 0 1 Description Output or input level of the P32 pin: ”L” Output or input level of the P32 pin: ”H” P31D 0 1 Description Output or input level of the P31 pin: ”L” Output or input level of the P31 pin: ”H” P30D 0 1 Description Output or input level of the P30 pin: ”L” Output or input level of the P30 pin: ”H” FEUL610Q438 20-4 ML610Q438/ML610Q439 User’s Manual Chapter 20 Port 3 20.2.3 Port 3 Direction Register (P3DIR) Address: 0F219H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 P3DIR   P35DIR P34DIR P33DIR P32DIR P31DIR P30DIR R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 P3DIR is a special function register (SFR) to select the input/output mode of Port 3. [Description of Bits] • P35DIR-P30DIR (bits 5-0) The P35DIR to P30DIR pins are used to set the input/output direction of the Port 3 pin. P35DIR 0 1 P35 pin: Output (initial value) P35 pin: Input P34DIR 0 1 P34 pin: Output (initial value) P34 pin: Input P33DIR 0 1 P33 pin: Output (initial value) P33 pin: Input P32DIR 0 1 P32 pin: Output (initial value) P32 pin: Input P31DIR 0 1 P31 pin: Output (initial value) P31 pin: Input P30DIR 0 1 P30 pin: Output (initial value) P30 pin: Input FEUL610Q438 Description Description Description Description Description Description 20-5 ML610Q438/ML610Q439 User’s Manual Chapter 20 Port 3 20.2.4 Port 3 control registers 0, 1 (P3CON0, P3CON1) Address: 0F21AH Access: R/W Access size: 8/16 bits Initial value: 00H 7 6 5 4 3 2 1 0 P3CON0   P35C0 P34C0 P33C0 P32C0 P31C0 P30C0 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Address: 0F21BH Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 P3CON1   P35C1 P34C1 P33C1 P32C1 P31C1 P30C1 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 P3CON0 and P3CON1 are special function registers (SFRs) to select input/output state of the Port 3 pin. The input/output state is different between input mode and output mode. Input or output is selected by using the P3DIR register. [Description of Bits] • P35C1-P30C1, P35C0-P30C0 (bits 5-0) The P35C1 to P30C1 pins and the P35C0 to P30C0 pins are used to select high-impedance output, P-channel open drain output, N-channel open drain output, or CMOS output in output mode and to select high-impedance input, input with a pull-down resistor, or input with a pull-up resistor in input mode. When output mode is selected (P35DIR bit = “0”) P35C1 P35C0 0 0 0 1 1 1 0 1 Description P35 pin: High-impedance output (initial P35 pin: High-impedance input value) P35 pin: P-channel open drain output P35 pin: Input with a pull-down resistor P35 pin: N-channel open drain output P35 pin: Input with a pull-up resistor P35 pin: CMOS output P35 pin: High-impedance input When output mode is selected (P34DIR bit = “0”) P34C1 P34C0 0 0 0 1 1 1 0 1 FEUL610Q438 When input mode is selected (P35DIR bit = “1”) When input mode is selected (P34DIR bit = “1”) Description P34 pin: High-impedance output (initial P34 pin: High-impedance input value) P34 pin: P-channel open drain output P34 pin: Input with a pull-down resistor P34 pin: N-channel open drain output P34 pin: Input with a pull-up resistor P34 pin: CMOS output P34 pin: High-impedance input 20-6 ML610Q438/ML610Q439 User’s Manual Chapter 20 Port 3 When output mode is selected (P33DIR bit = “0”) P33C1 P33C0 0 0 0 1 1 1 0 1 Description P33 pin: High-impedance output (initial P33 pin: High-impedance input value) P33 pin: P-channel open drain output P33 pin: Input with a pull-down resistor P33 pin: N-channel open drain output P33 pin: Input with a pull-up resistor P33 pin: CMOS output P33 pin: High-impedance input When output mode is selected (P32DIR bit = “0”) P32C1 P32C0 0 0 0 1 1 1 0 1 P31C0 0 0 0 1 1 1 0 1 P30C0 0 0 0 1 1 1 0 1 FEUL610Q438 When input mode is selected (P31DIR bit = “1”) Description P31 pin: High-impedance output (initial P31 pin: High-impedance input value) P31 pin: P-channel open drain output P31 pin: Input with a pull-down resistor P31 pin: N-channel open drain output P31 pin: Input with a pull-up resistor P31 pin: CMOS output P31 pin: High-impedance input When output mode is selected (P30DIR bit = “0”) P30C1 When input mode is selected (P32DIR bit = “1”) Description P32 pin: High-impedance output (initial P32 pin: High-impedance input value) P32 pin: P-channel open drain output P32 pin: Input with a pull-down resistor P32 pin: N-channel open drain output P32 pin: Input with a pull-up resistor P32 pin: CMOS output P32 pin: High-impedance input When output mode is selected (P31DIR bit = “0”) P31C1 When input mode is selected (P33DIR bit = “1”) When input mode is selected (P30DIR bit = “1”) Description P30 pin: High-impedance output (initial P30 pin: High-impedance input value) P30 pin: P-channel open drain output P30 pin: Input with a pull-down resistor P30 pin: N-channel open drain output P30 pin: Input with a pull-up resistor P30 pin: CMOS output P30 pin: High-impedance input 20-7 ML610Q438/ML610Q439 User’s Manual Chapter 20 Port 3 20.2.5 Port 3 mode registers 0, 1 (P3MOD0, P3MOD1) Address: 0F21CH Access: R/W Access size: 8/16 bits Initial value: 00H 7 6 5 4 3 2 1 0 P3MOD0   P35MD0 P34MD0 P33MD0 P32MD0 P31MD0 P30MD0 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 P3MOD1   P35MD1 P34MD1 P33MD1 P32MD1 P31MD1 P30MD1 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Address: 0F21DH Access: R/W Access size: 8 bits Initial value: 00H P3MOD0 and P3MOD1 are special function registers (SFRs) to select the primary, secondary, or tertiary function of Port 3. [Description of Bits] • P35MD1, P35MD0 (bit 5) The P35MD1 and P35MD0 bits are used to select the primary or secondary function of the P35 pin. P35MD1 0 0 1 1 P35MD0 0 1 0 1 Description General-purpose input/output mode (initial value) RC oscillation monitor pin for RC-ADC PWM1 output pin Prohibited • P34MD1, P34MD0 (bit 4) The P34MD1 and P34MD0 bits are used to select the primary, secondary, or tertiary function of the P34 pin. P34MD1 0 P34MD0 0 0 1 1 1 0 1 Description General-purpose input/output mode (initial value) Resistor/capacitor sensor connection pin for measurement for RC-ADC (channel 0) PWM0 output pin Prohibited • P33MD1, P33MD0 (bit 3) The P33MD1 and P33MD0 bits are used to select the primary or secondary function of the P33 pin. P33MD1 0 P33MD0 0 0 1 1 1 0 1 FEUL610Q438 Description General-purpose input/output mode (initial value) Resistor/capacitor sensor connection pin for measurement for RC-ADC (channel 0) Prohibited Prohibited 20-8 ML610Q438/ML610Q439 User’s Manual Chapter 20 Port 3 • P32MD1, P32MD0 (bit 2) The P32MD1 and P32MD0 bits are used to select the primary or secondary function of the P32 pin. P32MD1 0 0 1 1 P32MD0 0 1 0 1 Description General-purpose input/output mode (initial value) Reference resistor connection pin for RC-ADC (channel 0) Prohibited Prohibited • P31MD1, P31MD0 (bit 1) The P31MD1 and P31MD0 bits are used to select the primary or secondary function of the P31 pin. P31MD1 0 0 1 1 P31MD0 0 1 0 1 Description General-purpose input/output mode (initial value) Reference capacitor connection pin for RC-ADC (channel 0) Prohibited Prohibited • P30MD1, P30MD0 (bit 0) The P30MD1 and P30MD0 bits are used to select the primary or secondary function of the P30 pin. P30MD1 0 0 1 1 P30MD0 0 1 0 1 Description General-purpose input/output mode (initial value) RC oscillation waveform input pin for RC-ADC (channel 0) PWM2 output pin Prohibited Note: If any bit combination out of the above is set to “Prohibited” and the corresponding bit of the port 3 is sepecified to output mode (selected in port3 control register), status of corresponding pin is fixed, regardless the contents of Port3 register (P3D) High-impedance output mode: High-impedance P-channel open drain output mode: High-impedance N-channel open drain output mode: Fixed to “L” CMOS output mode: High-impedance: Fixed to “L” When using RC-ADC as the secondary function, specify each pin be “High-impedance input” even the RC oscillation monitor pin. Pull-up or Pull-down input makes drawing the current. FEUL610Q438 20-9 ML610Q438/ML610Q439 User’s Manual Chapter 20 Port 3 20.3 Description of Operation 20.3.1 Input/Output Port Functions For each pin of Port 3, either output or input is selected by setting the Port 3 direction register (P3DIR). In output mode, high-impedance output mode, P-channel open drain output mode, N-channel open drain output mode, or CMOS output mode can be selected by setting the Port 3 control registers 0 and 1 (P3CON0 and P3CON1). In input mode, high-impedance input mode, input mode with a pull-down resistor, or input mode with a pull-up resistor can be selected by setting the Port 3 control registers 0 and 1 (P3CON0 and P3CON1). At a system reset, high-impedance output mode is selected as the initial state. In output mode, “L” or “H” level is output to each pin of Port 3 depending on the value set by the Port 3 data register (P3D). In input mode, the input level of each pin of Port 3 can be read from the Port 3 data register (P3D). 20.3.2 Secondary and Tertiary Functions Secondary and tertiary functions are assigned to Port 3 as the RC-ADC (channel 0) oscillation pins (IN0, CS0, RS0, RT0, CRT0, RCM), the PWM0 output pin (PWM0), the PWM1 output pin (PWM1) and the PWM2 output pin (PWM2). These pins can be used in a secondary or tertiary function mode by setting the P35MD0 to P30MD0 bits and the P35MD1 to P30MD1 bits of the Port 3 mode registers (P3MOD0, P3MOD1). Note: All the port 3 pins except P35/RCM are configured as pins dedicated to the RC-ADC function during A/D conversion. Therefore, if there is any unused pin, that pin cannot be used as its primary function during A/D conversion. For the RC-ADC, see Chapter 24, “RC Oscillation Type A/D Converter”. FEUL610Q438 20-10 Chapter 21 Port 4 ML610Q438/ML610Q439 User’s Manual Chapter 21 Port 4 21. Port 4 21.1 Overview This LSI includes Port 4 (P40 to P47) which is an 8-bit input/output port. This port can have the I2C bus, RC-ADC, synchronous serial port, and PWM output functions as secondary and tertiary functions. See the following chapters for reference: I2C bus: Chapter 15 “I2C Bus Interface” UART: Chapter 14 “UART” RC-ADC: Chapter 24 “RC Oscillation Type A/D Converter” Synchronous serial port: Chapter 13 “Synchronous Serial Port” PWM: Chapter 11 “PWM” 21.1.1 Features • Allows selection of high-impedance output, P-channel open drain output, N-channel open drain output, or CMOS output for each bit in output mode. • Allows selection of high-impedance input, input with a pull-down resistor, or input with a pull-up resistor for each bit in input mode. • The P44 and P45 pins can be used as external clock input pins for the timer and PWM. • The I2C bus interface pins (SDA, SCL), UART pins (RXD0, TXD0), RC-ADC (channel 1) oscillation pins (IN1, CS1, RS1, RT1), synchronous serial port pins (SIN0, SCK0, SOUT0), PWM0 output pin (PWM0), and the PWM1 output pin (PWM1) can be used as the secondary functions. 21.1.2 Configuration Figure 21-1 shows the configuration of Port 4. VDD Data bus Pull-up Pull-down Controller VDD P4DIR P4MOD0, 1 P4CON0, 1 VSS VDD P40 to P47 Port4 Output Controller 8 P4D 2 10 8 VSS 8 VSS P4D P4DIR P4CON0 P4CON1 P4MOD0 P4MOD1 2 Inputs for I C (SDA, SCL) Input for UART (RXD0) Input for RC-ADC (IN0) Inputs for SIO (SIN0, SCK0) Inputs for timer PWM (T02P0CK, T13P1CK) : Port 4 data register : Port 4 direction register : Port 4 control register 0 : Port 4 control register 1 : Port 4 mode register 0 : Port 4 mode register 1 Figure 21-1 FEUL610Q438 Outputs for I C (SDA, SCL) Output for UART (TXD0) Outputs for RC-ADC (CS1, RS1, RT1) Outputs for SIO (SCK0, SOUT) Output for PWM0 (PWM0) Output for PWM1 (PWM1) Configuration of Port 4 21-1 ML610Q438/ML610Q439 User’s Manual Chapter 21 Port 4 21.1.3 List of Pins Pin name I/O Primary function Secondary function Tertiary function 2 P40/SDA/SIN0 I/O Input/output port P41/SCL/SCK0 I/O Input/output port P42/RXD0/SOUT0 P43/TXD0/PWM0 I/O I/O P44/ T02P0CK /IN1/SIN0/ I/O P45/ T13P1CK /CS1/SCK0/ I/O Input/output port Input/output port Input/output port, Timer 0/PWM0 external clock Input/output port, Timer 1/PWM1 external clock P46/RS1/SOUT0 I/O Input/output port P47/RT1/PWM1 I/O Input/output port FEUL610Q438 I C bus 0 data input/output pin 2 I C bus 0 clock input/output pin UART0 data input pin UART0 data output pin SSIO0 data input pin SSIO0 clock input/output pin SSIO0 data output pin PWM0 output pin RC oscillation waveform input pin for RC-ADC SSIO0 data input pin Reference capacitor connection pin for RC-ADC SSIO0 clock input/output pin Reference resistor connection pin for RC-ADC Resistor sensor connection pin for measurement for RC-ADC SSIO0 data output pin PWM1 output pin 21-2 ML610Q438/ML610Q439 User’s Manual Chapter 21 Port 4 21.2 Description of Registers 21.2.1 List of Registers Address 0F220H 0F221H 0F222H 0F223H 0F224H 0F225H FEUL610Q438 Name Port 4 data register Port 4 direction register Port 4 control register 0 Port 4 control register 1 Port 4 mode register 0 Port 4 mode register 1 Symbol (Byte) P4D P4DIR P4CON0 P4CON1 P4MOD0 P4MOD1 Symbol (Word)   P4CON P4MOD R/W R/W R/W R/W R/W R/W R/W Size 8 8 8/16 8 8/16 8 Initial value 00H 00H 00H 00H 00H 00H 21-3 ML610Q438/ML610Q439 User’s Manual Chapter 21 Port 4 21.2.2 Port 4 Data Register (P4D) Address: 0F220H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 P4D P47D P46D P45D P44D P43D P42D P41D P40D R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 P4D is a special function register (SFR) to set the value to be output to the Port 4 pin or to read the input level of the Port 4. In output mode, the value of this register is output to the Port 4 pin. The value written to P4D is readable. In input mode, the input level of the Port 4 pin is read when P4D is read. Output mode or input mode is selected by using the port mode register (P4DIR) described later. [Description of Bits] • P47D-P40D (bits 7-0) The P47D to P40D bits are used to set the output value of the Port 4 pin in output mode and to read the pin level of the Port 4 pin in input mode. P47D 0 1 Description Output or input level of the P47 pin: ”L” Output or input level of the P47 pin: ”H” P46D 0 1 Description Output or input level of the P46 pin: ”L” Output or input level of the P46 pin: ”H” P45D 0 1 Description Output or input level of the P45 pin: ”L” Output or input level of the P45 pin: ”H” P44D 0 1 Description Output or input level of the P44 pin: ”L” Output or input level of the P44 pin: ”H” P43D 0 1 Description Output or input level of the P43 pin: ”L” Output or input level of the P43 pin: ”H” P42D 0 1 Description Output or input level of the P42 pin: ”L” Output or input level of the P42 pin: ”H” P41D 0 1 Description Output or input level of the P41 pin: ”L” Output or input level of the P41 pin: ”H” P40D 0 1 Description Output or input level of the P40 pin: ”L” Output or input level of the P40 pin: ”H” FEUL610Q438 21-4 ML610Q438/ML610Q439 User’s Manual Chapter 21 Port 4 21.2.3 Port 4 Direction Register (P4DIR) Address: 0F221H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 P4DIR P47DIR P46DIR P45DIR P44DIR P43DIR P42DIR P41DIR P40DIR R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 P4DIR is a special function register (SFR) to select the input/output mode of Port 4. [Description of Bits] • P47DIR-P40DIR (bits 7-0) The P47DIR to P40DIR pins are used to set the input/output direction of the Port 4 pin. P47DIR 0 1 P47 pin: Output (initial value) P47 pin: Input P46DIR 0 1 P46 pin: Output (initial value) P46 pin: Input P45DIR 0 1 P45 pin: Output (initial value) P45 pin: Input P44DIR 0 1 P44 pin: Output (initial value) P44 pin: Input P43DIR 0 1 P43 pin: Output (initial value) P43 pin: Input P42DIR 0 1 P42 pin: Output (initial value) P42 pin: Input P41DIR 0 1 P41 pin: Output (initial value) P41 pin: Input P40DIR 0 1 P40 pin: Output (initial value) P40 pin: Input FEUL610Q438 Description Description Description Description Description Description Description Description 21-5 ML610Q438/ML610Q439 User’s Manual Chapter 21 Port 4 21.2.4 Port 4 Control Registers 0, 1 (P4CON0, P4CON1) Address: 0F222H Access: R/W Access size: 8/16 bits Initial value: 00H 7 6 5 4 3 2 1 0 P4CON0 P47C0 P46C0 P45C0 P44C0 P43C0 P42C0 P41C0 P40C0 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Address: 0F223H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 P4CON1 P47C1 P46C1 P45C1 P44C1 P43C1 P42C1 P41C1 P40C1 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 P4CON0 and P4CON1 are special function registers (SFRs) to select input/output state of the Port 4 pin. The input/output state is different between input mode and output mode. Input or output is selected by using the P4DIR register. [Description of Bits] • P47C1-P40C1, P47C0-P40C0 (bits 7-0) The P47C1 to P40C1 pins and the P47C0 to P40C0 pins are used to select high-impedance output, P-channel open drain output, N-channel open drain output, or CMOS output in output mode and to select high-impedance input, input with a pull-down resistor, or input with a pull-up resistor in input mode. Setting of P47 pin P47C1 0 0 1 1 P47C0 0 1 0 1 Setting of P46 pin P46C1 0 0 1 1 P46C0 0 1 0 1 Setting of P45 pin P45C1 0 0 1 1 FEUL610Q438 P45C0 0 1 0 1 When output mode is selected (P47DIR bit = “0”) When input mode is selected (P47DIR bit = “1”) Description High-impedance output (initial value) High-impedance input P-channel open drain output Input with a pull-down resistor N-channel open drain output Input with a pull-up resistor CMOS output High-impedance input When output mode is selected (P46DIR bit = “0”) When input mode is selected (P46DIR bit = “1”) Description High-impedance output (initial value) High-impedance input P-channel open drain output Input with a pull-down resistor N-channel open drain output Input with a pull-up resistor CMOS output High-impedance input When output mode is selected (P45DIR bit = “0”) When input mode is selected (P45DIR bit = “1”) Description High-impedance output (initial value) High-impedance input P-channel open drain output Input with a pull-down resistor N-channel open drain output Input with a pull-up resistor CMOS output High-impedance input 21-6 ML610Q438/ML610Q439 User’s Manual Chapter 21 Port 4 Setting of P44 pin P44C1 0 0 1 1 P44C0 0 1 0 1 Setting of P43 pin P43C1 0 0 1 1 P43C0 0 1 0 1 Setting of P42 pin P42C1 0 0 1 1 P42C0 0 1 0 1 Setting of P41 pin P41C1 0 0 1 1 P41C0 0 1 0 1 Setting of P40 pin P40C1 0 0 1 1 FEUL610Q438 P40C0 0 1 0 1 When output mode is selected (P44DIR bit = “0”) When input mode is selected (P44DIR bit = “1”) Description High-impedance output (initial value) High-impedance input P-channel open drain output Input with a pull-down resistor N-channel open drain output Input with a pull-up resistor CMOS output High-impedance input When output mode is selected (P43DIR bit = “0”) When input mode is selected (P43DIR bit = “1”) Description High-impedance output (initial value) High-impedance input P-channel open drain output Input with a pull-down resistor N-channel open drain output Input with a pull-up resistor CMOS output High-impedance input When output mode is selected (P42DIR bit = “0”) When input mode is selected (P42DIR bit = “1”) Description High-impedance output (initial value) High-impedance input P-channel open drain output Input with a pull-down resistor N-channel open drain output Input with a pull-up resistor CMOS output High-impedance input When output mode is selected (P41DIR bit = “0”) When input mode is selected (P41DIR bit = “1”) Description High-impedance output (initial value) High-impedance input P-channel open drain output Input with a pull-down resistor N-channel open drain output Input with a pull-up resistor CMOS output High-impedance input When output mode is selected (P40DIR bit = “0”) When input mode is selected (P40DIR bit = “1”) Description High-impedance output (initial value) High-impedance input P-channel open drain output Input with a pull-down resistor N-channel open drain output Input with a pull-up resistor CMOS output High-impedance input 21-7 ML610Q438/ML610Q439 User’s Manual Chapter 21 Port 4 21.2.5 Port 4 Mode Registers 0, 1 (P4MOD0, P4MOD1) Address: 0F224H Access: R/W Access size: 8/16 bits Initial value: 00H 7 6 5 4 3 2 1 0 P4MOD0 P47MD0 P46MD0 P45MD0 P44MD0 P43MD0 P42MD0 P41MD0 P40MD0 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Address: 0F225H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 P4MOD1 P47MD1 P47MD1 P45MD1 P44MD1 P43MD1 P42MD1 P41MD1 P40MD1 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 P4MOD0 and P4MOD1 are special function registers (SFRs) to select the primary, secondary, or tertiary function of Port 4. [Description of Bits] • P47MD1, P47MD0 (bit 7) The P47MD1 and P47MD0 bits are used to select the primary or secondary function of the P47 pin. P47MD1 0 P47MD0 0 0 1 1 1 0 1 Description General-purpose input/output mode (initial value) Resistor sensor connection pin for measurement for RC-ADC (channel 1) PWM0 output pin Prohibited • P46MD1, P46MD0 (bit 6) The P46MD1 and P46MD0 bits are used to select the primary, secondary, or tertiary function of the P46 pin. P46MD1 0 0 1 1 P46MD0 0 1 0 1 Description General-purpose input/output mode (initial value) Reference resistor connection pin for RC-ADC (channel 1) SIO0 data output pin Prohibited • P45MD1, P45MD0 (bit 5) The P45MD1 and P45MD0 bits are used to select the primary, secondary, or tertiary function of the P45 pin. P45MD1 0 0 1 1 FEUL610Q438 P45MD0 0 1 0 1 Description General-purpose input/output mode (initial value) Reference capacitor connection pin for RC-ADC (channel 1) SIO0 clock input/output pin Prohibited 21-8 ML610Q438/ML610Q439 User’s Manual Chapter 21 Port 4 • P44MD1, P44MD0 (bit 4) The P44MD1 and P44MD0 bits are used to select the primary, secondary, or tertiary function of the P44 pin. P44MD1 0 0 1 1 P44MD0 0 1 0 1 Description General-purpose input/output mode (initial value) RC oscillation waveform input pin for RC-AD (channel 1) SIO0 data input pin Prohibited • P43MD1, P43MD0 (bit 3) The P43MD1 and P43MD0 bits are used to select the primary, secondary, or tertiary function of the P43 pin. P43MD1 0 0 1 1 P43MD0 0 1 0 1 Description General-purpose input/output mode (initial value) UART0 data output pin PWM0 output pin Prohibited • P42MD1, P42MD0 (bit 2) The P42MD1 and P42MD0 bits are used to select the primary, secondary, or tertiary function of the P42 pin. P42MD1 0 0 1 1 P42MD0 0 1 0 1 Description General-purpose input/output mode (initial value) UART0 input pin SIO0 data output pin Prohibited • P41MD1, P41MD0 (bit 1) The P41MD1 and P41MD0 bits are used to select the primary, secondary, or tertiary function of the P41 pin. P41MD1 0 0 1 1 P41MD0 0 1 0 1 Description General-purpose input/output mode (initial value) 2 I C bus 0 clock input/output pin SIO0 clock input/output pin Prohibited • P40MD1, P40MD0 (bit 0) The P40MD1 and P40MD0 bits are used to select the primary, secondary, or tertiary function of the P40 pin. P40MD1 0 0 1 1 P40MD0 0 1 0 1 Description General-purpose input/output mode (initial value) 2 I C bus 0 data input/output pin SIO0 data input pin Prohibited Note: If any bit combination out of the above is set to “Prohibited” and the corresponding bit of the port 4 is specified to output mode (selected in port4 control register), status of corresponding pin is fixed, regardless the contents of Port4 register (P4D) High-impedance output mode: High-impedance P-channel open drain output mode: High-impedance N-channel open drain output mode: Fixed to “L” CMOS output mode: High-impedance: Fixed to “L” FEUL610Q438 21-9 ML610Q438/ML610Q439 User’s Manual Chapter 21 Port 4 When using RC-ADC as the secondary function, specify each pin be “High-impedance input” even the RC oscillation monitor pin. Pull-up or Pull-down input makes drawing the current. FEUL610Q438 21-10 ML610Q438/ML610Q439 User’s Manual Chapter 21 Port 4 21.3 Description of Operation 21.3.1 Input/Output Port Functions For each pin of Port 4, either output or input is selected by setting the Port 4 direction register (P4DIR). In output mode, high-impedance output mode, P-channel open drain output mode, N-channel open drain output mode, or CMOS output mode can be selected by setting the Port 4 control registers 0 and 1 (P4CON0 and P4CON1). In input mode, high-impedance input mode, input mode with a pull-down resistor, or input mode with a pull-up resistor can be selected by setting the Port 4 control registers 0 and 1 (P4CON0 and P4CON1). At a system reset, high-impedance output mode is selected as the initial state. In output mode, “L” or “H” level is output to each pin of Port 4 depending on the value set by the Port 4 data register (P4D). In input mode, the input level of each pin of Port 4 can be read from the Port 4 data register (P4D). 21.3.2 Secondary and Tertiary Functions Secondary and tertiary functions are assigned to Port 4 as the I2C bus 0 pins (SDA, SCL), UART 0 pins (RXD0, TXD0), RC-ADC (channel 1) oscillation pins (IN1, CS1, RS1, RT1), synchronous serial port 0 pins (SIN0, SCK0, SOUT), PWM0 output pin (PWM0), and the PWM1 output pin (PWM1). These pins can be used in a secondary or tertiary function mode by setting the P47MD0 to P40MD0 bits and the P47MD1 to P40MD1 bits of the Port 4 mode registers (P4MOD0, P4MOD1). Note: The P44 to P47 pins of port 4 are configured as pins dedicated to the RC-ADC function during A/D conversion. Therefore, if there is any unused pin, that pin cannot be used during A/D conversion. For the RC-ADC, see Chapter 24, “RC Oscillation Type A/D Converter”. FEUL610Q438 21-11 Chapter 22 Port A ML610Q438/ML610Q439 User’s Manual Chapter 22 Port A 22. Port A 22.1 Overview Port A (PA0 to PA5) is an 6-bit input/output port. 22.1.1 Features • Allows selection of high-impedance output, P-channel open drain output, N-channel open drain output, or CMOS output for each bit in output mode. • Allows selection of high-impedance input, input with a pull-down resistor, or input with a pull-up resistor for each bit in input mode. 22.1.2 Configuration Figure 22-1 shows the configuration of Port A. VDD Data bus Pull-up Pull-down Controller VDD PADIR PACON0, 1 VSS VDD PA0 to PA5 Port A Output Controller 6 PAD 6 VSS VSS PAD PADIR PACON0 PACON1 : Port A data register : Port A direction register : Port A control register 0 : Port A control register 1 Figure 22-1 Configuration of Port A 22.1.3 List of Pins Pin name PA0 PA1 PA2 PA3 PA4 PA5 FEUL610Q438 I/O I/O I/O I/O I/O I/O I/O Description Input/output port Input/output port Input/output port Input/output port Input/output port Input/output port 22-1 ML610Q438/ML610Q439 User’s Manual Chapter 22 Port A 22.2 Description of Registers 22.2.1 List of Registers Address 0F250H 0F251H 0F252H 0F253H FEUL610Q438 Name Port A data register Port A direction register Port A control register 0 Port A control register 1 Symbol (Byte) PAD PADIR PACON0 PACON1 Symbol (Word)   PACON R/W R/W R/W R/W R/W Size 8 8 8/16 8 Initial value 00H 00H 00H 00H 22-2 ML610Q438/ML610Q439 User’s Manual Chapter 22 Port A 22.2.2 Port A Data Register (PAD) Address: 0F250H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 PAD   PA5D PA4D PA3D PA2D PA1D PA0D R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 PAD is a special function register (SFR) to set the value to be output to the Port A pin or to read the input level of the Port A. In output mode, the value of this register is output to the Port 4 pin. The value written to PAD is readable. In input mode, the input level of the Port A pin is read when PAD is read. Output mode or input mode is selected by using the port mode register (PADIR) described later. [Description of Bits] • PA5D-PA0D (bits 5-0) The PA5D to PA0D bits are used to set the output value of the Port A pin in output mode and to read the pin level of the Port A pin in input mode. PA5D 0 1 Description Output or input level of the PA5 pin: ”L” Output or input level of the PA5 pin: ”H” PA4D 0 1 Description Output or input level of the PA4 pin: ”L” Output or input level of the PA4 pin: ”H” PA3D 0 1 Description Output or input level of the PA3 pin: ”L” Output or input level of the PA3 pin: ”H” PA2D 0 1 Description Output or input level of the PA2 pin: ”L” Output or input level of the PA2 pin: ”H” PA1D 0 1 Description Output or input level of the PA1 pin: ”L” Output or input level of the PA1 pin: ”H” PA0D 0 1 Description Output or input level of the PA0 pin: ”L” Output or input level of the PA0 pin: ”H” FEUL610Q438 22-3 ML610Q438/ML610Q439 User’s Manual Chapter 22 Port A 22.2.3 Port A Direction Register (PADIR) Address: 0F251H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 PADIR   PA5DIR PA4DIR PA3DIR PA2DIR PA1DIR PA0DIR R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 PADIR is a special function register (SFR) to select the input/output mode of Port A. [Description of Bits] • PA5DIR-PA0DIR (bits 5-0) The PA5DIR to PA0DIR pins are used to set the input/output direction of the Port A pin. PA5DIR 0 1 Description PA5 pin: Output (initial value) PA5 pin: Input PA4DIR 0 1 Description PA4 pin: Output (initial value) PA4 pin: Input PA3DIR 0 1 Description PA3 pin: Output (initial value) PA3 pin: Input PA2DIR 0 1 Description PA2 pin: Output (initial value) PA2 pin: Input PA1DIR 0 1 Description PA1 pin: Output (initial value) PA1 pin: Input PA0DIR 0 1 Description PA0 pin: Output (initial value) PA0 pin: Input FEUL610Q438 22-4 ML610Q438/ML610Q439 User’s Manual Chapter 22 Port A 22.2.4 Port A Control Registers 0, 1 (PACON0, PACON1) Address: 0F252H Access: R/W Access size: 8/16 bits Initial value: 00H 7 6 5 4 3 2 1 0 PACON0   PA5C0 PA4C0 PA3C0 PA2C0 PA1C0 PA0C0 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Address: 0F253H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 PACON1   PA5C1 PA4C1 PA3C1 PA2C1 PA1C1 PA0C1 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 PACON0 and PACON1 are special function registers (SFRs) to select input/output state of the Port A pin. The input/output state is different between input mode and output mode. Input or output is selected by using the PADIR register. [Description of Bits] • PA5C1-PA0C1, PA5C0-PA0C0 (bits 5-0) The PA5C1 to PA0C1 pins and the PA5C0 to PA0C0 pins are used to select high-impedance output, P-channel open drain output, N-channel open drain output, or CMOS output in output mode and to select high-impedance input, input with a pull-down resistor, or input with a pull-up resistor in input mode. Setting of PA5 pin PA5C1 0 0 1 1 PA5C0 0 1 0 1 Setting of PA4 pin PA4C1 0 0 1 1 PA4C0 0 1 0 1 Setting of PA3 pin PA3C1 0 0 1 1 FEUL610Q438 PA3C0 0 1 0 1 When output mode is selected (PA5DIR bit = “0”) When input mode is selected (PA5DIR bit = “1”) Description High-impedance output (initial value) High-impedance input P-channel open drain output Input with a pull-down resistor N-channel open drain output Input with a pull-up resistor CMOS output High-impedance input When output mode is selected (PA4DIR bit = “0”) When input mode is selected (PA4DIR bit = “1”) Description High-impedance output (initial value) High-impedance input P-channel open drain output Input with a pull-down resistor N-channel open drain output Input with a pull-up resistor CMOS output High-impedance input When output mode is selected (PA3DIR bit = “0”) When input mode is selected (PA3DIR bit = “1”) Description High-impedance output (initial value) High-impedance input P-channel open drain output Input with a pull-down resistor N-channel open drain output Input with a pull-up resistor CMOS output High-impedance input 22-5 ML610Q438/ML610Q439 User’s Manual Chapter 22 Port A Setting of PA2 pin PA2C1 0 0 1 1 PA2C0 0 1 0 1 Setting of PA1 pin PA1C1 0 0 1 1 PA1C0 0 1 0 1 Setting of PA0 pin PA0C1 0 0 1 1 FEUL610Q438 PA0C0 0 1 0 1 When output mode is selected (PA2DIR bit = “0”) When input mode is selected (PA2DIR bit = “1”) Description High-impedance output (initial value) High-impedance input P-channel open drain output Input with a pull-down resistor N-channel open drain output Input with a pull-up resistor CMOS output High-impedance input When output mode is selected (PA1DIR bit = “0”) When input mode is selected (PA1DIR bit = “1”) Description High-impedance output (initial value) High-impedance input P-channel open drain output Input with a pull-down resistor N-channel open drain output Input with a pull-up resistor CMOS output High-impedance input When output mode is selected (PA0DIR bit = “0”) When input mode is selected (PA0DIR bit = “1”) Description High-impedance output (initial value) High-impedance input P-channel open drain output Input with a pull-down resistor N-channel open drain output Input with a pull-up resistor CMOS output High-impedance input 22-6 ML610Q438/ML610Q439 User’s Manual Chapter 22 Port A 22.3Description of Operation 22.3.1Input/Output Port Functions For each pin of Port A, either output or input is selected by setting the Port A direction register (PADIR). In output mode, high-impedance output mode, P-channel open drain output mode, N-channel open drain output mode, or CMOS output mode can be selected by setting the Port A control registers 0 and 1 (PACON0 and PACON1). In input mode, high-impedance input mode, input mode with a pull-down resistor, or input mode with a pull-up resistor can be selected by setting the Port A control registers 0 and 1 (PACON0 and PACON1). At system reset, high-impedance output mode is selected as the initial state. In output mode, “L” or “H” level is output to each pin of Port A depending on the value set by the Port A data register (PAD). In input mode, the input level of each pin of Port A can be read from the Port A data register (PAD). FEUL610Q438 22-7 Chapter 23 Melody Driver ML610Q438/ML610Q439 User’s Manual Chapter 23 Melody Driver 23. Melody Driver 23.1 Overview This LSI includes one channel of the melody driver. To use the melody driver, the secondary function of port 2 should be set. For the secondary function of port 2, see Chapter 19, "Port 2". For the clock to be used in this melody driver, see Chapter 6, "Clock Generation Circuit". 23.1.1 Features • In melody output mode, 29 scales (melody audio frequency: 508Hz to 32.768kHz), 63 tone lengths, and 15 tempos) are available. • In buzzer output mode, 4 output modes, 8 frequencies, and 15 duties can be set. 23.1.2 Configuration Figure 23-1 shows the configuration of the melody driver. LSCLK×2 MD0INT Melody interrupt Tempo generation circuit/ Buzzer mode select circuit Control circuit MD0CON Tempo code MD0TMP Tone length generation circuit/ Duty select circuit Tone generation circuit/ Buzzer output circuit Tone length buffer Tone buffer Tone length code MD0LEN Scale code MD0TON P22/MD0 Data bus MD0CON MD0TMP MD0TON MD0LEN : Melody 0 control register : Melody 0 tempo code register : Melody 0 scale code register : Melody 0 tone length code register Figure 23-1 Configuration of Melody Driver 23.1.3 List of Pins Pin name I/O P22/MD0 O FEUL610Q438 Description Melody 0 signal output pin Used as the secondary of the P22 pin. 23-1 ML610Q438/ML610Q439 User’s Manual Chapter 23 Melody Driver 23.2 Description of Registers 23.2.1 List of Registers Address 0F2C0H 0F2C1H 0F2C2H 0F2C3H Name Melody 0 control register Melody 0 tempo code register Melody 0 scale code register Melody 0 tone length code register FEUL610Q438 Symbol (Byte) Symbol (Word) R/W Size Initial value MD0CON MD0TMP MD0TON MD0LEN   R/W R/W R/W R/W 8 8 8/16 8 00H 00H 00H 00H MD0TL 23-2 ML610Q438/ML610Q439 User’s Manual Chapter 23 Melody Driver 23.2.2 Melody 0 Control Register (MD0CON) Address: 0F2C0H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 MD0CON       BZMD M0RUN R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 MD0CON is a special function register (SFR) to control a melody and the buzzer. [Description of Bits] • BZMD (bit 1) The BZMD bit is used to select melody mode or buzzer mode. BZMD 0 1 Description Melody mode (initial value) Buzzer mode • M0RUN (bit 0) The M0RUN bit is used to control start/stop of the MD0 output. M0RUN 0 1 Description Stops MD0 output. (Initial value) Starts MD0 output. Note: For melody output, use the 2×low-speed clock (LSCLK×2). Enable the 2×low-speed clock by setting bit 2 (ENMLT) of frequency control register 1 (FCON1) to “1” and then start melody output by setting M0RUN to “1”. FEUL610Q438 23-3 ML610Q438/ML610Q439 User’s Manual Chapter 23 Melody Driver 23.2.3 Melody 0 Tempo Code Register (MD0TMP) Address: 0F2C1H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 MD0TMP     M0TM3 M0TM2 M0TM1 M0TM0 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 MD0TMP is a special function register (SFR) to set the tempo code of a melody when melody mode is selected and the output mode of a buzzer sound waveform when buzzer mode is selected. [Description of Bits] • M0TM3, M0TM2, M0TM1, M0TM0 (bits 3-0) M0TM3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 M0TM2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 When melody mode is selected (BZMD bit = “0”) M0TM1 M0TM0 Description 0 0 ♪ = 480 (initial value) 0 1 ♪ = 480 1 0 ♪ = 320 1 1 ♪ = 240 0 0 ♪ = 192 0 1 ♪ = 160 1 0 ♪ ≅ 137 1 1 ♪ = 120 0 0 ♪ ≅ 107 0 1 ♪ = 96 1 0 ♪ ≅ 87 1 1 ♪ = 80 0 0 ♪ ≅ 74 0 1 ♪ ≅ 69 1 0 ♪ = 64 1 1 ♪ = 60 M0TM3 * * * * M0TM2 * * * * When buzzer mode is selected (BZMD bit = “1”) M0TM1 M0TM0 Description 0 0 Intermittent 1 output (initial value) 0 1 Intermittent 2 output 1 0 Single sound output 1 1 Continuous sound output FEUL610Q438 23-4 ML610Q438/ML610Q439 User’s Manual Chapter 23 Melody Driver 23.2.4 Melody 0 Scale Code Register (MD0TON) Address: 0F2C2H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 MD0TON  M0TN6 M0TN5 M0TN4 M0TN3 M0TN2 M0TN1 M0TN0 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 MD0TON is a special function register (SFR) to set the scale code of a melody when melody mode is selected and a buzzer output frequency when buzzer mode is selected. [Description of Bits] • M0TN6, M0TN5, M0TN4, M0TN3, M0TN2, M0TN1, M0TN0 (bits 6-0) When melody mode is selected (BZMD bit = “0”) Description M0TN6 to 0 Sets the corresponding scale code. For scale codes, see Section 23.3.4, "Scale Codes". M0TN6 to 3 * * * * * * * * M0TN2 0 0 0 0 1 1 1 1 When buzzer mode is selected (BZMD bit = “1”) M0TN1 M0TN0 Description 0 0 4.096 kHz (initial value) 0 1 2.048 kHz 1 0 1.365 kHz 1 1 1.024 kHz 0 0 819 Hz 0 1 683 Hz 1 0 585 Hz 1 1 512 Hz Note: In buzzer mode, the M0TN6 to M0TN3 bits are not used.(Don't care) FEUL610Q438 23-5 ML610Q438/ML610Q439 User’s Manual Chapter 23 Melody Driver 23.2.5 Melody 0 Tone Length Code Register (MD0LEN) Address: 0F2C3H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 MD0LEN   M0LN5 M0LN4 M0LN3 M0LN2 M0LN1 M0LN0 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 MD0LEN is a special function register (SFR) to set the tone length code of a melody when melody mode is selected and buzzer output duty when buzzer mode is selected. [Description of Bits] • M0LN5, M0LN4, M0LN3, M0LN2, M0LN1, M0LN0 (bits 5-0) When melody mode is selected (BZMD bit = “0”) Description M0LN5 to 0 Sets the corresponding tone length code. For tone length codes, see Section 23.3.3, "Tone Length Codes". M0LN5 to 4 * * * * * * * * * * * * * * * * M0LN3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 When buzzer mode is selected (BZMD bit = “1”) M0LN2 M0LN1 M0LN0 Description 0 0 0 1/16 DUTY (initial value) 0 0 1 1/16 DUTY 0 1 0 2/16 DUTY 0 1 1 3/16 DUTY 1 0 0 4/16 DUTY 1 0 1 5/16 DUTY 1 1 0 6/16 DUTY 1 1 1 7/16 DUTY 0 0 0 8/16 DUTY 0 0 1 9/16 DUTY 0 1 0 10/16 DUTY 0 1 1 11/16 DUTY 1 0 0 12/16 DUTY 1 0 1 13/16 DUTY 1 1 0 14/16 DUTY 1 1 1 15/16 DUTY Note: In buzzer mode, the M0LN5 to M0LN4 bits are not used.(Don't care) FEUL610Q438 23-6 ML610Q438/ML610Q439 User’s Manual Chapter 23 Melody Driver 23.3 Description of Operation 23.3.1 Operation of Melody Output Melody is output in the following procedure. (1) (2) (3) (4) (5) (6) Select melody mode by setting the BZMD bit of the melody 0 control register (MD0CON) to “0”. Set a melody tempo in the melody 0 tempo code register (MD0TMP). Set a tone length code in the melody 0 tone length code register (MD0LEN). Set a scale code in the melody 0 scale code register (MD0TON). Set bit 2 (ENMLT) of the frequency control register 1(FCON1) to “1” to enable the 2×low-speed clock. When the M0RUN bit of the melody 0 control register (MD0CON) is set to “1”, the tone length code and scale code are transferred to the tone length buffer and scale buffer and melody output is started from the MD0 pin. At the same time, a melody 0 interrupt (MD0INT) is requested. When an interrupt occurs and program is passed to the interrupt routine, the interrupt request flag is cleared. The melody 0 signal output pin (MD0) is assigned as the secondary function of Port 2. See Chapter 19, “Port 2,” for the secondary function settings of Port 2. In the software processing after melody 0 interrupt, the tone length code and the scale code of the note that are output next are set to MD0LEN and MD0TON, respectively. When there is no next note to be output, rest data “00H” is set in MD0TON, the M0RUN bit is set to “0” by the software processing after the next melody 0 interrupt, and melody output is terminated. By setting the M0RUN bit to “0”, melody can be terminated forcibly during melody output. Figure 23-2 shows the operation waveform of the melody driver. M0RUN MD0INT MD0LEN MD0TON Tone length/Tone buffer 1st sound XX XX Melody output waveform MD0* 1st sound 1st sound waveform Figure 23-2 FEUL610Q438 2nd sound 3rd sound 2nd sound 3rd sound 2nd sound waveform 3rd sound waveform Final sound Rest data Final sound Rest data Final sound waveform Operation Waveform of Melody Driver 23-7 ML610Q438/ML610Q439 User’s Manual Chapter 23 Melody Driver 23.3.2 Tempo Codes A tempo code is set in the melody 0 tempo code register (MD0TEM). Table 23-1 shows the correspondence between tempos and tempo codes. The tempo when all the bits are set to "0" is equal to the shortest tone length (the tempo when the only M0TP0 bit is set to "1"). Table 23-1 Correspondence between Tempos and Tempo Codes Tempo FEUL610Q438 M0TP3 Tempo code (MD0TMP) M0TP2 M0TP1 M0TP0 M0TP3 to 0 = 480 0 0 0 0 0H = 480 0 0 0 1 1H = 320 0 0 1 0 2H = 240 0 0 1 1 3H = 192 0 1 0 0 4H = 160 0 1 0 1 5H ≅ 137 0 1 1 0 6H = 120 0 1 1 1 7H ≅ 107 1 0 0 0 8H = 96 1 0 0 1 9H ≅ 87 1 0 1 0 AH = 80 1 0 1 1 BH ≅ 74 1 1 0 0 CH ≅ 69 1 1 0 1 DH = 64 1 1 1 0 EH = 60 1 1 1 1 FH 23-8 ML610Q438/ML610Q439 User’s Manual Chapter 23 Melody Driver 23.3.3 Tone Length Codes A tone length code is set in the melody 0 tone length code register (MD0LEN). Table 23-2 shows the correspondence between tone lengths and tone length codes. The tone length when all the bits are set to "0" is equal to the shortest tone length (the tone length when the only M0LN0 bit is set to "1"). Table 23-2 Tone length Correspondence between Tone Lengths and Tone Length Codes Tone length code (MD0LEN) M0LN3 M0LN2 M0LN1 M0LN1 M0LN5 M0LN4 M0LN5–0 1 1 1 1 1 1 3FH 1 0 1 1 1 1 2FH 0 1 1 1 1 1 1FH 0 1 0 1 1 1 17H 0 0 1 1 1 1 0FH 0 0 1 0 1 1 0BH 0 0 0 1 1 1 07H 0 0 0 1 0 1 05H 0 0 0 0 1 1 03H 0 0 0 0 1 0 02H 0 0 0 0 0 1 01H The tone length set by a tone length code and a tempo code is expressed by the following equation. Tone length = 1.953125 × ( TP + 1 ) × ( LN + 1 ) ms where TP is an integer of 1 to 15, and LN is an integer of 1 to 63. The bit correspondence between TP and tempo codes is expressed by the following equation. TP = 23M0TP3 + 22M0TP2 + 21M0TP1 + 20M0TP0 The bit correspondence between LN and tone length codes is expressed by the following equation. LN = 25M0LN5 + 24M0LN4 + 23M0LN3 + 22M0LN2 + 21M0LN1 + 20M0LN0 FEUL610Q438 23-9 ML610Q438/ML610Q439 User’s Manual Chapter 23 Melody Driver 23.3.4 Scale Codes A scale code is set in the melody 0 scale code register (MD0TON). In the melody driver, a frequency that can be output is expressed by the following equation. 65536 ( TN + 1 ) Hz (where TN is an integer of 4 to 127.) The bit correspondence between TN and scale codes is expressed by the following equation. TN = 26M0TN6 + 25M0TN5 + 24M0TN4 + 23M0TN3 + 22M0TN2 + 21M0TN1 + 20M0TN0 Table 23-3 shows the correspondence between scales and scale codes. When the M0TN6 to M0TN2 bits are set to "0", scale becomes a rest. The rest length is set by the tone length code (MD0LEN). Table 23-3 Scale 1 C Cis 1 1 D Dis 1 M0TN6 M0TN5 M0TN4 M0TN3 M0TN2 M0TN1 M0TN0 M0TN6–0 529 1 1 1 1 0 1 1 7BH 560 1 1 1 0 1 0 0 74H 590 1 1 0 1 1 1 0 6EH 624 1 1 0 1 0 0 0 68H 662 1 1 0 0 0 1 0 62H 1 705 1 0 1 1 1 0 0 5CH 745 1 0 1 0 1 1 1 57H 790 1 0 1 0 0 1 0 52H 840 1 0 0 1 1 0 1 4DH 886 1 0 0 1 0 0 1 49H 936 1 0 0 0 1 0 1 45H 993 1 0 0 0 0 0 1 41H 1057 0 1 1 1 1 0 1 3DH Fis 1 1 G Gis 1 1 A Ais 1 1 B 2 C Cis 2 2 D Dis 2 1111 0 1 1 1 0 1 0 3AH 1192 0 1 1 0 1 1 0 36H 1260 0 1 1 0 0 1 1 33H 2 1338 0 1 1 0 0 0 0 30H 2 1394 0 1 0 1 1 1 0 2EH 1490 0 1 0 1 0 1 1 2BH 1560 0 1 0 1 0 0 1 29H 1680 0 1 0 0 1 1 0 26H 1771 0 1 0 0 1 0 0 24H E F Scale code (MD0TON) Frequency (Hz) 1 E F Correspondence between Scales and Scale Codes Fis 2 2 G Gis 2 2 A Ais 2 1872 0 1 0 0 0 1 0 22H 2 1986 0 1 0 0 0 0 0 20H 3 2114 0 0 1 1 1 1 0 1EH 3 B C D 2341 0 0 1 1 0 1 1 1BH 3 2521 0 0 1 1 0 0 1 19H 2621 0 0 1 1 0 0 0 18H 3 2979 0 0 1 0 1 0 1 15H Dis 3 E Fis FEUL610Q438 23-10 ML610Q438/ML610Q439 User’s Manual Chapter 23 Melody Driver 23.3.5 Example of Using Melody Circuit Figure 23-3 shows an example of a melody notation, and Table 23-4 shows note codes of melody examples. = 120 4 4 Figure 23-3 Table 23-4 Example of Melody Notation Note Codes of Melody Examples Note code Note 5 4 2 1 0 1 2 0 0 G 2 0  MD0TON 3 2 1 0 6 5 4 1 1 1 0 1 0 1 1 1 1 1 0 1 1 0 1 1 1 1 0 1 0 0 0 1 1 1 0 2 0 0 0 1 1 1 G 2 0 0 1 1 1  0 0 0 1 2 0 0 0 2 1 1 2 1 1 G D D A B G FEUL610Q438 MD0LEN 3 2 hexadecimal 1 0 0 0 0 2F28H 0 1 0 1 0F35H 0 1 0 0 0 0F28H 0 0 0 0 0 0 0700H 0 1 1 0 1 0 1 0735H 1 0 1 0 1 0 0 0 0F28H 1 1 0 0 0 0 0 0 0 0700H 1 1 1 0 1 0 0 0 1 1 0723H 1 1 1 1 0 0 1 1 1 1 1 3F1FH 1 1 1 1 0 1 0 1 0 0 0 3F28H 23-11 ML610Q438/ML610Q439 User’s Manual Chapter 23 Melody Driver 23.3.6 Operations of Buzzer Output A buzzer sound is output in the following procedure. (1) Select a buzzer mode by setting the BZMD bit of the melody 0 control register (MD0CON) to “1”. (2) Select a buzzer output mode using the melody 0 tempo code register (MD0TMP). (3) Select a duty of the High level width of the buzzer output waveform using the melody 0 tone length code register (MD0LEN). (4) Set the buzzer output frequency in the melody 0 scale code register (MD0TON). (5) Set bit 2 (ENMLT) of the frequency control register 1(FCON1) to “1” to enable the 2×low-speed clock. (6) When the M0RUN bit of the melody 0 control register (MD0CON) is set to “1”, the waveform equivalent to the buzzer sound that is set from the MD0 pin is output. Figure 23-4 shows the output waveform of each buzzer output mode. MD0CON.M0RUN T8HZ Buzzer output waveform MD0* (1/4) Output waveform of intermittent sound 1 MD0CON.M0RUN T8HZ T1HZ Buzzer output waveform MD0* (2/4) Output waveform of intermittent sound 2 MD0CON.M0RUN T8HZ Buzzer output waveform MD0* (3/4) Output waveform of single sound MD0CON.M0RUN Buzzer output waveform MD0* (4/4) Output waveform of continuous sound Figure 23-4 FEUL610Q438 Output Waveform of Each Buzzer Output Mode 23-12 ML610Q438/ML610Q439 User’s Manual Chapter 23 Melody Driver 23.4 Specifying port registers When you want to make sure the Melody/Buzzer function is working, please check related port registers are specified. See Chapter 19, “Port 2” for detail about the port registers. 23.4.1 Functioning P22 (MD0) as the Melody or Buzzer output Set P22MD bit (bit0 of P2MOD register) to “1” for specifying the melody or buzzer output as the secondary function of P22. Reg. name P2MOD register (Address: 0F214H) Bit 7 6 5 4 3 2 1 0 Bit name - - - - - P22MD P21MD P20MD Data - - - - - 1 * * Set P22C1 bit (bit０ of P2CON1 register) to “1” and set P22C0 bit(bit０ of P2CON0 register) to “1”, for specifying the P22 as CMOS output. Reg. name P2CON1 register (Address: 0F213H) Bit 7 6 5 4 3 2 1 0 Bit name - - - - - P22C1 P21C1 P20C1 Data - - - - - 1 * * Reg. name P2CON0 register (Address: 0F212H) Bit 7 6 5 4 3 2 1 0 Bit name - - - - - P22C0 P21C0 P20C0 Data - - - - - 1 * * Data of P２０D bit (bit０ of P2D register) does not affect to the melody or buzzer function, so don’t care the data for the function. Reg. name P2D register (Address: 0F210H) Bit 7 6 5 4 3 2 1 0 Bit name - - - - - P22D P21D P20D Data - - - - - ** * * - : Bit does not exist. * : Bit not related to the melody or buzzer function ** : Don’t care the data. Note: - P20(Port2) is an output-only port, does not have an register to select the data direction(input or output). - The output characteristics of port22 corresponds to VOL1 and VOH1 when P22MD bit is “1” (melody/buzzer nd is selected as the 2 function), and corresponds to VOL2 and VOH2 when the P22MD bit is “0”, which are shown in Appendix C, "Electrical Characteristics". FEUL610Q438 23-13 Chapter 24 RC Oscillation Type A/D Converter ML610Q438/ML610Q439 User’s Manual Chapter 24 RC Oscillation Type A/D Converter 24. RC Oscillation Type A/D Converter 24.1 Overview This LSI has a built-in 2-channel RC oscillation type A/D converter (RC-ADC). The RC-ADC converts resistance values or capacitance values to digital values by counting the oscillator clock whose frequency changes according to the resistor or capacitor connected to the RC oscillator circuits. By using a thermistor or humidity sensor as a resistor, a thermometer or hygrometer can be formed. In addition, a different sensor for each of the two channels of RC-ADC’s RC oscillator circuit can be used to broaden RC-ADC applications; for example, the conveter can be used for expansion of measurement range or measurement at two points. For input clock, see Chapter 6, “Clock Generation Circuit.” 24.1.1 Features • 2-channel system by time division 24.1.2 Configuration The RC-ADC consists of two RC oscillator circuits to form two channels, Counter A (RADCA0–2) and Counter B (RADCB0–2) as 24-bit binary counters, and an RC-ADC control circuit (RADCON, RADMOD). Figure 24-1 shows the configuration of the RC-ADC. LSCLK LSCLK×2 HSCLK Clock control circuit BSCLK 24-bit binary counter OVFA Interrupt control RADINT Counter A (RADCA0–2) P35/RCM RCCLK P34/RCT0 P33/RT0 P32/RS0 P31/CS0 P30/IN0 CR oscillation (RCOSC0) P47/RT1 P46/RS1 P45/CS1 P44/IN1 RC oscillation (RCOSC1) 24-bit binary counter OVFB Counter B (RADCB0–2) RC-ADC control circuit (RADCON) (RADMOD) Data bus RADMOD: RADCON: RADCA0–2: RADCB0–2: RC-ADC mode register RC-ADC control register RC-ADC Counter A registers 0–2 RC-ADC Counter B registers 0–2 Figure 24-1 FEUL610Q438 Configuration of RC-ADC 24-1 ML610Q438/ML610Q439 User’s Manual Chapter 24 RC Oscillation Type A/D Converter 24.1.3 List of Pins Pin name I/O P30/IN0 I P31/CS0 O P32/RS0 O P33/RT0 O P34/RCT0 O P35/RCM O P44/IN1 I P45/CS1 O P46/RS1 O P47/RT1 O FEUL610Q438 Description Channel 0 oscillation input pin. Used for the secondary function of the P30 pin. Channel 0 reference capacitor connection pin. Used for the secondary function of the P31 pin. Channel 0 reference resistor connection pin. Used for the secondary function of the P32 pin. Pin for connection with a resistive sensor for measurement on Channel 0. Used for the secondary function of the P33 pin. Pin for connection with a resistive/capacitive sensor for measurement on Channel 0. Used for the secondary function of the P34 pin. RC oscillation monitor pin. Used for the secondary function of the P35 pin. Channel 1 oscillation input pin. Used for the secondary function of the P44 pin. Channel 1 reference capacitor connection pin. Used for the secondary function of the P45 pin. Channel 1 reference resistor connection pin. Used for the secondary function of the P46 pin. Pin for connection with a resistive sensor for measurement on Channel 1. Used for the secondary function of the P47 pin. 24-2 ML610Q438/ML610Q439 User’s Manual Chapter 24 RC Oscillation Type A/D Converter 24.2 Description of Registers 24.2.1 List of Registers Address 0F300H 0F301H 0F302H 0F304H 0F305H 0F306H 0F308H 0F309H Name RC-ADC Counter A register 0 RC-ADC Counter A register 1 RC-ADC Counter A register 2 RC-ADC Counter B register 0 RC-ADC Counter B register 1 RC-ADC Counter B register 2 RC-ADC mode register RC-ADC control register FEUL610Q438 Symbol (Byte) Symbol (Word) RADCA0 RADCA1 RADCA2 RADCB0 RADCB1 RADCB2 RADMOD RADCON — — — — — — — — R/W Size Initial value R/W R/W R/W R/W R/W R/W R/W R/W 8 8 8 8 8 8 8 8 00H 00H 00H 00H 00H 00H 00H 00H 24-3 ML610Q438/ML610Q439 User’s Manual Chapter 24 RC Oscillation Type A/D Converter 24.2.2 RC-ADC Counter A Registers (RADCA0–2) Address: 0F300H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 RADCA0 RAA7 RAA6 RAA5 RAA4 RAA3 RAA2 RAA1 RAA0 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 RADCA1 RAA15 RAA14 RAA13 RAA12 RAA11 RAA10 RAA9 RAA8 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 RADCA2 RAA23 RAA22 RAA21 RAA20 RAA19 RAA18 RAA17 RAA16 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Address: 0F301H Access: R/W Access size: 8 bits Initial value: 00H Address: 0F302H Access: R/W Access size: 8 bits Initial value: 00H RADCA0–2, which serve as a 24-bit binary counter (Counter A), are special function registers (SFRs) used to perform read/write operations to Counter A itself. Note: After writing data into the RC-ADC counter A register, be sure to read it to check that the data has been written correctly. When A/D conversion starts after data is written, the value that has been written is read during A/D conversion (RARUN = 1). When A/D conversion terminates (RARUN = 0), the count value is read. FEUL610Q438 24-4 ML610Q438/ML610Q439 User’s Manual Chapter 24 RC Oscillation Type A/D Converter 24.2.3 RC-ADC Counter B Registers (RADCB0–2) Address:0F304H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 RADCB0 RAB7 RAB6 RAB5 RAB4 RAB3 RAB2 RAB1 RAB0 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Address:0F305H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 RADCB1 RAB15 RAB14 RAB13 RAB12 RAB11 RAB10 RAB9 RAB8 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 RADCB2 RAB23 RAB22 RAB21 RAB20 RAB19 RAB18 RAB17 RAB16 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Address:0F306H Access: R/W Access size: 8 bits Initial value: 00H RADCB0–2, which serve as a 24-bit binary counter (Counter B), are special function registers (SFRs) used to perform read/write operations to Counter B itself. Note: After writing data into the RC-ADC counter B register, be sure to read it to check that the data has been written correctly. When A/D conversion starts after data is written, the value that has been written is read during A/D conversion (RARUN = 1). When A/D conversion terminates (RARUN = 0), the count value is read. FEUL610Q438 24-5 ML610Q438/ML610Q439 User’s Manual Chapter 24 RC Oscillation Type A/D Converter 24.2.4 RC-ADC Mode Register (RADMOD) Address: 0F308H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 RADMOD RACK2 RACK1 RACK0 RADI OM3 OM2 OM1 OM0 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RADMOD is a special function register (SFR) used to select an A/D conversion mode of the RC-ADC. [Description of Bits] • OM3-0 (bits 3-0) The OM3–0 bits are used to select an oscillation mode for the RC oscillator circuits. OM3 0 0 0 0 0 0 0 0 1 OM2 0 0 0 0 1 1 1 1 * OM1 0 0 1 1 0 0 1 1 * OM0 0 1 0 1 0 1 0 1 * Description IN0 pin external clock input mode (initial value) RS0–CS0 oscillation mode RT0–CS0 oscillation mode RT0-1–CS0 oscillation mode RS0–CT0 oscillation mode RS1–CS1 oscillation mode RT1–CS1 oscillation mode IN1 pin external clock input mode Setting prohibited • RADI (bit 4) The RADI bit is used to choose whether to generate the RC-ADC interrupt request signal (RADINT) by an overflow at Counter A or Counter B. RADI 0 1 Description Generates an interrupt request by Counter A overflow (initial value). Generates an interrupt request by Counter B overflow. • RACK2-0 (bits 7-5) The RACK2–0 bits are used to select the base clock of Conter A (BSCLK). RACK2 0 0 0 0 1 1 1 RACK1 0 0 1 1 0 0 1 RACK0 0 1 0 1 0 1 * Description LSCLK (initial value) LSCLK×2 HSCLK 1/2HSCLK 1/4HSCLK 1/8HSCLK Setting prohibited (no clock is supplied) Note: When specifying LSCLK×2 for the base clock, enable the operation of the 2×low-speed clock by setting bit 2 (ENMLT) of the frequency control register 1 (FCON1) to “1”. FEUL610Q438 24-6 ML610Q438/ML610Q439 User’s Manual Chapter 24 RC Oscillation Type A/D Converter 24.2.5 RC-ADC Control Register (RADCON) Address: 0F309H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 RADCON — — — — — — — RARUN R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RADCON is a special function register (SFR) used to control A/D conversion operation of the RC-ADC. [Description of Bits] • RARUN (bit 0) The RARUN bit is used to start A/D conversion of the RC-ADC. When RARUN is set to “1”, A/D conversion starts. If Counter A or Counter B overflows with RARUN set to “1”, the bit is automatically reset to “0”. RARUN is set to “0” at system reset. RARUN 0 1 Description Stops A/D conversion (initial value). Starts A/D conversion. Note: When A/D conversion is stopped by resetting the RARUN to “0”, the RC-ADC does not perform properly without the following procedures. 1) Set the "DRAD" bit of the Block Control Register 4 (BLKCON4) to "1" , in order to disable the RC-ADC. 2) Reset the "DRAD" bit of the Block Control Register 4 (BLKCON4) to "0" , in order to enable the RC-ADC. 3) Set up the RC-ADC again by following the required procedures, then restart. FEUL610Q438 24-7 ML610Q438/ML610Q439 User’s Manual Chapter 24 RC Oscillation Type A/D Converter 24.3 Description of Operation Counter A (RADCA0–2) is a 24-bit binary counter for counting the base clock (BSCLK), which is used as the standard of time. Counter A can count up to 0FFFFFFH. Counter B (RADCB0–2) is a 24-bit binary counter for counting the oscillator clock (RCCLK) of the RC oscillator circuits. Counter B can count up to 0FFFFFFH. Counters A and B are provided with overflow flags (OVFA and OVFB, respectively). Each overflow output results in generation of an RC-ADC interrupt request signal (RADINT). Use the RADI bit of the RC-AC mode register (RADMOD) to select whether to generate an overflow interrupt by an overflow on Counter A or Counter B: setting RADI to “0” specifies Counter A overflow and setting it to “1” specifies Counter B overflow. The RARUN bit of the RC-AD control register (RADCON) is used to start or stop RC-ADC conversion operation. When RARUN is set to “0”, the oscillator circuits stop, so that counting will not be performed. When RARUN is set to “1”, RC oscillation starts, when the RC oscillator clock (RCCLK) and the base clock (BSCLK) start counting through Counter B and Counter A. The RC oscillation section has a total of eight types of oscillation modes based on the two oscillator circuits of RCOSC0 and RCOSC1, and mode selection is made by the RC-ADC mode register (RADMOD). P30–34, P44–47, and P35 must be configured as their secondary function input or output when using 1) the RC oscillator circuit RCOSC0, 2) the RC oscillator circuit RCOSC1, and 3) the RC monitor pin (RCM) that outputs RC oscillation waveforms, respectively. For the configuration of the RC oscillator circuits, see Section 24.1.2, “Configuration”; for the secondary functions of Port 3, see Chapter 20, “Port 3”; for the secondary functions of Port 4, see Chapter 21, “Port 4”. 24.3.1 RC Oscillator Circuits RC-ADC performs A/D conversion by converting the oscillation frequency ratio between a reference resistor (or capacitor) and a resistive sensor (or capacitive sensor) such as a thermistor to digital data. By making RC oscillation occur both on the reference side and on the sensor side with the reference capacitor the error factor that the RS oscillator circuit itself is eliminated, thereby making it possible to perform the A/D conversion of the characteristics of the sensor itself. Also, by calculating the ratio between the oscillation frequency on the reference side and that on the sensor side and then calculating the correlation between the calculated ratio and temperatures that the sensor characteristics have in advance, a temperature can be obtained based on that calculated ratio. Table 24-1 lists the eight types of oscillation modes, one of which is selected by the RC-ADC mode register (RADMOD) OM3–0 bits. Table 24-1 Mode No. 0 Oscillation Modes from Which Selection Is Made by OM3–0 Bits RADMOD RCOSC0 output pin RCOSC1 output pin OM3 OM2 OM1 OM0 RS0 RT0 CRT0 CS0 RS1 RT1 CS1 0 0 0 0 Z Z Z Z Z Z Z Mode 1 0 0 0 1 1/0 Z Z 0/1 Z Z Z 2 0 0 1 0 Z 1/0 Z 0/1 Z Z Z IN0 external clock input mode RCOSC0 RS0–CS0 oscillation oscillation mode RT0–CS0 oscillation 3 0 0 1 1 Z Z 1/0 0/1 Z Z Z RT0-1–CS0 oscillation 4 0 1 0 0 1/0 Z 0/1 Z Z Z Z RS0–CT0 oscillation 5 0 1 0 1 Z Z Z Z 1/0 Z 0/1 RS1–CS1 oscillation 0 1 0 1 1 * * Z 1/0, 0/1 1 1 * 0 1 * 6 7 8 Note) (Setting prohibited) FEUL610Q438 RCOSC1 oscillation mode Z Z Z Z Z 1/0 0/1 RT1–CS1 oscillation Z Z Z Z Z Z Z IN1 external clock input mode Z Z Z Z Z Z Z (Setting prohibited) : Indicates “arbitrary.” : Indicates high-impedance output. : Indicates active output. : The oscillator clock is not supplied even by setting the RARUN bit to “1” or by starting A/D conversion. 24-8 ML610Q438/ML610Q439 User’s Manual Chapter 24 RC Oscillation Type A/D Converter In Table 24-1, mode No.0 and mode No.7 are modes where external clocks to be input to the IN0 or IN1 pin are used for measurement with the RC oscillator circuit stopped. As shown in Table 24-1, the two oscillator circuits, RCOSC0 and RCOSC1, are so specified that they cannot operate concurrenty in order to prevent interference in oscillation from occurring when they oscillate concurrently. The relationship between an oscillation frequency fRCCLK and an RC constant is expressed by the following equation: 1 fRCCLK = tRCCLK = kRCCLK•R•C where tRCCLK is the period of the oscillator clock, kRCCLK the proportional constant, and RC the product of capacitances CS and CT and resistances RS and RT. CS, CT, RS, and RT concern oscillation. The value of kRCCLK slightly changes depending on the value of the supply voltage VDD, R, or C. Table 24-2 lists the typical kRCCLK values. Table 24-2 VDD (V) Typical Values of the Proportional Constant kRCCLK of RC Oscillator Circuits CSn, CTn (pF) CVRｎ(pF) RSn, RTn (kΩ) kRCCLK (Typ.) 560 560 560 560 820 820 820 820 100 10 100 10 1.2 1.2 1.2 1.3 3 1.5 Note) n = 0, 1 Notes: • Out of the Port 3 and Port 4 pins, pins that are to be used for the RC-ADC function must be configured as secondary function input or output using the mode register (P3MOD0, P3MOD1, P4MOD0, P4MOD1) of the corresponding port. • All the Port 3 pins except P35/RCM (see Section 24.1.3, “List of Pins”) are configured as pins dedicated to the RC-ADC function during A/D conversion. Therefore, during A/D conversion, all the Port 3 pins except P35 cannot be used as their primary functions in oscillation mode No. 0, 1, 2, 3 or 4, which is selected by the RADMOD register. In the same way, the P44 to P47 pins of Port 4 cannot be used as their primary functions in oscillation mode No. 5, 6 or 7. FEUL610Q438 24-9 ML610Q438/ML610Q439 User’s Manual Chapter 24 RC Oscillation Type A/D Converter Figures 24-2 to 24-5 show the oscillator circuit configurations, the modes of oscillation for each configuration, and the OM3–0 bit settings. RCT0 RT0 RT0 RS0 RS0 CS0 CS0 RI0 IN0 Figure 24-2 OM3 OM2 OM1 OM0 0 0 0 1 0 0 1 0 Mode of oscillation Oscillates with the reference resistor RS0 and CS0 Oscillates with the sensor RT0 and CS0 When RCOSC0 Is Used for Measurement with One Resistive Sensor Note: The unused pin RCT0 shown in the figure above is configured as a pin dedicated to the RC-ADC function during A/D conversion; therefore, during A/D conversion, RCT0 cannot be used as a port (P34). RT0-1 RCT0 RT0 RT0 RS0 RS0 CS0 CS0 RI0 IN0 Figure 24-3 CT0 OM3 OM2 OM1 OM0 0 0 0 1 0 0 1 0 0 0 1 1 When RCOSC0 Is Used for Measurement with One Resistive Sensor (Two points are adjusted with two reference resistors) RCT0 OM3 OM2 OM1 OM0 0 0 0 1 0 1 0 0 RT0 RS0 RS0 CS0 CS0 RI0 IN0 Figure 24-4 Mode of oscillation Oscillates with the reference resistor RS0 and CS0 Oscillates with the sensor RT0 and CS0 Oscillates with the reference resistor RT0-1 and CS0 Mode of oscillation Oscillates with the reference resistor RS0 and CS0 Oscillates with the sensor RS0 and CT0 When RCOSC0 Is Used for Measurement with One Capacitive Sensor Note: The unused pin RT0 shown in the figure above is configured as a pin dedicated to the RC-ADC function during A/D conversion; therefore, during A/D conversion, RT0 cannot be used as a port (P33). FEUL610Q438 24-10 ML610Q438/ML610Q439 User’s Manual Chapter 24 RC Oscillation Type A/D Converter RT1 RT1 OM3 OM2 OM1 OM0 RS1 RS1 0 1 0 1 CS1 CS1 RI1 IN1 0 1 1 0 Figure 24-5 Mode of oscillation Oscillates with the reference resistor RS1 and CS1 Oscillates with the sensor RT1 and CS1 When RCOSC1 Is Used for Measurement with One Resistive Sensor 24.3.2 Counter A/Counter B Reference Modes There are the following two modes of RC-ADC conversion operation: • Counter A reference mode (RADMOD RADI = “0”) In this mode, a gate time is determined by Counter A and the base clock (BSCLK), which is used as the time reference, then the RC oscillator clock (RCCLK) is counted by Counter B within the gate time to make the content of Counter B an A/D conversion value. The A/D conversion value is proportional to RC oscillation frequency. • Counter B reference mode (RADMOD RADI = “1”) In this mode, a gate time is determined by Counter B and the RC oscillator clock (RCCLK), and the base clock (BSCLK), which is used as the time reference, is counted by Counter A within the gate time to make the content of Counter A an A/D conversion value. The /D conversion value is inversely proportional to RC oscillation frequency. (1) Operation in Counter A reference mode Figure 24-6 shows the operation timing in Counter A reference mode. Following is an example of operation procedure in Counter A reference mode:  Preset to Counter A (RADCA2–0) the value obtained by subtracting the count value “nA0” from the maximum value + 1 (1000000H). The product of the count value “nA0” and the BSCLK clock period indicates the gate time.  Preset “000000H” to Counter B (RADCB2–0).  Set the OM3–OM0 bits of RADMOD to desired oscillation mode (see Table 24-1).  Set the RADI bit of RADMOD to “0” to specify generating of an interrupt request signal by Counter A overflow.  Set the RARUN bit of RADCON to “1” to start A/D conversion. FEUL610Q438 24-11 ML610Q438/ML610Q439 User’s Manual Chapter 24 RC Oscillation Type A/D Converter Counter A starts counting of the base clock (BSCLK) when RARUN is set to “1” and the RCON signal (signal synchronized with the fall of the base clock) is set to “1”. When Counter A overflows, the RARUN bit is automatically reset to “0” () and counting is terminated. At the same time, an RC-ADC interrupt request (RADIN) occurs (). When the RCON signal is set to “1”, the RC oscillator circuit starts operation and Counter B starts counting of the RC oscillator clock (RCCLK). When the RARUN bit is reset to “0” due to overflow of Counter A, RC oscillation stops and Counter B stops counting. The final count value “nB0” of Counter B is the RCCLK count value during the gate time “nA0tBSCLK” and is expressed by the following expression: nB0 ≅ tBSCLK tRCCLK nA0• ∝ fRCCLK where tBSCLK indicates the BSCLK period and tRCCLK the RCCLK period. RC oscillation frequency fRCCLK. That is, “nB0” is a value proportional to the   RARUN tBSCLK BSCLK RCON  Overflow Counter A (1000000H – nA0) (+1) (+2) (+3) 0FFFFFCH 0FFFFFDH 0FFFFFEH 0FFFFFFH 000000H Gate time nA0·tBSCLK tRCCLK CR oscillator circuit Input waveform IN0/IN1 RCCLK  Counter B 000000H 000001H 000002H nB0 – 2 nB0 – 1 nB0 nB0·tRCCLK RADINT nA0: Reference count value nB0: Measurement count value Figure 24-6 FEUL610Q438  (Interrupt request) Operation Timing in Counter A Reference Mode 24-12 ML610Q438/ML610Q439 User’s Manual Chapter 24 RC Oscillation Type A/D Converter (2) Operation in Counter B reference mode Figure 24-7 shows the operation timing in Counter B reference mode. Following is an example of operation procedure in Counter B reference mode:  Preset to Counter B (RADCB2–0) the value obtained by subtracting the count value “nB1” from the maximum value + 1 (1000000H). The product of the count value “nB1” and the RCCLKclock period indicates the gate time.  Preset “000000H” to Counter A (RADCA2–0).  Set the OM3–OM0 bits of RADMOD to desired oscillation mode (see Table 24-1).  Set the RADI bit of RADMOD to “1” to specify generating of an interrupt request signal by Counter B overflow.  Set the RARUN bit of RADCON to “1” to start A/D conversion. When the RARUN bit is set to “1” and the RCON signal (signal synchronized with the fall of the base clock) is set to”1”, the RC oscillator circuit starts operation and Counter B starts counting of the RC oscillator clock (RCCLK). When Counter B overflows, the RARUN bit is automatically reset () and conversion operation terminates. At the same time, an RC-ADC interrupt request (RADINT) occurs. () When the RCON signal is set to “1”, Counter A starts counting of the base clock (BSCLK). When the RARUN bit is reset due to overflow of Counter B, Counter A stops counting. The final count “nA1” of Counter A is the CLK count value during the gate time “nB1tRCCLK” and is expressed by the following expression: nA1 ≅ nB1• tRCCLK tBSCLK ∝ 1 fRCCLK That is, “nA1” is a value inversely proportional to the RC oscillation frequency fRCCLK. FEUL610Q438 24-13 ML610Q438/ML610Q439 User’s Manual Chapter 24 RC Oscillation Type A/D Converter  RARUN  tBSCLK BSCLK RCON  Counter A 000000H 000001H 000002H nA1 nA1 – 3 nA1 – 2 nA1 – 1 000003H nA1tBSCLK tRCCLK RC oscillator circuit Input waveform IN0/IN1 RCCLK  Overflow Counter B (1000000H – nB1) (+1) (+2) 0FFFFFDH 0FFFFFEH 0FFFFFFH 000000H nB1tRCCLK Gate time RADINT nA1: Measurement count value nB1: Reference count value Figure 24-7 FEUL610Q438  (Interrupt request) Operation Timing in Counter B Reference Mode 24-14 ML610Q438/ML610Q439 User’s Manual Chapter 24 RC Oscillation Type A/D Converter 24.3.3 Example of Use of RC Oscillation Type A/D Converter This section describes the method of performing A/D conversion for sensor values in Counter A and B reference modes by taking temperature measurement by a thermistor as an example. Figure 24-8 shows the configuration of 1-thermistor RC oscillator circuit using RCOSC0. Thermistor RT0 RT0 Reference resistor RS0 RS0 CS0 CS0 RI0 IN0 Figure 24-8 Configuration of 1-Thermistor RC Oscillator Circuit Using RCOSC0 Digital value nT0 Thermistor resistance RT0 Figure 24-9 shows the temperature characteristics of the thermistor resistance RT0. RT0 = f(T) RT0 Temperature T Figure 24-9 nT0 = K•RT0 = K•f(T) Temperature Characteristics of Thermistor Figure 24-10 A/D Conversion Characteristics (Ideal characteristics when nT0 is proportional to RT0) RT0 is expressed as a function of temperature T by the following equation: RT0 = f (T) Figure 24-10 shows the ideal characteristics of A/D conversion with the assumption that RT0 is an analog quantity. In the ideal characteristics, the A/D conversion value nT0 will purely depend on RT0 only. Assuming that nT0 is proportional to RT0, let proportional constant be K, then nT0 has the following relationship with temperature T: nT0 = KRT0 = Kf (T) …… Expression A Therefore, temperature T can be expressed as a digital value by performing the conversion processing that accords with the characteristics shown in Figure 24-9 for nT0 by software. FEUL610Q438 24-15 ML610Q438/ML610Q439 User’s Manual Chapter 24 RC Oscillation Type A/D Converter To convert from an RT0 value to a digital value, the ratio is used between a) the oscillation frequency by the thermistor connected to the RT0 pin and the capacitor connected to the CS0 pin and b) the oscillation frequency by the reference resistor (which ideally should have no temperature characteristics) connected to the RS0 pin and the capacitor connected to the CS0 pin. This is for making the conditions other than resistance equal to eliminate the error factor in oscillation characteristics. As shown in Figures 24-9 and 24-11, the RT0 value depends on temperature T and the RS0 value is assumed to be constant regardless of temperature T. It is ideal if the characteristics of the oscillation frequency fOSC to temperature T using these resistances will be like the solid lines in Figures 24-12 and 24-13; however, in reality, it would appear that they will be like the dotted lines due to error factors such as IC temperature characteristics. Since the condition of fRCCLK (RT0) and that of fRCCLK (RS0) are the same except for the resistances, the error ratios are almost the same; therefore, errors can almost be eliminated by using the ratio between fRCCLK (RT0) and fRCCLK (RS0). The ratio between fRCCLK (RT0) and fRCCLK (RS0) is equivalent to the above-mentioned A/D conversion value nT0 that should ideally depend only on RT0. fRCCLK Includes errors due to factors other than RT0 Reference resistance RS0 (RT0) fRCLK(RS0) = Temperature T Figure 24-11 Ideal 1 kRCCLK·(CS0+CSR)·RT0 Temperature T Temperature Characteristics of Reference Resistor Figure 24-12 Oscillation Characteristics of Thermistor fRCLK (RS0) Includes errors due to factors other than RT0 Ideal fRCCLK(RS0) = 1 kRCCLK·(CS0+CVR)·RS0 Temperature T Figure 24-13 FEUL610Q438 Oscillation Characteristics of Reference Resistor 24-16 ML610Q438/ML610Q439 User’s Manual Chapter 24 RC Oscillation Type A/D Converter Figure 24-14 shows, as an example of method, a timing diagram of one cycle of conversion from analog value RT0 to a digital value, that is, A/D conversion. Basically, one A/D conversion cycle must consist of two steps, as shown in Figure 24-14. The reason for requiring two steps is that the reference resistor and the thermistor must first be oscillated separately and then the ratio between the oscillation frequencies of them is used, as described above. In the example below, operation for these two steps is performed using the following combination: • First step = RC oscillation with RS0 in Counter A reference mode • Second step = RC oscillation with RT0 in Counter B reference mode Besides this, there would be several possible A/D conversion methods. In the above method, the operation time (gate time) for the second step fluctuates depending on the value of thermistor RT0. To avoid the fluctuation of the operation time, using a method that uses the following combination is recommended: • First step = RC oscillation with RS0 in Counter B reference mode • Second step = RC oscillation with RT0 in Counter A reference mode FEUL610Q438 24-17 ML610Q438/ML610Q439 User’s Manual Chapter 24 RC Oscillation Type A/D Converter A/D conversion procedure is explained below by taking Figure 24-14 as an example.  Base clock BSCLK 32.768 kHz  RADMOD (bits 4–0)  01H 12H (c)  RADCON (bit 0) 01H (ERAD=1) 00H 00H nA0·tBSCLK=nB0·tRCCLK(RS0) CR oscillating state (CROSC0) 01H (ERAD=1) 0.366 sec Oscillates with RS0 Stop  Stop 0FFFB50H (Counter B reference mode) Overflow (Increments by BSCLK) 000000H → 00000H (Increments by BSCLK) nA1 Overflow (Increments by RCCLK (RS0)) 000000H (Increments by RCCLK (RT0)) nB0  RC−ADC interrupt request 000000H 1000000H − nB0 (a) RADINT Stop Oscillates with RS0  CNTB2–0 00H nB0·tRCCLK(RT0)=nA1·tBSCLK (Counter A reference mode) CNTA2–0 (f)  (d) INT generated  INT generated  HLT (b) (e) Note) nA0=4B0H, tSYSCLK=1/32768 Hz;  to : Software processing; (a) to (f): Hardware processing Figure 24-14 FEUL610Q438 Timing Diagram for 1 Cycle of A/D Conversion (Example) 24-18 ML610Q438/ML610Q439 User’s Manual Chapter 24 RC Oscillation Type A/D Converter     Set the base clock to 32.768 kHz. (Write “00H” in FCON0.) Preset “1000000H – nA0” in Counter A. Preset “000000H” in Counter B. Write “01H” in RADMOD to select Counter A reference mode and the oscillation mode that uses reference resistance RS0.  Write “01H” in RADCON to start A/D conversion operation.  Write “1” in the HLT bit of SBYCON (see Chapter 4, “MCU”) to set the device to HALT mode. Note: In this example, nA0 is set to 4B0H because the gate time “nA0tBSCLK” in oscillation mode with reference resistor RS0 is set to 0.3666 second. The value of nA0 is related to how much the margin of the quantizatoin error of the A/D conversion is: the greater the nA0 value is, the smaller the margin of error becomes. To reduce noise contamination to the RC oscillator circuit caused by CPU operation, it is recommended to constantly put the device into HALT mode during operation of RC oscillation. From this point of time, the RC oscillator circuit (RCOSC0) continues oscillation for about 0.366 second with the reference resistance RS0. Then, when Counter A overflows, the RADINT signal is set to “1” and an RC-ADC interrupt request is generated (section (a)). Also, the generation of interrupt request releases HALT mode (section (b)) and at the same time, A/D conversion operation stops (section (c), RARUN bit = “0”). At this time, Counter A is set to “000000H”. The content of Counter B at this time is expressed by the following expression: nB0 = nA0 tBSCLK tRCCLK(RS0) …… Expression B That completes the operations in First Step .  Calculate “1000000H – nB0” from the content of Counter B “nB0” and set the obtained value in Counter B. At this point, Counter A needs to be cleared; however, no processing is required since the counter is already set to “000000H”.  Write “12H” in RADMOD to select Counter B reference mode and the oscillation mode that uses thermistor RT0.  Write “01H” in RADCON to start A/D conversion operation.  Write “1” in the HLT bit of SBYCON (see Chapter 4, “MCU”) to set the device to HALT mode. The RC oscillator circuit (RCOSC0) oscillates with thermistor RT0 from this point until Counter B overflows. This period is equal to the product of “nB0” obtained in the First Step and the oscillation period tRCCLK (RT0) using RT0. When Counter B overflows, the RADINT signal is set to “1” and an RC-ADC interrupt request is generated (section (d)). Also, the generation of interrupt request releases HALT mode (section (e)) and at the same time, A/D conversion operation stops (section (f), RARUN bit = “0”). This completes the operations in Second Step . The content of Counter A at this time becomes the A/D converison value nA1, which is expressed by the following expression: nA1 = nB0 tRCCLK (RT0) tBSCLK …… Expression C From expressions B and C, nA1 is expressed by the following expression: nA1 FEUL610Q438 = nA0 tRCCLK (RT0) tRCCLK (RS0) …… Expression D 24-19 ML610Q438/ML610Q439 User’s Manual Chapter 24 RC Oscillation Type A/D Converter where tRCCLK (RS0) is the oscillator clock period by reference resistor RS0 and tRCCLK (RT0) the oscillator clock period by thermistor RT0. Since the oscillation period is expressed by “tRCCLK = kRCCLKRC”, tRCCLK (RS0) and tRCCLK (RT0) are expressed by the following expressions: tRCCLK (RS0) = kRCCLK(CS0+CVR)RS0 tRCCLK (RT0) = kRCCLK(CS0+CVR)RT0 …… Expression E When expression E is substituted for expression D, nA1 will be: nA1 = nA0 RT0 RS0 Since “nA0” (“4B0H” in this example) and RS0 are constants whose values are fixed, “nA1” is a digital value proportional to RT0. This very “nA1” corresponds to “nT0” in expression A. That concludes the description of the A/D conversion method using a thermistor. “nA1” that has been obtained must further be converted to a value such as a temperature indication value for thermometer by program according to the temperature-to-resistance characteristics of the themistor. 24.3.4 Monitoring RC Oscillation The RC oscillator clock (RCCLK) can be output using the secondary function of the P35 pin of Port 3. See Chapter 20, “Port 3,” for the details of the secondary function of P35. Monitoring RC oscillation is useful for checking the characteristics of the RC oscillator circuit. That is, the relationship between a sensor, such as a thermistor, and the oscillation frequency can be measured. For instance, the coefficient for conversion from the above-described nA1 value to a temperature indication value can be obtained by checking the relationship between the ambient temperature of a themistor-incorporated RC oscillator, the oscillation frequency with thermistor RT0, and the oscillation frequency with reference resistor RS0. Note: • P35 (RCM) is a monitor pin for oscillation clock. The channel 0(P34-P30) and channel 1(P47-P44) share the monitor pin. • Please use P35 (RCM) for the evaluation purpose and disable the output while operating in an actual application to minimize the noise. FEUL610Q438 24-20 ML610Q438/ML610Q439 User’s Manual Chapter 24 RC Oscillation Type A/D Converter 24.4 Specifying port registers When you want to make sure the RC-ADC function is working, please check related port registers are specified. See Chapter 20, “Port 3” and Chapter 21, “Port 4” for detail about the port registers. 24.4.1 Functioning P35(RCM), P34(RCT0), P33(RT0), P32(RS0), P31(CS0) and P30(IN0) as the RC-ADC(Ch0) Set P35MD1-P30MD1 bits(bit5-bit0 of P3MOD1 register) to “0” and set P35MD0-P30MD0(bit5-bit0 of P3MOD0 register) to “1”, for specifying the RC-ADC as the secondary function of P35, P34, P33, P32, P31 and P30. Reg. name P3MOD1 register (Address: 0F21DH) Bit 7 6 5 4 3 2 1 0 Bit name P37MD1 P36MD1 P35MD1 P34MD1 P33MD1 P32MD1 P31MD1 P30MD1 Data - - 0 0 0 0 0 0 Reg. name P3MOD0 register (Address: 0F21CH) Bit 7 6 5 4 3 2 1 0 Bit name P37MD0 P36MD0 P35MD0 P34MD0 P33MD0 P32MD0 P31MD0 P30MD0 Data - - 1 1 1 1 1 1 Set P35C1-P30C1 bit(bit5-0 of P3CON1 register) to “0”, set P35C0-P30C0 bit(bit5-0 of P3CON0 register) to “0”, and set P35DIR-P30DIR bit(bit5-0 of P3DIR register) to “1”, for specifying the P35-P30 as high-impedance inputs. The P35C1-P30C1 bit and P35C0-P30C0 bit can be set to all “1” instead of all “0” to select the high-impedance inputs. Reg. name P3CON1 register (Address: 0F21BH) Bit 7 6 5 4 3 2 1 0 Bit name P37C1 P36C1 P35C1 P34C1 P33C1 P32C1 P31C1 P30C1 Data - - 0 0 0 0 0 0 Reg. name P3CON0 register (Address: 0F21AH) Bit 7 6 5 4 3 2 1 0 Bit name P37C0 P36C0 P35C0 P34C0 P33C0 P32C0 P31C0 P30C0 Data - - 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Bit name P37DIR P36DIR P35DIR P34DIR P33DIR P32DIR P31DIR P30DIR Data - - 1 1 1 1 1 1 Reg. name P3DIR register (Address: 0F219H) Data of P35D-P30D bits (bit5-0 of P3D register) do not affect to the RC-ADC function, so don’t care the data for the function. Reg. name P3D register (Address: 0F218H) Bit 7 6 5 4 3 2 1 0 Bit name P37D P36D P35D P34D P33D P32D P31D P30D Data - - ** ** ** ** ** ** - : Bit does not exist. * : Bit not related to the RC-ADC channel 0(using P35,P34,P33,P32,P31 and P30) function ** : Don’t care the data FEUL610Q438 24-21 ML610Q438/ML610Q439 User’s Manual Chapter 24 RC Oscillation Type A/D Converter 24.4.2 Functioning P47(RT1), P46(RS1), P45(CS1) and P44(IN1) as the RC-ADC(Ch1) Set P47MD1-P44MD1 bits(bit7-bit4 of P4MOD1 register) to “0” and set P47MD0-P44MD0(bit7-bit4 of P4MOD0 register) to “1”, for specifying the RC-ADC as the secondary function of P47, P46, P45 and P44. Reg. name P4MOD1 register (Address: 0F225H) Bit 7 6 5 4 3 2 1 0 Bit name P47MD1 P46MD1 P45MD1 P44MD1 P43MD1 P42MD1 P41MD1 P40MD1 Data 0 0 0 0 * * * * Reg. name P4MOD0 register (Address: 0F224H) Bit 7 6 5 4 3 2 1 0 Bit name P47MD0 P46MD0 P45MD0 P44MD0 P43MD0 P42MD0 P41MD0 P40MD0 Data 1 1 1 1 * * * * Set P47C1-P44C1 bit(bit7-4 of P4CON1 register) to “0”, set P47C0-P44C0 bit(bit7-4 of P4CON0 register) to “0”, and set P47DIR-P44DIR bit(bit7-4 of P4DIR register) to “1”, for specifying the P47-P44 as high-impedance inputs. The P47C1-P44C1 bit and P47C0-P44C0 bit can be set to all “1” instead of all “0” to select the high-impedance inputs. Reg. name P4CON1 register (Address: 0F223H) Bit 7 6 5 4 3 2 1 0 Bit name P47C1 P46C1 P45C1 P44C1 P43C1 P42C1 P41C1 P40C1 Data 0 0 0 0 * * * * Bit 7 6 5 4 3 2 1 0 Bit name P47C0 P46C0 P45C0 P44C0 P43C0 P42C0 P41C0 P40C0 Data 0 0 0 0 * * * * Reg. name P4CON0 register (Address: 0F222H) Reg. name P4DIR register (Address: 0F221H) Bit 7 6 5 4 3 2 1 0 Bit name P47DIR P46DIR P45DIR P44DIR P43DIR P42DIR P41DIR P40DIR Data 1 1 1 1 * * * * Data of P47D-P44D bits (bit7-4 of P4D register) do not affect to the RC-ADC function, so don’t care the data for the function. Reg. name P4D register (Address: 0F220H) Bit 7 6 5 4 3 2 1 0 Bit name P47D P46D P45D P44D P43D P42D P41D P40D Data ** ** ** ** * * * * * : Bit not related to the RC-ADC channel 1(using P47,P46,P45 and P44) function ** : Don’t care the data Note: Status of output pins P31-P34 and P45-P47 changes according to the RC oscillation mode specified by OM0-OM3 bit of RADMOD register. FEUL610Q438 24-22 Chapter 25 Successive Approximation Type A/D Converter ML610Q438/ML610Q439 User’s Manual Chapter 25 Successive Approximation Type A/D Converter 25. Successive Approximation Type A/D Converter 25.1 Overview This LSI has a built-in 2-channel successive approximation type A/D converter (SA-ADC). The LSI, which also incorporates the amplifier that can adjust gain and offset and allows differential input to be applied, can handle various types of analog input. 25.1.1 Features • Built-in sample/hold 12-bit successive approximation type A-D converter, which enables channel selection from 2 channels • Built-in two-stage amplifiers which consist of 1st amplifier that handles differential amplification input and 2nd amplifier that handles offset adjustment • At differential amplification input, offset measurement of each individual amplifier is possible by shorting the input pins. • A combination of amplifiers enables handling of a variety of analog input. 25.1.2 Configuration Figure 25-1 shows the configuration of SA-ADC. AVDD VREF AVSS AMPCON0 AIN0 AIN1 1st amplifier (differential input) Successive approximation type A/D converter AMPGAIN 2nd amplifier (inversion amplifier) SADRnL, SADRnH Analog selector AMPOF SADCON0,SADCON1, SADMOD0 HSCLK (4.096MHz/500KHz) SADINT 8 Data bus SADR0L: SADR0H: SADR1L: SADR1H: SADCON0: SADCON1: SADMOD0: AMPOFFS: AMPGAIN: AMPCON0: SA-ADC result register 0L SA-ADC result register 0H SA-ADC result register 1L SA-ADC result register 1H SA-ADC control register 0 SA-ADC control register 1 SA-ADC mode register 0 Amplifier offset register Amplifier gain register Amplifier control register 0 Figure 25-1 FEUL610Q438 Configuration of SA-ADC 25-1 ML610Q438/ML610Q439 User’s Manual Chapter 25 Successive Approximation Type A/D Converter 25.1.3 List of Pins Pin name I/O AVDD  VREF  AVSS  AIN0 AIN1 I I FEUL610Q438 Description Positive power supply pin for the successive approximation type A/D converter Reference power supply pin for the successive approximation type A/D converter Negative power supply pin for the successive approximation type A/D converter Successive approximation type A/D converter input pin 0 Successive approximation type A/D converter input pin 1 25-2 ML610Q438/ML610Q439 User’s Manual Chapter 25 Successive Approximation Type A/D Converter 25.2 Description of Registers 25.2.1 List of Registers Address 0F2D0H 0F2D1H 0F2D2H 0F2D3H 0F2F0H 0F2F1H 0F2F2H 0F2F4H 0F2F5H 0F2F6H Name SA-ADC result register 0L SA-ADC result register 0H SA-ADC result register 1L SA-ADC result register 1H SA-ADC control register 0 SA-ADC control register 1 SA-ADC mode register 0 Amplifier offset register Amplifier gain register Amplifier control register 0 FEUL610Q438 Symbol (Byte) SADR0L SADR0H SADR1L SADR1H SADCON0 SADCON1 SADMOD0 AMPOFFS AMPGAIN AMPCON0 Symbol (Word) SADR0 SADR1 SADCON     R/W Size Initial value R R R R R/W R/W R/W R/W R/W R/W 8/16 8 8/16 8 8/16 8 8 8 8 8 00H 00H 00H 00H 02H 00H 00H 03H 00H 00H 25-3 ML610Q438/ML610Q439 User’s Manual Chapter 25 Successive Approximation Type A/D Converter 25.2.2 SA-ADC Result Register 0L (SADR0L) Address: 0F2D0H Access: R Access size: 8/16 bits Initial value: 00H 7 6 5 4 3 2 1 0 SADR0L SAR03 SAR02 SAR01 SAR00     R/W Initial value R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 SADR0L is a special function register (SFR) used to store SA-ADC conversion results on channel 0. SADR0L is updated after A/D conversion. [Description of Bits] • SAR03-SAR00 (bits 7-4) The SAR03–SAR00 bits are used to store the values of bit 3 to bit 0 of A/D conversion results (12 bits) on channel 0. 25.2.3 SA-ADC Result Register 0H (SADR0H) Address: 0F2D1H Access: R Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 SADR0H SAR0B SAR0A SAR09 SAR08 SAR07 SAR06 SAR05 SAR04 R/W Initial value R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 SADR0H is a special function register (SFR) used to store SA-ADC conversion results on channel 0. SADR0H is updated after A/D conversion. [Description of Bits] • SAR0B-SAR04 (bits 7-0) The SAR0B3–SAR04 bits are used to store the values of bit 11 to bit 4 of A/D conversion results (12 bits) on channel 0. FEUL610Q438 25-4 ML610Q438/ML610Q439 User’s Manual Chapter 25 Successive Approximation Type A/D Converter 25.2.4 SA-ADC Result Register 1L (SADR1L) Address: 0F2D2H Access: R Access size: 8/16 bits Initial value: 00H 7 6 5 4 3 2 1 0 SADR1L SAR13 SAR12 SAR11 SAR10     R/W Initial value R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 SADR1L is a special function register (SFR) used to store SA-ADC conversion results on channel 1. SADR1L is updated after A/D conversion. [Description of Bits] • SAR13-SAR10 (bits 7-4) The SAR13–SAR10 bits are used to store the values of bit 3 to bit 0 of A/D conversion results (12 bits) on channel 1. 25.2.5 SA-ADC Result Register 1H (SADR1H) Address: 0F2D3H Access: R Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 SADR1H SAR1B SAR1A SAR19 SAR18 SAR17 SAR16 SAR15 SAR14 R/W Initial value R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 SADR1H is a special function register (SFR) used to store SA-ADC conversion results on channel 1. SADR1H is updated after A/D conversion. [Description of Bits] • SAR1B-SAR14 (bits 7-0) The SAR1B–SAR14 bits are used to store the values of bit 11 to bit 4 of A/D conversion results (12 bits) on channel 1. FEUL610Q438 25-5 ML610Q438/ML610Q439 User’s Manual Chapter 25 Successive Approximation Type A/D Converter 25.2.6 SA-ADC Control Register 0 (SADCON0) Address: 0F2F0H Access: R/W Access size: 8/16 bits Initial value: 02H 7 6 5 4 3 2 1 0 SADCON0       SACK SALP R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 SADCON0 is a special function register (SFR) used to control the operation of the SA-ADC. [Description of Bits] • SALP (bit 0) SALP 0 1 Description Single A/D conversion only (Initial value) Consecutive A/D conversion This bit is used to select whether A/D conversion is performed once only for each channel or consecutively. When this bit is set to “0”, A/D conversion is performed once only for each channel and when it is set to “1”, A/D conversion is performed consecutively according to the settings of the amplifier control register 0 (AMPCON0) and SA-ADC mode register (SADMOD0). Notes: When amplification input or differential amplification input is selected by amplifier control register 0, the amplifier settling time is required before starting A/D conversion. So set the SALP bit to “0” without using the setting of “Consecutive A/D conversion”. Set the SALP bit when the SARUN bit of the SADCON1 register is “0” (A/D conversion inactive). Use the SADMOD0 register to select a channel. See Section 25.3.2, A/D Conversion Channel Settings, for the details. • SACK (bit 1) SACK 0 1 Description HSCLK is set to the range of 375kHz to 625kHz. HSCLK is set to the range of 1.5MHz to 4.2MHz (Initial value) The SACK bit is used to set an A/D conversion time. As a conversion time is set by counting HSCLK, set this bit to “0” when HSCLK is set in the range of 375kHz to 625kHz and when HSCLK is set in the range of 1.5MHz to 4.2MHz, set this bit to “1”. Note: Set the SACK bit when the SARUN bit of the SADCON1 register is “0” (A/D conversion inactive). SA-ADC is available only when VDD=1.8V to 3.6V and HSCLK is in the ranges of 375KHz to 625kHz and of 1.5MHz to 4.2MHz. FEUL610Q438 25-6 ML610Q438/ML610Q439 User’s Manual Chapter 25 Successive Approximation Type A/D Converter 25.2.7 SA-ADC Control Register 1 (SADCON1) Address: 0F2F1H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 SADCON1        SARUN R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 SADCON1 is a special function register (SFR) used to control the operation of the SA-ADC. [Description of Bits] • SARUN (bit 0) SARUN 0 1 Description Stops conversion. (Initial value) Starts conversion. The SARUN bit is used to start or stop SA-ADC conversion. Setting this bit to “1” starts A/D conversion and setting it to “0” stops A/D conversion. When SALP of SADCON0 is “0” and then A/D conversion on the channel with the largest channel number among the selected ones is terminated, the SARUN bit is automatically set to “0”. Notes: Use the SA-ADC with high-speed clock oscillation (HSCLK) enabled in the frequency control register (FCON0). The SA-ADC is available only when VDD = 1.8 to 3.6 V and HSCLK is in the ranges of 3.75kHz to 625kHz and of 1.5MHz to 4.2 MHz. Do not start A/D conversion in the state in which bits 1 (SACH1) and 0 (SACH0) of SA-ADC mode register 0 are “0” and “0” respectively. When A/D conversion is started in this state, A/D conversion is not done while the A/D converter is activated. Therefore, the SA-ADC result register is not updated, the A/D conversion termination interrupt is not generated, A/D conversion is not terminated automatically, and SARUN remains “1”. FEUL610Q438 25-7 ML610Q438/ML610Q439 User’s Manual Chapter 25 Successive Approximation Type A/D Converter 25.2.8 SA-ADC Mode Register 0 (SADMOD0) Address: 0F2F2H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 SADMOD0       SACH1 SACH0 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 SADMOD0 is a special function register (SFR) used to choose A/D conversion channel(s). [Description of Bits] • SACH0 (bit 0) SACH0 0 1 Description Stops conversion on channel 0. (Initial value) Performs conversion on channel 0. • SACH1 (bit 1) SACH1 0 1 Description Stops conversion on channel 1. (Initial value) Performs conversion on channel 1. The SACH1 and SACH0 bits are used to select channel(s) on which A/D conversion is performed. If both channel 1 and channel 0 are set to “1”, A/D conversion is performed on channel 0 first, and then channel 1. Depending on the combination of settings of this register and amplifier control register 0 (AMPCON0), the number of A/D conversion channels and the A/D conversion methods are varied. See Section 25.3.2, Settings of A/D Conversion Channels. Do not start A/D conversion both channel 1 and channel 0 set to 0. If conversion is started, the A/D conversion circuit is activated (ON), however, A/D conversion is not done. Therefore, the SA-ADC result register is not updated, A/D conversion termination interrupt does not occur, A/D conversion does not terminate automatically, and consequently, bit 0 (SARUN) of the SA-ADC control register (SADCON1) remains “1”. FEUL610Q438 25-8 ML610Q438/ML610Q439 User’s Manual Chapter 25 Successive Approximation Type A/D Converter 25.2.9 Amplifier Offset Register (AMPOFFS) Address: 0F2F4H Access: R/W Access size: 8 bits Initial value: 03H 7 6 5 4 3 2 1 0 AMPOFFS    AMPO4 AMPO3 AMPO2 AMPO1 AMPO0 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 1 R/W 1 AMPOFFS is a special function register (SFR) used to select the amount of the input offset of the 2nd amplifier. [Description of Bits] • AMPO4, AMPO3, AMPO2, AMPO1, AMPO0 (bits 4-0) AMPO4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FEUL610Q438 AMPO3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 AMPO2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 AMPO1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 AMPO0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Description Offset adjustment −1.5[%] Offset adjustment −1.0[%] Offset adjustment −0.5[%] Offset adjustment 0[%] (Initial value) Offset adjustment 0.5[%] Offset adjustment 1.0[%] Offset adjustment 1.5[%] Offset adjustment 2.0[%] Offset adjustment 2.5[%] Offset adjustment 3.0[%] Offset adjustment 3.5[%] Offset adjustment 4.0[%] Offset adjustment 4.5[%] Offset adjustment 5.0[%] Offset adjustment 5.5[%] Offset adjustment 6.0[%] Offset adjustment −9.5[%] Offset adjustment −9.0[%] Offset adjustment −8.5[%] Offset adjustment −8.0[%] Offset adjustment −7.5[%] Offset adjustment −7.0[%] Offset adjustment −6.5[%] Offset adjustment −6.0[%] Offset adjustment −5.5[%] Offset adjustment −5.0[%] Offset adjustment −4.5[%] Offset adjustment −4.0[%] Offset adjustment −3.5[%] Offset adjustment −3.0[%] Offset adjustment −2.5[%] Offset adjustment −2.0[%] 25-9 ML610Q438/ML610Q439 User’s Manual Chapter 25 Successive Approximation Type A/D Converter 25.2.10 Amplifier Gain Register (AMPGAIN) Address: 0F2F5H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 AMPGAIN     AMPG3 AMPG2 AMPG1 AMPG0 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 AMPGAIN is a special function register (SFR) used to select a gain (scaling factor) of the 2nd amplifier. [Description of Bits] • AMPG3, AMPG2, AMPG1, AMPG0 (bits 3-0) AMPG3 AMPG2 AMPG1 AMPG0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 AMP gain Differential amplification input 1 time (Initial value) 3 times (Initial value) 1.5 times 4.5 times 2 times 6 times 2.5 times 7.5 times 3 times 9 times 3.5 times 10.5 times 4 times 12 times 4.5 times 13.5 times 5 times 15 times 5.5 times 16.5 times 6 times 18 times 6.5 times 19.5 times 7 times 21 times 7.5 times 22.5 times 8 times 24 times 8.5 times 25.5 times Amplification input For the channel for which amplifier input is selected by the setting of amplifier control register 0 (AMPON0), the gain value is set according to the setting of AMPG3 to AMPG0 on the above table. The channel for which direct input is selected is not amplified. For the channel for which differential amplification input is selected, the total gain is 3 times the gain for amplification input since the gain of the 1st amplifier is 3 times. FEUL610Q438 25-10 ML610Q438/ML610Q439 User’s Manual Chapter 25 Successive Approximation Type A/D Converter 25.2.11 Amplifier Control Register 0 (AMPCON0) Address: 0F2F6H Access: R/W Access size: 8/16 bits Initial value: 00H 7 6 5 4 3 2 1 0 AMPCON0      AMPADJ AMPEN1 AMPEN0 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 AMPCON0 is a special function register used to control the 1st and 2nd amplifiers. [Description of Bits] • AMPEN1,AMPEN0 (bits 1-0) AMPEN1 AMPEN0 Configuration AIN0 0 0 SA-ADC AIN1 AIN0 0 1 SA-ADC 2nd AIN1 amplifier AIN0 1 0 1 2nd SA-ADC amplifier AIN1 AIN0 1 A/D conversion input AIN1 1st 2nd amplifier amplifier SA-ADC Channel 0: Direct input Channel 1: Direct input (Initial value) Channel 0: Direct input Channel 1: Amplification input Channel 0: Amplification input Channel 1: Amplification input Differential amplification input Using AMPEN1 and AMPEN0, set the amplification of analog input signals by the 1st amplifier and the 2nd amplifier for input pins AIN0 and AIN1. By using the 2nd amplifier, analog signals can be amplified and by using the 1st and 2nd amplifiers, differential amplification input is enabled through 2 pins, AIN0 and AIN2. When neither AMPEN1 nor AMPEN0 is 0, the power is supplied to the amplifiers. When an amplifier is used, start A/D conversion after the amplifier has settled after powered on. The direct input technique is suitable when amplification by the amplifier for analog input signals is not required in direct analog voltage conversion with SA-ADC. FEUL610Q438 25-11 ML610Q438/ML610Q439 User’s Manual Chapter 25 Successive Approximation Type A/D Converter • AMPADJ0 (bit 2) AMPADJ0 0 1 Description No offset adjustment (Initial value) Starts 1st amplifier offset adjustment When AMPEN1 and AMPEN0 are set to “differential amplification input”, the input pins, AIN0 and AIN1, are shorted. That is, the offsets of the individual 1st amplifier and 2nd amplifier can be A/D converted by SA-ADC. When neither AMPEN1 nor AMPEN0 is set to “differential amplification input”, the function is disabled regardless of the setting of AMPADJ. FEUL610Q438 25-12 ML610Q438/ML610Q439 User’s Manual Chapter 25 Successive Approximation Type A/D Converter 25.3 Description of Operation 25.3.1 Analog Input Settings This LSI, which incorporates the 1st amplifier with differential input and the 2nd amplifier of the inversion structure with programmable gain and offset structure, enables A/D conversion according to the analog input signals by selecting the amplifier configuration according to the characteristics of the analog input signal. An analog input setting is selectable from three types: direct input without using the amplifier, amplification input that amplifies the analog voltage, and differential amplification input that amplifies the voltage difference between the two pins. In the following description, the A/D conversion range refers to the A/D conversion input range (AVREF to AVSS), the A/D conversion resolution refers to the change of the A/D conversion input value corresponding to the change of the A/D conversion result by 1, that is, the value produced by dividing the A/D conversion input range (AVREF to AVSS) by 4096 (12 bits), and the analog input change range refers to the range of analog input voltages which can change. 1. Direct input If the A/D conversion resolution is enough as required when analog input signals are converted by direct A/D conversion and the A/D conversion result range for the analog input change range satisfies the requirement, select direct input. For the direct input settings, set bits 1 and 0 of the amplifier controller register 0 (AMPCON0) to 0. Since the amplifier is not used, the amplifier settling time is not required. In direct A/D conversion, the A/D conversion result increases when the input voltage increases. 2. Amplification input that amplifies analog voltages If the resolution is insufficient in direct input, the 2nd amplifier can be used. The A/D conversion is performed after analog input signals are amplified. To set channel 0 to “direct input” and channel 1 to “amplification input”, set bits 1 and 0 of the amplifier control register 0 (AMPCON0) to 0 and 1. To set both channels 0 and 1 to “amplification input”, set bits 1 and 0 of the amplifier control register 0 (AMPCON0) to 1 and 0. The 2nd amplifier can amplify the gain within the range from 1 to 8.5 times by the setting of the amplification gain register (AMPGAIN). Through the setting of the amplification offset register (AMPOFFS), the offset can be adjusted within the range from -9.5% to 6.0%. Adjust the gain and offset so that the analog signal after amplification does not exceed the A/D conversion range. In amplification input, the amplification settling time is required. As the 2nd amplifier applies the inversion amplifier configuration, the A/D conversion result decreases when the input voltage increases. 3. Differential amplification input that amplifies the voltage difference between the two pins The output of the bridge configuration sensor, which is typical of a pressure sensor, is produced as a voltage difference between two pins. To use the voltage difference between two pins as analog input, select differential amplification input. For differential amplification input, set bits 1 and 0 of amplifier control register 0 (AMPCON0) to 1 and 1. By using the 1st amplifier of the differential input configuration, the voltage difference of the two pins can be extracted. The 1st amplifier has an amplification rate of 3 times. By setting the gain through the amplifier gain register (AMPGAIN), analog signals can be amplified within the range from 1 to 8.5 times in the 2nd amplifier. Therefore, the total amplification rate of the amplifiers will be from 3 to 25.5 times. By setting the amplification offset register (AMPOFFS), the offset can be adjusted within the range from -9.5% to 6.0%. Adjust the gain and offset so that the analog signals after amplified do not exceed the A/D conversion range. For differential amplification input, the amplifier settling time is required. As the 2nd amplifier applies the inversion amplifier configuration, the A/D conversion result decreases when the input voltage increases. For differential amplification input, the offset voltage of the amplifier itself can be A/D converted. The A/D conversion value eliminating offset can be obtained by subtracting the A/D conversion value of the offset voltage of the amplifier itself form the A/D conversion value of the differential input. To perform A/D conversion of the offset voltage of the amplifier itself, set bit 2 (AMPADJ) of amplifier control register 0 (AMPCON0) to “1”. FEUL610Q438 25-13 ML610Q438/ML610Q439 User’s Manual Chapter 25 Successive Approximation Type A/D Converter Direct input A/D conversion input voltage AVDD VREF AVSS AINx 12-bit successive VADIN approximation variation range type A/D converter VADIN VREF AVSS A/D conversion input voltage Amplification input AVDD VREF AVSS AINx VAINx 2nd amplifier (inversion amplifier) AMPGAIN VADIN VREF 12-bit successive VADIN approximation variation range type A/D converter Amplifier input voltage VAINx variation range AMPOFFS A/D conversion input voltage Differential amplification input AVDD VREF AVSS AIN0 AIN1 VAIN0 VAIN1 1st amplifier (differential input) 2nd amplifier (inversion amplifier) AMPGAIN VAINdiff = VAIN1 AMPOFFS VAINdiff Amplifier input voltage difference variation range − VAIN0 Figure 25-2 FEUL610Q438 VADIN VREF 12-bit successive VADIN approximation variation range type A/D converter Amplifier Configurations 25-14 ML610Q438/ML610Q439 User’s Manual Chapter 25 Successive Approximation Type A/D Converter 25.3.2 Settings of A/D Conversion Channels A/D conversion for channels 0 and 1 for SA-ADC mode register 0 (SADMOD0) and the amplifier control register varies according to the combination. When SA-ADC mode register 0 (SADMOD0) and the amplifier control register (AMPCON0) is combined, A/D conversion is performed as shown below and A/D conversion results are stored in the SA-ADC result register. SA-ADC result register Channel 0: Direct input Channel 1: Direct input Channel 0: Direct input Channel 1: Amplification input AMP EN1 0 AMP EN1 0 SA-ADC mode register 0 SACH0/1 0/1 SACH0 0 AMP EN0 0 SADR0 SACH1 1 SADR1 AIN1 direct input SACH0 1 SADR0 AIN0 direct input SACH1 SACH0 0 1 SADR1 SADR0 SACH1 1 SADR1 AIN0 direct input* AMP EN0 1 Channel 0: Amplification input Channel 1: Amplification input AMP AMP EN1 EN0 1 0 Differential amplification input AMP AMP EN1 EN0 1 1 AIN0 to 1 differential amplification input AIN1 amplification input AIN0 direct input AIN1 amplification input AIN0 amplification input AIN0 to 1 differential amplification input AIN0 direct input AIN0 amplification input* AIN0 to 1 differential amplification input AIN1 direct input* The values of the result register for the sections with a slash mark remain unchanged. Do not start A/D conversion when bits 1 (SACH1) and 0 (SACH0) of SA-ADC mode register 0 (SADMOD0) are 0 and 0. If A/D conversion is started, the A/D conversion circuit is set to ON. However, as A/D conversion is not performed, the SA-ADC result register is not updated, an A/D conversion termination interrupt is not generated, A/D conversion does not terminate automatically, and bit 0 (SARUN) of the SA-ADC control register (SADCON1) remains “1”. FEUL610Q438 25-15 ML610Q438/ML610Q439 User’s Manual Chapter 25 Successive Approximation Type A/D Converter 25.3.3 Operation of the Successive Approximation A/D Converter in Direct Input For direct input, operate SA-ADC in the following procedure. 1. Before starting SA-ADC, start oscillation of the high-speed clock (HSCLK) and wait until the oscillator settles. 2. When HSCLK is within the range from 375KHz to 625kHz, set bit 1 (SACK) of the SA-ADC control register (SADCON0) to “0” and when HSCLK is within the range from 1.5MHz to 4.2MHz, set it to “1”. 3. Set the amplifier control register (AMPCON0) and SA-ADC mode register 0 (SADMOD0). 4. When bit 0 (SARUN) of SA-ADC control register 1 (SADCON1) is set to “1”, the SA-ADC circuit becomes active and performs A/D conversion from the lower channel number that is selected in the SA-ADC mode register (SADMOD0). 5. A/D conversion results are stored in the applicable SA-ADC result registers (SADRnL, SADRnH) and when A/D conversion of the largest channel number that is selected terminates, an SA-ADC conversion termination interrupt (ADSINT) is generated. 6. Finally, using bit 0 (SALP) of the SADCON0 register, it is possible to select whether A/D conversion is terminated (SARUN bit is “0”) or A/D conversion is automatically restarted at termination of A/D conversion of the last channel. Even if a channel is switched during A/D conversion, the channel that is selected at the start of A/D conversion is maintained until an A/D conversion termination interrupt occurs. Figure 25-3 shows the SA-ADC operation timing when channel 0 and channel 1 are selected. HSCLK SARUN A/D operation signal Conversion time 26.86 µs@4.096MHz Conversion time 26.86 µs@4.096MHz A/D conversion on channel 0 A/D conversion on channel 1 SADINT Figure 25-3 SA-ADC Operation Timing at Direct Input Note: A/D conversion time in 500kHzRC oscillation mode is 46 µs. FEUL610Q438 25-16 ML610Q438/ML610Q439 User’s Manual Chapter 25 Successive Approximation Type A/D Converter 25.3.4 Operation of the Successive Approximation A/D Converter in Amplification Input For amplification input, operate SA-ADC in the following procedure. 1. Before starting SA-ADC, start oscillation of the high-speed clock (HSCLK) and wait until the oscillator settles. 2. When HSCLK is within the range from 375KHz to 625kHz, set bit 1 (SACK) of the SA-ADC control register (SADCON0) to “0” and when HSCLK is within the range from 1.5MHz to 4.2MHz, set it to “1”. Set bit 0 (SALP) to “0”. 3. Set the amplifier control register (AMPCON0) and SA-ADC mode register 0 (SADMOD0). 4. Set amplifier offset register (AMPOFFS) and amplifier gain register (AMPGAIN). 5. When bit 0 (SARUN) of SA-ADC control register 1 (SADCON1) is set to “1” after the amplifier control register (AMPCON0 ) has been set and then the amplifier has been settled *, the SA-ADC circuit becomes active and performs A/D conversion from the lower channel number that is selected in the SA-ADC mode register (SADMOD0). 6. A/D conversion results are stored in the applicable SA-ADC result registers (SADRnL, SADRnH), and when A/D conversion terminates, the SA-ADC conversion termination interrupt is generated. 7. A/D conversion is stopped when the A/D conversion terminates, and bit 0 (SARUN) of SA-ADC control register 1 (SADCON1) is set to “0”. Even if a channel is switched during A/D conversion, the channel that is selected at the start of A/D conversion is maintained until an A/D conversion termination interrupt occurs. Figure 25-4 shows the SA-ADC operation timing when channel 0 and channel 1 are selected. HSCLK AMPEN1, AMPEN0 SARUN A/D operation signal Amplifier settling time 84 µs@Max Conversion time 26.86 µs@4.096MHz A/D conversion SADINT Figure 25-4 SA-ADC Operation Timing at Amplification Input * Amplifier settling time The power-up time of the amplifier is 30 µs, the settling time of the amplifier after powered up is 54 µs, and the total time is 84 µs. Power-up of the amplifier means that amplifier control registers AMPEN1 and AMPEN0 are set from “0” and “0” to “1” and “1” or to “1” and “0”, respectively. Notes: Since the supply current is increased while the amplifier is powered up, set amplifier control registers AMPEN1 and AMPEN0 to “0” and “0” respectively to stop operating the amplifier if the amplifier is not used. The A/D conversion time in 500 kHz RC oscillation mode is 46 µs. FEUL610Q438 25-17 ML610Q438/ML610Q439 User’s Manual Chapter 25 Successive Approximation Type A/D Converter 25.3.5 Operation of the Successive Approximation A/D Converter in Differential Amplification Input For differential amplification input, operate SA-ADC in the following procedure. 1. Before starting SA-ADC, start oscillation of the high-speed clock (HSCLK) and wait until the oscillator settles. 2. When HSCLK is within the range from 375KHz to 625kHz, set bit 1 (SACK) of the SA-ADC control register (SADCON0) to “0” and when HSCLK is within the range from 1.5MHz to 4.2MHz, set it to “1”. Set bit 0 (SALP) to “0”. 3. Set differential amplification input by setting bits 1 and 0 (AMPEN1 and AMPEN0) of amplifier control register 0 (AMPCON0) to “1” and “1” and set bits 1 and 0 (SACH1 and SACH0) of SA-ADC mode register 0 (SADMOD0) to “0” and “1”. 4. Set amplifier offset register (AMPOFFS) and amplifier gain register (AMPGAIN). 5. When bit 0 (SARUN) of SA-ADC control register 1 (SADCON1) is set to “1” after the amplifier control register (AMPCON0 ) has been set and then the amplifier has been settled *, the SA-ADC circuit becomes active and staers A/D conversion. 6. A/D conversion results are stored in the SA-ADC result registers (SADR0L, SADR0H), and when A/D conversion terminates, the SA-ADC conversion termination interrupt is generated. 7. A/D conversion is stopped when the A/D conversion terminates, and bit 0 (SARUN) of SA-ADC control register 1 (SADCON1) is set to “0”. Even if a channel is switched during A/D conversion, the channel that is selected at the start of A/D conversion is maintained until an A/D conversion termination interrupt occurs. Figure 25-5 shows the SA-ADC operation timing when channel 0 and channel 1 are selected. HSCLK AMPEN0 SARUN A/D operation signal Amplifier settling time 94µs@Max Conversion time 26.86µs@4.096MHz A/D conversion SADINT Figure 25-5 SA-ADC Operation Timing at Differential Amplification Input * Amplifier settling time The power-up time of the amplifier is 30 µs, the settling time of the amplifier after powered up is 64 µs, and the total time is 94 µs. Power-up of the amplifier means that amplifier control registers AMPEN1 and AMPEN0 are set from “0” and “0” to “1” and “1”, respectively. Notes: Since the supply current is increased while the amplifier is powered up, set amplifier control registers AMPEN1 and AMPEN0 to “0” and “0” respectively to stop operating the amplifier if the amplifier is not used. The A/D conversion time in 500 kHz RC oscillation mode is 46 µs. FEUL610Q438 25-18 Chapter 26 LCD Drivers ML610Q438/ML610Q439 User’s Manual Chapter 26 LCD Drivers 26. LCD Drivers 26.1 Overview This LSI includes LCD drivers that display the contents that are set in the display register. The LCD drivers handle the LCD display functions with four blocks. 1. 2. 3. 4. Display registers Display allocation Display control Drivers Drivers Display allocation Display registers DSPRFE DSPRFD Segment map configuration Type1 or Type2 or Typ3 COM driver Allocation RAM Type 3 Allocation Register A, B COM pins SEG driver SEG pins 1 0 Type1 or 2 or 3 DSPR02 DSPR01 DSPR00 LCD Panel Bias Bias multiplying clock Duty Contrast Frame frequency Select by DADM1, DADM0,and DASN bit (DSPMOD1 register) Display control Figure 26-1 Configuration of LCD Display Function The display registers are used to store the contents to be displayed as bit patterns. The bit pattern storage method depends on the specification of the LCD panel to be used (display pattern and assignment of the COM pin and SEG pin) and the setting of the display allocation circuit. The display allocation block controls mapping of the display register for the LCD common/segment. Using the display allocation register A and B or not using them is selectable. When using them (Set DASN bit of DSPMOD1 register to “1”), the segment mapping of the display register can be specified in bit units by programming according to the contents of display allocation registers A and B. Therefore, the display register array can be changed in flexible and simplify the software process for display (This function is defined as the programmable display allocation function in the user’s manual). Also, the data specified to the register A and B can be easily prepared by using LAPIS semiconductor LCD allocation Tool. Select type 3 for the display register segment map when using the programmable allocation function. LAPIS semiconductor LCD Tool only generates table data can be used for the type 3. When not using the display allocation register A and B (Set DASN bit of DSPMOD1 register to “0”), select one of three types of display registers segment map and control the display with the display register only. The display control circuit generates LCD drive waveforms according to the characteristics of the LCD. A bias, a bias voltage multiplying clock, a duty, a frame frequency, and a contrast suitable for the LCD panel can be selected. Note: - The programmable display allocation function is available only when 1/1~1/8 duty is selected (when using eight COMs or less for display), it does not work when 1/9~1/24 duty is selected (when using nine COMs or more for display). - Select type 3 for the display register segment map (Set DADM1 bit of DSPMOD1 register to “1”) when using the programmable allocation function. LAPIS semiconductor LCD Tool only generates table data can be used for the type 3. - When the programmable display function is not used (DASN = “0”), display allocation register A (0F400H to 0F5FFH) and display allocation register B (0F600H to 0F7FFH) can be used as 1K-byte data memory(RAM). FEUL610Q438 26-1 ML610Q438/ML610Q439 User’s Manual Chapter 26 LCD Drivers A) When not using Programmable display allocation function (DASN bit of DSPMOD1 register is “0”) Suitable for the dot matrix type LCD panel whose common/segment array is approximated to the bit array of the display register. One of three types for the display register segment mapping can be selected, the numbe of used COM pins determines the recommended type. See section 26.2.5, 26.2.9, and 26.3.2 for more detail. When the programmable display function is not used, display allocation register A and display allocation register B (See section 26.2.7 and 26.2.8) can be used as 1K-byte data memory. b i t 7 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 C O M 23 b i t 0 DSPRFE DSPRFD C O M 22 C O M 16 SEG63 Fixed display allocation (Type 1) Display registers C O M 15 C O M 8 C C C O O O M M M 2 1 0 C O M 7 Dot Matrix LCD SEG3 SEG1 SEG0 DSPR4 Unused DSPR2 DSPR1 DSPR0 Figure 26-2 An example of correlation between display register and dot matrix type LCD B) When using Programmable display allocation function (DASN bit of DSPMOD1 register is “１”) The programmable display allocation function is suitable for the LCD panel of segment type or character type whose common/segment array is restricted by the design or wiring. Segment mapping of the display register can be assigned in bit units by programming according to the contents of display allocation registers A and B. Therefore, the display register array can be changed in flexible and simplify the software process for display. Contents of the registers A(DSmCnA) specify addresses of the display registers (DSPR00 to FE) and contents of the registers B(DSmCnB) specify bits of the display registers, that are output to common “n” of segment “m”. b b b i i i t t t 7 6 5 b b b i i i t t t 4 3 2 C O M 7 b b i i t t 1 0 C O M 5 C O M 4 C O M 3 C O M 2 C O M 1 C O M 0 SEG63 DSPRFE DSPRFD Display registers Programmable display allocation 4A SEG4 SEG3 SEG1 DSPR04 Unused DSPR02 DSPR01 DSPR00 C O M 6 4F 4B 2F 4G 2G 4E 2E 4D 4H 2B 1F 1G 2C 4C SEG0 4H 4G 4F 4E 4D 4C 4B 4A 1A 2A 2H 1B 0F 0B 0G 1C 1E 2D 0A 0C 0E 1D 1H 0D 0H 2H 2G 2F 2E 2D 2C 2B 2A 1H 1G 1F 1E 1D 1C 1B 1A 0H 0G 0F 0E 0D 0C 0B 0A DSPR … DSPR4 … DSPR0 DSPR0 DSPR0 Figure 26-3 FEUL610Q438 bit … 6 … 2 1 0 Symbol … 4G … 0C 0B 0A COM … 7 … 0 0 1 SEG … 1 .. 3 4 4 An example of correlation between display registers and segment type LCD 26-2 ML610Q438/ML610Q439 User’s Manual Chapter 26 LCD Drivers 26.1.1 Features The LCD drivers are applicable to various types of LCD panels. The features include: • • • • • • • • ML610Q438: 1344 dots max. (56seg × 24com) ML610Q439: 1024 dots max. (64seg × 16com) 1/1 to 1/24 duty 1/3 and 1/4 bias (4 types) Frame frequency selectable (4 types) Bias voltage multiplying clock selectable (8 types) Contrast adjustment (1/3 bias:32 steps, 1/4 bias: 20 steps) Programmable display allocation function (available only when 1/1~1/8 duty is selected) The programmable display allocation function facilitates software display processing. By using “ALL LCDs on mode” and “ALL LCDs off mode”, LCD panel inspection processing software can be easily created. FEUL610Q438 26-3 ML610Q438/ML610Q439 User’s Manual Chapter 26 LCD Drivers 26.1.2 Configuration of the LCD Drivers Figure 26-4 shows the configuration of the LCD drivers and the bias generation circuit. COM0 COM15/23 SEG0 Common drivers VDD Bias generation circuit SEG63/55 Segment drivers Regulated power supply circuit Cd Cc VL4 VL3 Cb VL2 Ca VL1 C34 C4 Voltage multiplier Display allocation control circuit C3 C12 C2 C1 BIASCON DSPCNT DSPMOD0 DSPMOD1 DSPCON DSPR00 – DSPRFE DSmCnA DSmCnB VSS Data bus BIASCON DSPCNT DSPMOD0 DSPMOD1 DSPCON DSmCnA DSmCnB DSPR00 to DSPRFE Figure 26-4 FEUL610Q438 : Bias circuit control register : Display contrast register : Display mode register 0 : Display mode register 1 : Display control register : Allocation register A (m = 0 to 63, n = 0 to 7) : Allocation register B (m = 0 to 63, n = 0 to 7) : Display registers Configuration of LCD Drivers and Bias Generation Circuit 26-4 ML610Q438/ML610Q439 User’s Manual Chapter 26 LCD Drivers 26.1.3 Configuration of the Bias Generation Circuit The bias generation circuit generates LCD drive voltages (VL1 to VL4) by multiplying the voltage (VL1) generated by the voltage regulator with the capacitors (C12 and C34). When the BSON bit of the bias circuit control register (BIASCON) is set to “1”, the bias generation circuit starts operation. Display contrast adjustment is possible in 32 steps by using the display contrast register (DSPCNT). Figure 26-5 shows the configurations of the bias generation circuit with 1/3 bias and with 1/4 bias. VDD Regulated power supply circuit Cb VL4 VL3 VL2 Ca VL1 C34 C4 Cd Selection of bias circuit On (BSON) Voltage multiplier Selection of 1/3 bias (BSEL) To LCD drivers (VL1 to VL4) C3 C12 Display contrast adjustment (LCN4 to LCN0) C2 C1 VSS (1) 1/3 Bias VDD Regulated power supply circuit Cd Cc VL4 VL3 Cb VL2 Ca VL1 C34 C4 Selection of bias circuit On (BSON) Voltage multiplier Selection of 1/4 bias (BSEL) To LCD drivers (VL1 to VL4) C3 C12 Display contrast adjustment (LCN4 to LCN0) C2 C1 VSS (2) 1/4 Bias Figure 26-5 Configuration of Bias Generation Circuit Note: When using 1/3 bias, connect the VL2 pin and the VL3 pin externally. FEUL610Q438 26-5 ML610Q438/ML610Q439 User’s Manual Chapter 26 LCD Drivers 26.1.4 List of Pins Pin name VL1 VL2 VL3 VL4 I/O     Description Power supply pin for LCD bias (internally generated) Power supply pin for LCD bias (internally generated) Power supply pin for LCD bias (internally generated) Power supply pin for LCD bias (internally generated) C1  Capacitor connection pin for LCD bias generation C2 C3 C4 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23    O O O O O O O O O O O O O O O O O O O O O O O O Capacitor connection pin for LCD bias generation Capacitor connection pin for LCD bias generation Capacitor connection pin for LCD bias generation LCD common pin LCD common pin LCD common pin LCD common pin LCD common pin LCD common pin LCD common pin LCD common pin LCD common pin LCD common pin LCD common pin LCD common pin LCD common pin LCD common pin LCD common pin LCD common pin LCD common pin LCD common pin LCD common pin LCD common pin LCD common pin LCD common pin LCD common pin LCD common pin FEUL610Q438 26-6 ML610Q438/ML610Q439 User’s Manual Chapter 26 LCD Drivers Pin name SEG0 SEG1 SEG2 SEG3 LCD segment pin LCD segment pin LCD segment pin LCD segment pin SEG4 I/O O O O O O SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 O O O O O O O O O O O O O O O O O O O O O O O O O O O LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin FEUL610Q438 Description LCD segment pin 26-7 ML610Q438/ML610Q439 User’s Manual Chapter 26 LCD Drivers Pin name SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 FEUL610Q438 I/O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O Description LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin 26-8 ML610Q438/ML610Q439 User’s Manual Chapter 26 LCD Drivers 26.2 Description of Registers 26.2.1 List of Registers Address 0F0F0H 0F0F1H 0F0F2H 0F0F3H 0F0F4H 0F100H to 0F1FEH 0F400H to 0F5FFH 0F600H to 0F7FFH Name Bias circuit control register Display contrast register Display mode register 0 Display mode register 1 Display control register Display register 00 to Display register FE Display allocation register A Display allocation register B FEUL610Q438 Symbol (Byte) BIASCON DSPCNT DSPMOD0 DSPMOD1 DSPCON DSPR00 to DSPRFE DS0C0A to DS63C7A DS0C0B to DS63C7B Symbol (Word)   R/W Size Initial value R/W R/W R/W R/W R/W 8 8 8/16 8 8 08H 00H 00H 00H 00H  R/W 8 Undefined  R/W 8 Undefined  R/W 8 Undefined DSPMOD 26-9 ML610Q438/ML610Q439 User’s Manual Chapter 26 LCD Drivers 26.2.2 Bias Circuit Control Register 0 (BIASCON) Address: 0F0F0H Access: R/W Access size: 8 bits Initial value: 08H 7 6 5 4 3 2 1 0 BIASCON    BSEL BSN2 BSN1 BSN0 BSON R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 1 R/W 0 R/W 0 R/W 0 BIASCON is a special function register (SFR) to control the bias generation circuit. [Description of Bits] • BSON (bit 0) The BSON bit is used to control the operation of the bias generation circuit. When BSON is set to “1”, the bias generation circuit generates the LCD drive voltages (VL1 to VL4). BSON 0 1 Description Bias circuit Off (initial value) Bias circuit On • BSN2-BSN0 (bits 3-1) The BSN2 to BSN0 bits are used to select a clock for multiplying the bias voltage in the bias generation circuit. LSCLK to 1/128LSCLK can be selected. BSN2 0 0 0 0 1 1 1 1 BSN1 0 0 1 1 0 0 1 1 BSN0 0 1 0 1 0 1 0 1 Description 1/1 LSCLK (32 kHz) 1/2 LSCLK (16 kHz) 1/4 LSCLK (8 kHz) 1/8 LSCLK (4 kHz) 1/16 LSCLK (2 kHz) (initial value) 1/32 LSCLK (1 kHz) 1/64 LSCLK (512 Hz) 1/128 LSCLK (256 Hz) • BSEL (bit 4) The BSEL bit is used to set the bias in the bias generation circuit. 1/3 bias or 1/4 bias can be selected. BSEL 0 1 FEUL610Q438 Description 1/3 bias (initial value) 1/4 bias 26-10 ML610Q438/ML610Q439 User’s Manual Chapter 26 LCD Drivers 26.2.3 Display Control Register (DSPCNT) Address: 0F0F1H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 DSPCNT    LCN4 LCN3 LCN2 LCN1 LCN0 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 DSPCNT is a special function register (SFR) to adjust the contrast of display (32 steps). For the setting value of DSPCNT and the LCD drive voltages (VL1, VL2, VL3, VL4), see Appendix C, “Electrical Characteristics”. [Description of Bits] • LCN4-LCN0 (bits 4-0) The LCN4 to LCN0 bits are used to adjust the contrast of display (32 steps). LCN4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 LCN3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 LCN2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 LCN1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 LCN0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Description Low VL1 = 1.32 V when 1/4 bias is selected. High VL1 voltage (typ.) V 0.94 (initial value) 0.96 0.98 1.00 1.02 1.04 1.06 1.08 1.10 1.12 1.14 1.16 1.18 1.20 1.22 1.24 1.26 1.28 1.30 1.32 1.34 1.36 1.38 1.40 1.42 1.44 1.46 1.48 1.50 1.52 1.54 1.56 Note: Only the 20-step adjustment is usable when 1/4 bias is selected (when the BSEL bit of the BIASCON register is “1”). FEUL610Q438 26-11 ML610Q438/ML610Q439 User’s Manual Chapter 26 LCD Drivers 26.2.4 Display Mode Register 0 (DSPMOD0) Address: 0F0F2H Access: R/W Access size: 8/16 bits Initial value: 00H 7 6 5 4 3 2 1 0 DSPMOD0 FRM2 FRM1 FRM0 DUTY4 DUTY3 DUTY2 DUTY1 DUTY0 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 DSPMOD0 is a special function register (SFR) to control the display mode of the LCD drivers. [Description of Bits] • DUTY4-DUTY0 (bits 4-0) The DUTY4 to DUTY0 bits are used to specify the duty in 24 steps (1/1 to 1/24). DUTY4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FEUL610Q438 DUTY3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 DUTY2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 DUTY1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 DUTY0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Description 1/1 duty (initial value) 1/2 duty 1/3 duty 1/4 duty 1/5 duty 1/6 duty 1/7 duty 1/8 duty 1/9 duty 1/10 duty 1/11 duty 1/12 duty 1/13 duty 1/14 duty 1/15 duty 1/16 duty 1/17 duty 1/18 duty 1/19 duty 1/20 duty 1/21 duty 1/22 duty 1/23 duty 1/24 duty 26-12 ML610Q438/ML610Q439 User’s Manual Chapter 26 LCD Drivers • FRM2-FRM0 (bits 7-5) The FRM2 to FRM0 bits are used to select a frame frequency of the LCD drivers. The reference frequency of a frame frequency (LLSCLK = 32.768 kHz) is selectable from 64 Hz, 73 Hz, 85 Hz, 102 Hz, or 32Hz. FRM2 0 0 0 0 1 FRM1 0 0 1 1 * FRM0 0 1 0 1 * Description Reference frequency: 64 Hz (initial value) Reference frequency: 73 Hz Reference frequency: 85 Hz Reference frequency: 102 Hz Reference frequency: 32 Hz The frame frequency for each duty is listed in Table 26-1. Table 26-1 Duty 1/1 duty 1/2 duty 1/3 duty 1/4 duty 1/5 duty 1/6 duty 1/7 duty 1/8 duty 1/9 duty 1/10 duty 1/11 duty 1/12 duty 1/13 duty 1/14 duty 1/15 duty 1/16 duty 1/17 duty 1/18 duty 1/19 duty 1/20 duty 1/21 duty 1/22 duty 1/23 duty 1/24 duty FEUL610Q438 Frame Frequency for Each Duty Reference frequency 64Hz 64.00 64.00 64.25 64.00 64.25 64.25 64.13 64.00 86.69 78.02 70.93 65.02 78.77 73.14 68.27 64.00 77.10 72.82 68.99 65.54 74.30 70.93 67.84 65.02 Frame frequency [Hz] Reference Reference frequency 73Hz frequency 85Hz 73.14 85.33 73.14 85.33 73.31 85.33 73.14 85.33 73.64 86.23 73.80 85.33 73.14 86.69 73.14 85.33 98.40 113.78 88.56 102.40 80.51 93.09 73.80 85.33 90.02 105.03 83.59 97.52 78.02 91.02 73.14 85.33 87.61 101.45 82.75 95.81 78.39 90.77 74.47 86.23 86.69 97.52 82.75 93.09 79.15 89.04 75.85 85.33 Reference frequency 102Hz 102.40 102.40 103.04 102.40 102.40 103.04 104.03 102.40 140.03 126.03 114.57 105.03 126.03 117.03 109.23 102.40 120.47 113.78 107.79 102.40 120.03 114.57 109.59 105.03 26-13 ML610Q438/ML610Q439 User’s Manual Chapter 26 LCD Drivers 26.2.5 Display Mode Register 1 (DSPMOD1) Address: 0F0F3H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 DSPMOD1      DASN DADM1 DADM0 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 DSPMOD1 is a special register (SFR) to control the display mode of the LCD drivers. Use DSPMOD1 to select a type of display register segment map and determine to use or unuse the programmable display allocation function (display allocation RAM). [Description of Bits] • DADM1, DADM0 (bits 1-0) DADM1 and DADM0 are used to select a type of display register segment map. Three types are available; type 1, type 2, and type 3 . See section 26.2.9 and section 26.3.2. DADM1 0 0 1 DADM0 0 1 * Description Display register segment map type 1 (initial value) Display register segment map type 2 Display register segment map type 3 • DASN (bit 2) The DASN bit is used to control the operation of the display allocation function. Setting the DASN bit to “1” enables the display allocation function. DASN 0 1 Description Not use Programmable display allocation (initial value) Use Programmable display allocation Note: When using the programmable display allocation, select type 3 for the display register segment map. LAPIS semiconductor LCD Tool only generates table data can be used for the type 3. FEUL610Q438 26-14 ML610Q438/ML610Q439 User’s Manual Chapter 26 LCD Drivers 26.2.6 Display Control Register (DSPCON) Address: 0F0F4H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 DSPCON       LMD1 LMD0 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 DSPCON is a special function register (SFR) to control the LCD drivers. [Description of Bits] • LMD1-LMD0 (bits 1, 0) The LMD1 and LMD0 bits are used to select an LCD display mode. LCD stop mode, all LCDs off mode, LCD display mode, and all LCDs on mode can be selected. In LCD stop mode, Vss level is output to all the common drivers and segment drivers. The charge and discharge current to and from the display panel can be stopped. In all LCDs off mode, off waveform is output to all the segment drivers irrespective of the contents of the display registers. In LCD display mode, the contents of the display registers are output to each segment driver. In all LCDs on mode, on waveform is output to all the segment drivers irrespective of the contents of the display registers. LMD1 0 0 1 1 FEUL610Q438 LMD0 0 1 0 1 Description LCD stop mode (initial value) All LCDs off mode LCD display mode All LCDs on mode 26-15 ML610Q438/ML610Q439 User’s Manual Chapter 26 LCD Drivers 26.2.7 Display Allocation Register A (DS0C0A to DS63C7A) Address: 0F400H to 0F5FFH Access: R/W Access size: 8 bits Initial value: Undefined 7 6 5 4 3 2 1 0 DSmCnA a7 a6 a5 a4 a3 a2 a1 a0 R/W Initial value R/W x R/W x R/W x R/W x R/W x R/W x R/W x R/W x DSmCnA (m= 0 to 63, n = 0 to 7) are special function registers (SFRs) that are used for the programmable display allocation function. Each valid bit of DSmCnA becomes undefined at system reset. When the programmable display allocation function is not used (DASN bit of DSPMOD1 reigster is reset to “0”), DSmCnA can be used as data memory space (512-byte RAM). Table 26-2 shows a list of the display allocation register A. [Description of Bits] • a7-a0 (bits 7-0) The a7 to a0 bits of DSmCnA (m= 0 to 63, n = 0 to 7) are used to select the lower 8 bits of the addresses of the display registers (DSPR00 to FE) that are output to common n of segment m. Set DSmCnA when the DASN bit of the display mode register 1 (DSPMOD1) is “0”. When the DASN bit is “1”, access from the CPU is invalid. FEUL610Q438 26-16 ML610Q438/ML610Q439 User’s Manual Chapter 26 LCD Drivers Table 26-2 Segment Common SEG0 SEG1 SEG2 SEG3 : SEG63 SEG0 : SEG63 SEG0 : SEG63 SEG0 : SEG63 SEG0 : SEG63 SEG0 : SEG63 SEG0 : SEG63 SEG0 : SEG63 FEUL610Q438 COM0 COM0 COM0 COM0 : COM0 COM1 : COM1 COM2 : COM2 COM3 : COM3 COM4 : COM4 COM5 : COM5 COM6 : COM6 COM7 : COM7 Register name DS0C0A DS1C0A DS2C0A DS3C0A : DS63C0A DS0C1A : DS63C1A DS0C2A : DS63C2A DS0C3A : DS63C3A DS0C4A : DS63C4A DS0C5A : DS63C5A DS0C6A : DS63C6A DS0C7A : DS63C7A Display Allocation Register A Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 R/W 0F400H 0F401H 0F402H 0F403H : 0F43FH 0F440H : 0F47FH 0F480H : 0F4BFH 0F4C0H : 0F4FFH 0F500H : 0F53FH 0F540H : 0F57FH 0F580H : 0F5BFH 0F5C0H : 0F5FFH a7 a7 a7 a7 : a7 a7 : a7 a7 : a7 a7 : a7 a7 : a7 a7 : a7 a7 : a7 a7 : a7 a6 a6 a6 a6 : a6 a6 : a6 a6 : a6 a6 : a6 a6 : a6 a6 : a6 a6 : a6 a6 : a6 a5 a5 a5 a5 : a5 a5 : a5 a5 : a5 a5 : a5 a5 : a5 a5 : a5 a5 : a5 a5 : a5 a4 a4 a4 a4 : a4 a4 : a4 a4 : a4 a4 : a4 a4 : a4 a4 : a4 a4 : a4 a4 : a4 a3 a3 a3 a3 : a3 a3 : a3 a3 : a3 a3 : a3 a3 : a3 a3 : a3 a3 : a3 a3 : a3 a2 a2 a2 a2 : a2 a2 : a2 a2 : a2 a2 : a2 a2 : a2 a2 : a2 a2 : a2 a2 : a2 a1 a1 a1 a1 : a1 a1 : a1 a1 : a1 a1 : a1 a1 : a1 a1 : a1 a1 : a1 a1 : a1 a0 a0 a0 a0 : a0 a0 : a0 a0 : a0 a0 : a0 a0 : a0 a0 : a0 a0 : a0 a0 : a0 R/W R/W R/W R/W : R/W R/W : R/W R/W : R/W R/W : R/W R/W : R/W R/W : R/W R/W : R/W R/W : R/W 26-17 ML610Q438/ML610Q439 User’s Manual Chapter 26 LCD Drivers 26.2.8 Display Allocation Register B (DS0C0B to DS63C7B) Address: 0F600H to 0F7FFH Access: R/W Access size: 8 bits Initial value: Undefined 7 6 5 4 3 2 1 0 DSmCnB b7 b6 b5 b4 b3 b2 b1 b0 R/W Initial value R/W x R/W x R/W x R/W x R/W x R/W x R/W x R/W x DSmCnB (m= 0 to 63, n = 0 to 7) are special function registers (SFRs) to store segment allocation data. Each valid bit of DSmCnB becomes undefined at system reset. When the programmable display allocation function is not used (DASN bit of DSPMOD1 reigster is reset to “0”), DSmCnB can be used as data memory space (512-byte RAM). Table 26-3 shows a list of display allocation register B. [Description of Bits] • b2-b0 (bits 2-0) The b2 to b0 bits of DSmCnB (m= 0 to 63, n = 0 to 7) are used to set the bits of the display registers (DSPR00 to FE) that are output to common n of segment m. Set DSmCnB when the DASN bit of the display control register 0 (DSPCON0) is “0”. When the DASN bit is “1”, access from the CPU is invalid. b2 0 0 0 0 1 1 1 1 FEUL610Q438 b1 0 0 1 1 0 0 1 1 b0 0 1 0 1 0 1 0 1 Description Selects bit 0 Selects bit 1 Selects bit 2 Selects bit 3 Selects bit 4 Selects bit 5 Selects bit 6 Selects bit 7 26-18 ML610Q438/ML610Q439 User’s Manual Chapter 26 LCD Drivers Table 26-3 Segment Common SEG0 SEG1 SEG2 SEG3 : SEG63 SEG0 : SEG63 SEG0 : SEG63 SEG0 : SEG63 SEG0 : SEG63 SEG0 : SEG63 SEG0 : SEG63 SEG0 : SEG63 FEUL610Q438 COM0 COM0 COM0 COM0 : COM0 COM1 : COM1 COM2 : COM2 COM3 : COM3 COM4 : COM4 COM5 : COM5 COM6 : COM6 COM7 : COM7 Register name DS0C0B DS1C0B DS2C0B DS3C0B : DS63C0B DS0C1B : DS63C1B DS0C2B : DS63C2B DS0C3B : DS63C3B DS0C4B : DS63C4B DS0C5B : DS63C5B DS0C6B : DS63C6B DS0C7B : DS63C7B Display Allocation Register B Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 R/W 0F600H 0F601H 0F602H 0F603H : 0F63FH 0F640H : 0F67FH 0F680H : 0F6BFH 0F6C0H : 0F6FFH 0F700H : 0F73FH 0F740H : 0F77FH 0F780H : 0F7BFH 0F7C0H : 0F7FFH b7 b7 b7 b7 : b7 b7 : b7 b7 : b7 b7 : b7 b7 : b7 b7 : b7 b7 : b7 b7 : b7 b6 b6 b6 b6 : b6 b6 : b6 b6 : b6 b6 : b6 b6 : b6 b6 : b6 b6 : b6 b6 : b6 b5 b5 b5 b5 : b5 b5 : b5 b5 : b5 b5 : b5 b5 : b5 b5 : b5 b5 : b5 b5 : b5 b4 b4 b4 b4 : b4 b4 : b4 b4 : b4 b4 : b4 b4 : b4 b4 : b4 b4 : b4 b4 : b4 b3 b3 b3 b3 : b3 b3 : b3 b3 : b3 b3 : b3 b3 : b3 b3 : b3 b3 : b3 b3 : b3 b2 b2 b2 b2 : b2 b2 : b2 b2 : b2 b2 : b2 b2 : b2 b2 : b2 b2 : b2 b2 : b2 b1 b1 b1 b1 : b1 b1 : b1 b1 : b1 b1 : b1 b1 : b1 b1 : b1 b1 : b1 b1 : b1 b0 b0 b0 b0 : b0 b0 : b0 b0 : b0 b0 : b0 b0 : b0 b0 : b0 b0 : b0 b0 : b0 R/W R/W R/W R/W : R/W R/W : R/W R/W : R/W R/W : R/W R/W : R/W R/W : R/W R/W : R/W R/W : R/W 26-19 ML610Q438/ML610Q439 User’s Manual Chapter 26 LCD Drivers 26.2.9 Display Registers (DSPR00 to DSPRFE) Address: 0F100H to 0F1FEH Access: R/W Access size: 8 bits Initial value: Undefined 7 6 5 4 3 2 1 0 DSPRxx c23/15/7 c22/14/6 c21/13/5 c20/12/4 c19/11/3 c18/10/2 c17/9/1 c16/8/0 R/W Initial value R/W x R/W x R/W x R/W x R/W x R/W x R/W x R/W x DSPRxx (xx = 00 to FF) are special function registers (SFRs) to store display data. Each valid bit of DSPRxx becomes undefined at system reset. The display registers that are not used for LCD display can be used for data memories. Set data in DSPRxx before setting LCD display mode. Tables 26-4 to 26-6 list display registers segment map type 1 to type 3 respectively. The type can be selected by the DADM1 and DADM0 bits of the display mode register 1 (DSPMOD1). [Description of Bits] • c23-c0 (bits 7-0) The c23 to c0 bits are used to set display data. c23 to c0 0 1 FEUL610Q438 Description off waveform on waveform 26-20 ML610Q438/ML610Q439 User’s Manual Chapter 26 LCD Drivers Table 26-4 Register name Address DSPR00 DSPR01 DSPR02 Not used DSPR04 DSPR05 DSPR06 Not used DSPR08 DSPR09 DSPR0A Not used DSPR0C DSPR0D DSPR0E Not used DSPR10 DSPR11 DSPR12 Not used DSPR14 DSPR15 DSPR16 Not used DSPR18 DSPR19 DSPR1A Not used DSPR1C DSPR1D DSPR1E Not used DSPR20 DSPR21 DSPR22 Not used DSPR24 DSPR25 DSPR26 Not used DSPR28 DSPR29 DSPR2A Not used DSPR2C DSPR2D DSPR2E Not used DSPR30 DSPR31 DSPR32 Not used 0F100H 0F101H 0F102H 0F103H 0F104H 0F105H 0F106H 0F107H 0F108H 0F109H 0F10AH 0F10BH 0F10CH 0F10DH 0F10EH 0F10FH 0F110H 0F111H 0F112H 0F113H 0F114H 0F115H 0F116H 0F117H 0F118H 0F119H 0F11AH 0F11BH 0F11CH 0F11DH 0F11EH 0F11FH 0F120H 0F121H 0F122H 0F123H 0F124H 0F125H 0F126H 0F127H 0F128H 0F129H 0F12AH 0F12BH 0F12CH 0F12DH 0F12EH 0F12FH 0F130H 0F131H 0F132H 0F133H FEUL610Q438 Segment Map Type 1 of Display Registers (1/5) Corresponding segment SEG0  SEG1  SEG2  SEG3  SEG4  SEG5  SEG6  SEG7  SEG8  SEG9  SEG10  SEG11  SEG12  bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 R/W c7 c15 c23  c7 c15 c23  c7 c15 c23  c7 c15 c23  c7 c15 c23  c7 c15 c23  c7 c15 c23  c7 c15 c23  c7 c15 c23  c7 c15 c23  c7 c15 c23  c7 c15 c23  c7 c15 c23  c6 c14 c22  c6 c14 c22  c6 c14 c22  c6 c14 c22  c6 c14 c22  c6 c14 c22  c6 c14 c22  c6 c14 c22  c6 c14 c22  c6 c14 c22  c6 c14 c22  c6 c14 c22  c6 c14 c22  c5 c13 c21  c5 c13 c21  c5 c13 c21  c5 c13 c21  c5 c13 c21  c5 c13 c21  c5 c13 c21  c5 c13 c21  c5 c13 c21  c5 c13 c21  c5 c13 c21  c5 c13 c21  c5 c13 c21  c4 c12 c20  c4 c12 c20  c4 c12 c20  c4 c12 c20  c4 c12 c20  c4 c12 c20  c4 c12 c20  c4 c12 c20  c4 c12 c20  c4 c12 c20  c4 c12 c20  c4 c12 c20  c4 c12 c20  c3 c11 c19  c3 c11 c19  c3 c11 c19  c3 c11 c19  c3 c11 c19  c3 c11 c19  c3 c11 c19  c3 c11 c19  c3 c11 c19  c3 c11 c19  c3 c11 c19  c3 c11 c19  c3 c11 c19  c2 c10 c18  c2 c10 c18  c2 c10 c18  c2 c10 c18  c2 c10 c18  c2 c10 c18  c2 c10 c18  c2 c10 c18  c2 c10 c18  c2 c10 c18  c2 c10 c18  c2 c10 c18  c2 c10 c18  c1 c9 c17  c1 c9 c17  c1 c9 c17  c1 c9 c17  c1 c9 c17  c1 c9 c17  c1 c9 c17  c1 c9 c17  c1 c9 c17  c1 c9 c17  c1 c9 c17  c1 c9 c17  c1 c9 c17  c0 c8 c16  c0 c8 c16  c0 c8 c16  c0 c8 c16  c0 c8 c16  c0 c8 c16  c0 c8 c16  c0 c8 c16  c0 c8 c16  c0 c8 c16  c0 c8 c16  c0 c8 c16  c0 c8 c16  R/W R/W R/W  R/W R/W R/W  R/W R/W R/W  R/W R/W R/W  R/W R/W R/W  R/W R/W R/W  R/W R/W R/W  R/W R/W R/W  R/W R/W R/W  R/W R/W R/W  R/W R/W R/W  R/W R/W R/W  R/W R/W R/W  26-21 ML610Q438/ML610Q439 User’s Manual Chapter 26 LCD Drivers Table 26-4 Register name Address DSPR34 DSPR35 DSPR36 Not used DSPR38 DSPR39 DSPR3A Not used DSPR3C DSPR3D DSPR3E Not used DSPR40 DSPR41 DSPR42 Not used DSPR44 DSPR45 DSPR46 Not used DSPR48 DSPR49 DSPR4A Not used DSPR4C DSPR4D DSPR4E Not used DSPR50 DSPR51 DSPR52 Not used DSPR54 DSPR55 DSPR56 Not used DSPR58 DSPR59 DSPR5A Not used DSPR5C DSPR5D DSPR5E Not used DSPR60 DSPR61 DSPR62 Not used DSPR64 DSPR65 DSPR66 Not used 0F134H 0F135H 0F136H 0F137H 0F138H 0F139H 0F13AH 0F13BH 0F13CH 0F13DH 0F13EH 0F13FH 0F140H 0F141H 0F142H 0F143H 0F144H 0F145H 0F146H 0F147H 0F148H 0F149H 0F14AH 0F14BH 0F14CH 0F14DH 0F14EH 0F14FH 0F150H 0F151H 0F152H 0F153H 0F154H 0F155H 0F156H 0F157H 0F158H 0F159H 0F15AH 0F15BH 0F15CH 0F15DH 0F15EH 0F15FH 0F160H 0F161H 0F162H 0F163H 0F164H 0F165H 0F166H 0F167H FEUL610Q438 Segment Map Type 1 of Display Registers (2/5) Corresponding segment SEG13  SEG14  SEG15  SEG16  SEG17  SEG18  SEG19  SEG20  SEG21  SEG22  SEG23  SEG24  SEG25  bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 R/W c7 c15 c23  c7 c15 c23  c7 c15 c23  c7 c15 c23  c7 c15 c23  c7 c15 c23  c7 c15 c23  c7 c15 c23  c7 c15 c23  c7 c15 c23  c7 c15 c23  c7 c15 c23  c7 c15 c23  c6 c14 c22  c6 c14 c22  c6 c14 c22  c6 c14 c22  c6 c14 c22  c6 c14 c22  c6 c14 c22  c6 c14 c22  c6 c14 c22  c6 c14 c22  c6 c14 c22  c6 c14 c22  c6 c14 c22  c5 c13 c21  c5 c13 c21  c5 c13 c21  c5 c13 c21  c5 c13 c21  c5 c13 c21  c5 c13 c21  c5 c13 c21  c5 c13 c21  c5 c13 c21  c5 c13 c21  c5 c13 c21  c5 c13 c21  c4 c12 c20  c4 c12 c20  c4 c12 c20  c4 c12 c20  c4 c12 c20  c4 c12 c20  c4 c12 c20  c4 c12 c20  c4 c12 c20  c4 c12 c20  c4 c12 c20  c4 c12 c20  c4 c12 c20  c3 c11 c19  c3 c11 c19  c3 c11 c19  c3 c11 c19  c3 c11 c19  c3 c11 c19  c3 c11 c19  c3 c11 c19  c3 c11 c19  c3 c11 c19  c3 c11 c19  c3 c11 c19  c3 c11 c19  c2 c10 c18  c2 c10 c18  c2 c10 c18  c2 c10 c18  c2 c10 c18  c2 c10 c18  c2 c10 c18  c2 c10 c18  c2 c10 c18  c2 c10 c18  c2 c10 c18  c2 c10 c18  c2 c10 c18  c1 c9 c17  c1 c9 c17  c1 c9 c17  c1 c9 c17  c1 c9 c17  c1 c9 c17  c1 c9 c17  c1 c9 c17  c1 c9 c17  c1 c9 c17  c1 c9 c17  c1 c9 c17  c1 c9 c17  c0 c8 c16  c0 c8 c16  c0 c8 c16  c0 c8 c16  c0 c8 c16  c0 c8 c16  c0 c8 c16  c0 c8 c16  c0 c8 c16  c0 c8 c16  c0 c8 c16  c0 c8 c16  c0 c8 c16  R/W R/W R/W  R/W R/W R/W  R/W R/W R/W  R/W R/W R/W  R/W R/W R/W  R/W R/W R/W  R/W R/W R/W  R/W R/W R/W  R/W R/W R/W  R/W R/W R/W  R/W R/W R/W  R/W R/W R/W  R/W R/W R/W  26-22 ML610Q438/ML610Q439 User’s Manual Chapter 26 LCD Drivers Table 26-4 Register name Address DSPR68 DSPR69 DSPR6A Not used DSPR6C DSPR6D DSPR6E Not used DSPR70 DSPR71 DSPR72 Not used DSPR74 DSPR75 DSPR76 Not used DSPR78 DSPR79 DSPR7A Not used DSPR7C DSPR7D DSPR7E Not used DSPR80 DSPR81 DSPR82 Not used DSPR84 DSPR85 DSPR86 Not used DSPR88 DSPR89 DSPR8A Not used DSPR8C DSPR8D DSPR8E Not used DSPR90 DSPR91 DSPR92 Not used DSPR94 DSPR95 DSPR96 Not used DSPR98 DSPR99 DSPR9A Not used 0F168H 0F169H 0F16AH 0F16BH 0F16CH 0F16DH 0F16EH 0F16FH 0F170H 0F171H 0F172H 0F173H 0F174H 0F175H 0F176H 0F177H 0F178H 0F179H 0F17AH 0F17BH 0F17CH 0F17DH 0F17EH 0F17FH 0F180H 0F181H 0F182H 0F183H 0F184H 0F185H 0F186H 0F187H 0F188H 0F189H 0F18AH 0F18BH 0F18CH 0F18DH 0F18EH 0F18FH 0F190H 0F191H 0F192H 0F193H 0F194H 0F195H 0F196H 0F197H 0F198H 0F199H 0F19AH 0F19BH FEUL610Q438 Segment Map Type 1 of Display Registers (3/5) Corresponding segment SEG26  SEG27  SEG28  SEG29  SEG30  SEG31  SEG32  SEG33  SEG34  SEG35  SEG36  SEG37  SEG38  bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 R/W c7 c15 c23  c7 c15 c23  c7 c15 c23  c7 c15 c23  c7 c15 c23  c7 c15 c23  c7 c15 c23  c7 c15 c23  c7 c15 c23  c7 c15 c23  c7 c15 c23  c7 c15 c23  c7 c15 c23  c6 c14 c22  c6 c14 c22  c6 c14 c22  c6 c14 c22  c6 c14 c22  c6 c14 c22  c6 c14 c22  c6 c14 c22  c6 c14 c22  c6 c14 c22  c6 c14 c22  c6 c14 c22  c6 c14 c22  c5 c13 c21  c5 c13 c21  c5 c13 c21  c5 c13 c21  c5 c13 c21  c5 c13 c21  c5 c13 c21  c5 c13 c21  c5 c13 c21  c5 c13 c21  c5 c13 c21  c5 c13 c21  c5 c13 c21  c4 c12 c20  c4 c12 c20  c4 c12 c20  c4 c12 c20  c4 c12 c20  c4 c12 c20  c4 c12 c20  c4 c12 c20  c4 c12 c20  c4 c12 c20  c4 c12 c20  c4 c12 c20  c4 c12 c20  c3 c11 c19  c3 c11 c19  c3 c11 c19  c3 c11 c19  c3 c11 c19  c3 c11 c19  c3 c11 c19  c3 c11 c19  c3 c11 c19  c3 c11 c19  c3 c11 c19  c3 c11 c19  c3 c11 c19  c2 c10 c18  c2 c10 c18  c2 c10 c18  c2 c10 c18  c2 c10 c18  c2 c10 c18  c2 c10 c18  c2 c10 c18  c2 c10 c18  c2 c10 c18  c2 c10 c18  c2 c10 c18  c2 c10 c18  c1 c9 c17  c1 c9 c17  c1 c9 c17  c1 c9 c17  c1 c9 c17  c1 c9 c17  c1 c9 c17  c1 c9 c17  c1 c9 c17  c1 c9 c17  c1 c9 c17  c1 c9 c17  c1 c9 c17  c0 c8 c16  c0 c8 c16  c0 c8 c16  c0 c8 c16  c0 c8 c16  c0 c8 c16  c0 c8 c16  c0 c8 c16  c0 c8 c16  c0 c8 c16  c0 c8 c16  c0 c8 c16  c0 c8 c16  R/W R/W R/W  R/W R/W R/W  R/W R/W R/W  R/W R/W R/W  R/W R/W R/W  R/W R/W R/W  R/W R/W R/W  R/W R/W R/W  R/W R/W R/W  R/W R/W R/W  R/W R/W R/W  R/W R/W R/W  R/W R/W R/W  26-23 ML610Q438/ML610Q439 User’s Manual Chapter 26 LCD Drivers Table 26-4 Register name Address DSPR9C DSPR9D DSPR9E Not used DSPRA0 DSPRA1 DSPRA2 Not used DSPRA4 DSPRA5 DSPRA6 Not used DSPRA8 DSPRA9 DSPRAA Not used DSPRAC DSPRAD DSPRAE Not used DSPRB0 DSPRB1 DSPRB2 Not used DSPRB4 DSPRB5 DSPRB6 Not used DSPRB8 DSPRB9 DSPRBA Not used DSPRBC DSPRBD DSPRBE Not used DSPRC0 DSPRC1 DSPRC2 Not used DSPRC4 DSPRC5 DSPRC6 Not used DSPRC8 DSPRC9 DSPRCA Not used DSPRCC DSPRCD DSPRCE 0F19CH 0F19DH 0F19EH 0F19FH 0F1A0H 0F1A1H 0F1A2H 0F1A3H 0F1A4H 0F1A5H 0F1A6H 0F1A7H 0F1A8H 0F1A9H 0F1AAH 0F1ABH 0F1ACH 0F1ADH 0F1AEH 0F1AFH 0F1B0H 0F1B1H 0F1B2H 0F1B3H 0F1B4H 0F1B5H 0F1B6H 0F1B7H 0F1B8H 0F1B9H 0F1BAH 0F1BBH 0F1BCH 0F1BDH 0F1BEH 0F1BFH 0F1C0H 0F1C1H 0F1C2H 0F1C3H 0F1C4H 0F1C5H 0F1C6H 0F1C7H 0F1C8H 0F1C9H 0F1CAH 0F1CBH 0F1CCH 0F1CDH 0F1CEH FEUL610Q438 Segment Map Type 1 of Display Registers (4/5) Corresponding segment SEG39  SEG40  SEG41  SEG42  SEG43  SEG44  SEG45  SEG46  SEG47  SEG48  SEG49  SEG50  SEG51 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 R/W c7 c15 c23  c7 c15 c23  c7 c15 c23  c7 c15 c23  c7 c15 c23  c7 c15 c23  c7 c15 c23  c7 c15 c23  c7 c15 c23  c7 c15 c23  c7 c15 c23  c7 c15 c23  c7 c15 c23 c6 c14 c22  c6 c14 c22  c6 c14 c22  c6 c14 c22  c6 c14 c22  c6 c14 c22  c6 c14 c22  c6 c14 c22  c6 c14 c22  c6 c14 c22  c6 c14 c22  c6 c14 c22  c6 c14 c22 c5 c13 c21  c5 c13 c21  c5 c13 c21  c5 c13 c21  c5 c13 c21  c5 c13 c21  c5 c13 c21  c5 c13 c21  c5 c13 c21  c5 c13 c21  c5 c13 c21  c5 c13 c21  c5 c13 c21 c4 c12 c20  c4 c12 c20  c4 c12 c20  c4 c12 c20  c4 c12 c20  c4 c12 c20  c4 c12 c20  c4 c12 c20  c4 c12 c20  c4 c12 c20  c4 c12 c20  c4 c12 c20  c4 c12 c20 c3 c11 c19  c3 c11 c19  c3 c11 c19  c3 c11 c19  c3 c11 c19  c3 c11 c19  c3 c11 c19  c3 c11 c19  c3 c11 c19  c3 c11 c19  c3 c11 c19  c3 c11 c19  c3 c11 c19 c2 c10 c18  c2 c10 c18  c2 c10 c18  c2 c10 c18  c2 c10 c18  c2 c10 c18  c2 c10 c18  c2 c10 c18  c2 c10 c18  c2 c10 c18  c2 c10 c18  c2 c10 c18  c2 c10 c18 c1 c9 c17  c1 c9 c17  c1 c9 c17  c1 c9 c17  c1 c9 c17  c1 c9 c17  c1 c9 c17  c1 c9 c17  c1 c9 c17  c1 c9 c17  c1 c9 c17  c1 c9 c17  c1 c9 c17 c0 c8 c16  c0 c8 c16  c0 c8 c16  c0 c8 c16  c0 c8 c16  c0 c8 c16  c0 c8 c16  c0 c8 c16  c0 c8 c16  c0 c8 c16  c0 c8 c16  c0 c8 c16  c0 c8 c16 R/W R/W R/W  R/W R/W R/W  R/W R/W R/W  R/W R/W R/W  R/W R/W R/W  R/W R/W R/W  R/W R/W R/W  R/W R/W R/W  R/W R/W R/W  R/W R/W R/W  R/W R/W R/W  R/W R/W R/W  R/W R/W R/W 26-24 ML610Q438/ML610Q439 User’s Manual Chapter 26 LCD Drivers Table 26-4 Register name Address DSPRD0 DSPRD1 DSPRD2 Not used DSPRD4 DSPRD5 DSPRD6 Not used DSPRD8 DSPRD9 DSPRDA Not used DSPRDC DSPRDD DSPRDE Not used DSPRE0 DSPRE1 DSPRE2 Not used DSPRE4 DSPRE5 DSPRE6 Not used DSPRE8 DSPRE9 DSPREA Not used DSPREC DSPRED DSPREE Not used DSPRF0 DSPRF1 DSPRF2 Not used DSPRF4 DSPRF5 DSPRF6 Not used DSPRF8 DSPRF9 DSPRFA Not used DSPRFC DSPRFD DSPRFE Not used 0F1D0H 0F1D1H 0F1D2H 0F1D3H 0F1D4H 0F1D5H 0F1D6H 0F1D7H 0F1D8H 0F1D9H 0F1DAH 0F1DBH 0F1DCH 0F1DDH 0F1DEH 0F1DFH 0F1E0H 0F1E1H 0F1E2H 0F1E3H 0F1E4H 0F1E5H 0F1E6H 0F1E7H 0F1E8H 0F1E9H 0F1EAH 0F1EBH 0F1ECH 0F1EDH 0F1EEH 0F1EFH 0F1F0H 0F1F1H 0F1F2H 0F1F3H 0F1F4H 0F1F5H 0F1F6H 0F1F7H 0F1F8H 0F1F9H 0F1FAH 0F1FBH 0F1FCH 0F1FDH 0F1FEH 0F1FFH FEUL610Q438 Segment Map Type 1 of Display Registers (5/5) Corresponding segment SEG52  SEG53  SEG54  SEG55  SEG56  SEG57  SEG58  SEG59  SEG60  SEG61  SEG62  SEG63  bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 R/W c7 c15 c23  c7 c15 c23  c7 c15 c23  c7 c15 c23  c7 c15 c23  c7 c15 c23  c7 c15 c23  c7 c15 c23  c7 c15 c23  c7 c15 c23  c7 c15 c23  c7 c15 c23  c6 c14 c22  c6 c14 c22  c6 c14 c22  c6 c14 c22  c6 c14 c22  c6 c14 c22  c6 c14 c22  c6 c14 c22  c6 c14 c22  c6 c14 c22  c6 c14 c22  c6 c14 c22  c5 c13 c21  c5 c13 c21  c5 c13 c21  c5 c13 c21  c5 c13 c21  c5 c13 c21  c5 c13 c21  c5 c13 c21  c5 c13 c21  c5 c13 c21  c5 c13 c21  c5 c13 c21  c4 c12 c20  c4 c12 c20  c4 c12 c20  c4 c12 c20  c4 c12 c20  c4 c12 c20  c4 c12 c20  c4 c12 c20  c4 c12 c20  c4 c12 c20  c4 c12 c20  c4 c12 c20  c3 c11 c19  c3 c11 c19  c3 c11 c19  c3 c11 c19  c3 c11 c19  c3 c11 c19  c3 c11 c19  c3 c11 c19  c3 c11 c19  c3 c11 c19  c3 c11 c19  c3 c11 c19  c2 c10 c18  c2 c10 c18  c2 c10 c18  c2 c10 c18  c2 c10 c18  c2 c10 c18  c2 c10 c18  c2 c10 c18  c2 c10 c18  c2 c10 c18  c2 c10 c18  c2 c10 c18  c1 c9 c17  c1 c9 c17  c1 c9 c17  c1 c9 c17  c1 c9 c17  c1 c9 c17  c1 c9 c17  c1 c9 c17  c1 c9 c17  c1 c9 c17  c1 c9 c17  c1 c9 c17  c0 c8 c16  c0 c8 c16  c0 c8 c16  c0 c8 c16  c0 c8 c16  c0 c8 c16  c0 c8 c16  c0 c8 c16  c0 c8 c16  c0 c8 c16  c0 c8 c16  c0 c8 c16  R/W R/W R/W  R/W R/W R/W  R/W R/W R/W  R/W R/W R/W  R/W R/W R/W  R/W R/W R/W  R/W R/W R/W  R/W R/W R/W  R/W R/W R/W  R/W R/W R/W  R/W R/W R/W  R/W R/W R/W  26-25 ML610Q438/ML610Q439 User’s Manual Chapter 26 LCD Drivers Table 26-5 Register name Address DSPR00 DSPR01 DSPR02 DSPR03 DSPR04 DSPR05 DSPR06 DSPR07 DSPR08 DSPR09 DSPR0A DSPR0B DSPR0C DSPR0D DSPR0E DSPR0F DSPR10 DSPR11 DSPR12 DSPR13 DSPR14 DSPR15 DSPR16 DSPR17 DSPR18 DSPR19 DSPR1A DSPR1B DSPR1C DSPR1D DSPR1E DSPR1F DSPR20 DSPR21 DSPR22 DSPR23 DSPR24 DSPR25 DSPR26 DSPR27 DSPR28 DSPR29 DSPR2A DSPR2B DSPR2C DSPR2D DSPR2E DSPR2F DSPR30 DSPR31 DSPR32 DSPR33 0F100H 0F101H 0F102H 0F103H 0F104H 0F105H 0F106H 0F107H 0F108H 0F109H 0F10AH 0F10BH 0F10CH 0F10DH 0F10EH 0F10FH 0F110H 0F111H 0F112H 0F113H 0F114H 0F115H 0F116H 0F117H 0F118H 0F119H 0F11AH 0F11BH 0F11CH 0F11DH 0F11EH 0F11FH 0F120H 0F121H 0F122H 0F123H 0F124H 0F125H 0F126H 0F127H 0F128H 0F129H 0F12AH 0F12BH 0F12CH 0F12DH 0F12EH 0F12FH 0F130H 0F131H 0F132H 0F133H FEUL610Q438 Segment Map Type 2 of Display Registers (1/5) Corresponding segment SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 R/W c7 c15 c7 c15 c7 c15 c7 c15 c7 c15 c7 c15 c7 c15 c7 c15 c7 c15 c7 c15 c7 c15 c7 c15 c7 c15 c7 c15 c7 c15 c7 c15 c7 c15 c7 c15 c7 c15 c7 c15 c7 c15 c7 c15 c7 c15 c7 c15 c7 c15 c7 c15 c6 c14 c6 c14 c6 c14 c6 c14 c6 c14 c6 c14 c6 c14 c6 c14 c6 c14 c6 c14 c6 c14 c6 c14 c6 c14 c6 c14 c6 c14 c6 c14 c6 c14 c6 c14 c6 c14 c6 c14 c6 c14 c6 c14 c6 c14 c6 c14 c6 c14 c6 c14 c5 c13 c5 c13 c5 c13 c5 c13 c5 c13 c5 c13 c5 c13 c5 c13 c5 c13 c5 c13 c5 c13 c5 c13 c5 c13 c5 c13 c5 c13 c5 c13 c5 c13 c5 c13 c5 c13 c5 c13 c5 c13 c5 c13 c5 c13 c5 c13 c5 c13 c5 c13 c4 c12 c4 c12 c4 c12 c4 c12 c4 c12 c4 c12 c4 c12 c4 c12 c4 c12 c4 c12 c4 c12 c4 c12 c4 c12 c4 c12 c4 c12 c4 c12 c4 c12 c4 c12 c4 c12 c4 c12 c4 c12 c4 c12 c4 c12 c4 c12 c4 c12 c4 c12 c3 c11 c3 c11 c3 c11 c3 c11 c3 c11 c3 c11 c3 c11 c3 c11 c3 c11 c3 c11 c3 c11 c3 c11 c3 c11 c3 c11 c3 c11 c3 c11 c3 c11 c3 c11 c3 c11 c3 c11 c3 c11 c3 c11 c3 c11 c3 c11 c3 c11 c3 c11 c2 c10 c2 c10 c2 c10 c2 c10 c2 c10 c2 c10 c2 c10 c2 c10 c2 c10 c2 c10 c2 c10 c2 c10 c2 c10 c2 c10 c2 c10 c2 c10 c2 c10 c2 c10 c2 c10 c2 c10 c2 c10 c2 c10 c2 c10 c2 c10 c2 c10 c2 c10 c1 c9 c1 c9 c1 c9 c1 c9 c1 c9 c1 c9 c1 c9 c1 c9 c1 c9 c1 c9 c1 c9 c1 c9 c1 c9 c1 c9 c1 c9 c1 c9 c1 c9 c1 c9 c1 c9 c1 c9 c1 c9 c1 c9 c1 c9 c1 c9 c1 c9 c1 c9 c0 c8 c0 c8 c0 c8 c0 c8 c0 c8 c0 c8 c0 c8 c0 c8 c0 c8 c0 c8 c0 c8 c0 c8 c0 c8 c0 c8 c0 c8 c0 c8 c0 c8 c0 c8 c0 c8 c0 c8 c0 c8 c0 c8 c0 c8 c0 c8 c0 c8 c0 c8 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 26-26 ML610Q438/ML610Q439 User’s Manual Chapter 26 LCD Drivers Table 26-5 Register name Address DSPR34 DSPR35 DSPR36 DSPR37 DSPR38 DSPR39 DSPR3A DSPR3B DSPR3C DSPR3D DSPR3E DSPR3F DSPR40 DSPR41 DSPR42 DSPR43 DSPR44 DSPR45 DSPR46 DSPR47 DSPR48 DSPR49 DSPR4A DSPR4B DSPR4C DSPR4D DSPR4E DSPR4F DSPR50 DSPR51 DSPR52 DSPR53 DSPR54 DSPR55 DSPR56 DSPR57 DSPR58 DSPR59 DSPR5A DSPR5B DSPR5C DSPR5D DSPR5E DSPR5F DSPR60 DSPR61 DSPR62 DSPR63 DSPR64 DSPR65 DSPR66 DSPR67 0F134H 0F135H 0F136H 0F137H 0F138H 0F139H 0F13AH 0F13BH 0F13CH 0F13DH 0F13EH 0F13FH 0F140H 0F141H 0F142H 0F143H 0F144H 0F145H 0F146H 0F147H 0F148H 0F149H 0F14AH 0F14BH 0F14CH 0F14DH 0F14EH 0F14FH 0F150H 0F151H 0F152H 0F153H 0F154H 0F155H 0F156H 0F157H 0F158H 0F159H 0F15AH 0F15BH 0F15CH 0F15DH 0F15EH 0F15FH 0F160H 0F161H 0F162H 0F163H 0F164H 0F165H 0F166H 0F167H FEUL610Q438 Segment Map Type 2 of Display Registers (2/5) Corresponding segment SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 R/W c7 c15 c7 c15 c7 c15 c7 c15 c7 c15 c7 c15 c7 c15 c7 c15 c7 c15 c7 c15 c7 c15 c7 c15 c7 c15 c7 c15 c7 c15 c7 c15 c7 c15 c7 c15 c7 c15 c7 c15 c7 c15 c7 c15 c7 c15 c7 c15 c7 c15 c7 c15 c6 c14 c6 c14 c6 c14 c6 c14 c6 c14 c6 c14 c6 c14 c6 c14 c6 c14 c6 c14 c6 c14 c6 c14 c6 c14 c6 c14 c6 c14 c6 c14 c6 c14 c6 c14 c6 c14 c6 c14 c6 c14 c6 c14 c6 c14 c6 c14 c6 c14 c6 c14 c5 c13 c5 c13 c5 c13 c5 c13 c5 c13 c5 c13 c5 c13 c5 c13 c5 c13 c5 c13 c5 c13 c5 c13 c5 c13 c5 c13 c5 c13 c5 c13 c5 c13 c5 c13 c5 c13 c5 c13 c5 c13 c5 c13 c5 c13 c5 c13 c5 c13 c5 c13 c4 c12 c4 c12 c4 c12 c4 c12 c4 c12 c4 c12 c4 c12 c4 c12 c4 c12 c4 c12 c4 c12 c4 c12 c4 c12 c4 c12 c4 c12 c4 c12 c4 c12 c4 c12 c4 c12 c4 c12 c4 c12 c4 c12 c4 c12 c4 c12 c4 c12 c4 c12 c3 c11 c3 c11 c3 c11 c3 c11 c3 c11 c3 c11 c3 c11 c3 c11 c3 c11 c3 c11 c3 c11 c3 c11 c3 c11 c3 c11 c3 c11 c3 c11 c3 c11 c3 c11 c3 c11 c3 c11 c3 c11 c3 c11 c3 c11 c3 c11 c3 c11 c3 c11 c2 c10 c2 c10 c2 c10 c2 c10 c2 c10 c2 c10 c2 c10 c2 c10 c2 c10 c2 c10 c2 c10 c2 c10 c2 c10 c2 c10 c2 c10 c2 c10 c2 c10 c2 c10 c2 c10 c2 c10 c2 c10 c2 c10 c2 c10 c2 c10 c2 c10 c2 c10 c1 c9 c1 c9 c1 c9 c1 c9 c1 c9 c1 c9 c1 c9 c1 c9 c1 c9 c1 c9 c1 c9 c1 c9 c1 c9 c1 c9 c1 c9 c1 c9 c1 c9 c1 c9 c1 c9 c1 c9 c1 c9 c1 c9 c1 c9 c1 c9 c1 c9 c1 c9 c0 c8 c0 c8 c0 c8 c0 c8 c0 c8 c0 c8 c0 c8 c0 c8 c0 c8 c0 c8 c0 c8 c0 c8 c0 c8 c0 c8 c0 c8 c0 c8 c0 c8 c0 c8 c0 c8 c0 c8 c0 c8 c0 c8 c0 c8 c0 c8 c0 c8 c0 c8 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 26-27 ML610Q438/ML610Q439 User’s Manual Chapter 26 LCD Drivers Table 26-5 Register name Address DSPR68 DSPR69 DSPR6A DSPR6B DSPR6C DSPR6D DSPR6E DSPR6F DSPR70 DSPR71 DSPR72 DSPR73 DSPR74 DSPR75 DSPR76 DSPR77 DSPR78 DSPR79 DSPR7A DSPR7B DSPR7C DSPR7D DSPR7E DSPR7F DSPR80 Not used DSPR82 Not used DSPR84 Not used DSPR86 Not used DSPR88 Not used DSPR8A Not used DSPR8C Not used DSPR8E Not used DSPR90 Not used DSPR92 Not used DSPR94 Not used DSPR96 Not used DSPR98 Not used DSPR9A Not used 0F168H 0F169H 0F16AH 0F16BH 0F16CH 0F16DH 0F16EH 0F16FH 0F170H 0F171H 0F172H 0F173H 0F174H 0F175H 0F176H 0F177H 0F178H 0F179H 0F17AH 0F17BH 0F17CH 0F17DH 0F17EH 0F17FH 0F180H 0F181H 0F182H 0F183H 0F184H 0F185H 0F186H 0F187H 0F188H 0F189H 0F18AH 0F18BH 0F18CH 0F18DH 0F18EH 0F18FH 0F190H 0F191H 0F192H 0F193H 0F194H 0F195H 0F196H 0F197H 0F198H 0F199H 0F19AH 0F19BH FEUL610Q438 Segment Map Type 2 of Display Registers (3/5) Corresponding segment SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG0  SEG1  SEG2  SEG3  SEG4  SEG5  SEG6  SEG7  SEG8  SEG9  SEG10  SEG11  SEG12  SEG13  bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 R/W c7 c15 c7 c15 c7 c15 c7 c15 c7 c15 c7 c15 c7 c15 c7 c15 c7 c15 c7 c15 c7 c15 c7 c15 c23  c23  c23  c23  c23  c23  c23  c23  c23  c23  c23  c23  c23  c23  c6 c14 c6 c14 c6 c14 c6 c14 c6 c14 c6 c14 c6 c14 c6 c14 c6 c14 c6 c14 c6 c14 c6 c14 c22  c22  c22  c22  c22  c22  c22  c22  c22  c22  c22  c22  c22  c22  c5 c13 c5 c13 c5 c13 c5 c13 c5 c13 c5 c13 c5 c13 c5 c13 c5 c13 c5 c13 c5 c13 c5 c13 c21  c21  c21  c21  c21  c21  c21  c21  c21  c21  c21  c21  c21  c21  c4 c12 c4 c12 c4 c12 c4 c12 c4 c12 c4 c12 c4 c12 c4 c12 c4 c12 c4 c12 c4 c12 c4 c12 c20  c20  c20  c20  c20  c20  c20  c20  c20  c20  c20  c20  c20  c20  c3 c11 c3 c11 c3 c11 c3 c11 c3 c11 c3 c11 c3 c11 c3 c11 c3 c11 c3 c11 c3 c11 c3 c11 c19  c19  c19  c19  c19  c19  c19  c19  c19  c19  c19  c19  c19  c19  c2 c10 c2 c10 c2 c10 c2 c10 c2 c10 c2 c10 c2 c10 c2 c10 c2 c10 c2 c10 c2 c10 c2 c10 c18  c18  c18  c18  c18  c18  c18  c18  c18  c18  c18  c18  c18  c18  c1 c9 c1 c9 c1 c9 c1 c9 c1 c9 c1 c9 c1 c9 c1 c9 c1 c9 c1 c9 c1 c9 c1 c9 c17  c17  c17  c17  c17  c17  c17  c17  c17  c17  c17  c17  c17  c17  c0 c8 c0 c8 c0 c8 c0 c8 c0 c8 c0 c8 c0 c8 c0 c8 c0 c8 c0 c8 c0 c8 c0 c8 c16  c16  c16  c16  c16  c16  c16  c16  c16  c16  c16  c16  c16  c16  R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W  R/W  R/W  R/W  R/W  R/W  R/W  R/W  R/W  R/W  R/W  R/W  R/W  R/W  26-28 ML610Q438/ML610Q439 User’s Manual Chapter 26 LCD Drivers Table 26-5 Register name Address DSPR9C Not used DSPR9E Not used DSPRA0 Not used DSPRA2 Not used DSPRA4 Not used DSPRA6 Not used DSPRA8 Not used DSPRAA Not used DSPRAC Not used DSPRAE Not used DSPRB0 Not used DSPRB2 Not used DSPRB4 Not used DSPRB6 Not used DSPRB8 Not used DSPRBA Not used DSPRBC Not used DSPRBE Not used DSPRC0 Not used DSPRC2 Not used DSPRC4 Not used DSPRC6 Not used DSPRC8 Not used DSPRCA Not used DSPRCC Not used DSPRCE Not used 0F19CH 0F19DH 0F19EH 0F19FH 0F1A0H 0F1A1H 0F1A2H 0F1A3H 0F1A4H 0F1A5H 0F1A6H 0F1A7H 0F1A8H 0F1A9H 0F1AAH 0F1ABH 0F1ACH 0F1ADH 0F1AEH 0F1AFH 0F1B0H 0F1B1H 0F1B2H 0F1B3H 0F1B4H 0F1B5H 0F1B6H 0F1B7H 0F1B8H 0F1B9H 0F1BAH 0F1BBH 0F1BCH 0F1BDH 0F1BEH 0F1BFH 0F1C0H 0F1C1H 0F1C2H 0F1C3H 0F1C4H 0F1C5H 0F1C6H 0F1C7H 0F1C8H 0F1C9H 0F1CAH 0F1CBH 0F1CCH 0F1CDH 0F1CEH 0F1CFH FEUL610Q438 Segment Map Type 2 of Display Registers (4/5) Corresponding segment SEG14  SEG15  SEG16  SEG17  SEG18  SEG19  SEG20  SEG21  SEG22  SEG23  SEG24  SEG25  SEG26  SEG27  SEG28  SEG29  SEG30  SEG31  SEG32  SEG33  SEG34  SEG35  SEG36  SEG37  SEG38  SEG39  bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 R/W c23  c23  c23  c23  c23  c23  c23  c23  c23  c23  c23  c23  c23  c23  c23  c23  c23  c23  c23  c23  c23  c23  c23  c23  c23  c23  c22  c22  c22  c22  c22  c22  c22  c22  c22  c22  c22  c22  c22  c22  c22  c22  c22  c22  c22  c22  c22  c22  c22  c22  c22  c22  c21  c21  c21  c21  c21  c21  c21  c21  c21  c21  c21  c21  c21  c21  c21  c21  c21  c21  c21  c21  c21  c21  c21  c21  c21  c21  c20  c20  c20  c20  c20  c20  c20  c20  c20  c20  c20  c20  c20  c20  c20  c20  c20  c20  c20  c20  c20  c20  c20  c20  c20  c20  c19  c19  c19  c19  c19  c19  c19  c19  c19  c19  c19  c19  c19  c19  c19  c19  c19  c19  c19  c19  c19  c19  c19  c19  c19  c19  c18  c18  c18  c18  c18  c18  c18  c18  c18  c18  c18  c18  c18  c18  c18  c18  c18  c18  c18  c18  c18  c18  c18  c18  c18  c18  c17  c17  c17  c17  c17  c17  c17  c17  c17  c17  c17  c17  c17  c17  c17  c17  c17  c17  c17  c17  c17  c17  c17  c17  c17  c17  c16  c16  c16  c16  c16  c16  c16  c16  c16  c16  c16  c16  c16  c16  c16  c16  c16  c16  c16  c16  c16  c16  c16  c16  c16  c16  R/W  R/W  R/W  R/W  R/W  R/W  R/W  R/W  R/W  R/W  R/W  R/W  R/W  R/W  R/W  R/W  R/W  R/W  R/W  R/W  R/W  R/W  R/W  R/W  R/W  R/W  26-29 ML610Q438/ML610Q439 User’s Manual Chapter 26 LCD Drivers Table 26-5 Register name Address DSPRD0 Not used DSPRD2 Not used DSPRD4 Not used DSPRD6 Not used DSPRD8 Not used DSPRDA Not used DSPRDC Not used DSPRDE Not used DSPRE0 Not used DSPRE2 Not used DSPRE4 Not used DSPRE6 Not used DSPRE8 Not used DSPREA Not used DSPREC Not used DSPREE Not used DSPRF0 Not used DSPRF2 Not used DSPRF4 Not used DSPRF6 Not used DSPRF8 Not used DSPRFA Not used DSPRFC Not used DSPRFE Not used 0F1D0H 0F1D1H 0F1D2H 0F1D3H 0F1D4H 0F1D5H 0F1D6H 0F1D7H 0F1D8H 0F1D9H 0F1DAH 0F1DBH 0F1DCH 0F1DDH 0F1DEH 0F1DFH 0F1E0H 0F1E1H 0F1E2H 0F1E3H 0F1E4H 0F1E5H 0F1E6H 0F1E7H 0F1E8H 0F1E9H 0F1EAH 0F1EBH 0F1ECH 0F1EDH 0F1EEH 0F1EFH 0F1F0H 0F1F1H 0F1F2H 0F1F3H 0F1F4H 0F1F5H 0F1F6H 0F1F7H 0F1F8H 0F1F9H 0F1FAH 0F1FBH 0F1FCH 0F1FDH 0F1FEH 0F1FFH FEUL610Q438 Segment Map Type 2 of Display Registers (5/5) Corresponding segment SEG40  SEG41  SEG42  SEG43  SEG44  SEG45  SEG46  SEG47  SEG48  SEG49  SEG50  SEG51  SEG52  SEG53  SEG54  SEG55  SEG56  SEG57  SEG58  SEG59  SEG60  SEG61  SEG62  SEG63  bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 R/W c23  c23  c23  c23  c23  c23  c23  c23  c23  c23  c23  c23  c23  c23  c23  c23  c23  c23  c23  c23  c23  c23  c23  c23  c22  c22  c22  c22  c22  c22  c22  c22  c22  c22  c22  c22  c22  c22  c22  c22  c22  c22  c22  c22  c22  c22  c22  c22  c21  c21  c21  c21  c21  c21  c21  c21  c21  c21  c21  c21  c21  c21  c21  c21  c21  c21  c21  c21  c21  c21  c21  c21  c20  c20  c20  c20  c20  c20  c20  c20  c20  c20  c20  c20  c20  c20  c20  c20  c20  c20  c20  c20  c20  c20  c20  c20  c19  c19  c19  c19  c19  c19  c19  c19  c19  c19  c19  c19  c19  c19  c19  c19  c19  c19  c19  c19  c19  c19  c19  c19  c18  c18  c18  c18  c18  c18  c18  c18  c18  c18  c18  c18  c18  c18  c18  c18  c18  c18  c18  c18  c18  c18  c18  c18  c17  c17  c17  c17  c17  c17  c17  c17  c17  c17  c17  c17  c17  c17  c17  c17  c17  c17  c17  c17  c17  c17  c17  c17  c16  c16  c16  c16  c16  c16  c16  c16  c16  c16  c16  c16  c16  c16  c16  c16  c16  c16  c16  c16  c16  c16  c16  c16  R/W  R/W  R/W  R/W  R/W  R/W  R/W  R/W  R/W  R/W  R/W  R/W  R/W  R/W  R/W  R/W  R/W  R/W  R/W  R/W  R/W  R/W  R/W  R/W  26-30 ML610Q438/ML610Q439 User’s Manual Chapter 26 LCD Drivers Table 26-6 Register name Address DSPR00 DSPR01 DSPR02 DSPR03 DSPR04 DSPR05 DSPR06 DSPR07 DSPR08 DSPR09 DSPR0A DSPR0B DSPR0C DSPR0D DSPR0E DSPR0F DSPR10 DSPR11 DSPR12 DSPR13 DSPR14 DSPR15 DSPR16 DSPR17 DSPR18 DSPR19 DSPR1A DSPR1B DSPR1C DSPR1D DSPR1E DSPR1F DSPR20 DSPR21 DSPR22 DSPR23 DSPR24 DSPR25 DSPR26 DSPR27 DSPR28 DSPR29 DSPR2A DSPR2B DSPR2C DSPR2D DSPR2E DSPR2F DSPR30 DSPR31 DSPR32 DSPR33 0F100H 0F101H 0F102H 0F103H 0F104H 0F105H 0F106H 0F107H 0F108H 0F109H 0F10AH 0F10BH 0F10CH 0F10DH 0F10EH 0F10FH 0F110H 0F111H 0F112H 0F113H 0F114H 0F115H 0F116H 0F117H 0F118H 0F119H 0F11AH 0F11BH 0F11CH 0F11DH 0F11EH 0F11FH 0F120H 0F121H 0F122H 0F123H 0F124H 0F125H 0F126H 0F127H 0F128H 0F129H 0F12AH 0F12BH 0F12CH 0F12DH 0F12EH 0F12FH 0F130H 0F131H 0F132H 0F133H FEUL610Q438 Segment Map Type 3 of Display Registers (1/4) Corresponding segment SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 R/W c7 c7 c7 c7 c7 c7 c7 c7 c7 c7 c7 c7 c7 c7 c7 c7 c7 c7 c7 c7 c7 c7 c7 c7 c7 c7 c7 c7 c7 c7 c7 c7 c7 c7 c7 c7 c7 c7 c7 c7 c7 c7 c7 c7 c7 c7 c7 c7 c7 c7 c7 c7 c6 c6 c6 c6 c6 c6 c6 c6 c6 c6 c6 c6 c6 c6 c6 c6 c6 c6 c6 c6 c6 c6 c6 c6 c6 c6 c6 c6 c6 c6 c6 c6 c6 c6 c6 c6 c6 c6 c6 c6 c6 c6 c6 c6 c6 c6 c6 c6 c6 c6 c6 c6 c5 c5 c5 c5 c5 c5 c5 c5 c5 c5 c5 c5 c5 c5 c5 c5 c5 c5 c5 c5 c5 c5 c5 c5 c5 c5 c5 c5 c5 c5 c5 c5 c5 c5 c5 c5 c5 c5 c5 c5 c5 c5 c5 c5 c5 c5 c5 c5 c5 c5 c5 c5 c4 c4 c4 c4 c4 c4 c4 c4 c4 c4 c4 c4 c4 c4 c4 c4 c4 c4 c4 c4 c4 c4 c4 c4 c4 c4 c4 c4 c4 c4 c4 c4 c4 c4 c4 c4 c4 c4 c4 c4 c4 c4 c4 c4 c4 c4 c4 c4 c4 c4 c4 c4 c3 c3 c3 c3 c3 c3 c3 c3 c3 c3 c3 c3 c3 c3 c3 c3 c3 c3 c3 c3 c3 c3 c3 c3 c3 c3 c3 c3 c3 c3 c3 c3 c3 c3 c3 c3 c3 c3 c3 c3 c3 c3 c3 c3 c3 c3 c3 c3 c3 c3 c3 c3 c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 c1 c1 c1 c1 c1 c1 c1 c1 c1 c1 c1 c1 c1 c1 c1 c1 c1 c1 c1 c1 c1 c1 c1 c1 c1 c1 c1 c1 c1 c1 c1 c1 c1 c1 c1 c1 c1 c1 c1 c1 c1 c1 c1 c1 c1 c1 c1 c1 c1 c1 c1 c1 c0 c0 c0 c0 c0 c0 c0 c0 c0 c0 c0 c0 c0 c0 c0 c0 c0 c0 c0 c0 c0 c0 c0 c0 c0 c0 c0 c0 c0 c0 c0 c0 c0 c0 c0 c0 c0 c0 c0 c0 c0 c0 c0 c0 c0 c0 c0 c0 c0 c0 c0 c0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 26-31 ML610Q438/ML610Q439 User’s Manual Chapter 26 LCD Drivers Table 26-6 Register name Address DSPR34 DSPR35 DSPR36 DSPR37 DSPR38 DSPR39 DSPR3A DSPR3B DSPR3C DSPR3D DSPR3E DSPR3F DSPR40 DSPR41 DSPR42 DSPR43 DSPR44 DSPR45 DSPR46 DSPR47 DSPR48 DSPR49 DSPR4A DSPR4B DSPR4C DSPR4D DSPR4E DSPR4F DSPR50 DSPR51 DSPR52 DSPR53 DSPR54 DSPR55 DSPR56 DSPR57 DSPR58 DSPR59 DSPR5A DSPR5B DSPR5C DSPR5D DSPR5E DSPR5F DSPR60 DSPR61 DSPR62 DSPR63 DSPR64 DSPR65 DSPR66 DSPR67 0F134H 0F135H 0F136H 0F137H 0F138H 0F139H 0F13AH 0F13BH 0F13CH 0F13DH 0F13EH 0F13FH 0F140H 0F141H 0F142H 0F143H 0F144H 0F145H 0F146H 0F147H 0F148H 0F149H 0F14AH 0F14BH 0F14CH 0F14DH 0F14EH 0F14FH 0F150H 0F151H 0F152H 0F153H 0F154H 0F155H 0F156H 0F157H 0F158H 0F159H 0F15AH 0F15BH 0F15CH 0F15DH 0F15EH 0F15FH 0F160H 0F161H 0F162H 0F163H 0F164H 0F165H 0F166H 0F167H FEUL610Q438 Segment Map Type 3 of Display Registers (2/4) Corresponding segment SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 R/W c7 c7 c7 c7 c7 c7 c7 c7 c7 c7 c7 c7 c15 c15 c15 c15 c15 c15 c15 c15 c15 c15 c15 c15 c15 c15 c15 c15 c15 c15 c15 c15 c15 c15 c15 c15 c15 c15 c15 c15 c15 c15 c15 c15 c15 c15 c15 c15 c15 c15 c15 c15 c6 c6 c6 c6 c6 c6 c6 c6 c6 c6 c6 c6 c14 c14 c14 c14 c14 c14 c14 c14 c14 c14 c14 c14 c14 c14 c14 c14 c14 c14 c14 c14 c14 c14 c14 c14 c14 c14 c14 c14 c14 c14 c14 c14 c14 c14 c14 c14 c14 c14 c14 c14 c5 c5 c5 c5 c5 c5 c5 c5 c5 c5 c5 c5 c13 c13 c13 c13 c13 c13 c13 c13 c13 c13 c13 c13 c13 c13 c13 c13 c13 c13 c13 c13 c13 c13 c13 c13 c13 c13 c13 c13 c13 c13 c13 c13 c13 c13 c13 c13 c13 c13 c13 c13 c4 c4 c4 c4 c4 c4 c4 c4 c4 c4 c4 c4 c12 c12 c12 c12 c12 c12 c12 c12 c12 c12 c12 c12 c12 c12 c12 c12 c12 c12 c12 c12 c12 c12 c12 c12 c12 c12 c12 c12 c12 c12 c12 c12 c12 c12 c12 c12 c12 c12 c12 c12 c3 c3 c3 c3 c3 c3 c3 c3 c3 c3 c3 c3 c11 c11 c11 c11 c11 c11 c11 c11 c11 c11 c11 c11 c11 c11 c11 c11 c11 c11 c11 c11 c11 c11 c11 c11 c11 c11 c11 c11 c11 c11 c11 c11 c11 c11 c11 c11 c11 c11 c11 c11 c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 c10 c10 c10 c10 c10 c10 c10 c10 c10 c10 c10 c10 c10 c10 c10 c10 c10 c10 c10 c10 c10 c10 c10 c10 c10 c10 c10 c10 c10 c10 c10 c10 c10 c10 c10 c10 c10 c10 c10 c10 c1 c1 c1 c1 c1 c1 c1 c1 c1 c1 c1 c1 c9 c9 c9 c9 c9 c9 c9 c9 c9 c9 c9 c9 c9 c9 c9 c9 c9 c9 c9 c9 c9 c9 c9 c9 c9 c9 c9 c9 c9 c9 c9 c9 c9 c9 c9 c9 c9 c9 c9 c9 c0 c0 c0 c0 c0 c0 c0 c0 c0 c0 c0 c0 c8 c8 c8 c8 c8 c8 c8 c8 c8 c8 c8 c8 c8 c8 c8 c8 c8 c8 c8 c8 c8 c8 c8 c8 c8 c8 c8 c8 c8 c8 c8 c8 c8 c8 c8 c8 c8 c8 c8 c8 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 26-32 ML610Q438/ML610Q439 User’s Manual Chapter 26 LCD Drivers Table 26-6 Register name Address DSPR68 DSPR69 DSPR6A DSPR6B DSPR6C DSPR6D DSPR6E DSPR6F DSPR70 DSPR71 DSPR72 DSPR73 DSPR74 DSPR75 DSPR76 DSPR77 DSPR78 DSPR79 DSPR7A DSPR7B DSPR7C DSPR7D DSPR7E DSPR7F DSPR80 DSPR81 DSPR82 DSPR83 DSPR84 DSPR85 DSPR86 DSPR87 DSPR88 DSPR89 DSPR8A DSPR8B DSPR8C DSPR8D DSPR8E DSPR8F DSPR90 DSPR91 DSPR92 DSPR93 DSPR94 DSPR95 DSPR96 DSPR97 DSPR98 DSPR99 DSPR9A DSPR9B 0F168H 0F169H 0F16AH 0F16BH 0F16CH 0F16DH 0F16EH 0F16FH 0F170H 0F171H 0F172H 0F173H 0F174H 0F175H 0F176H 0F177H 0F178H 0F179H 0F17AH 0F17BH 0F17CH 0F17DH 0F17EH 0F17FH 0F180H 0F181H 0F182H 0F183H 0F184H 0F185H 0F186H 0F187H 0F188H 0F189H 0F18AH 0F18BH 0F18CH 0F18DH 0F18EH 0F18FH 0F190H 0F191H 0F192H 0F193H 0F194H 0F195H 0F196H 0F197H 0F198H 0F199H 0F19AH 0F19BH FEUL610Q438 Segment Map Type 3 of Display Registers (3/4) Corresponding segment SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 R/W c15 c15 c15 c15 c15 c15 c15 c15 c15 c15 c15 c15 c15 c15 c15 c15 c15 c15 c15 c15 c15 c15 c15 c15 c23 c23 c23 c23 c23 c23 c23 c23 c23 c23 c23 c23 c23 c23 c23 c23 c23 c23 c23 c23 c23 c23 c23 c23 c23 c23 c23 c23 c14 c14 c14 c14 c14 c14 c14 c14 c14 c14 c14 c14 c14 c14 c14 c14 c14 c14 c14 c14 c14 c14 c14 c14 c22 c22 c22 c22 c22 c22 c22 c22 c22 c22 c22 c22 c22 c22 c22 c22 c22 c22 c22 c22 c22 c22 c22 c22 c22 c22 c22 c22 c13 c13 c13 c13 c13 c13 c13 c13 c13 c13 c13 c13 c13 c13 c13 c13 c13 c13 c13 c13 c13 c13 c13 c13 c21 c21 c21 c21 c21 c21 c21 c21 c21 c21 c21 c21 c21 c21 c21 c21 c21 c21 c21 c21 c21 c21 c21 c21 c21 c21 c21 c21 c12 c12 c12 c12 c12 c12 c12 c12 c12 c12 c12 c12 c12 c12 c12 c12 c12 c12 c12 c12 c12 c12 c12 c12 c20 c20 c20 c20 c20 c20 c20 c20 c20 c20 c20 c20 c20 c20 c20 c20 c20 c20 c20 c20 c20 c20 c20 c20 c20 c20 c20 c20 c11 c11 c11 c11 c11 c11 c11 c11 c11 c11 c11 c11 c11 c11 c11 c11 c11 c11 c11 c11 c11 c11 c11 c11 c19 c19 c19 c19 c19 c19 c19 c19 c19 c19 c19 c19 c19 c19 c19 c19 c19 c19 c19 c19 c19 c19 c19 c19 c19 c19 c19 c19 c10 c10 c10 c10 c10 c10 c10 c10 c10 c10 c10 c10 c10 c10 c10 c10 c10 c10 c10 c10 c10 c10 c10 c10 c18 c18 c18 c18 c18 c18 c18 c18 c18 c18 c18 c18 c18 c18 c18 c18 c18 c18 c18 c18 c18 c18 c18 c18 c18 c18 c18 c18 c9 c9 c9 c9 c9 c9 c9 c9 c9 c9 c9 c9 c9 c9 c9 c9 c9 c9 c9 c9 c9 c9 c9 c9 c17 c17 c17 c17 c17 c17 c17 c17 c17 c17 c17 c17 c17 c17 c17 c17 c17 c17 c17 c17 c17 c17 c17 c17 c17 c17 c17 c17 c8 c8 c8 c8 c8 c8 c8 c8 c8 c8 c8 c8 c8 c8 c8 c8 c8 c8 c8 c8 c8 c8 c8 c8 c16 c16 c16 c16 c16 c16 c16 c16 c16 c16 c16 c16 c16 c16 c16 c16 c16 c16 c16 c16 c16 c16 c16 c16 c16 c16 c16 c16 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 26-33 ML610Q438/ML610Q439 User’s Manual Chapter 26 LCD Drivers Table 26-6 Register name Address DSPR9C DSPR9D DSPR9E DSPR9F DSPRA0 DSPRA1 DSPRA2 DSPRA3 DSPRA4 DSPRA5 DSPRA6 DSPRA7 DSPRA8 DSPRA9 DSPRAA DSPRAB DSPRAC DSPRAD DSPRAE DSPRAF DSPRB0 DSPRB1 DSPRB2 DSPRB3 DSPRB4 DSPRB5 DSPRB6 DSPRB7 DSPRB8 DSPRB9 DSPRBA DSPRBB DSPRBC DSPRBD DSPRBE DSPRBF 0F19CH 0F19DH 0F19EH 0F19FH 0F1A0H 0F1A1H 0F1A2H 0F1A3H 0F1A4H 0F1A5H 0F1A6H 0F1A7H 0F1A8H 0F1A9H 0F1AAH 0F1ABH 0F1ACH 0F1ADH 0F1AEH 0F1AFH 0F1B0H 0F1B1H 0F1B2H 0F1B3H 0F1B4H 0F1B5H 0F1B6H 0F1B7H 0F1B8H 0F1B9H 0F1BAH 0F1BBH 0F1BCH 0F1BDH 0F1BEH 0F1BFH 0F1C0H to 0F1FFH Not used FEUL610Q438 Segment Map Type 3 of Display Registers (4/4) Corresponding segment SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63  bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 R/W c23 c23 c23 c23 c23 c23 c23 c23 c23 c23 c23 c23 c23 c23 c23 c23 c23 c23 c23 c23 c23 c23 c23 c23 c23 c23 c23 c23 c23 c23 c23 c23 c23 c23 c23 c23 c22 c22 c22 c22 c22 c22 c22 c22 c22 c22 c22 c22 c22 c22 c22 c22 c22 c22 c22 c22 c22 c22 c22 c22 c22 c22 c22 c22 c22 c22 c22 c22 c22 c22 c22 c22 c21 c21 c21 c21 c21 c21 c21 c21 c21 c21 c21 c21 c21 c21 c21 c21 c21 c21 c21 c21 c21 c21 c21 c21 c21 c21 c21 c21 c21 c21 c21 c21 c21 c21 c21 c21 c20 c20 c20 c20 c20 c20 c20 c20 c20 c20 c20 c20 c20 c20 c20 c20 c20 c20 c20 c20 c20 c20 c20 c20 c20 c20 c20 c20 c20 c20 c20 c20 c20 c20 c20 c20 c19 c19 c19 c19 c19 c19 c19 c19 c19 c19 c19 c19 c19 c19 c19 c19 c19 c19 c19 c19 c19 c19 c19 c19 c19 c19 c19 c19 c19 c19 c19 c19 c19 c19 c19 c19 c18 c18 c18 c18 c18 c18 c18 c18 c18 c18 c18 c18 c18 c18 c18 c18 c18 c18 c18 c18 c18 c18 c18 c18 c18 c18 c18 c18 c18 c18 c18 c18 c18 c18 c18 c18 c17 c17 c17 c17 c17 c17 c17 c17 c17 c17 c17 c17 c17 c17 c17 c17 c17 c17 c17 c17 c17 c17 c17 c17 c17 c17 c17 c17 c17 c17 c17 c17 c17 c17 c17 c17 c16 c16 c16 c16 c16 c16 c16 c16 c16 c16 c16 c16 c16 c16 c16 c16 c16 c16 c16 c16 c16 c16 c16 c16 c16 c16 c16 c16 c16 c16 c16 c16 c16 c16 c16 c16 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W          26-34 ML610Q438/ML610Q439 User’s Manual Chapter 26 LCD Drivers 26.2.10 Segout Data Registers 0 (SEGOUT0) Address: 0F0F6H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 SEGOUT0 SEGO63 SEGO62 SEGO61 SEGO60 SEGO59 SEGO58 SEGO57 SEGO56 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 ML610Q438: SEGOUT0 is a special function register (SFR). ML610Q439: SEGOUT0 cannot be used. FEUL610Q438 26-35 ML610Q438/ML610Q439 User’s Manual Chapter 26 LCD Drivers 26.2.11 Segout Data Registers 1 (SEGOUT1) Address: 0F0F7H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 SEGOUT1 SEGO55 SEGO54 SEGO53 SEGO52 SEGO51 SEGO50 SEGO49 SEGO48 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 ML610Q438: SEGOUT1 is a special function register (SFR). ML610Q439: SEGOUT1 cannot be used. [Description of Bits] • SEGO55-SEGO48 (bits 7-0) The SEGO55 to SEGO48 bits are used to set the output value of the SEG55 to SEG48 pin. SEGO55 0 1 Description Output level of the SEG55 pin: ”L” Output level of the SEG55 pin: ”H” SEGO54 0 1 Description Output level of the SEG54 pin: ”L” Output level of the SEG54 pin: ”H” SEGO53 0 1 Description Output level of the SEG53 pin: ”L” Output level of the SEG53 pin: ”H” SEGO52 0 1 Description Output level of the SEG52 pin: ”L” Output level of the SEG52 pin: ”H” SEGO51 0 1 Description Output level of the SEG51 pin: ”L” Output level of the SEG51 pin: ”H” SEGO50 0 1 Description Output level of the SEG50 pin: ”L” Output level of the SEG50 pin: ”H” SEGO49 0 1 Description Output level of the SEG49 pin: ”L” Output level of the SEG49 pin: ”H” SEGO48 0 1 Description Output level of the SEG48 pin: ”L” Output level of the SEG48 pin: ”H” FEUL610Q438 26-36 ML610Q438/ML610Q439 User’s Manual Chapter 26 LCD Drivers 26.2.12 Segout Data Registers 2 (SEGOUT2) Address: 0F0F8H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 SEGOUT2 SEGO47 SEGO46 SEGO45 SEGO44 SEGO43 SEGO42 SEGO41 SEGO40 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 ML610Q438: SEGOUT2 is a special function register (SFR). ML610Q439: SEGOUT2 cannot be used. [Description of Bits] • SEGO47-SEGO40 (bits 7-0) The SEGO47 to SEGO40 bits are used to set the output value of the SEG47 to SEG40 pin. SEGO47 0 1 Description Output level of the SEG47 pin: ”L” Output level of the SEG47 pin: ”H” SEGO46 0 1 Description Output level of the SEG46 pin: ”L” Output level of the SEG46 pin: ”H” SEGO45 0 1 Description Output level of the SEG45 pin: ”L” Output level of the SEG45 pin: ”H” SEGO44 0 1 Description Output level of the SEG44 pin: ”L” Output level of the SEG44 pin: ”H” SEGO43 0 1 Description Output level of the SEG43 pin: ”L” Output level of the SEG43 pin: ”H” SEGO42 0 1 Description Output level of the SEG42 pin: ”L” Output level of the SEG42 pin: ”H” SEGO41 0 1 Description Output level of the SEG41 pin: ”L” Output level of the SEG41 pin: ”H” SEGO40 0 1 Description Output level of the SEG40 pin: ”L” Output level of the SEG40 pin: ”H” FEUL610Q438 26-37 ML610Q438/ML610Q439 User’s Manual Chapter 26 LCD Drivers 26.2.13 Segout Data Registers 3 (SEGOUT3) Address: 0F0F9H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 SEGOUT3 SEGO39 SEGO38 SEGO37 SEGO36 SEGO35 SEGO34 SEGO33 SEGO32 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 ML610Q438: SEGOUT3 is a special function register (SFR). ML610Q439: SEGOUT3 cannot be used. [Description of Bits] • SEGO39-SEGO32 (bits 7-0) The SEGO39 to SEGO32 bits are used to set the output value of the SEG39 to SEG32 pin. SEGO39 0 1 Description Output level of the SEG39 pin: ”L” Output level of the SEG39 pin: ”H” SEGO38 0 1 Description Output level of the SEG38 pin: ”L” Output level of the SEG38 pin: ”H” SEGO37 0 1 Description Output level of the SEG37 pin: ”L” Output level of the SEG37 pin: ”H” SEGO36 0 1 Description Output level of the SEG36 pin: ”L” Output level of the SEG36 pin: ”H” SEGO35 0 1 Description Output level of the SEG35 pin: ”L” Output level of the SEG35 pin: ”H” SEGO34 0 1 Description Output level of the SEG34 pin: ”L” Output level of the SEG34 pin: ”H” SEGO33 0 1 Description Output level of the SEG33 pin: ”L” Output level of the SEG33 pin: ”H” SEGO32 0 1 Description Output level of the SEG32 pin: ”L” Output level of the SEG32 pin: ”H” FEUL610Q438 26-38 ML610Q438/ML610Q439 User’s Manual Chapter 26 LCD Drivers 26.3 Description of Operation 26.3.1 Operation of LCD Drivers and Bias Generation Circuit Figure 26-6 shows the operation of the LCD drivers and the bias generation circuit. Reset RESET_N BIASCON.BSON LCD bias voltage VL1 to VL4 Generation of LCD bias voltage BIAS activation time (TBIAS) LMD1, LMD0 Common output COM0 to COM15/23 VSS Common output waveform Segment output SEG0 to SEG63 VSS Segment output waveform  Figure 26-6    Operation of LCD Drivers and Bias Generation Circuit  System reset causes the bias generation circuit and the LCD drivers to stop operation and Vss level to be output to each of the common and segment pins.  By using the bias circuit control register (BIASCON), select 1/3 bias or 1/4 bias and lock of bias voltage multiplying, and set the bias generation circuit to on (BSON = “1”).  When the programmable display allocation function is used, set LCD allocation data in the display allocation registers A and B (DS0C0A to DS63C7A and DS0C0B to DS63C7B).  Set a frame frequency and a duty by using the display mode register 0 (DSPMOD0). When using the programmable display allocation function, set the DASN bit of DSPMOD1 register to “1” and set DADM1 bit to “1” to select type 3 for the display register segment map. When not using the programmable display allocation function, set the DASN bit to “0” and select a type of segment map for display registers.  Set display data in the display registers (DSPR00 to DSPRFE).  After elapse of the bias activation time (TBIAS) or longer, set the mode to display mode by using the LMD1 and LMD0 bits of the display control register (DSPCON). (Display waveform is output to each segment pin.) For the bias activation time (TBIAS), see the “Electrical Characteristics” Section in Appendix C. FEUL610Q438 26-39 ML610Q438/ML610Q439 User’s Manual Chapter 26 LCD Drivers 26.3.2 Segment Mapping When the Programmable Display Allocation Function is Not Used COM0 COM7 COM8 COM16 COM15 COM23 When not using the programmable display function (DASN bit of DSPMOD1 register is “0”), three types of segment map are available for the display registers (DSPR00 to FE), selected by the DADM1 bit and DADM0 bit. DSPRFE DSPRFA DSPRFD DSPRF9 DSPRFC DSPRF8 SEG63 SEG62 DSPR0E DSPR0A DSPR06 DSPR02 DSPR0D DSPR09 DSPR05 DSPR01 DSPR0C DSPR08 DSPR04 DSPR00 SEG3 SEG2 SEG1 SEG0 COM0 COM7 COM8 COM16 COM15 COM23 (1) Type 1: Recommended for when using COM16 to COM23 (1/17 to 1/24 duty) DSPRBF DSPRBE DSPR7F DSPR7D DSPR7E DSPR7C SEG63 SEG62 DSPR86 DSPR84 DSPR82 DSPR80 DSPR07 DSPR05 DSPR03 DSPR01 DSPR06 DSPR04 DSPR02 DSPR00 SEG3 SEG2 SEG1 SEG0 COM0 COM7 COM8 COM16 COM15 COM23 (2) Type 2: Recommended for when using COM9 to COM15 (1/9 to 1/16 duty) DSPRBF DSPRBE DSPR7F DSPR7E DSPR3F DSPR3E SEG63 SEG62 DSPR83 DSPR82 DSPR81 DSPR80 DSPR43 DSPR42 DSPR41 DSPR40 DSPR03 DSPR02 DSPR01 DSPR00 SEG3 SEG2 SEG1 SEG0 (3) Type 3: Recommended for when using COM0 to COM7 (1/1 to 1/8 duty) Figure 26-7 Configurations of Display register segment map types Note: When the programmable display function is not used (DASN = “0”), display allocation register A (0F400H to 0F5FFH) and display allocation register B (0F600H to 0F7FFH) can be used as 1K-byte data memory(RAM). FEUL610Q438 26-40 ML610Q438/ML610Q439 User’s Manual Chapter 26 LCD Drivers 26.3.3 Segment Mapping When the Programmable Display Allocation Function is Used When the programmable display allocation function is used (DASN bit of DSPMOD1 register is “1”), display registers (DSPR00 to FE) segment mapping can be set in bit units according to the contents of display allocation registers A and B (DSmCnA, DSmCnB: m = 0 to 63, n = 0 to 7). Table 26-7 shows the frame frequencies and the duty conditions that allow the use of the programmable allocation function. Table 26-7 Conditions That Allow the Use of Programmable Allocation Function Frame frequency Approx. 64 Hz Approx. 73 Hz Approx. 85 Hz Approx. 102 Hz Duty that allows the use of duty 1/1 to 1/8 Duty 1/1 to 1/7 Duty 1/1 to 1/6 Duty 1/1 to 1/5 Duty Note: - When the duty is other than those indicated in Table 26-7, the programmable allocation function can not be used regardless of the content of the DASN bit of DSPMOD1. The programmable display allocation function is available only when 1/1~1/8 duty is selected (when using eight COMs or less for display), it does not work when 1/9~1/24 duty is selected (when using nine COMs or more for display). - Select type 3 for the display register segment map (Set DADM1 bit of DSPMOD1 register to “1”) when using the programmable allocation function. Figure 26-8 shows the configuration when using the programmable display allocation function. Display allocation register A 0F5FFH Display allocation register B Mapping specification of SEG63-COM7 0F5FEH DS63C7A DS62C7A 0F402H 0F401H 0F400H DS2C0A DS1C0A DS0C0A Mapping specification of SEG2-COM0 8 Mapping specification of SEG62-COM7 Mapping specification of SEG1-COM0 Mapping specification of SEG0-COM0 Specifies the Display register addresses of a display register DSPRFE | DSPR00 DS63C7B DS62C7B 0F7FFH 0F7FEH DS2C0B DS1C0B DS0C0B 0F602H 0F601H 0F600H 3 Specifies a bit of a display register SEG63 SEG62 Segment drivers Selector 8 1 SEG2 SEG1 SEG0 Data bus Figure 26-8 FEUL610Q438 Configuration When Using the Programmable Display Allocation Function 26-41 ML610Q438/ML610Q439 User’s Manual Chapter 26 LCD Drivers In display allocation register A (DSmCnA: m = 0 to 63, n = 0 to 8), set the lower 8 bits (00H to 0FEH) of the addresses of the display registers (DSPR00 to DSPRFE) that are output to common n of segment n. In display allocation register B (DSmCnB: m = 0 to 63, n = 0 to 8), set the bits of the display registers (DSPR00 to DSPRFE) that are output to common n of segment m. For instance, to display bit 6 of display register 23 to common 3 of segment 16, set as follows. DS16C3A (0F416H) b7 0 b6 0 b5 1 b4 0 b3 0 b2 0 b1 1 b0 1 Address specification of display register "*" indicates an arbitrary value. DS16C3B (0F616H) b7 * b6 * b5 * b4 * b3 * b2 1 b1 1 b0 0 Bit specification of display register Note: - Set display allocation data to display allocation registers A and B when the DASN bit of display control register 0 (DSPMOD1) is “0”. When the DASN bit is “1”, access from the CPU is invalid. - Select type 3 for the display register segment map (Set DADM1 bit of DSPMOD1 register to “1”) when using the programmable allocation function. FEUL610Q438 26-42 ML610Q438/ML610Q439 User’s Manual Chapter 26 LCD Drivers 26.3.4 Common Output Waveforms Figure 26-9 shows the common output waveforms for 1/8 duty and 1/3 bias and for 1/24 duty and 1/4 bias. Frame frequency Approx. 64Hz/73Hz/85Hz/102Hz 0 1 2 3 4 5 6 7 0 COM1 FEUL610Q438 3 4 5 6 7   COM2 Figure 26-9 (1) 2 VL4 VL2, VL3 VL1 VSS VL4 VL2, VL3 VL1 VSS VL4 VL2, VL3 VL1 VSS COM0 COM7 1 VL4 VL2, VL3 VL1 VSS Common Output Waveforms for 1/8 Duty and 1/3 Bias 26-43 ML610Q438/ML610Q439 User’s Manual Chapter 26 LCD Drivers Frame frequency Approx. 64Hz/73Hz/85Hz/102Hz 0 1 2 3 4 5 6 7 8 9 10 11    22 23 0 1 2 3 4 5 6 7 8 9 10 11    22 23 VL4 VL3 VL2 VL1 VSS VL4 VL3 VL2 VL1 VSS VL4 VL3 VL2 VL1 VSS COM0 COM1   COM2 VL4 VL3 VL2 COM23 VL1 VSS Figure 26-9 (2) FEUL610Q438 Common Output Waveforms for 1/8 Duty and 1/3 Bias 26-44 ML610Q438/ML610Q439 User’s Manual Chapter 26 LCD Drivers 26.3.5 Segment Output Waveform Figure 26-5 shows the segment output waveforms for 1/8 duty and 1/3 bias and for 1/24 duty and 1/4 bias. Frame frequency Approx. 64Hz/73Hz/85Hz/102Hz Data 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 SEGn Data SEGn Data SEGn Data Data 0 SEGn Data SEGn Data SEGn Figure 26-10 (1) FEUL610Q438 VL4 VL2, VL3 VL1 VSS VL4 VL2, VL3 VL1 VSS VL4 VL2, VL3 VL1 VSS   SEGn Data VL4 VL2, VL3 VL1 VSS   SEGn VL4 VL2, VL3 VL1 VSS VL4 VL2, VL3 VL1 VSS VL4 VL2, VL3 VL1 VSS VL4 VL2, VL3 VL1 VSS Segment Output Waveforms for 1/8 Duty and 1/3 Bias 26-45 ML610Q438/ML610Q439 User’s Manual Chapter 26 LCD Drivers Frame frequency Approx. 64Hz/73Hz/85Hz/102Hz 0 1 2 3 4 5 6 7 8 9 10 11    22 23 0 1 2 3 4 5 6 7 8 9 10 11    22 23 Data 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEGn Data 1 0 0 0 0 0 0 0 0 0 0 0  0 0 1 0 0 0 0 0 0 0 0 0 0 0  0 0 SEGn Data 0 1 0 0 0 0 0 0 0 0 0 0  0 0 0 1 0 0 0 0 0 0 0 0 0 0  0 0 SEGn Data 1 1 0 0 0 0 0 0 0 0 0 0  0 0 1 1 0 0 0 0 0 0 0 0 0 0  0 0   SEGn Data 0 1 0 1 0 1 0 1 0 1 0 1  0 1 0 1 0 1 0 1 0 1 0 1 0 1  0 1   SEGn Data 1 0 1 1 1 1 1 1 1 1 1 1  1 1 1 0 1 1 1 1 1 1 1 1 1 1  1 1 SEGn Data 0 1 1 1 1 1 1 1 1 1 1 1  1 1 0 1 1 1 1 1 1 1 1 1 1 1  1 1 SEGn Data 1 1 1 1 1 1 1 1 1 1 1 1  1 1 1 1 1 1 1 1 1 1 1 1 1 1  1 1 SEGn Figure 26-10 (2) FEUL610Q438 VL4 VL3 VL2 VL1 VSS VL4 VL3 VL2 VL1 VSS VL4 VL3 VL2 VL1 VSS VL4 VL3 VL2 VL1 VSS VL4 VL3 VL2 VL1 VSS VL4 VL3 VL2 VL1 VSS VL4 VL3 VL2 VL1 VSS VL4 VL3 VL2 VL1 VSS Segment Output Waveforms for 1/24 Duty and 1/4 Bias 26-46 Chapter 27 Battery Level Detector ML610Q438/ML610Q439 User’s Manual Chapter 27 Battery Level Detector 27. Battery Level Detector 27.1 Overview This LSI includes a Battery Level Detector (BLD). 16 levels of threshold voltages can be selected by setting Battery Level Detector control register 0 (BLDCON0). 27.1.1 Features • Threshold voltages: One out of the 16 levels can be selected • Accuracy: ±2% (Typ.) • Temperature deviation: ±0.1%/°C 27.1.2 Configuration BLD consists of the comparator and threshold voltage select circuits. Figure 27-1 shows the configuration of the Battery Level Detector. Comparator VDD BLDF Threshold voltage select circuit BLDCON0 ENBL BLDCON1 Data bus BLDCON0 : Battery Level Detector control register 0 BLDCON1 : Battery Level Detector control register 1 Figure 27-1 FEUL610Q438 Configuration of Battery Level Detector 27-1 ML610Q438/ML610Q439 User’s Manual Chapter 27 Battery Level Detector 27.2 Description of Registers 27.2.1 List of Registers Address 0F0D0H 0F0D1H FEUL610Q438 Name Battery Level Detector control register 0 Battery Level Detector control register 1 Symbol (Byte) Symbol (Word) BLDCON0 R/W Size Initial value R/W 8/16 00H R/W 8 00H BLDCON BLDCON1 27-2 ML610Q438/ML610Q439 User’s Manual Chapter 27 Battery Level Detector 27.2.2 Battery Level Detector Control Register 0 (BLDCON0) Address: 0F0D0H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 BLDCON0     LD3 LD2 LD1 LD0 R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 BLDCON0 is a special function register (SFR) to control the Battery Level Detector [Description of Bits] • LD3, LD2, LD1, LD0 (bits 3-0) The LD3, LD2, LD1, and LD0 bits are used to select a threshold voltage (VCMP) of the Battery Level Detector. 16 levels of threshold voltages can be selected. LD3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FEUL610Q438 LD2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 LD1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 LD0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Description 1.35 V ±2% (initial value) 1.40 V ±2% 1.45 V ±2% 1.50 V ±2% 1.60 V ±2% 1.70 V ±2% 1.80 V ±2% 1.90 V ±2% 2.00 V ±2% 2.10 V ±2% 2.20 V ±2% 2.30 V ±2% 2.40 V ±2% 2.50 V ±2% 2.70 V ±2% 2.90 V ±2% 27-3 ML610Q438/ML610Q439 User’s Manual Chapter 27 Battery Level Detector 27.2.3 Battery Level Detector Control Register 1 (BLDCON1) Address: 0F0D1H Access: R/W Access size: 8 bits Initial value: 00H 7 6 5 4 3 2 1 0 BLDCON1       BLDF ENBL R/W Initial value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R 0 R/W 0 BLDCON1 is a special function register (SFR) to control the Battery Level Detector. [Description of Bits] • ENBL (bit 0) The ENBL bit is used to control activation (ON) or deactivation (OFF) of the Battery Level Detector. The Battery Level Detector is activated (ON) and deactivated (OFF) by setting the ENBL bit to “1” and “0”, respectively. ENBL 0 1 Description Deactivates the Battery Level Detector (OFF) (initial value) Activates the Battery Level Detector (ON). • BLDF (bit 1) The BLDF bit is the judgment result flag of the Battery Level Detector. The BLDF bit is set to “1” or “0” when the power supply voltage (VDD) is lower than or higher than the threshold voltage selected by LD3 to LD0 bits of BLDCON0 register, respectively. BLDF 0 1 FEUL610Q438 Description Higher than the threshold voltage (initial value) Lower than the threshold voltage 27-4 ML610Q438/ML610Q439 User’s Manual Chapter 27 Battery Level Detector 27.3 Description of Operation 27.3.1 Threshold Voltage The threshold voltage (VCMP) is selected by setting the bits of BLDCON0. Table 28-1 shows the threshold voltages and the accuracy. Table 28-1 LD3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FEUL610Q438 BLDCON0 LD2 LD1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 LD0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Threshold Voltages and Accuracy Threshold voltage VCMP 1.35 V 1.40 V 1.45 V 1.50 V 1.60 V 1.70 V 1.80 V 1.90 V 2.00 V 2.10 V 2.20 V 2.30 V 2.40 V 2.50 V 2.70 V 2.90 V Accuracy Ta = 25°C Temperature deviation ±2.0% ±0.1%/°C 27-5 ML610Q438/ML610Q439 User’s Manual Chapter 27 Battery Level Detector 27.3.2 Operation of Battery Level Detector Activation (ON) and deactivation (OFF) of the Battery Level Detector are controlled by setting the ENBL bit of the Battery Level Detector control register (BLDCON1), and the result of the comparison of the power supply voltage (VDD) to the threshold voltage is output to the BLDF bit of BLDCON1. When ENBL, the enable control bit of the Battery Level Detector, is set to “1”, the detector is activated (ON). When ENBL is set to “0”, the detector is deactivated (OFF) and has no supply current. BLDF indicates the result of comparison. When BLDF bit is set to “1”, it indicates the power supply voltage is lower than the threshold voltage. When BLDF bit is set to “0”, it indicates the power supply voltage (VDD) is higher than the threshold voltage. The Battery Level Detector requires a settling time. Read BLDF bit 1ms or more after ENBL bit is set to “1”. Figure 27-2 shows an example of the operation timing diagram. Set ENBL ↓ Operation  Read BLDF ↓ Set ENBL ↓ ENBL Threshold voltage VCMP VSS VCMP “1” or “0” BLDF Wait for settling time of BLD (Min. 1 ms) Figure 27-2 Example of Operation Timing Diagram The operations in Figure 28-2 are described below.     The Battery Level Detector is activated (ON) by setting the ENBL bit to “1”. Wait the settling time (min. 1 ms) of the Battery Level Detector. Read BLDF bit. Set ENBL bit to “0”. Note: Select the threshold voltage (VCMP) when the ENBL bit is “0”. FEUL610Q438 27-6 Chapter 28 Power Supply Circuit ML610Q438/ML610Q439 User’s Manual Chapter 28 Power Supply Circuit 28. Power Supply Circuit 28.1 Overview This LSI includes a regulated power supply for the internal logic (VRL) and a regulated power supply for low-speed oscillation (VRX). The VRL outputs the operating voltage, VDDL, of the internal logic, program memory, RAM, etc. The VRX outputs the operating voltage, VDDX, for low-speed oscillation. For the circuit configuration of the power supplies for LCD (VL1 to VL4), see Chapter 26, “LCD Driver”. 28.1.1 Features • VRL outputs the operating voltage, VDDL, of the internal logic, program memory, RAM, etc. • VRX outputs the operating voltage, VDDX, for low-speed oscillation. 28.1.2 Configuration Figure 28-1 shows the configuration of the power supply circuit. VDD = 1.1 to 3.6V VDD Low-voltage circuit for low-speed oscillation VRX Cl VDDL Cx VDDX High-speed oscillation circuit Port GPIO Low-speed oscillation circuit XT0 XT1 Low-voltage circuit for logic VRL OSC0* OSC1* General-purpose ports Logic circuis VSS *: Shows the secondary function of the port. Figure 28-1 Configuration of Power Supply Circuit 28.1.3 List of Pins Pin name VDDL VDDX FEUL610Q438 I/O   Description Positive power supply pin for the internal logic circuits Positive power supply pin for low-speed oscillation 28-1 ML610Q438/ML610Q439 User’s Manual Chapter 28 Power Supply Circuit 28.2 Description of Operation VDDL and VDDX become approx. 1.2 V at a system reset. VDDL becomes approx. 1.65 V (Typ.) when high-speed oscillation starts in crystal/ceramic oscillation mode or PLL oscillation mode or external clock mode or 2MHz CR oscillation mode. When high-speed oscillation stops, the voltage becomes about 1.2V (Typ.). VDDX becomes approx. 0.6 V (Typ.) after 4096 low-speed oscillation clock (XTCLK) pulses are counted after the system reset is released. As a result of release of STOP mode (generation of external interrupt), VDDX becomes approx. 1.2 V(Typ.) and then approx. 0.6 V (Typ.) after 4096 low-speed oscillation clock (XTCLK) pulses are counted. Figure 28-2 shows the operation waveforms of the power supply circuit. System reset RESET_S Power supply for logic VDDL Power supply for low-speed oscillation VDDX RESET_VRX Approx. 1.65V Approx. 1.2V Approx. 1.2V Approx. 0.6V Approx. 1.2V Approx. 1.2V Approx. 0.6V Low-speed oscillation 4096-pulse count Low-speed oscillation 4096-pulse count STOP mode Generation of external interrupt Start of high-speed Stop of high-speed oscillation*1 oscillation*1 *1: Crystal/ceramic oscillation, PLL oscillation, External clock input mode, 2MHz CR oscillation (500 kHz CR oscillation not included) Figure 28-2 FEUL610Q438 Operation Waveforms of Power Supply Circuit 28-2 Chapter 29 On-Chip Debug Function ML610Q438/ML610Q439 User’s Manual Chapter 29 On-Chip Debug Function 29. On-Chip Debug Function 29.1 Overview This LSI has an on-chip debug function allowing Flash memory rewriting. The on-chip debug emulator (uEASE) is connected to this LSI to perform the on-chip debug function. 29.2 Method of Connecting to On-Chip Debug Emulator Figure 30-1 shows connection to the on-chip debug emulator (uEASE). For on-chip debug emulator, see “uEASE User’s Manual”. User application circuit uEASE Interface connector VPP ML610Q438/439 VPP VDDL VDDL VDD VDD VSS VSS TEST TEST RESET_N RESET_N Reset signal is switched with a jumper, etc. Figure 30-1 System reset circuit Connection to On-chip Debug Emulator (uEASE) Note: − Please do not apply LSIs used for debugging to mass production. − When using the on-chip debug function or the flash rewrite function after mounting of the board, design the board so that the 5 pins (VPP, VDD, VSS, RESET_N, and TEST_N) required for connection to the on-chip debug emulator can be connected. − “3.0V to 3.6V” has to be supplied to VDD while debugging and writing flash. − When the system reset circuit is included in the user application circuit, enable switching of the connection in the user application circuit, as shown above. When the system reset circuit is not included in the user application circuit, the RESET_N pin can be connected directy to the RESET_N pin of this LSI. For details, see “uEASE User’s Manual” and “uEASE Target Connection Manual”. FEUL610Q438 29-1 ML610Q438/ML610Q439 User’s Manual Chapter 29 On-Chip Debug Function 29.3 Flash Memory Rewrite Function Flash memory erase/write can be performed with the the memory mounted on board by using the commands from the on-chip debug emulator (uEASE). For more details on the on-chip debug emulator, see “uEASE User’s Manual”. Table 29-2 shows the Flash memory rewrite functions. Table 29-2 Flash Memory Rewrite Functions Function Outline Erase of 48 Kwords (overall area) Erase of 8 Kwords (16 Kbytes) Write of 1 word (2 bytes) Read of input address Chip erase Block erase 1-word write Random read Table 29-3 shows the conditions and specifications of Flash memory rewrite. Table 29-3 Specifications of Flash Memory Rewrite Parameter Rewrite count Operating temperature Operating voltage VPP VDD VDDL Chip-erase time Block-erase time 1-word (16 bits) write Overall-word (32K × 16 bits) write Specifications 80 0°C to 40°C 8 V (Typ.) (Supplied from uEASE) 3.0V to 3.6 V 2.7 V (Typ.) (Supplied from uEASE) 77 ms (Typ.), 100 ms (Max.) 77 ms (Typ.), 100 ms (Max.) 41 µs (Typ.), 64 µs (Max.) Approx. 1.35s (Typ.), Approx. 2.1s (Max.) Note: When performing Flash memory rewrite (erase, write), a voltage within the range from 3.0V to 3.6 V needs to be applied to the power supply voltage VDD. FEUL610Q438 29-2 Appendixes ML610Q438/ML610Q439 User’s Manual Appendix A Registers Appendix A Registers Contents of Registers Address 0F000H 0F001H 0F002H 0F003H 0F008H 0F009H 0F00AH 0F00BH 0F00CH 0F00DH 0F00EH 0F00FH 0F011H 0F012H 0F013H 0F014H 0F015H 0F016H 0F017H 0F018H 0F019H 0F01AH 0F01BH 0F01CH 0F01DH 0F01EH 0F01FH 0F020H 0F021H 0F022H 0F028H 0F029H 0F02AH 0F02BH 0F02CH 0F030H 0F031H 0F032H 0F033H 0F034H 0F035H 0F036H 0F037H 0F038H 0F039H Name Data segment register Reset status register Frequency control register 0 Frequency control register 1 Stop code acceptor Standby control register Low-speed time base counter divide register High-speed time base counter divide register Low-speed time base counter frequency adjustment register L Low-speed time base counter frequency adjustment register H Watchdog timer control register Watchdog timer mode register Inperrupt permit register 1 Inperrupt permit register 2 Inperrupt permit register 3 Inperrupt permit register 4 Inperrupt permit register 5 Inperrupt permit register 6 Inperrupt permit register 7 Inperrupt request register 0 Inperrupt request register 1 Inperrupt request register 2 Inperrupt request register 3 Inperrupt request register 4 Inperrupt request register 5 Inperrupt request register 6 Inperrupt request register 7 External interrupt control register 0 External interrupt control register 1 External interrupt control register 2 Block control register 0 Block control register 1 Block control register 2 Block control register 3 Block control register 4 Timer 0 data register Timer 0 counter register Timer 0 control register 0 Timer 0 control register 1 Timer 1 data register Timer 1 counter register Timer 1 control register 0 Timer 1 control register 1 Timer 2 data register Timer 2 counter register FEUL610Q438 Symbol (Byte) DSR RSTAT FCON0 FCON1 STPACP SBYCON LTBR HTBDR Symbol (Word)   FCON     LTBADJL Initial value 00H R/W Size R/W R/W R/W R/W W W R/W R/W 8 8 8/16 8 8 8 8 8 R/W 8/16 00H R/W 8 00H R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8/16 8 8/16 8 8/16 8 8/16 8 8/16 8 00H 02H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 0FFH 00H 00H 00H 0FFH 00H 00H 00H 0FFH 00H Undefined 33H 03H Undefined 00H 00H 00H LTBADJ LTBADJH WDTCON WDTMOD IE1 IE2 IE3 IE4 IE5 IE6 IE7 IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 EXICON0 EXICON1 EXICON2 BLKCON0 BLKCON1 BLKCON2 BLKCON3 BLKCON4 TM0D TM0C TM0CON0 TM0CON1 TM1D TM1C TM1CON0 TM1CON1 TM2D TM2C                          TM0DC TM0CON TM1DC TM1CON TM2DC A -1 ML610Q438/ML610Q439 User’s Manual Appendix A Registers Address 0F03AH 0F03BH 0F03CH 0F03DH 0F03EH 0F03FH 0F080H 0F081H 0F082H 0F090H 0F091H 0F092H 0F093H 0F0A0H 0F0A1H 0F0A2H 0F0A3H 0F0A4H 0F0A5H 0F0A6H 0F0A7H 0F0A8H 0F0A9H 0F0AAH 0F0ABH 0F0ACH 0F0ADH 0F0AEH 0F0AFH 0F0B0H 0F0B1H 0F0B2H 0F0B3H 0F0B4H 0F0B5H 0F0B6H 0F0B7H 0F0D0H 0F0D1H 0F0F0H 0F0F1H 0F0F2H 0F0F3H 0F0F４H 0F0F6H 0F0F7H 0F0F8H 0F0F9H 0F100H 0F101H Name Timer control register 0 Timer 2 control register 1 Timer 3 data register Timer 3 counter register Timer 3 control register 0 Timer 3 control register 1 1kHz timer count register L 1kHz timer count register H 1kHz timer control register Capture control register Capture status register Capture data register 0 Capture data register 1 PWM0 period register L PWM0 period register H PWM0 duty register L PWM0 duty register H PWM0 dounter register L PWM0 dounter register H PWM0 control register 0 PWM0 control register 1 PWM1 period register L PWM1 period register H PWM1 duty register L PWM1 duty register H PWM1 dounter register L PWM1 dounter register H PWM1 control register 0 PWM1 control register 1 PWM2 period register L PWM2 period register H PWM2 duty register L PWM2 duty register H PWM2 dounter register L PWM2 dounter register H PWM2 control register 0 PWM2 control register 1 Battery Level Detector control register 0 Battery Level Detector control register 1 Bias circuit control register Display contrast register Display mode register 0 Display mode register 1 Display control register Segout data register 0 Segout data register 1 Segout data register 2 Segout data register 3 Display register 00 Display register 01 FEUL610Q438 Symbol (Byte) TM2CON0 TM2CON1 TM3D TM3C TM3CON0 TM3CON1 T1KCRL T1KCRH T1KCON CAPCON CAPSTAT CAPR0 CAPR1 PW0PL PW0PH PW0DL PW0DH PW0CL PW0CH PW0CON0 PW0CON1 PW1PL PW1PH PW1DL PW1DH PW1CL PW1CH PW1CON0 PW1CON1 PW2PL PW2PH PW2DL PW2DH PW2CL PW2CH PW2CON0 PW2CON1 BLDCON0 BLDCON1 BIASCON DSPCNT DSPMOD0 DSPMOD1 DSPCON SEGOUT0 SEGOUT1 SEGOUT2 SEGOUT3 DSPR00 DSPR01 Symbol (Word) TM2CON TM3DC TM3CON T1KCR      PW0P PW0D PW0C PW0CON PW1P PW1D PW1C PW1CON PW2P PW2D PW2C PW2CON BLDCON   DSPMOD        R/W Size R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8/16 8 8/16 8 8/16 8 8/16 8 8 8 8 8 8 8/16 8 8/16 8 8/16 8 8/16 8 8/16 8 8/16 8 8/16 8 8/16 8 8/16 8 8/16 8 8/16 8 8/16 8 8/16 8 8 8 8/16 8 8 8 8 8 8 8 8 Initial value 00H 00H 0FFH 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 0FFH 0FFH 00H 00H 00H 00H 00H 40H 0FFH 0FFH 00H 00H 00H 00H 00H 40H 0FFH 0FFH 00H 00H 00H 00H 00H 40H 00H 00H 08H 00H 00H 00H 00H 00H 00H 00H 00H Undefined Undefined A -2 ML610Q438/ML610Q439 User’s Manual Appendix A Registers Address 0F102H 0F104H 0F105H 0F106H 0F108H 0F109H 0F10AH 0F10CH 0F10DH 0F10EH 0F110H 0F111H 0F112H 0F114H 0F115H 0F116H 0F118H 0F119H 0F11AH 0F11CH 0F11DH 0F11EH 0F120H 0F121H 0F122H 0F124H 0F125H 0F126H 0F128H 0F129H 0F12AH 0F12CH 0F12DH 0F12EH 0F130H 0F131H 0F132H 0F134H 0F135H 0F136H 0F138H 0F139H 0F13AH 0F13CH 0F13DH 0F13EH 0F140H 0F141H 0F142H 0F144H Name Display register 02 Display register 04 Display register 05 Display register -06 Display register 08 Display register 09 Display register 0A Display register 0C Display register 0D Display register 0E Display register 10 Display register 11 Display register 12 Display register 14 Display register 15 Display register 16 Display register 18 Display register 19 Display register 1A Display register 1C Display register 1D Display register 1E Display register 20 Display register 21 Display register 22 Display register 24 Display register 25 Display register 26 Display register 28 Display register 29 Display register 2A Display register 2C Display register 2D Display register 2E Display register 30 Display register 31 Display register 32 Display register 34 Display register 35 Display register 36 Display register 38 Display register 39 Display register 3A Display register 3C Display register 3D Display register 3E Display register 40 Display register 41 Display register 42 Display register 44 FEUL610Q438 Symbol (Byte) DSPR02 DSPR04 DSPR05 DSPR06 DSPR08 DSPR09 DSPR0A DSPR0C DSPR0D DSPR0E DSPR10 DSPR11 DSPR12 DSPR14 DSPR15 DSPR16 DSPR18 DSPR19 DSPR1A DSPR1C DSPR1D DSPR1E DSPR20 DSPR21 DSPR22 DSPR24 DSPR25 DSPR26 DSPR28 DSPR29 DSPR2A DSPR2C DSPR2D DSPR2E DSPR30 DSPR31 DSPR32 DSPR34 DSPR35 DSPR36 DSPR38 DSPR39 DSPR3A DSPR3C DSPR3D DSPR3E DSPR40 DSPR41 DSPR42 DSPR44 Symbol (Word)                                                   R/W Size R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined A -3 ML610Q438/ML610Q439 User’s Manual Appendix A Registers Address 0F145H 0F146H 0F148H 0F149H 0F14AH 0F14CH 0F14DH 0F14EH 0F150H 0F151H 0F152H 0F154H 0F155H 0F156H 0F158H 0F159H 0F15AH 0F15CH 0F15DH 0F15EH 0F160H 0F161H 0F162H 0F164H 0F165H 0F166H 0F168H 0F169H 0F16AH 0F16CH 0F16DH 0F16EH 0F170H 0F171H 0F172H 0F174H 0F175H 0F176H 0F178H 0F179H 0F17AH 0F17CH 0F17DH 0F17EH 0F180H 0F181H 0F182H 0F184H 0F185H 0F186H Name Display register 45 Display register 46 Display register 48 Display register 49 Display register 4A Display register 4C Display register 4D Display register 4E Display register 50 Display register 51 Display register 52 Display register 54 Display register 55 Display register 56 Display register 58 Display register 59 Display register 5A Display register 5C Display register 5D Display register 5E Display register 60 Display register 61 Display register 62 Display register 64 Display register 65 Display register 66 Display register 68 Display register 69 Display register 6A Display register 6C Display register 6D Display register 6E Display register 70 Display register 71 Display register 72 Display register 74 Display register 75 Display register 76 Display register 78 Display register 79 Display register 7A Display register 7C Display register 7D Display register 7E Display register 80 Display register 81 Display register 82 Display register 84 Display register 85 Display register 86 FEUL610Q438 Symbol (Byte) DSPR45 DSPR46 DSPR48 DSPR49 DSPR4A DSPR4C DSPR4D DSPR4E DSPR50 DSPR51 DSPR52 DSPR54 DSPR55 DSPR56 DSPR58 DSPR59 DSPR5A DSPR5C DSPR5D DSPR5E DSPR60 DSPR61 DSPR62 DSPR64 DSPR65 DSPR66 DSPR68 DSPR69 DSPR6A DSPR6C DSPR6D DSPR6E DSPR70 DSPR71 DSPR72 DSPR74 DSPR75 DSPR76 DSPR78 DSPR79 DSPR7A DSPR7C DSPR7D DSPR7E DSPR80 DSPR81 DSPR82 DSPR84 DSPR85 DSPR86 Symbol (Word)                                                   R/W Size R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined A -4 ML610Q438/ML610Q439 User’s Manual Appendix A Registers Address 0F188H 0F189H 0F18AH 0F18CH 0F18DH 0F18EH 0F190H 0F191H 0F192H 0F194H 0F195H 0F196H 0F198H 0F199H 0F19AH 0F19CH 0F19DH 0F19EH 0F1A0H 0F1A1H 0F1A2H 0F1A4H 0F1A5H 0F1A6H 0F1A8H 0F1A9H 0F1AAH 0F1ACH 0F1ADH 0F1AEH 0F1B0H 0F1B1H 0F1B2H 0F1B4H 0F1B5H 0F1B6H 0F1B8H 0F1B9H 0F1BAH 0F1BCH 0F1BDH 0F1BEH 0F1C0H 0F1C1H 0F1C2H 0F1C4H 0F1C5H 0F1C6H 0F1C8H 0F1C9H Name Display register 88 Display register 89 Display register 8A Display register 8C Display register 8D Display register 8E Display register 90 Display register 91 Display register 92 Display register 94 Display register 95 Display register 96 Display register 98 Display register 99 Display register 9A Display register 9C Display register 9D Display register 9E Display register A0 Display register A1 Display register A2 Display register A4 Display register A5 Display register A6 Display register A8 Display register A9 Display register AA Display register AC Display register AD Display register AE Display register B0 Display register B1 Display register B2 Display register B4 Display register B5 Display register B6 Display register B8 Display register B9 Display register BA Display register BC Display register BD Display register BE Display register C0 Display register C1 Display register C2 Display register C4 Display register C5 Display register C6 Display register C8 Display register C9 FEUL610Q438 Symbol (Byte) DSPR88 DSPR89 DSPR8A DSPR8C DSPR8D DSPR8E DSPR90 DSPR91 DSPR92 DSPR94 DSPR95 DSPR96 DSPR98 DSPR99 DSPR9A DSPR9C DSPR9D DSPR9E DSPRA0 DSPRA1 DSPRA2 DSPRA4 DSPRA5 DSPRA6 DSPRA8 DSPRA9 DSPRAA DSPRAC DSPRAD DSPRAE DSPRB0 DSPRB1 DSPRB2 DSPRB4 DSPRB5 DSPRB6 DSPRB8 DSPRB9 DSPRBA DSPRBC DSPRBD DSPRBE DSPRC0 DSPRC1 DSPRC2 DSPRC4 DSPRC5 DSPRC6 DSPRC8 DSPRC9 Symbol (Word)                                                   R/W Size R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined A -5 ML610Q438/ML610Q439 User’s Manual Appendix A Registers Address 0F1CAH 0F1CCH 0F1CDH 0F1CEH 0F1D0H 0F1D1H 0F1D2H 0F1D4H 0F1D5H 0F1D6H 0F1D8H 0F1D9H 0F1DAH 0F1DCH 0F1DDH 0F1DEH 0F1E0H 0F1E1H 0F1E2H 0F1E4H 0F1E5H 0F1E6H 0F1E8H 0F1E9H 0F1EAH 0F1ECH 0F1EDH 0F1EEH 0F1F0H 0F1F1H 0F1F2H 0F1F4H 0F1F5H 0F1F6H 0F1F8H 0F1F9H 0F1FAH 0F1FCH 0F1FDH 0F1FEH 0F200H 0F201H 0F204H 0F206H 0F207H 0F208H 0F20AH 0F20BH 0F210H 0F212H Name Display register CA Display register CC Display register CD Display register CE Display register D0 Display register D1 Display register D2 Display register D4 Display register D5 Display register D6 Display register D8 Display register D9 Display register DA Display register DC Display register DD Display register DE Display register E0 Display register E1 Display register E2 Display register E4 Display register E5 Display register E6 Display register E8 Display register E9 Display register EA Display register EC Display register ED Display register EE Display register F0 Display register F1 Display register F2 Display register F4 Display register F5 Display register F6 Display register F8 Display register F9 Display register FA Display register FC Display register FD Display register FE NMI data register NMI control register Port 0 data register Port 0 control register 0 Port 0 control register 1 Port 1 data register Port 1 control register 0 Port 1 control register 1 Port 2 data register Port 2 control register 0 FEUL610Q438 Symbol (Byte) DSPRCA DSPRCC DSPRCD DSPRCE DSPRD0 DSPRD1 DSPRD2 DSPRD4 DSPRD5 DSPRD6 DSPRD8 DSPRD9 DSPRDA DSPRDC DSPRDD DSPRDE DSPRE0 DSPRE1 DSPRE2 DSPRE4 DSPRE5 DSPRE6 DSPRE8 DSPRE9 DSPREA DSPREC DSPRED DSPREE DSPRF0 DSPRF1 DSPRF2 DSPRF4 DSPRF5 DSPRF6 DSPRF8 DSPRF9 DSPRFA DSPRFC DSPRFD DSPRFE NMID NMICON P0D P0CON0 P0CON1 P1D P1CON0 P1CON1 P2D P2CON0 Symbol (Word)                                            P0CON  P1CON  P2CON R/W Size R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R R/W R/W R R/W R/W R/W R/W 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8/16 8 8 8/16 8 8 8/16 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 00H Undefined 00H 00H Undefined 00H 00H 00H 00H A -6 ML610Q438/ML610Q439 User’s Manual Appendix A Registers Address 0F213H 0F214H 0F215H 0F216H 0F218H 0F219H 0F21AH 0F21BH 0F21CH 0F21DH 0F220H 0F221H 0F222H 0F223H 0F224H 0F225H 0F250H 0F251H 0F252H 0F253H 0F280H 0F281H 0F282H 0F284H 0F285H 0F290H 0F291H 0F292H 0F293H 0F294H 0F295H 0F296H 0F2A0H 0F2A1H 0F2A2H 0F2A3H 0F2A4H 0F2A5H 0F2C0H 0F2C1H 0F2C2H 0F2C3H 0F2D0H 0F2D1H 0F2D2H 0F2D3H 0F2F0H 0F2F1H 0F2F2H 0F2F4H Name Port 2 control register 1 Port 2 mode register 0 Port 2 mode register 1 Port 2 mode register 2 Port 3 data register Port 3 direction register Port 3 control register 0 Port 3 control register 1 Port 3 mode register 0 Port 3 mode register 1 Port 4 data register Port 4 direction register Port 4 control register 0 Port 4 control register 1 Port 4 mode register 0 Port 4 mode register 1 Port A data register Port A direction register Port A control register 0 Port A control register 1 Serial port 0 transmit/receive buffer L Serial port 0 transmit/receive buffer H Serial port 0 control register Serial port 0 mode register 0 Serial port 0 mode register 1 UART0 transmit/receive buffer UART0 control register UART0 mode register 0 UART0 mode register 1 UART0 baud rate register L UART0 baud rate register H UART0 status register I2C bus 0 receive data register I2C bus 0 slave address register I2C bus 0 transmit data register I2C bus 0 control register I2C bus 0 mode register I2C bus 0 status register Melody 0 control register Melody 0 tempo code register Melody 0 tone scale code register Melody 0 tone length code register SA-ADC result register 0L SA-ADC result register 0H SA-ADC result register 1L SA-ADC result register 1H SA-ADC control register 0 SA-ADC control register 1 SA-ADC mode register 0 Amp offset register FEUL610Q438 Symbol (Byte) P2CON1 P2MOD0 P2MOD1 P2MOD2 P3D P3DIR P3CON0 P3CON1 P3MOD0 P3MOD1 P4D P4DIR P4CON0 P4CON1 P4MOD0 P4MOD1 PAD PADIR PACON0 PACON1 SIO0BUFL SIO0BUFH SIO0CON SIO0MOD0 SIO0MOD1 UA0BUF UA0CON UA0MOD0 UA0MOD1 UA0BRTL UA0BRTH UA0STAT I2C0RD I2C0SA I2C0TD I2C0CON I2C0MOD I2C0STAT MD0CON MD0TMP MD0TON MD0LEN SADR0L SADR0H SADR1L SADR1H SADCON0 SADCON1 SADMOD0 AMPOFFS Symbol (Word) P2MOD    P3CON P3MOD   P4CON P4MOD   PACON SIO0BUF  SIO0MOD   UA0MOD UA0BRT          MD0TL SADR0 SADR1 SADCON   R/W Size R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R R/W R/W R/W R/W R R R R R/W R/W R/W R/W 8 8/16 8 8 8 8 8/16 8 8/16 8 8 8 8/16 8 8/16 8 8 8 8/16 8 8/16 8 8 8/16 8 8 8 8/16 8 8/16 8 8 8 8 8 8 8 8 8 8 8/16 8 8/16 8 8/16 8 8/16 8 8 8 Initial value 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 03H A -7 ML610Q438/ML610Q439 User’s Manual Appendix A Registers Address 0F2F5H 0F2F6H 0F300H 0F301H 0F302H 0F304H 0F305H 0F306H 0F308H 0F309H 0F400H 0F401H 0F402H 0F403H 0F404H 0F405H 0F406H 0F407H 0F408H 0F409H 0F40AH 0F40BH 0F40CH 0F40DH 0F40EH 0F40FH 0F410H 0F411H 0F412H 0F413H 0F414H 0F415H 0F416H 0F417H 0F418H 0F419H 0F41AH 0F41BH 0F41CH 0F41DH 0F41EH 0F41FH 0F420H 0F421H 0F422H 0F423H 0F424H 0F425H 0F426H 0F427H Name Amp gain register Amp control register0 RC-ADC counter A register 0 RC-ADC counterA register 1 RC-ADC counterA register 2 RC-ADC counterB register 0 RC-ADC counterB register 1 RC-ADC counterB register 2 RC-ADC mode register RC-ADC control register Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A FEUL610Q438 Symbol (Byte) AMPGAIN AMPCON0 RADCA0 RADCA1 RADCA2 RADCB0 RADCB1 RADCB2 RADMOD RADCON DS0C0A DS1C0A DS2C0A DS3C0A DS4C0A DS5C0A DS6C0A DS7C0A DS8C0A DS9C0A DS10C0A DS11C0A DS12C0A DS13C0A DS14C0A DS15C0A DS16C0A DS17C0A DS18C0A DS19C0A DS20C0A DS21C0A DS22C0A DS23C0A DS24C0A DS25C0A DS26C0A DS27C0A DS28C0A DS29C0A DS30C0A DS31C0A DS32C0A DS33C0A DS34C0A DS35C0A DS36C0A DS37C0A DS38C0A DS39C0A Symbol (Word)                                                   R/W Size R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Initial value 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined A -8 ML610Q438/ML610Q439 User’s Manual Appendix A Registers Address 0F428H 0F429H 0F42AH 0F42BH 0F42CH 0F42DH 0F42EH 0F42FH 0F430H 0F431H 0F432H 0F433H 0F434H 0F435H 0F436H 0F437H 0F438H 0F439H 0F43AH 0F43BH 0F43CH 0F43DH 0F43EH 0F43FH 0F440H 0F441H 0F442H 0F443H 0F444H 0F445H 0F446H 0F447H 0F448H 0F449H 0F44AH 0F44BH 0F44CH 0F44DH 0F44EH 0F44FH 0F450H 0F451H 0F452H 0F453H 0F454H 0F455H 0F456H 0F457H 0F458H 0F459H Name Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A FEUL610Q438 Symbol (Byte) DS40C0A DS41C0A DS42C0A DS43C0A DS44C0A DS45C0A DS46C0A DS47C0A DS48C0A DS49C0A DS50C0A DS51C0A DS52C0A DS53C0A DS54C0A DS55C0A DS56C0A DS57C0A DS58C0A DS59C0A DS60C0A DS61C0A DS62C0A DS63C0A DS0C1A DS1C1A DS2C1A DS3C1A DS4C1A DS5C1A DS6C1A DS7C1A DS8C1A DS9C1A DS10C1A DS11C1A DS12C1A DS13C1A DS14C1A DS15C1A DS16C1A DS17C1A DS18C1A DS19C1A DS20C1A DS21C1A DS22C1A DS23C1A DS24C1A DS25C1A Symbol (Word)                                                   R/W Size R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined A -9 ML610Q438/ML610Q439 User’s Manual Appendix A Registers Address 0F45AH 0F45BH 0F45CH 0F45DH 0F45EH 0F45FH 0F460H 0F461H 0F462H 0F463H 0F464H 0F465H 0F466H 0F467H 0F468H 0F469H 0F46AH 0F46BH 0F46CH 0F46DH 0F46EH 0F46FH 0F470H 0F471H 0F472H 0F473H 0F474H 0F475H 0F476H 0F477H 0F478H 0F479H 0F47AH 0F47BH 0F47CH 0F47DH 0F47EH 0F47FH 0F480H 0F481H 0F482H 0F483H 0F484H 0F485H 0F486H 0F487H 0F488H 0F489H 0F48AH 0F48BH Name Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A FEUL610Q438 Symbol (Byte) DS26C1A DS27C1A DS28C1A DS29C1A DS30C1A DS31C1A DS32C1A DS33C1A DS34C1A DS35C1A DS36C1A DS37C1A DS38C1A DS39C1A DS40C1A DS41C1A DS42C1A DS43C1A DS44C1A DS45C1A DS46C1A DS47C1A DS48C1A DS49C1A DS50C1A DS51C1A DS52C1A DS53C1A DS54C1A DS55C1A DS56C1A DS57C1A DS58C1A DS59C1A DS60C1A DS61C1A DS62C1A DS63C1A DS0C2A DS1C2A DS2C2A DS3C2A DS4C2A DS5C2A DS6C2A DS7C2A DS8C2A DS9C2A DS10C2A DS11C2A Symbol (Word)                                                   R/W Size R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined A -10 ML610Q438/ML610Q439 User’s Manual Appendix A Registers Address 0F48CH 0F48DH 0F48EH 0F48FH 0F490H 0F491H 0F492H 0F493H 0F494H 0F495H 0F496H 0F497H 0F498H 0F499H 0F49AH 0F49BH 0F49CH 0F49DH 0F49EH 0F49FH 0F4A0H 0F4A1H 0F4A2H 0F4A3H 0F4A4H 0F4A5H 0F4A6H 0F4A7H 0F4A8H 0F4A9H 0F4AAH 0F4ABH 0F4ACH 0F4ADH 0F4AEH 0F4AFH 0F4B0H 0F4B1H 0F4B2H 0F4B3H 0F4B4H 0F4B5H 0F4B6H 0F4B7H 0F4B8H 0F4B9H 0F4BAH 0F4BBH 0F4BCH 0F4BDH Name Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A FEUL610Q438 Symbol (Byte) DS12C2A DS13C2A DS14C2A DS15C2A DS16C2A DS17C2A DS18C2A DS19C2A DS20C2A DS21C2A DS22C2A DS23C2A DS24C2A DS25C2A DS26C2A DS27C2A DS28C2A DS29C2A DS30C2A DS31C2A DS32C2A DS33C2A DS34C2A DS35C2A DS36C2A DS37C2A DS38C2A DS39C2A DS40C2A DS41C2A DS42C2A DS43C2A DS44C2A DS45C2A DS46C2A DS47C2A DS48C2A DS49C2A DS50C2A DS51C2A DS52C2A DS53C2A DS54C2A DS55C2A DS56C2A DS57C2A DS58C2A DS59C2A DS60C2A DS61C2A Symbol (Word)                                                   R/W Size R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined A -11 ML610Q438/ML610Q439 User’s Manual Appendix A Registers Address 0F4BEH 0F4BFH 0F4C0H 0F4C1H 0F4C2H 0F4C3H 0F4C4H 0F4C5H 0F4C6H 0F4C7H 0F4C8H 0F4C9H 0F4CAH 0F4CBH 0F4CCH 0F4CDH 0F4CEH 0F4CFH 0F4D0H 0F4D1H 0F4D2H 0F4D3H 0F4D4H 0F4D5H 0F4D6H 0F4D7H 0F4D8H 0F4D9H 0F4DAH 0F4DBH 0F4DCH 0F4DDH 0F4DEH 0F4DFH 0F4E0H 0F4E1H 0F4E2H 0F4E3H 0F4E4H 0F4E5H 0F4E6H 0F4E7H 0F4E8H 0F4E9H 0F4EAH 0F4EBH 0F4ECH 0F4EDH 0F4EEH 0F4EFH Name Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A FEUL610Q438 Symbol (Byte) DS62C2A DS63C2A DS0C3A DS1C3A DS2C3A DS3C3A DS4C3A DS5C3A DS6C3A DS7C3A DS8C3A DS9C3A DS10C3A DS11C3A DS12C3A DS13C3A DS14C3A DS15C3A DS16C3A DS17C3A DS18C3A DS19C3A DS20C3A DS21C3A DS22C3A DS23C3A DS24C3A DS25C3A DS26C3A DS27C3A DS28C3A DS29C3A DS30C3A DS31C3A DS32C3A DS33C3A DS34C3A DS35C3A DS36C3A DS37C3A DS38C3A DS39C3A DS40C3A DS41C3A DS42C3A DS43C3A DS44C3A DS45C3A DS46C3A DS47C3A Symbol (Word)                                                   R/W Size R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined A -12 ML610Q438/ML610Q439 User’s Manual Appendix A Registers Address 0F4F0H 0F4F1H 0F4F2H 0F4F3H 0F4F4H 0F4F5H 0F4F6H 0F4F7H 0F4F8H 0F4F9H 0F4FAH 0F4FBH 0F4FCH 0F4FDH 0F4FEH 0F4FFH 0F500H 0F501H 0F502H 0F503H 0F504H 0F505H 0F506H 0F507H 0F508H 0F509H 0F50AH 0F50BH 0F50CH 0F50DH 0F50EH 0F50FH 0F510H 0F511H 0F512H 0F513H 0F514H 0F515H 0F516H 0F517H 0F518H 0F519H 0F51AH 0F51BH 0F51CH 0F51DH 0F51EH 0F51FH 0F520H 0F521H Name Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A FEUL610Q438 Symbol (Byte) DS48C3A DS49C3A DS50C3A DS51C3A DS52C3A DS53C3A DS54C3A DS55C3A DS56C3A DS57C3A DS58C3A DS59C3A DS60C3A DS61C3A DS62C3A DS63C3A DS0C4A DS1C4A DS2C4A DS3C4A DS4C4A DS5C4A DS6C4A DS7C4A DS8C4A DS9C4A DS10C4A DS11C4A DS12C4A DS13C4A DS14C4A DS15C4A DS16C4A DS17C4A DS18C4A DS19C4A DS20C4A DS21C4A DS22C4A DS23C4A DS24C4A DS25C4A DS26C4A DS27C4A DS28C4A DS29C4A DS30C4A DS31C4A DS32C4A DS33C4A Symbol (Word)                                                   R/W Size R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined A -13 ML610Q438/ML610Q439 User’s Manual Appendix A Registers Address 0F522H 0F523H 0F524H 0F525H 0F526H 0F527H 0F528H 0F529H 0F52AH 0F52BH 0F52CH 0F52DH 0F52EH 0F52FH 0F530H 0F531H 0F532H 0F533H 0F534H 0F535H 0F536H 0F537H 0F538H 0F539H 0F53AH 0F53BH 0F53CH 0F53DH 0F53EH 0F53FH 0F540H 0F541H 0F542H 0F543H 0F544H 0F545H 0F546H 0F547H 0F548H 0F549H 0F54AH 0F54BH 0F54CH 0F54DH 0F54EH 0F54FH 0F550H 0F551H 0F552H 0F553H Name Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A FEUL610Q438 Symbol (Byte) DS34C4A DS35C4A DS36C4A DS37C4A DS38C4A DS39C4A DS40C4A DS41C4A DS42C4A DS43C4A DS44C4A DS45C4A DS46C4A DS47C4A DS48C4A DS49C4A DS50C4A DS51C4A DS52C4A DS53C4A DS54C4A DS55C4A DS56C4A DS57C4A DS58C4A DS59C4A DS60C4A DS61C4A DS62C4A DS63C4A DS0C5A DS1C5A DS2C5A DS3C5A DS4C5A DS5C5A DS6C5A DS7C5A DS8C5A DS9C5A DS10C5A DS11C5A DS12C5A DS13C5A DS14C5A DS15C5A DS16C5A DS17C5A DS18C5A DS19C5A Symbol (Word)                                                   R/W Size R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined A -14 ML610Q438/ML610Q439 User’s Manual Appendix A Registers Address 0F554H 0F555H 0F556H 0F557H 0F558H 0F559H 0F55AH 0F55BH 0F55CH 0F55DH 0F55EH 0F55FH 0F560H 0F561H 0F562H 0F563H 0F564H 0F565H 0F566H 0F567H 0F568H 0F569H 0F56AH 0F56BH 0F56CH 0F56DH 0F56EH 0F56FH 0F570H 0F571H 0F572H 0F573H 0F574H 0F575H 0F576H 0F577H 0F578H 0F579H 0F57AH 0F57BH 0F57CH 0F57DH 0F57EH 0F57FH 0F580H 0F581H 0F582H 0F583H 0F584H 0F585H Name Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A FEUL610Q438 Symbol (Byte) DS20C5A DS21C5A DS22C5A DS23C5A DS24C5A DS25C5A DS26C5A DS27C5A DS28C5A DS29C5A DS30C5A DS31C5A DS32C5A DS33C5A DS34C5A DS35C5A DS36C5A DS37C5A DS38C5A DS39C5A DS40C5A DS41C5A DS42C5A DS43C5A DS44C5A DS45C5A DS46C5A DS47C5A DS48C5A DS49C5A DS50C5A DS51C5A DS52C5A DS53C5A DS54C5A DS55C5A DS56C5A DS57C5A DS58C5A DS59C5A DS60C5A DS61C5A DS62C5A DS63C5A DS0C6A DS1C6A DS2C6A DS3C6A DS4C6A DS5C6A Symbol (Word)                                                   R/W Size R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined A -15 ML610Q438/ML610Q439 User’s Manual Appendix A Registers Address 0F586H 0F587H 0F588H 0F589H 0F58AH 0F58BH 0F58CH 0F58DH 0F58EH 0F58FH 0F590H 0F591H 0F592H 0F593H 0F594H 0F595H 0F596H 0F597H 0F598H 0F599H 0F59AH 0F59BH 0F59CH 0F59DH 0F59EH 0F59FH 0F5A0H 0F5A1H 0F5A2H 0F5A3H 0F5A4H 0F5A5H 0F5A6H 0F5A7H 0F5A8H 0F5A9H 0F5AAH 0F5ABH 0F5ACH 0F5ADH 0F5AEH 0F5AFH 0F5B0H 0F5B1H 0F5B2H 0F5B3H 0F5B4H 0F5B5H 0F5B6H 0F5B7H Name Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A FEUL610Q438 Symbol (Byte) DS6C6A DS7C6A DS8C6A DS9C6A DS10C6A DS11C6A DS12C6A DS13C6A DS14C6A DS15C6A DS16C6A DS17C6A DS18C6A DS19C6A DS20C6A DS21C6A DS22C6A DS23C6A DS24C6A DS25C6A DS26C6A DS27C6A DS28C6A DS29C6A DS30C6A DS31C6A DS32C6A DS33C6A DS34C6A DS35C6A DS36C6A DS37C6A DS38C6A DS39C6A DS40C6A DS41C6A DS42C6A DS43C6A DS44C6A DS45C6A DS46C6A DS47C6A DS48C6A DS49C6A DS50C6A DS51C6A DS52C6A DS53C6A DS54C6A DS55C6A Symbol (Word)                                                   R/W Size R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined A -16 ML610Q438/ML610Q439 User’s Manual Appendix A Registers Address 0F5B8H 0F5B9H 0F5BAH 0F5BBH 0F5BCH 0F5BDH 0F5BEH 0F5BFH 0F5C0H 0F5C1H 0F5C2H 0F5C3H 0F5C4H 0F5C5H 0F5C6H 0F5C7H 0F5C8H 0F5C9H 0F5CAH 0F5CBH 0F5CCH 0F5CDH 0F5CEH 0F5CFH 0F5D0H 0F5D1H 0F5D2H 0F5D3H 0F5D4H 0F5D5H 0F5D6H 0F5D7H 0F5D8H 0F5D9H 0F5DAH 0F5DBH 0F5DCH 0F5DDH 0F5DEH 0F5DFH 0F5E0H 0F5E1H 0F5E2H 0F5E3H 0F5E4H 0F5E5H 0F5E6H 0F5E7H 0F5E8H 0F5E9H Name Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A FEUL610Q438 Symbol (Byte) DS56C6A DS57C6A DS58C6A DS59C6A DS60C6A DS61C6A DS62C6A DS63C6A DS0C7A DS1C7A DS2C7A DS3C7A DS4C7A DS5C7A DS6C7A DS7C7A DS8C7A DS9C7A DS10C7A DS11C7A DS12C7A DS13C7A DS14C7A DS15C7A DS16C7A DS17C7A DS18C7A DS19C7A DS20C7A DS21C7A DS22C7A DS23C7A DS24C7A DS25C7A DS26C7A DS27C7A DS28C7A DS29C7A DS30C7A DS31C7A DS32C7A DS33C7A DS34C7A DS35C7A DS36C7A DS37C7A DS38C7A DS39C7A DS40C7A DS41C7A Symbol (Word)                                                   R/W Size R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined A -17 ML610Q438/ML610Q439 User’s Manual Appendix A Registers Address 0F5EAH 0F5EBH 0F5ECH 0F5EDH 0F5EEH 0F5EFH 0F5F0H 0F5F1H 0F5F2H 0F5F3H 0F5F4H 0F5F5H 0F5F6H 0F5F7H 0F5F8H 0F5F9H 0F5FAH 0F5FBH 0F5FCH 0F5FDH 0F5FEH 0F5FFH 0F600H 0F601H 0F602H 0F603H 0F604H 0F605H 0F606H 0F607H 0F608H 0F609H 0F60AH 0F60BH 0F60CH 0F60DH 0F60EH 0F60FH 0F610H 0F611H 0F612H 0F613H 0F614H 0F615H 0F616H 0F617H 0F618H 0F619H 0F61AH 0F61BH Name Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register A Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B FEUL610Q438 Symbol (Byte) DS42C7A DS43C7A DS44C7A DS45C7A DS46C7A DS47C7A DS48C7A DS49C7A DS50C7A DS51C7A DS52C7A DS53C7A DS54C7A DS55C7A DS56C7A DS57C7A DS58C7A DS59C7A DS60C7A DS61C7A DS62C7A DS63C7A DS0C0B DS1C0B DS2C0B DS3C0B DS4C0B DS5C0B DS6C0B DS7C0B DS8C0B DS9C0B DS10C0B DS11C0B DS12C0B DS13C0B DS14C0B DS15C0B DS16C0B DS17C0B DS18C0B DS19C0B DS20C0B DS21C0B DS22C0B DS23C0B DS24C0B DS25C0B DS26C0B DS27C0B Symbol (Word)                                                   R/W Size R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined A -18 ML610Q438/ML610Q439 User’s Manual Appendix A Registers Address 0F61CH 0F61DH 0F61EH 0F61FH 0F620H 0F621H 0F622H 0F623H 0F624H 0F625H 0F626H 0F627H 0F628H 0F629H 0F62AH 0F62BH 0F62CH 0F62DH 0F62EH 0F62FH 0F630H 0F631H 0F632H 0F633H 0F634H 0F635H 0F636H 0F637H 0F638H 0F639H 0F63AH 0F63BH 0F63CH 0F63DH 0F63EH 0F63FH 0F640H 0F641H 0F642H 0F643H 0F644H 0F645H 0F646H 0F647H 0F648H 0F649H 0F64AH 0F64BH 0F64CH 0F64DH Name Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B FEUL610Q438 Symbol (Byte) DS28C0B DS29C0B DS30C0B DS31C0B DS32C0B DS33C0B DS34C0B DS35C0B DS36C0B DS37C0B DS38C0B DS39C0B DS40C0B DS41C0B DS42C0B DS43C0B DS44C0B DS45C0B DS46C0B DS47C0B DS48C0B DS49C0B DS50C0B DS51C0B DS52C0B DS53C0B DS54C0B DS55C0B DS56C0B DS57C0B DS58C0B DS59C0B DS60C0B DS61C0B DS62C0B DS63C0B DS0C1B DS1C1B DS2C1B DS3C1B DS4C1B DS5C1B DS6C1B DS7C1B DS8C1B DS9C1B DS10C1B DS11C1B DS12C1B DS13C1B Symbol (Word)                                                   R/W Size R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined A -19 ML610Q438/ML610Q439 User’s Manual Appendix A Registers Address 0F64EH 0F64FH 0F650H 0F651H 0F652H 0F653H 0F654H 0F655H 0F656H 0F657H 0F658H 0F659H 0F65AH 0F65BH 0F65CH 0F65DH 0F65EH 0F65FH 0F660H 0F661H 0F662H 0F663H 0F664H 0F665H 0F666H 0F667H 0F668H 0F669H 0F66AH 0F66BH 0F66CH 0F66DH 0F66EH 0F66FH 0F670H 0F671H 0F672H 0F673H 0F674H 0F675H 0F676H 0F677H 0F678H 0F679H 0F67AH 0F67BH 0F67CH 0F67DH 0F67EH 0F67FH Name Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B FEUL610Q438 Symbol (Byte) DS14C1B DS15C1B DS16C1B DS17C1B DS18C1B DS19C1B DS20C1B DS21C1B DS22C1B DS23C1B DS24C1B DS25C1B DS26C1B DS27C1B DS28C1B DS29C1B DS30C1B DS31C1B DS32C1B DS33C1B DS34C1B DS35C1B DS36C1B DS37C1B DS38C1B DS39C1B DS40C1B DS41C1B DS42C1B DS43C1B DS44C1B DS45C1B DS46C1B DS47C1B DS48C1B DS49C1B DS50C1B DS51C1B DS52C1B DS53C1B DS54C1B DS55C1B DS56C1B DS57C1B DS58C1B DS59C1B DS60C1B DS61C1B DS62C1B DS63C1B Symbol (Word)                                                   R/W Size R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined A -20 ML610Q438/ML610Q439 User’s Manual Appendix A Registers Address 0F680H 0F681H 0F682H 0F683H 0F684H 0F685H 0F686H 0F687H 0F688H 0F689H 0F68AH 0F68BH 0F68CH 0F68DH 0F68EH 0F68FH 0F690H 0F691H 0F692H 0F693H 0F694H 0F695H 0F696H 0F697H 0F698H 0F699H 0F69AH 0F69BH 0F69CH 0F69DH 0F69EH 0F69FH 0F6A0H 0F6A1H 0F6A2H 0F6A3H 0F6A4H 0F6A5H 0F6A6H 0F6A7H 0F6A8H 0F6A9H 0F6AAH 0F6ABH 0F6ACH 0F6ADH 0F6AEH 0F6AFH 0F6B0H 0F6B1H Name Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B FEUL610Q438 Symbol (Byte) DS0C2B DS1C2B DS2C2B DS3C2B DS4C2B DS5C2B DS6C2B DS7C2B DS8C2B DS9C2B DS10C2B DS11C2B DS12C2B DS13C2B DS14C2B DS15C2B DS16C2B DS17C2B DS18C2B DS19C2B DS20C2B DS21C2B DS22C2B DS23C2B DS24C2B DS25C2B DS26C2B DS27C2B DS28C2B DS29C2B DS30C2B DS31C2B DS32C2B DS33C2B DS34C2B DS35C2B DS36C2B DS37C2B DS38C2B DS39C2B DS40C2B DS41C2B DS42C2B DS43C2B DS44C2B DS45C2B DS46C2B DS47C2B DS48C2B DS49C2B Symbol (Word)                                                   R/W Size R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined A -21 ML610Q438/ML610Q439 User’s Manual Appendix A Registers Address 0F6B2H 0F6B3H 0F6B4H 0F6B5H 0F6B6H 0F6B7H 0F6B8H 0F6B9H 0F6BAH 0F6BBH 0F6BCH 0F6BDH 0F6BEH 0F6BFH 0F6C0H 0F6C1H 0F6C2H 0F6C3H 0F6C4H 0F6C5H 0F6C6H 0F6C7H 0F6C8H 0F6C9H 0F6CAH 0F6CBH 0F6CCH 0F6CDH 0F6CEH 0F6CFH 0F6D0H 0F6D1H 0F6D2H 0F6D3H 0F6D4H 0F6D5H 0F6D6H 0F6D7H 0F6D8H 0F6D9H 0F6DAH 0F6DBH 0F6DCH 0F6DDH 0F6DEH 0F6DFH 0F6E0H 0F6E1H 0F6E2H 0F6E3H Name Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B FEUL610Q438 Symbol (Byte) DS50C2B DS51C2B DS52C2B DS53C2B DS54C2B DS55C2B DS56C2B DS57C2B DS58C2B DS59C2B DS60C2B DS61C2B DS62C2B DS63C2B DS0C3B DS1C3B DS2C3B DS3C3B DS4C3B DS5C3B DS6C3B DS7C3B DS8C3B DS9C3B DS10C3B DS11C3B DS12C3B DS13C3B DS14C3B DS15C3B DS16C3B DS17C3B DS18C3B DS19C3B DS20C3B DS21C3B DS22C3B DS23C3B DS24C3B DS25C3B DS26C3B DS27C3B DS28C3B DS29C3B DS30C3B DS31C3B DS32C3B DS33C3B DS34C3B DS35C3B Symbol (Word)                                                   R/W Size R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined A -22 ML610Q438/ML610Q439 User’s Manual Appendix A Registers Address 0F6E4H 0F6E5H 0F6E6H 0F6E7H 0F6E8H 0F6E9H 0F6EAH 0F6EBH 0F6ECH 0F6EDH 0F6EEH 0F6EFH 0F6F0H 0F6F1H 0F6F2H 0F6F3H 0F6F4H 0F6F5H 0F6F6H 0F6F7H 0F6F8H 0F6F9H 0F6FAH 0F6FBH 0F6FCH 0F6FDH 0F6FEH 0F6FFH 0F700H 0F701H 0F702H 0F703H 0F704H 0F705H 0F706H 0F707H 0F708H 0F709H 0F70AH 0F70BH 0F70CH 0F70DH 0F70EH 0F70FH 0F710H 0F711H 0F712H 0F713H 0F714H 0F715H Name Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B FEUL610Q438 Symbol (Byte) DS36C3B DS37C3B DS38C3B DS39C3B DS40C3B DS41C3B DS42C3B DS43C3B DS44C3B DS45C3B DS46C3B DS47C3B DS48C3B DS49C3B DS50C3B DS51C3B DS52C3B DS53C3B DS54C3B DS55C3B DS56C3B DS57C3B DS58C3B DS59C3B DS60C3B DS61C3B DS62C3B DS63C3B DS0C4B DS1C4B DS2C4B DS3C4B DS4C4B DS5C4B DS6C4B DS7C4B DS8C4B DS9C4B DS10C4B DS11C4B DS12C4B DS13C4B DS14C4B DS15C4B DS16C4B DS17C4B DS18C4B DS19C4B DS20C4B DS21C4B Symbol (Word)                                                   R/W Size R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined A -23 ML610Q438/ML610Q439 User’s Manual Appendix A Registers Address 0F716H 0F717H 0F718H 0F719H 0F71AH 0F71BH 0F71CH 0F71DH 0F71EH 0F71FH 0F720H 0F721H 0F722H 0F723H 0F724H 0F725H 0F726H 0F727H 0F728H 0F729H 0F72AH 0F72BH 0F72CH 0F72DH 0F72EH 0F72FH 0F730H 0F731H 0F732H 0F733H 0F734H 0F735H 0F736H 0F737H 0F738H 0F739H 0F73AH 0F73BH 0F73CH 0F73DH 0F73EH 0F73FH 0F740H 0F741H 0F742H 0F743H 0F744H 0F745H 0F746H 0F747H Name Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B FEUL610Q438 Symbol (Byte) DS22C4B DS23C4B DS24C4B DS25C4B DS26C4B DS27C4B DS28C4B DS29C4B DS30C4B DS31C4B DS32C4B DS33C4B DS34C4B DS35C4B DS36C4B DS37C4B DS38C4B DS39C4B DS40C4B DS41C4B DS42C4B DS43C4B DS44C4B DS45C4B DS46C4B DS47C4B DS48C4B DS49C4B DS50C4B DS51C4B DS52C4B DS53C4B DS54C4B DS55C4B DS56C4B DS57C4B DS58C4B DS59C4B DS60C4B DS61C4B DS62C4B DS63C4B DS0C5B DS1C5B DS2C5B DS3C5B DS4C5B DS5C5B DS6C5B DS7C5B Symbol (Word)                                                   R/W Size R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined A -24 ML610Q438/ML610Q439 User’s Manual Appendix A Registers Address 0F748H 0F749H 0F74AH 0F74BH 0F74CH 0F74DH 0F74EH 0F74FH 0F750H 0F751H 0F752H 0F753H 0F754H 0F755H 0F756H 0F757H 0F758H 0F759H 0F75AH 0F75BH 0F75CH 0F75DH 0F75EH 0F75FH 0F760H 0F761H 0F762H 0F763H 0F764H 0F765H 0F766H 0F767H 0F768H 0F769H 0F76AH 0F76BH 0F76CH 0F76DH 0F76EH 0F76FH 0F770H 0F771H 0F772H 0F773H 0F774H 0F775H 0F776H 0F777H 0F778H 0F779H Name Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B FEUL610Q438 Symbol (Byte) DS8C5B DS9C5B DS10C5B DS11C5B DS12C5B DS13C5B DS14C5B DS15C5B DS16C5B DS17C5B DS18C5B DS19C5B DS20C5B DS21C5B DS22C5B DS23C5B DS24C5B DS25C5B DS26C5B DS27C5B DS28C5B DS29C5B DS30C5B DS31C5B DS32C5B DS33C5B DS34C5B DS35C5B DS36C5B DS37C5B DS38C5B DS39C5B DS40C5B DS41C5B DS42C5B DS43C5B DS44C5B DS45C5B DS46C5B DS47C5B DS48C5B DS49C5B DS50C5B DS51C5B DS52C5B DS53C5B DS54C5B DS55C5B DS56C5B DS57C5B Symbol (Word)                                                   R/W Size R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined A -25 ML610Q438/ML610Q439 User’s Manual Appendix A Registers Address 0F77AH 0F77BH 0F77CH 0F77DH 0F77EH 0F77FH 0F780H 0F781H 0F782H 0F783H 0F784H 0F785H 0F786H 0F787H 0F788H 0F789H 0F78AH 0F78BH 0F78CH 0F78DH 0F78EH 0F78FH 0F790H 0F791H 0F792H 0F793H 0F794H 0F795H 0F796H 0F797H 0F798H 0F799H 0F79AH 0F79BH 0F79CH 0F79DH 0F79EH 0F79FH 0F7A0H 0F7A1H 0F7A2H 0F7A3H 0F7A4H 0F7A5H 0F7A6H 0F7A7H 0F7A8H 0F7A9H 0F7AAH 0F7ABH Name Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B FEUL610Q438 Symbol (Byte) DS58C5B DS59C5B DS60C5B DS61C5B DS62C5B DS63C5B DS0C6B DS1C6B DS2C6B DS3C6B DS4C6B DS5C6B DS6C6B DS7C6B DS8C6B DS9C6B DS10C6B DS11C6B DS12C6B DS13C6B DS14C6B DS15C6B DS16C6B DS17C6B DS18C6B DS19C6B DS20C6B DS21C6B DS22C6B DS23C6B DS24C6B DS25C6B DS26C6B DS27C6B DS28C6B DS29C6B DS30C6B DS31C6B DS32C6B DS33C6B DS34C6B DS35C6B DS36C6B DS37C6B DS38C6B DS39C6B DS40C6B DS41C6B DS42C6B DS43C6B Symbol (Word)                                                   R/W Size R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined A -26 ML610Q438/ML610Q439 User’s Manual Appendix A Registers Address 0F7ACH 0F7ADH 0F7AEH 0F7AFH 0F7B0H 0F7B1H 0F7B2H 0F7B3H 0F7B4H 0F7B5H 0F7B6H 0F7B7H 0F7B8H 0F7B9H 0F7BAH 0F7BBH 0F7BCH 0F7BDH 0F7BEH 0F7BFH 0F7C0H 0F7C1H 0F7C2H 0F7C3H 0F7C4H 0F7C5H 0F7C6H 0F7C7H 0F7C8H 0F7C9H 0F7CAH 0F7CBH 0F7CCH 0F7CDH 0F7CEH 0F7CFH 0F7D0H 0F7D1H 0F7D2H 0F7D3H 0F7D4H 0F7D5H 0F7D6H 0F7D7H 0F7D8H 0F7D9H 0F7DAH 0F7DBH 0F7DCH 0F7DDH Name Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B FEUL610Q438 Symbol (Byte) DS44C6B DS45C6B DS46C6B DS47C6B DS48C6B DS49C6B DS50C6B DS51C6B DS52C6B DS53C6B DS54C6B DS55C6B DS56C6B DS57C6B DS58C6B DS59C6B DS60C6B DS61C6B DS62C6B DS63C6B DS0C7B DS1C7B DS2C7B DS3C7B DS4C7B DS5C7B DS6C7B DS7C7B DS8C7B DS9C7B DS10C7B DS11C7B DS12C7B DS13C7B DS14C7B DS15C7B DS16C7B DS17C7B DS18C7B DS19C7B DS20C7B DS21C7B DS22C7B DS23C7B DS24C7B DS25C7B DS26C7B DS27C7B DS28C7B DS29C7B Symbol (Word)                                                   R/W Size R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined A -27 ML610Q438/ML610Q439 User’s Manual Appendix A Registers Address 0F7DEH 0F7DFH 0F7E0H 0F7E1H 0F7E2H 0F7E3H 0F7E4H 0F7E5H 0F7E6H 0F7E7H 0F7E8H 0F7E9H 0F7EAH 0F7EBH 0F7ECH 0F7EDH 0F7EEH 0F7EFH 0F7F0H 0F7F1H 0F7F2H 0F7F3H 0F7F4H 0F7F5H 0F7F6H 0F7F7H 0F7F8H 0F7F9H 0F7FAH 0F7FBH 0F7FCH 0F7FDH 0F7FEH 0F7FFH Name Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B Display allocation register B FEUL610Q438 Symbol (Byte) DS30C7B DS31C7B DS32C7B DS33C7B DS34C7B DS35C7B DS36C7B DS37C7B DS38C7B DS39C7B DS40C7B DS41C7B DS42C7B DS43C7B DS44C7B DS45C7B DS46C7B DS47C7B DS48C7B DS49C7B DS50C7B DS51C7B DS52C7B DS53C7B DS54C7B DS55C7B DS56C7B DS57C7B DS58C7B DS59C7B DS60C7B DS61C7B DS62C7B DS63C7B Symbol (Word)                                   R/W Size R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined A -28 ML610Q438/ML610Q439 User’s Manual Appendix B Package Dimensions Appendix B Package Dimensions (Unit: mm) Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). FEUL610Q438 B-1 ML610Q438/ML610Q439 User’s Manual Appendix C Electrical Characteristics Appendix C Electrical Characteristics  Absolute Maximum Ratings (VSS = AVSS = 0V) Parameter Symbol Condition Rating Unit Power supply voltage 1 VDD Ta = 25°C −0.3 to +4.6 V Power supply voltage 2 AVDD Ta = 25°C −0.3 to +4.6 V Power supply voltage 3 VPP Ta = 25°C −0.3 to +9.5 V Power supply voltage 4 VDDL Ta = 25°C −0.3 to +3.6 V Power supply voltage 5 VDDX Ta = 25°C −0.3 to +3.6 V Power supply voltage 6 VL1 Ta = 25°C −0.3 to +1.75 V Power supply voltage 7 VL2 Ta = 25°C −0.3 to +3.5 V Power supply voltage 8 VL3 Ta = 25°C −0.3 to +5.25 V Power supply voltage 9 VL4 Ta = 25°C −0.3 to +7.0 V Input voltage VIN Ta = 25°C −0.3 to VDD+0.3 V Output voltage VOUT Ta = 25°C −0.3 to VDD+0.3 V Output current 1 IOUT1 Port3–A, Ta = 25°C −12 to +11 mA Output current 2 IOUT2 Port2, Ta = 25°C −12 to +20 mA PD Ta = 25°C 122 mW TSTG  −55 to +150 °C Power dissipation Storage temperature  Recommended Operating Conditions (VSS = AVSS = 0V) Parameter Operating temperature Operating voltage Symbol TOP VDD AVDD Condition Range ML610Q438,ML610Q439 − 20 to +70 ML610Q439P − 40 to +85  1.1 to 3.6 V AVDD  2.2 to 3.6 30k to 36k 30k to 650k 30k to 4.2M 1.0±30% 0.1±30% Unit °C Operating frequency (CPU) fOP Capacitor externally connected to VDDL pin Capacitor externally connected to VDDX pin CL0 CL1 VDD = 1.1 to 3.6V VDD = 1.3 to 3.6V VDD = 1.8 to 3.6V   CX  0.1±30% µF Capacitors externally connected to VL1, 2, 3, 4 pins Ca, b, c, d  1.0±30% µF Capacitors externally connected across C1 and C2 pins and across C3 and C4 pins C12, C34  1.0±30% µF FEUL610Q438 Hz µF C-1 ML610Q438/ML610Q439 User’s Manual Appendix C Electrical Characteristics  Clock Generation Circuit Operating Conditions (VSS = 0V) Rating Parameter Low-speed crystal oscillation frequency Recommended equivalent series resistance value of low-speed crystal oscillation Low-speed crystal oscillation *1 external capacitor Symbol Condition Unit Min. Typ. Max. fXTL   32.768k  Hz RL    40k Ω  0  CDL/CGL CL=6pF of crystal *2 oscillation CL=9pF of crystal oscillation CL=12pF of crystal oscillation  6   12  pF High-speed crystal/ceramic fXTH   4.0M / 4.096M  Hz oscillation frequency CDH   24  High-speed crystal oscillation pF external capacitor CGH   24  *1 : The external CDL and CGL need to be adjusted in consideration of variation of internal loading capacitance CD and CG, and other additional capacitance such as PCB layout. *2 : When using a crystal oscillator CL = 6pF, there is a possibility that can not be adjusted by external CDL and CGL.  Operating Conditions of Flash Memory Parameter Operating temperature Operating voltage Write cycles Data retention Symbol TOP VDD VDDL VPP CEP YDR Condition At write/erase *1 At write/erase *1 At write/erase *1 At write/erase   (VSS = AVSS = 0V) Range Unit 0 to +40 °C 2.75 to 3.6 2.5 to 2.75 V 7.7 to 8.3 80 cycles years 10 *1 : In addition the power supply to VDD pin and VPP pin, within the range 2.5V to 2.75V has to be supplied to VDDL pin when programming and eraseing Flash ROM. FEUL610Q438 C-2 ML610Q438/ML610Q439 User’s Manual Appendix C Electrical Characteristics  DC Characteristics (1/6) (VDD = 1.1 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, unless otherwise specified ) (1/6) Rating Measuring Parameter Symbol Condition Unit circuit Min. Typ. Max. Typ. Typ. Ta = 25°C 500 kHz −10% +10% VDD = 500kHz RC oscillation Ta = −20 to Typ. Typ. fRC 1.3 to 500 kHz frequency +70°C −25% +25% 3.6V Ta = −40 to Typ. Typ. 500 kHz +85°C −35% +35% LSCLK = 32.768kHz 4 PLL oscillation frequency* fPLL -2.5% 8.192 +2.5% MHz VDD = 1.8 to 3.6V Low-speed crystal oscillation TXTL   0.3 2 s 2 start time* 500kHz RC oscillation start time TRC   50 500 µs 1 High-speed crystal oscillation TXTH VDD = 1.8 to 3.6V ― 2 20 3 start time* PLL oscillation start time TPLL VDD = 1.8 to 3.6V ― 1 10 ms Low-speed oscillation stop TSTOP  0.2 3 20 *1 detect time Reset pulse width PRST  200   µs Reset noise elimination PNRST    0.3 pulse width Power-on reset activation TPOR    10 ms power rise time *1: When low-speed crystal oscillation stops for a duration more than the low-speed oscillation stop detect time, the system is reset to shift to system reset mode. 2 * : Use 32.768KHz Crystal Resonator DT-26 (Load capacitance 6pF) (KDS: DAISHINKU CORP.) is used (CGL=CDL=12pF) 3 * : Use 4.096MHz Crystal Oscillator CHC49SFWB (Kyocera). 4 * : 1024 clock average. [Reset pulse width] VIL1 RESET_N VIL1 PRST Reset pulse width (PRST) [Power-on reset activation power rise time] 0.9xVDD VDD 0.1xVDD TPOR Power-on reset activation power rise time (TPOR ) FEUL610Q438 C-3 ML610Q438/ML610Q439 User’s Manual Appendix C Electrical Characteristics  DC Characteristics (2/6) (VDD = 1.1 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, unless otherwise specified) (2/6) Rating Measuring Parameter Symbol Condition Unit circuit Min. Typ. Max. CN4–0 = 00H 0.89 0.94 0.99 CN4–0 = 01H 0.91 0.96 1.01 CN4–0 = 02H 0.93 0.98 1.03 CN4–0 = 03H 0.95 1.00 1.05 CN4–0 = 04H 0.97 1.02 1.07 CN4–0 = 05H 0.99 1.04 1.09 CN4–0 = 06H 1.01 1.06 1.11 CN4–0 = 07H 1.03 1.08 1.13 CN4–0 = 08H 1.05 1.10 1.15 CN4–0 = 09H 1.07 1.12 1.17 CN4–0 = 0AH 1.09 1.14 1.19 CN4–0 = 0BH 1.11 1.16 1.21 CN4–0 = 0CH 1.13 1.18 1.23 CN4–0 = 0DH 1.15 1.20 1.25 CN4–0 = 0EH 1.17 1.22 1.27 CN4–0 = 0FH 1.19 1.24 1.29 VDD = 3.0V, VL1 voltage VL1 V Tj = 25°C CN4–0 = 10H 1.21 1.26 1.31 CN4–0 = 11H 1.23 1.28 1.33 CN4–0 = 12H 1.25 1.30 1.35 CN4–0 = 13H 1.27 1.32 1.37 *1 CN4–0 = 14H 1.29 1.34 1.39 *1 CN4–0 = 15H 1.31 1.36 1.41 1 *1 CN4–0 = 16H 1.33 1.38 1.43 *1 CN4–0 = 17H 1.35 1.40 1.45 *1 CN4–0 = 18H 1.37 1.42 1.47 *1 CN4–0 = 19H 1.39 1.44 1.49 *1 CN4–0 = 1AH 1.41 1.46 1.51 *1 CN4–0 = 1BH 1.43 1.48 1.53 *1 CN4–0 = 1CH 1.45 1.50 1.55 *1 CN4–0 = 1DH 1.47 1.52 1.57 *1 CN4–0 = 1EH 1.49 1.54 1.59 *1 CN4–0 = 1FH 1.51 1.56 1.61 VL1 temperature deviation ∆VL1 VDD = 3.0V  −1.5  mV/°C VL1 voltage dependency ∆VL1 VDD = 1.3 to 3.6V  5 20 mV/V VL2 voltage VL2 VL3 VL4 VL1×2 VL1×3 VL1×3 VL1×4 Typ. +4% Typ. +4% Typ. +5% V VL4 voltage Typ. −10% Typ. −10% Typ. −10% VL1×2 VL3 voltage VDD = 3.0V, Tj = 25°C 300kΩ load (VL4−VSS) 1/3 bias VDD = 3.0V, 1/4 bias Tj = 25°C 300kΩ load 1/3 bias (VL4−VSS) 1/4 bias    600 ms LCD bias voltage generation time TBIAS *1: When using 1/4 bias, the VL1 voltage is set to typ. 1.32 V (same voltage as in CN4–0 = 13H). FEUL610Q438 C-4 ML610Q438/ML610Q439 User’s Manual Appendix C Electrical Characteristics  DC Characteristics (3/6) (VDD = 1.1 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, unless otherwise specified) (3/6) Rating Measuring Parameter Symbol Condition Unit circuit Min. Typ. Max. BLD threshold voltage BLD threshold voltage temperature deviation VBLD ∆VBLD FEUL610Q438 VDD = 1.35 to 3.6V VDD = 1.35 to 3.6V LD2–0 = 0H LD2–0 = 1H LD2–0 = 2H LD2–0 = 3H LD2–0 = 4H LD2–0 = 5H LD2–0 = 6H LD2–0 = 7H LD2–0 = 8H LD2–0 = 9H LD2–0 = 0AH LD2–0 = 0BH LD2–0 = 0CH LD2–0 = 0DH LD2–0 = 0EH LD2–0 = 0FH Typ. −2%  1.35 1.4 1.45 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.7 2.9 Typ. +2% 0  V 1 %/°C C-5 ML610Q438/ML610Q439 User’s Manual Appendix C Electrical Characteristics  DC Characteristics (4/6) (VDD = 1.1 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, unless otherwise specified) (4/6) Supply current 1 Supply current 2 Supply current 3 Supply current 4 Supply current 5 Supply current 6 IDD1 IDD2 IDD3 IDD4 IDD5 IDD6 CPU: In STOP state. Low-speed/high-speed oscillation: stopped. CPU: In HALT state (LTBC, RTC: Operating*3*5). High-speed oscillation: Stopped. LCD/BIAS circuits: Stopped. CPU: In 32.768kHz operating state.*1*3 High-speed oscillation: Stopped. LCD/BIAS circuits: Operating.*2 CPU: In 500kHz CR operating state. LCD/BIAS circuits: Operating.*2*3 CPU: In 2MHt CR operating state. LCD/BIAS circuits: Operating.*2*3 CPU: In 4.096MHz operating state. PLL: In oscillating state. LCD/BIAS circuits: Operating. *2*3 VDD = 1.8 to 3.6V Ta = 25°C  0.15 0.5 Ta = -20 to +70°C   2.5 Ta = -40 to +85°C   8.5 Ta = 25°C  0.5 1.3 Ta = -20 to +70°C   3.5 Ta = -40 to +85°C   9.5 Ta = 25°C  5 7 Ta = -20 to +70°C   12 Ta = -40 to +85°C   16 Ta = 25°C  70 85 Ta = -20 to +70°C   100 Ta = -40 to +85°C   100 Ta = 25°C  0.45 0.65 Ta = -20 to +70°C   0.85 Ta = -40 to +85°C   0.85 Ta = 25°C  0.8 1.0 Ta = -20 to +70°C   1.2 Ta = -40 to +85°C   1.2 µA µA 1 µA µA mA mA 1 * : CPU operating rate is 100% (No HALT state). 2 * : All SEGs: off waveform, No LCD panel load, 1/3 bias, 1/3 duty, Frame frequency: Approx. 64 Hz, Bias voltage multiplying clock: 1/128 LSCLK (256Hz) 3 * : Use 32.768KHz Crystal Resonator DT-26 (Load capacitance 6pF) (KDS: DAISHINKU CORP.) is used (CGL=CDL=12pF) 4 * : Use 4.096MHz Crystal Oscillator CHC49SFWB (Kyocera). 5 * : Significant bits of BLKCON0~BLKCON4 registers are all “1”. FEUL610Q438 C-6 ML610Q438/ML610Q439 User’s Manual Appendix C Electrical Characteristics  DC Characteristics (5/6) (VDD = 1.1 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, unless otherwise specified) (5/6) Rating Measuring Parameter Symbol Condition Unit circuit Min. Typ. Max. VDD IOH1 = −0.5mA, VDD = 1.8 to 3.6V   −0.5 Output voltage 1 VDD nd IOH1 = -0.1mA, VDD = 1.3 to 3.6V   VOH1 (P20–P22/2 −0.3 VDD function is IOH1 = -0.03mA, VDD = 1.1 to 3.6V   −0.3 selected) IOL1 = +0.5mA, VDD = 1.8 to 3.6V   0.5 (P30–P36) IOL1 = +0.1mA, VDD = 1.3 to 3.6V   0.5 (P40–P47) VOL1 (PA0–PA5) IOL1 = +0.03mA, VDD = 1.1 to 3.6V 0.3   IOH1 = −0.5mA, VDD = 1.8 to 3.6V Output voltage 2 nd (P20–P22/2 function is Not selected) Output voltage 3 (P40–P41) VOH2 IOH1 = -0.03mA, VDD = 1.1 to 3.6V Input current 1 (RESET_N) Input current 1 (TEST) FEUL610Q438       0.5 VOL3 IOL3 = +3mA, VDD = 2.0 to 3.6V 2 (when I C mode is selected)   0.4 VOH4 IOH4 = −0.2mA, VL1=1.2V VL4 −0.2   IOMH4 = +0.2mA, VL1=1.2V   VL3 +0.2 VOMH4S IOMH4S = −0.2mA, VL1=1.2V VL3 −0.2   VOM4 IOM4 = +0.2mA, VL1=1.2V   VL2 +0.2 VOM4S IOM4S = −0.2mA, VL1=1.2V VL2 −0.2   IOML4 = +0.2mA, VL1=1.2V   VL1 +0.2 VOML4S IOML4S = −0.2mA, VL1=1.2V VL1 −0.2   VOL4 IOL4 = +0.2mA, VL1=1.2V   0.2 IOOH VOH = VDD (in high-impedance state)   1 IOOL VOL = VSS (in high-impedance state) −1   IIH1 VIH1 = VDD VDD = 1.8 to 3.6V VIL1 = VSS VDD = 1.3 to 3.6V VDD = 1.1 to 3.6V VDD = 1.8 to 3.6V VIH1 = VDD VDD = 1.3 to 3.6V VDD = 1.1 to 3.6V VIL1 = Vss 0 −600 −600 −600 20 10 2 -1  −300 −300 −300 300 300 300  1 −20 -10 -2 600 600 600  2 30 200 IIH2Z VDD = 1.3 to 3.6V VDD = 1.1 to 3.6V VDD = 1.8 to 3.6V VIL2 = VSS VDD = 1.3 to 3.6V (when pulled-up) VDD = 1.1 to 3.6V VIH2 = VDD (in high-impedance state) 0.2 0.01 −200 −200 −200  30 30 −30 −30 −30  200 200 −2 -0.2 -0.01 1 IIL2Z VIL2 = VSS (in high-impedance state) −1   IIL1 IIH1 IIL1 Input current 2 (NMI) (P00–P03) (P04–P07) (P10–P11) (P30–P35) (P40–P47) (PA0–PA5)  IOL2 = +5mA, VDD = 1.8 to 3.6V VOML4 Output leakage (P20–P22) (P30–P35) (P40–P47) (PA0–PA5)  VOL2 VOMH4 Output voltage 4 (COM0–23) (SEG0–63) IOH1 = -0.1mA, VDD = 1.3 to 3.6V VDD −0.5 VDD −0.3 VDD −0.3 IIH2 IIL2 VIH2 = VDD (when pulled-down) VDD = 1.8 to 3.6V V 2 µA 3 µA 4 C-7 ML610Q438/ML610Q439 User’s Manual Appendix C Electrical Characteristics  DC Characteristics (6/6) (VDD = 1.1 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, unless otherwise specified) (6/6) Rating Measuring Parameter Symbol Condition Unit circuit Min. Typ. Max. Input voltage 1 (RESET_N) (TEST) (NMI) (P00–P03) (P04–P07) (P10–P11) (P31–P35) (P40–P43) (P45–P47) (PA0–PA5) Hysteresis width (RESET_N) (TEST) (NMI) (P00–P03) (P04–P07) (P10–P11) (P31–P35) (P40–P43) (P45–P47) (PA0–PA5) Input voltage 2 (P30, P44) Input pin capacitance (NMI) (P00–P03) (P04–P07) (P10–P11) (P30–P35) (P40–P47) (PA0–PA5) FEUL610Q438 VDD = 1.3 to 3.6V 0.7 ×VDD  VDD VDD = 1.1 to 3.6V 0.7 ×VDD  VDD VDD = 1.3 to 3.6V 0  0.3 ×VDD VDD = 1.1 to 3.6V 0  0.2 ×VDD VDD = 2.0 to 3.6V 0.05 ×VDD 0.18 ×VDD 0.4 ×VDD VDD = 1.1 to 3.6V 0.02 ×VDD 0.18 ×VDD 0.4 ×VDD VIH2  0.7 ×VDD  VDD VIL2  0  0.3 ×VDD CIN f = 10kHz Vrms = 50mV Ta = 25°C   5 VIH1 VIL1 V 5 pF  ∆VT C-8 ML610Q438/ML610Q439 User’s Manual Appendix C Electrical Characteristics  Hysteresis Width ∆VT VDD Input signal VSS Internal signal VDDL VSS Measuring circuit 1 XT0 C4 XT1 C3 C2 C34 32.768kHz crystal CGH P10/OSC0 C12 C1 CDH CV: 1µF CL0: 1µF CL1: 0.1µF CX: 0.1µF Ca,Cb,Cc,Cd: 1µF C12,C34: 1µF CGH: 24pF CDH: 24pF 32.768KHz Crystal Resonator ： DT-26 (Load capacitance 6pF) (KDS: DAISHINKU CORP.) 4.096MHz crystal: HC49SFWB (Kyocera) P11/OSC1 4.096MHz crystal VDD AVDD VREFVDDL VDDX VL1 VL2 VL3 VL4 VSS AVSS A CV CL1 CL0 CX Ca Cb Cc Cd Measuring circuit 2 (*2) VIL Input pins (*1) Output pins VIH VDD VDDL VDDX VL1 VL2 VL3 V VL4 AVDDVREF VSSAVSS (*1) Input logic circuit to determine the specified measuring conditions. (*2) Measured at the specified output pins. FEUL610Q438 C-9 ML610Q438/ML610Q439 User’s Manual Appendix C Electrical Characteristics Measuring circuit 3 (*2) VIL Input pins RS1 Output pins VIH VDD VDDL VDDX VL1 VL2 VL3 A VL4 AVDDVREF VSSAVSS *1: Input logic circuit to determine the specified measuring conditions. *2: Measured at the specified output pins. Measuring circuit 4 Input pins A Output pins (*3) VDD VDDL VDDX VL1 VL2 VL3 VL4 AVDD VREF VSSAVSS *3: Measured at the specified output pins. FEUL610Q438 C-10 ML610Q438/ML610Q439 User’s Manual Appendix C Electrical Characteristics VIL Input pins (*1) Output pins VIH VDD VDDL VDDX VL1 VL2 VL3 Waveform monitoring Measuring circuit 5 VL4 AVDDVREF VSSAVSS *1: Input logic circuit to determine the specified measuring conditions. FEUL610Q438 C-11 ML610Q438/ML610Q439 User’s Manual Appendix C Electrical Characteristics  AC Characteristics (External Interrupt) (VDD = 1.1 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, unless otherwise specified) Rating Parameter Symbol Condition Unit Min. Typ. Max. External interrupt disable period TNUL Interrupt: Enabled (MIE = 1), CPU: NOP operation System clock: 32.768kHz  76.8 106.8 µs P00–P07 (Rising-edge interrupt) tNUL P00–P07 (Falling-edge interrupt) tNUL NMI, P00–P07 (Both-edge interrupt) tNUL  AC Characteristics (UART) (VDD = 1.1 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, unless otherwise specified) Rating Parameter Symbol Condition Unit Min. Typ. Max. Transmit baud rate tTBRT   1 BRT* 1  s 1 BRT* BRT* 1 BRT* −3% +3% *1: Baud rate period (including the error of the clock frequency selected) set with the UART baud rate register (UA0BRTL,H) and the UART mode register 0 (UA0MOD0). Receive baud rate tRBRT  s tTBRT TXD0* tRBRT RXD0* *: Indicates the secondary function of the port. FEUL610Q438 C-12 ML610Q438/ML610Q439 User’s Manual Appendix C Electrical Characteristics  AC Characteristics (Synchronous Serial Port) (VDD = 1.1 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, unless otherwise specified) Rating Parameter Symbol Condition Unit Min. Typ. Max. When high-speed oscillation 10   µs is not active SCLK input cycle tSCYC (slave mode) When high-speed oscillation 1   µs is active (VDD = 1.8 to 3.6V) SCLK output cycle 1 tSCYC   SCLK*  s (master mode) When high-speed oscillation 4   µs is not active SCLK input pulse width tSW (slave mode) When high-speed oscillation 0.4   µs is active (VDD = 1.8 to 3.6V) 1 1 1 SCLK* SCLK output pulse width SCLK* SCLK* tSW  s (master mode) ×0.4 ×0.5 ×0.6 SOUT output delay time tSD    180 ns (slave mode) SOUT output delay time tSD    80 ns (master mode) SIN input setup time tSS  80   ns (slave mode) SIN input setup time tSS  180   ns (master mode) SIN input tSH  80   ns hold time *1: Clock period selected with S0CK3–0 of the serial port 0 mode register (SIO0MOD1) tSCYC tSW tSW SCLK0* tSD tSD SOUT0* tSS tSH SIN0* *: Indicates the secondary function of the port. FEUL610Q438 C-13 ML610Q438/ML610Q439 User’s Manual Appendix C Electrical Characteristics  AC Characteristics (I2C Bus Interface: Standard Mode 100kHz) (VDD = 1.1 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, unless otherwise specified) Rating Parameter Symbol Condition Unit Min. Typ. Max. SCL clock frequency fSCL  0  100 kHz SCL hold time tHD:STA  4.0   µs (start/restart condition) SCL ”L” level time tLOW  4.7   µs SCL ”H” level time tHIGH  4.0   µs SCL setup time tSU:STA  4.7   µs (restart condition) SDA hold time tHD:DAT  0  3.45 µs SDA setup time tSU:DAT  0.25   µs SDA setup time tSU:STO  4.0   µs (stop condition) Bus-free time tBUF  4.7   µs  AC Characteristics (I2C Bus Interface: Fast Mode 400kHz) (VDD = 1.1 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, unless otherwise specified) Rating Parameter Symbol Condition Unit Min. Typ. Max. SCL clock frequency fSCL  0  400 kHz SCL hold time tHD:STA  0.6   µs (start/restart condition) SCL ”L” level time tLOW  1.3   µs SCL ”H” level time tHIGH  0.6   µs SCL setup time tSU:STA  0.6   µs (restart condition) SDA hold time tHD:DAT  0  0.9 µs SDA setup time tSU:DAT  0.1   µs SDA setup time tSU:STO  0.6   µs (stop condition) Bus-free time tBUF  1.3   µs Start condition Restart condition Stop condition P40/SDA P41/SCL tHD:STA FEUL610Q438 tLOW tHIGH tSU:STA tHD:STA tSU:DAT tHD:DAT tSU:STO tBUF C-14 ML610Q438/ML610Q439 User’s Manual Appendix C Electrical Characteristics  AC Characteristics (RC Oscillation A/D Converter) (VDD = 1.1 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, unless otherwise specified) Rating Parameter Symbol Condition Unit Min. Typ. Max. RS0, RS1, Resistors for oscillation RT0, CS0, CT0, CS1 ≥ 740pF 1   kΩ RT0-1,RT1 fOSC1 Resistor for oscillation = 1kΩ 209.4 330.6 435.1 kHz Oscillation frequency 55.27 64.16 41.29 fOSC2 Resistor for oscillation = 10kΩ kHz VDD = 1.5V 5.97 7.06 4.71 fOSC3 Resistor for oscillation = 100kΩ kHz 5.982 6.225 RT0, RT0-1, RT1 = 1kHz 5.567 Kf1  RS to RT oscillation 1 1.01 RT0, RT0-1, RT1 = 10 kHz 0.99 frequency ratio *1 Kf2  VDD = 1.5V 0.108 0.118 RT0, RT0-1, RT1 = 100 kHz 0.104 Kf3  fOSC1 fOSC2 fOSC3 Kf1 Kf2 Kf3 Oscillation frequency VDD = 3.0V RS to RT oscillation frequency ratio *1 VDD = 3.0V Resistor for oscillation = 1kΩ Resistor for oscillation = 10kΩ Resistor for oscillation = 100kΩ RT0, RT0-1, RT1 = 1kHz RT0, RT0-1, RT1 = 10 kHz RT0, RT0-1, RT1 = 100 kHz 407.3 49.76 5.04 8.006 0.99 0.100 486.7 59.28 5.993 8.210 1 0.108 594.6 72.76 7.04 8.416 1.01 0.115 kHz kHz kHz    *1: Kfx is the ratio of the oscillation frequency by the sensor resistor to the oscillation frequency by the reference resistor on the same conditions. fOSCX(RT0-1−CS0 oscillation) fOSCX(RS0−CS0 oscillation) , IN0 CS0 RCT0 (*1) VIL *1: Input logic circuit to determine the specified measuring conditions. VDDL fOSCX(RT1−CS1 oscillation) fOSCX(RS1−CS1 oscillation) VDDX RT0, RT0-1, RT1: 1kΩ /10kΩ/100kΩ RS0, RS1: 10kΩ CS0, CT0, CS1: 560pF CVR0, CVR1: 820pF IN1 CS1 RS1 RT1 RCM VDD CV RT1 RT0 RS0 RS0 RT0 Input pins VIH , CVR1 RI0-1 CT0 CS0 CVR0 RS1 fOSCX(RT0−CS0 oscillation) fOSCX(RS0−CS0 oscillation) (x = 1, 2, 3) CS1 Kfx = Frequency measurement (fOSCX) VSS CL1 CL0 CX Note: - Please have the shortest layout for the common node (wiring patterns which are connected to the external capacitors, resistors and IN0/IN1 pin), including CVR0/CVR1. Especially, do not have long wire between IN0/IN1 and RS0/RS1. The coupling capacitance on the wires may occur incorrect A/D conversion. Also, please do not have signals which may be a source of noise around the node. FEUL610Q438 C-15 ML610Q438/ML610Q439 User’s Manual Appendix C Electrical Characteristics - When RT0/RT1 (Thermistor and etc.) requires long wiring due to the restricted placement, please have VSS(GND) trace next to the signal. - Please make wiring to components (capacitor, resisteor and etc.) necessory for objective measurement. Wiring to reserved components may affect to the A/D conversion operation by noise the components itself may have.  Electrical Characteristics of Successive Approximation Type A/D Converter (VDD = 1.1 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, unless otherwise specified) Rating Parameter Symbol Condition Unit Min. Typ. Max. Resolution n    12 bit 2.7V ≤ VREF ≤ 3.6V −4  +4 Integral non-linearity error IDL 2.2V ≤ VREF ≤ 2.7V −6  +6 2.7V ≤ VREF ≤ 3.6V −3  +3 LSB Differential non-linearity error DNL 2.2V ≤ VREF ≤ 2.7V −5  +5 Zero-scale error VOFF  −6  +6 Full-scale error FSE  −6  +6 Reference voltage VREF  2.2  AVDD V SACK = 0  25  (HSCLK = 375kHz to 625kHz) Conversion time tCONV φ/CH SACK = 1  112  (HSCLK = 1.5MHz to 4.2MHz) φ: Period of high-speed clock (HSCLK) AVDD Reference voltage VREF VDD VDDL 10µF 1µF A 0.1µF − 1µF RI≤5kΩ + Analog input 0.1µF FEUL610Q438 VDDX AIN0, AIN1 0.1µF VSS AVSS C-16 ML610Q438/ML610Q439 User’s Manual Appendix D Application Circuit Example Appendix D Application Circuit Example LCD 3.0V uEASE I/F VDD UVDD_O VTref RESET_N COM0~15(ML610Q439) COM0~23(ML610Q438) CV SEG0~63(ML610Q439) SEG0~55(ML610Q438) NMI P00/CAP0 RESET_N P01/CAP1 P02 TEST Vpp VDDL Vss TEST Vpp VDDL Vss CL1 CL0 C1 P30/IN0 ML610Q438 P31/CS0 P32/RS0 CX Cd Cc or VDDX Ca ML610Q439 RT0 P44/IN1 VL2 P45/CS1 VL1 P46/RS1 C34 CS1 RT1 AVDD AVref C12 C1 XT0 CGL CAV AVSS XL P42 (Output) XT1 32.768KHz Xtal CVR1 RS1 P47/RT1 C3 C2 CDL RS0 P35/RCM C4 1/4 Bias CVR0 P34/RCT0 VL4 VL3 Cb P33/RT0 CS0 EN VDD P22 /MD0 P20 /LED0 AIN0 P21 P43 P41 P40 /LED1 (Output) /SCL /SDA OUT GND ML8511 UV sensor Buzzer WP SCL SDA LED I C EEPROM A0 CV CL1 C1 Ca, Cb, Cc, Cd CGL CAV CS0, CS1 RT0, RT1 :1uF :0.1uF :1uF :1uF : 0 ~ 12pF :1uF : 560 pF : Thermistor (103AT/Semitec) Vcc 2 A1 A2 Vss CL0 CX C12,C34 CDL RS0, RS1 CVR0, CVR1 :1uF :0.1uF :1uF : 0 ~ 12pF : 10 KΩ : 820 pF *: For the configuration of the low-speed clock generation circuit, see Section 6.3.1, “Low-Speed Clock”. Figure D-1 Application Circuit Example FEUL610Q438 D-1 ML610Q438/ML610Q439 User’s Manual Appendix E Check List Appendix E Check List This Check List has notes to prevent commonly-made programming mistakes and frequently overlooked or misunderstood hardware features of the MCU. Check each note listed up chapter by chapter while coding the program or evaluating it using the MCU. Chapter 1 Overview [ ] Please confirm how to handle the unused pins(Refer to Section 1.3.4 in the user’s manual). Chapter 2 CPU and Memory • Program Memory size [ ] 129,024 Byte (0:0000H to 1:FFFFH) • Data RAM size [ ] 6144 Byte (0:D800H to 0:EFFFH) • Unused area [ ] Please fill test area 0:FC00H to 0:FDFFH with BRK instruction code “0FFH” (Refer to a startup file “S61043XSW.asm” for programming in the source code). [ ] For fail safe in your system, please fill unused program memory area (your program code does not use) with BRK instruction code “0FFH”. We will fill the area with the code “0FFH” at LAPIS semiconductor’s factory programming. • Initializing RAM [ ] The hardware reset does not initialize RAM. Please initialize RAM by the software. Chapter 3 Reset • Reset activation pulse width [ ] Minimum 200us (Refer to Appendix C-2 in the user’s manual) • Power-on reset occurrence power rising time [ ] Maximum 10ms (Refer to Appendix C-2 in the user’s manual) • Reset status flag [ ] No flag is provided that indicates the occurrence of reset by the RESET_N pin (Refer to section 3.2.2. in the user’s manual). • BRK instruction reset [ ] In system reset by the BRK instruction, no special function register (SFR) is initialized either. Therefore initialize the SFRs by your software. Chapter 4 Standby control / MCU control • STOP mode [ ] Please note the STPACP is not enabled when both interrupt enable flags and the interrupt request flags are “1” & MIE flag is “0” (Refer to Section 4.2.2~4.2.3. in the user’s manual). [ ] Place two NOP instructions next to the instruction that sets the STP bit to “1”(Refer to Section 4.3.3. in the user’s manual). • HALT mode [ ] Place two NOP instructions next to the instruction that sets the HLT bit to “1”(Refer to Section 4.3.2. in the user’s manual). • BLKCON registers [ ] BLKCON registers enable or disable corresponsive each peripheral (Refer to Section 4.2.4 ~ 4.2.8. in the user’s manual). [ ] When certain bits of block control registers are set to “1”, corresponding peripherals are reset (all registers are reset) and operating clocks for the peripherals stop. [ ] DXTSP bit (bit 4) of BLKCON4 register disables the operation of 32kHz oscillation stop detector in only HALT mode. Chapter 5 Interrupt • Unused interrupt vector table [ ] Please define all unused interrupt vector tables for fail safe. • Non-maskable interrupt [ ] The watchdog timer interrupt (WDTINT) and the NMI interrupt (NMINT) are non-maskable interrupts that do not depend on MIE flag(Refer to Section 5.2.9. and 5.3). FEUL610Q438 E-1 ML610Q438/ML610Q439 User’s Manual Appendix E Check List Chapter 6 Clock generation circuit • Initial System clock [ ] At power up or system reset, both built-in 500kHz RC oscillation and 32.768kHz crystal oscillation are oscillating, and 1/8 of the 500kHz RC oscillation clock(62.5kHz) is selected as a system clock for CPU. • PLL oscillation clock [ ] The PLL oscillation generates 8MHz clock which can be driven to an output pin, however the maximum CPU operating frequency is 4MHz. • Switching high-speed clock operation mode to low-speed clock operation mode [ ] When switching the high-speed clock to the low-speed clock after the power up, confirm the low-speed clock is oscillating for sure by checking Q128H bit is “1”. • Switching high-speed clock operation mode to another high-speed clock operation mode [ ] When switching the high-speed clock mode, the clock must be first switched back to low clock before switching to other high-speed clock (Refer to Section 6.2.2.). • Port 2 nd Function nd [ ] Specify the 2 function for the port 2 when driving a clock to the pin(Refer to Section 6.4 in the user’s manual). nd [ ] A high-speed crystal/ceramic oscillation or an external clock input mode does not require specifying the 2 function for the port 1(Refer to Section 19.3.2.) Chapter 7 TBC (Time Base Counter) • HTBCLK [ ] HTBLK goes through the HTBDR register. Set proper valute to the register(Refer to Section 7.2.3. in the user’s manual). • How to read LTBC [ ] Read consecutively LTBC(Low-speed Time Base Counter) twice until the last data coincides the previous data to prevent reading of uncertain data while counting up the clock (Refer to Section 7.3.1 in the user’s manual). Chapter 10 Timer • How to read the timer counter registers [ ] Check notes for reading the timer counter registers while counting up(Refer to Section 10.2.6. ~ 10.2.9. in the user’s manual). Chapter 11 PWM • Used Pin [ ] P34(PWM0) pin or P43(PWM0) pin is used. [ ] P35(PWM1) pin or P47(PWM1) pin is used. [ ] P20(PWM2) pin or P30(PWM2) pin is used. • How to read the PWM counter registers [ ] Check notes for reading the PWM counter registers while the PWM is operating(Refer to Section 11.2.4. in the user’s manual). • Port 2 nd Function [ ] Specify the 2 nd Function for the port(Refer to Section 11.4 in the user’s manual). Chapter 12 WDT • Overflow period Clear WDT during the selected overflow period: [ ] 125ms, [ ] 500ms, [ ] 2s, [ ] 8s • WDP [ ] Check the WDP before writing to the WDTCON and determine writing “5AH” or “0A5H” (Refer to Section 12.2.2. in the user’s manual). FEUL610Q438 E-2 ML610Q438/ML610Q439 User’s Manual Appendix E Check List Chapter 13 SSIO • Used pin [ ] P40(SIN0), P41(SCK0) and P42(SOUT0) are used, or P44(SIN0), P45(SCK0) and P46(SOUT0) are used. • Port 2 nd Function [ ] Specify the 2 nd Function for the port (Refer to Section 13.4. in the user’s manual) Chapter 14 UART • Used pin [ ] P02(RXD0) and P43(TXD0) are used, or [ ] P42(RXD0) and P43(TXD0) are used. [ ] Select the P02 or P42 for RXD0 by specifying U0RSEL bit of UA0MOD0 register. • Port 2 nd Function [ ] Specify the 2 nd Function for the port (Refer to Section 14.4. in the user’s manual) Chapter 15 I2C • Used pin [ ] P40(SDA) pin and P41(SCL) pin used. • Port 2 nd Function [ ] Specify the 2 nd Function for the port (Refer to Section 15.4. in the user’s manual) Chapter 16 NMI • Handling the pin [ ] Don’t leave Hi-impedance NMI pin in floating state. Chapter 17 ~ Chapter 22 Port • Handling the pin [ ] Don’t leave Hi-impedance Input ports in floating state. • Port 2 nd Function [ ] Specify properly PnCON0/1 and PnMOD0/1 registers for each port. Chapter 23 Melody / Buzzer • Enabling the LSCLK x 2 [ ] Set ENMLT bit of FCON1 register to “1” to enable the low-speed double clock (LSCLK x 2) before stating the melody or buzzer outputs. • Port 2 nd Function [ ] Specify the 2 nd Function for the port (Refer to Section 23.4. in the user’s manual) Chapter 24 RC oscillation type A/D converter • Counter register [ ] Reading the counter register A or B during the A/D conversion, returns the data written before starting the A/D conversion. • Oscillation monitor pin [ ] P35/RCM pin is a monitor pin for oscillation clock. The channel 0(P34-P30) and channel 1(P47-P44) share the monitor pin. [ ] Please use P35/RCM for the evaluation purpose and disable the output while operating in an actual application to minimize the noise. • Port 2 nd Function nd [ ] Specify the 2 Function for the port (Refer to Section 24.4. in the user’s manual). [ ] All the Port 3 pins except P35/RCM are configured as pins dedicated to the RC-ADC function during A/D conversion(Refer to Section 24.3.1. in the user’s manual). FEUL610Q438 E-3 ML610Q438/ML610Q439 User’s Manual Appendix E Check List Chapter 25 Successive Approximation type A/D converter • Operating conditions [ ] Please confirm the operating voltage and the clock frequency. VDD=1.8V~3.6V (HSCLK=375KHz~1.1MHz or 1.99MHz~4.2MHz）, AVDD=2.2V~3.6V • Others [ ] Use the A/D converter when the HSCLK is oscillating. [ ] Do not set SARUN bit of SADCON1 register to “1” on the condition both SACH0 bit and SACH1 bit of SADMOD0 register are “0” (Refer to Section 25.2.7 ~ Section 25.2). Chapter 26 LCD driver • Bias [ ] 1/3 bias or [ ] 1/4 bias • Duty [ ] ML610Q438: 1/1 ~ 1/24 duty [ ] ML610Q439: 1/1 ~ 1/16 duty • COM/SEG [ ] ML610Q438: 24COM x 56SEG [ ] ML610Q439: 16COM x 64SEG • External capacitor (1/3 bias) [ ] Ca=1uF(connected to VL1 pin), [ ] Cb=1uF(connected to VL2 pin), [ ] Cd=1uF(connected to VL4 pin), [ ] C12=1uF（connected between C1 and C2 pin）, [ ] C34=1uF(connected between C3 and C4 pin) (1/4 bias) [ ] Ca=1uF(connected to VL1 pin), [ ] Cb=1uF(connected to VL2 pin), [ ] Cc=1uF(connected to VL3 pin), [ ] Cd=1uF(connected to VL4 pin), [ ] C12=1uF（connected between C1 and C2 pin）, [ ] C34=1uF(connected between C3 and C4 pin) Chapter 27 BLD (Battery Low Detector) • Changing the threshold [ ] Please select the threshold voltage when the BLD circuit is OFF. Chapter 28 Power circuit • External capacitor [ ] CL0=1uF （connected to VDDL pin）, [ ] Cx =0.1uF (connected to VDDX pin） Chapter 29 On-chip debug [ ] Supply 3.0V ~ 3.6V to VDD pin when programming (erasing and writing) the Flash ROM with LAPIS semiconductor development tool uEASE. [ ] Please do not apply LSIs being used for debugging to mass production. [ ] Please validate the ROM code on your production board without LAPIS semiconductor development tool uEASE. Appendix A SFR (Specific Function Registers) • Initial data [ ] Please confirm there are some SFRs have undefined initial value at reset (Refer to Appendix A in the user’s manual). Appendix C Electrical Characteristics • Operating temperature [ ] -20’C to +70’C , [ ] -40’C to +85’C • Operating voltage vs Operating frequency [ ] Please confirm the operating conditions. [ ] +1.1V to +3.6V (0kHz to 36kHz: Low-speed crystal oscillation clock operation) [ ] +1.3V to +3.6V (30kHz to 625kHz: Built-in RC oscillation clock operation) [ ] +1.8V to +3.6V (30kHz to 4.2MHz: High-speed crystal/ceramic oscillation clock or built-in PLL oscillation clock) FEUL610Q438 E-4 Revision History ML610Q438/ML610Q439 User’s Manual Revision History Revision History Document No. Date FEUL610Q438-01 Oct.18, 2010 FEUL610Q438-02 Feb.2, 2011 FEUL610Q438-03 FEUL610Q438 May.08,2015 Page Previous Current Edition Edition – – B-1 B-1 All All 1-3, 26-3, 26-35 to 26-38, 26-47, E-4 1-3, 26-3, 26-35 to 26-38, 26-47, E-4 1-3 1-4 1-3 1-4 6-6 6-6 24-7 24-7 C-1 to C-7, C-11 to C-15 C-3 to C-8, C-14 to C-16 15-1, 15-6 to 15-9, 15-11 15-1, 15-6 to 15-9, 15-11 1-4, E-4 1-3 E-4 Description Final edition 1.0 Change of a Package Dimensions Change header and footer Delete the metal option of only ML610Q439’s LCD driver Delete the ML610Q438P(Chip), the ML610Q438P(144-pin plastic LQFP) and the ML610Q439(144-pin plastic LQFP). Change from "Shipment" to " Product name – Supported Function " Add the internal loading capacitance of the low-speed clock generation circuit. Add notes of the case that RC-ADC is stopped by software during A / D conversion. Change ELECTRICAL CHARACTERISTICS Corrected a typo. “100kbps@1MHz HSCLK” 100kbps@4MHz HSCLK. is corrected to Delete arbitration function (multi-master) and clock synchronization (handshake). Corrected a typo. R-1