Dear customer
LAPIS Semiconductor Co., Ltd. ("LAPIS Semiconductor"), on the 1st day of October,
2020, implemented the incorporation-type company split (shinsetsu-bunkatsu) in which
LAPIS established a new company, LAPIS Technology Co., Ltd. (“LAPIS
Technology”) and LAPIS Technology succeeded LAPIS Semiconductor’s LSI business.
Therefore, all references to "LAPIS Semiconductor Co., Ltd.", "LAPIS Semiconductor"
and/or "LAPIS" in this document shall be replaced with "LAPIS Technology Co., Ltd."
Furthermore, there are no changes to the documents relating to our products other than
the company name, the company trademark, logo, etc.
Thank you for your understanding.
LAPIS Technology Co., Ltd.
October 1, 2020
FEDL620Q150A-01
Issue Date: May 7, 2015
ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A
16-bit micro controller
GENERAL DESCRIPTION
This LSI is a high-performance 16-bit CMOS microcontroller into which rich peripheral circuits, such as 10-bit A/D converter,
timer, PWM, synchronous serial port, UART, I2C bus interface (master), Low level detect circuit, are incorporated around 16-bit
CPU nX-U16/100.
The CPU nX-U16/100 is capable of efficient instruction execution in 1-instruction 1-clock mode by 3-stage pipe line architecture
parallel procesing. and, this LSI has a data flash-memory fill area by a software which can be written in. In addition, it has an
on-chip debugging function, which allows software debugging/rewriting with the LSI mounted on the board.
FEATURES
• CPU
− 16-bit RISC CPU (CPU name: nX-U16/100)
− Instruction system:16-bit instructions
− Instruction set:Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations,
bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on
− On-Chip debug function
− Minimum instruction execution time
Approx 30.5 µs (at 32.768kHz system clock)
Approx 0.122 µs (at 8.192MHz system clock)
• Internal memory
− Flash-memory
Product
Program area
ML620Q151A/ML620Q154A/ML620Q157A
32-Kbyte* (16K × 16-bit)
ML620Q152A/ML620Q155A/ML620Q158A
48-Kbyte* (24K × 16-bit)
ML620Q153A/ML620Q156A/ML620Q159A
64-Kbyte* (32K × 16-bit)
* including unusable 1KByte TEST area
Internal 2-Kbyte Data Flash (1-Kbyte × 2) Rewrite cycle: 10,000 times
− SRAM: Internal 2-Kbyte RAM (2-Kbyte × 8 -bits)
Rewrite
cycle
100
• Interrupt controller
− 2 non-maskable interrupt sources (Internal source: BACK-UP CLOCK, WDT)
− maskable interrupt
Product
Interrupt source
ML620Q151A/ML620Q154A/ML620Q157A
27 (Internal source: 20, External source: 7)
ML620Q152A/ML620Q155A/ML620Q158A
28 (Internal source: 20, External source: 8)
ML620Q153A/ML620Q156A/ML620Q159A
28 (Internal source: 20, External source: 8)
− 4 steps of interrupt level, and a mask function
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FEDL620Q150A-01
ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A
• Time base counter
−
Low-speed time base counter × 1 channel
• Watchdog timer
− Generates a non-maskable interrupt upon the first overflow and a system reset occurs upon the second
− Free running
− Overflow period: 4 types selectable (125ms, 500ms, 2s, 8s @32.768kHz)
• Timers
− 8 bits × 2ch (16-bits configuration available × 1ch)
− 16 bits × 4ch
• PWM
− 16bits × 4ch
− The auto reload timer mode / PWM mode
− Timer start-stop function by the software and an external trigger.
− A pulse width can be measured using an external-trigger input.
− An external event can be selected as the counter clock.
− Complement synchronous PWM
• Synchronous serial port
− 1ch
− Master/slave selectable
− LSB first/MSB first selectable
− 8-bit length/16-bit length selectable
• UART
− Full-duplex × 1ch ( Half-duplex × 2ch )
− Bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits
− Positive logic/negative logic selectable
− Built-in baud rate generator
• I2C bus interface
− Master function only
− Fast mode (400kbit/s), Standard mode (100kbit/s)
• Successive approximation type A/D converter
− 10-bit A/D converter
− Input: 12ch （Maximum）
− Conversion time: 43us, 13.5µs per channel (conversion-time is selectable)
• Analog Comparator
− 1ch
− Edge for the interrupt and sampling function is selectable.
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FEDL620Q150A-01
ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A
• General-purpose ports （including secondary functions）
− Input-only ports
Product
ML620Q151A/ML620Q152A/ML620Q153A
ML620Q154A/ML620Q155A/ML620Q156A
ML620Q157A/ML620Q158A/ML620Q159A
− Output-only ports : 4ch
− Input/output ports
Product
ML620Q151A/ML620Q152A/ML620Q153A
ML620Q154A/ML620Q155A/ML620Q156A
ML620Q157A/ML620Q158A/ML620Q159A
Input-only ports (including multiple
functions)
When not using the When using the
crystal resonator
crystal resonator
6ch
5ch
7ch
6ch
7ch
6ch
Input/output ports (including multiple
functions)
When not using the When using the
crystal resonator
crystal resonator
31ch
30ch
34ch
33ch
46ch
45ch
• Reset
− Reset through the RESET_N pin
− Power-on reset generation when powered on
− Reset by the watchdog timer (WDT) overflow
− Reset by the Low Level Detector (LLD)
• Low Level detect function
− Threshold voltages: 4values (1.9V/2.55V/3.7V/4.2V)
A threshold voltage is selected as Code-Option.
− LLD is a ready as a supply-voltage supervisory reset.
Reset or an interrupt output is selectable as Code-Option.
• Clock
− Low-speed clock (This LSI can not guarantee the operation without low-speed clock)
Crystal oscillation (32.768 kHz) or Built-in RC oscillation (32.768kHz)
Crystal oscillation or Built-in RC oscillation is selectable as Code-Option.
− High-speed clock
Built-in RC oscillation (2.097MHz) or Built-in PLL oscillation (8.192MHz)
• Power management
− HALT mode: Instruction execution by CPU is suspended (peripheral circuits are in operating states).
− STOP mode: Stop of low-speed oscillation and high-speed oscillation (Operations of CPU and peripheral circuits are
stopped.)
− Clock gear: The frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, or 1/8 of the oscillation
clock)
− Block control function: Operation of an intact functional block circuit is powerd down. (register reset and clock stop)
3/36
FEDL620Q150A-01
ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A
• Package
Product
ML620Q151A/ML620Q152A/ML620Q153A
ML620Q154A/ML620Q155A/ML620Q156A
ML620Q157A/ML620Q158A/ML620Q159A
Package
48pinTQFP (P-TQFP48-0707-0.50-QK)
52pinTQFP (P-TQFP52-1010-0.65-TK)
64pinQFP (P-QFP64-1414-0.80-UK)
• Guaranteed operating range
− Operating temperature: −40°C to +105°C
− Operating voltage: VDD = 1.8V to 5.5V
The difference point of this LSI is shown below.
function
ML620Q151A/152A/153A
ML620Q154A/155A/156A
ML620Q157A/158A/159A
Shipment
48pinTQFP
32Kbyte(ML620Q151A)
48Kbyte(ML620Q152A)
52Kbyte(ML620Q153A)
27
52pinTQFP
32Kbyte(ML620Q154A)
48Kbyte(ML620Q155A)
52Kbyte(ML620Q156A)
28
64pinQFP
32Kbyte(ML620Q157A)
48Kbyte(ML620Q158A)
52Kbyte(ML620Q159A)
28
6
7
7
−
Available
Available
31
34
46
−
−
−
−
−
Available
−
−
−
−
flash capacity
(program area)
maskable interrupt
Input-only port
(At the case of crystal unused)
P05 port
Input/output port
(At the case of crystal unused)
P36,P53,P64 ports
P37 port
P50～P52 ports
P65～P67 ports
P70～P74 ports
Available
Available
Available
Available
Available
−:none
4/36
FEDL620Q150A-01
ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A
BLOCK DIAGRAM
Block Diagram of ML620Q151A/ML620Q152A/ML620Q153A(TQFP48)
CPU (nX-U16/100)
EPSW1∼3
GREG
0∼15
PSW
Timing
ALU
Controller
On-Chip
ICE
ELR1∼3
ECSR1∼3
LR
DSR/CSR
EA
PC
Instruction
Instruction
Decoder
Register
BUS
Controller
Data-bus
VDD
RESET N
3
TEST0*
TEST1_N
XT0
XT1
RAM
2Kbyte
Power
Interrupt
Controller
RESET &
TEST
INT
1
OSC
LSCLK*
OUTCLK*
INT
1
WDT
SCK0*
SIN0*
SOUT0*
2
UARTx1
(*1)
INT
1
RXD0*
TXD0*
RXD1*
TXD1*
I2Cx1
SDA0*
SA-ADC
INT
INT
LLD
SCL0*
INT
TBC
4
8bit Timer
×2
16bit Timer
×4
16bitTimer
with PWMx4
1
INT
AIN0 to AIN11
INT
CMP0P
CMP0M
SSIOx1
6
INT
4
INT
1
INT
VDD
VREF
INT
1
VSS
VDDL
Program
Memory
(FLASH)
32/48/64Kbyte
SP
Analog
1
Comparator
×1
* Secondary or tertiary or quaternary function
1
* Full-duplex × 1ch ( Half-duplex × 2ch )
2
* Cannot be used as I/O port when connecting the crystal resonator
3
* Cannot be used as I/O port when connecting the uEASE(On-chip debug emualtor)
7
GPIO
TMHAOUT*
TMHBOUT*
PWM4*
PWM5*
PWM6*
PWM7*
PW45EV0*
PW45EV1*
PW67EV0*
PW67EV1*
P00 to P04
2
P12*
2
P13*
3
P14*
P20 to P23
P30 to P35
P40 to P47
P54 to P57
P60 to P63
P80 to P87
Figure 1-1 Block Diagram of ML620Q151A/ML620Q152A/ML620Q153A(TQFP48)
5/36
FEDL620Q150A-01
ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A
Block Diagram of ML620Q154A/ML620Q155A/ML620Q156A(TQFP52)
CPU (nX-U16/100)
EPSW1∼3
GREG
0∼15
PSW
Timing
ALU
Controller
On-Chip
ICE
RESET N
3
TEST0*
TEST1_N
XT0
XT1
LR
DSR/CSR
EA
PC
Instruction
Instruction
Decoder
Register
INT
SSIOx1
SCK0*
SIN0*
SOUT0*
2
UARTx1
(*1)
INT
1
RXD0*
TXD0*
RXD1*
TXD1*
I2Cx1
SDA0*
1
RAM
2Kbyte
Power
Interrupt
Controller
RESET &
TEST
INT
1
OSC
INT
1
WDT
SA-ADC
INT
TBC
INT
LLD
SCL0*
INT
6
INT
4
INT
1
INT
4
8bit Timer
×2
16bit Timer
×4
16bitTimer
with PWMx4
1
INT
AIN0 to AIN11
INT
CMP0P
CMP0M
Program
Memory
(FLASH)
32/48/64Kbyte
BUS
Controller
Data-bus
LSCLK*
OUTCLK*
VDD
VREF
ECSR1∼3
SP
VDD
VSS
VDDL
ELR1∼3
Analog
8
1
Comparator
×1
* Secondary or tertiary or quaternary function
1
* Full-duplex × 1ch ( Half-duplex × 2ch )
2
* Cannot be used as I/O port when connecting the crystal resonator
3
* Cannot be used as I/O port when connecting the uEASE(On-chip debug emualtor)
GPIO
TMHAOUT*
TMHBOUT*
PWM4*
PWM5*
PWM6*
PWM7*
PW45EV0*
PW45EV1*
PW67EV0*
PW67EV1*
P00 to P05
2
P12*
2
P13*
3
P14*
P20 to P23
P30 to P36
P40 to P47
P54 to P57
P60 to P64
P80 to P87
Figure 1-2 Block Diagram of ML620Q154A/ML620Q155A/ML620Q156A(TQFP52)
6/36
FEDL620Q150A-01
ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A
Block Diagram of ML620Q157A/ML620Q158A/ML620Q159A(QFP64)
CPU (nX-U16/100)
EPSW1∼3
GREG
0∼15
PSW
Timing
ALU
Controller
On-Chip
ICE
RESET N
3
TEST0*
TEST1_N
XT0
XT1
LR
DSR/CSR
EA
PC
Instruction
Instruction
Decoder
Register
INT
SSIOx1
SCK0*
SIN0*
SOUT0*
2
UARTx1
(*1)
INT
1
RXD0*
TXD0*
RXD1*
TXD1*
I2Cx1
SDA0*
1
RAM
2Kbyte
Power
Interrupt
Controller
RESET &
TEST
INT
1
OSC
INT
1
WDT
SA-ADC
INT
TBC
INT
LLD
SCL0*
INT
6
INT
4
INT
1
INT
4
8bit Timer
×2
16bit Timer
×4
16bitTimer
with PWMx4
1
INT
AIN0 to AIN11
INT
CMP0P
CMP0M
Program
Memory
(FLASH)
32/48/64Kbyte
BUS
Controller
Data-bus
LSCLK*
OUTCLK*
VDD
VREF
ECSR1∼3
SP
VDD
VSS
VDDL
ELR1∼3
Analog
8
1
Comparator
×1
* Secondary or tertiary or quaternary function
1
* Full-duplex × 1ch ( Half-duplex × 2ch )
2
* Cannot be used as I/O port when connecting the crystal resonator
3
* Cannot be used as I/O port when connecting the uEASE(On-chip debug emualtor)
GPIO
TMHAOUT*
TMHBOUT*
PWM4*
PWM5*
PWM6*
PWM7*
PW45EV0*
PW45EV1*
PW67EV0*
PW67EV1*
P00 to P05
2
P12*
2
P13*
3
P14*
P20 to P23
P30 to P37
P40 to P47
P54 to P57
P60 to P64
P70 to P74
P80 to P87
Figure 1-3 Block Diagram of ML620Q157A/ML620Q158A/ML620Q159A(QFP64)
7/36
FEDL620Q150A-01
ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A
PIN CONFIGURATION
P63/PW67EV1
P62/PW45EV1
P61/SCL/TMHBOUT/PWM7
P60/SDA/TMHAOUT/PWM6
P86/RXD0/SOUT0
P85/TXD1/SCK0
P84/RXD1/SIN0
P83/PWM5
P82/SOUT0
P81/SCL/SCK0
P80/SDA/SIN0
36
35
34
33
32
31
30
29
28
27
26
25
P87/TXD0/PWM4
ML620Q151A/ML620Q152A/ML620Q153A TQFP48 package product
P00/EXI0/PW45EV0
P01/EXI1/PW67EV0
P02/EXI2/RXD0
P03/EXI3/RXD1
P04/EXI4
P20/LED0/LSCLK/PWM4
P21/LED1/OUTCLK/PWM5
P22/LED2/TMHAOUT/PWM6
P23/LED3/TMHBOUT/PWM7
(TOP VIEW)
TQFP48
24
23
22
21
20
19
18
17
16
15
14
13
P57/SOUT0/PWM7
P56/SCK0
P55/TXD0/SIN0/TXD1
P54/RXD0
P47/AIN11/T16CK1/PWM5
P46/AIN10/T16CK0/SOUT0
P45/AIN9/T1P5CK/SCK0
P44/AIN8/T0P4CK/SIN0
P43/AIN7/TXD0/PWM4/TXD1
P42/AIN6/RXD0/SOUT0
P41/SCL/SCK0/CMP0P
P40/SDA/SIN0/CMP0M
P13/XT1
VSS
VDDL
VDD
VREF
P30/EXI6/AIN0/PW45EV1
P31/EXI7/AIN1/PW67EV1
P32/AIN2/PW45EV0
P33/AIN3/PW67EV0
P34/AIN4/PWM4
P35/AIN5/PWM5
P12/XT0
1
2
3
4
5
6
7
8
9
10
11
12
P14/TEST0
RESET_N
TEST1_N
37
38
39
40
41
42
43
44
45
46
47
48
Figure 1-4 Pin Layout of ML620Q151A/ML620Q152A/ML620Q153A TQFP48 Package
8/36
FEDL620Q150A-01
ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A
40
41
42
43
44
45
46
47
48
49
50
51
52
P86 /RXD0/SOUT0
P85/TXD1/SCK0
P84/RXD1/SIN0
P83 /PWM5
P82/SOUT0
P81/SCL/SCK0
P80/SDA/SIN0
P64/PWM4
P63/PW67EV1
P62/PW45EV1
P61/SCL/TMHBOUT/PWM7
P60/SDA/TMHAOUT/PWM6
(TOP VIEW)
TQFP52
26
25
24
23
22
21
20
19
18
17
16
15
14
P57/SOUT0/PWM7
P56/SCK0
P55/TXD0/SIN0/TXD1
P54/RXD0
P53/TXD1/PWM6
P47/AIN11/T16CK1/PWM5
P46/AIN10/T16CK0/SOUT0
P45/AIN9/T1P5CK/SCK0
P44/AIN8/T0P4CK/SIN0
P43/AIN7/TXD0/PWM4/TXD1
P42/AIN6/RXD0/SOUT0
P41/SCL/SCK0/CMP0P
P40/SDA/SIN0/CMP0M
P13/XT1
VSS
VDDL
VDD
VREF
P30/EXI6/AIN0/PW45EV1
P31/EXI7/AIN1/PW67EV1
P32/AIN2/PW45EV0
P33/AIN3/PW67EV0
P34/AIN4/PWM4
P35/AIN5/PWM5
P36/LSCLK
P12/XT0
1
2
3
4
5
6
7
8
9
10
11
12
13
P00/EXI0/PW45EV0
P01/EXI1/PW67EV0
P02/EXI2/RXD0
P03/EXI3/RXD1
P04/EXI4
P05/EXI5
P20/LED0/LSCLK/PWM4
P21/LED1/OUTCLK/PWM5
P22/LED2/TMHAOUT/PWM6
P23/LED3/TMHBOUT/PWM7
P14/TEST0
RESET_N
TEST1_N
39
38
37
36
35
34
33
32
31
30
29
28
27
P87/TXD0/PWM4
ML620Q154A/ML620Q155A/ML620Q156A TQFP52 package product
Figure 1-5 Pin Layout of ML620Q154A/ML620Q155A/ML620Q156A TQFP52 Package
9/36
FEDL620Q150A-01
ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P87/TXD0/PWM4
P86 /RXD0/SOUT0
P85/TXD1/SCK0
P84/RXD1/SIN0
P83 /PWM5
P82/SOUT0
P81/SCL/SCK0
P80/SDA/SIN0
P67
P66/OUTCLK/PWM6
P65/LSCK/PWM5
P64/PWM4
P63/PW67EV1
P62/PW45EV1
P61/SCL/TMHBOUT/PWM7
P60/SDA/TMHAOUT/PWM6
ML620Q157A/ML620Q158A/ML620Q159A QFP64 package product
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
(TOP VIEW)
QFP64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
P57/SOUT0/PWM7
P56/SCK0
P55/TXD0/SIN0/TXD1
P54/RXD0
P53/TXD1/PWM6
P52/RXD1/SOUT0
P51/SCL/SCK0
P50/SDA/SIN0
P47/AIN11/T16CK1/PWM5
P46/AIN10/T16CK0/SOUT0
P45/AIN9/T1P5CK/SCK0
P44/AIN8/T0P4CK/SIN0
P43/AIN7/TXD0/PWM4/TXD1
P42/AIN6/RXD0/SOUT0
P41/SCL/SCK0/CMP0P
P40/SDA/SIN0/CMP0M
P13/XT1
VSS
VDDL
VDD
VREF
P30/EXI6/AIN0/PW45EV1
P31/EXI7/AIN1/PW67EV1
P32/AIN2/PW45EV0
P33/AIN3/PW67EV0
P34/AIN4/PWM4
P35/AIN5/PWM5
P36/LSCLK
P37/OUTCLK
P70/PWM6
P71/PWM7
P12/XT0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
P00/EXI0/PW45EV0
P01/EXI1/PW67EV0
P02/EXI2/RXD0
P03/EXI3/RXD1
P04/EXI4
P05/EXI5
P20/LED0/LSCLK/PWM4
P21/LED1/OUTCLK/PWM5
P22/LED2/TMHAOUT/PWM6
P23/LED3/TMHBOUT/PWM7
P72/RXD1/SIN0
P73/TXD1/SCK0/TXD0
P74/SOUT0
P14/TEST0
RESET_N
TEST1_N
Figure 1-6 Pin Layout of ML620Q157A/ML620Q158A/ML620Q159A QFP64 Package
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FEDL620Q150A-01
ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A
List of Pins
48
Pin
No.
52
Pin
No.
64
Pin
No.
3
3
5
Primary function
Pin
name
I/O
3
Vss
⎯
5
5
VDD
⎯
4
4
4
VDDL
⎯
46
50
62
47
48
51
52
63
64
1
1
1
P12/
XT0
I
2
2
2
P13/
XT1
I/O
6
6
6
VREF
⎯
37
40
49
P00/EXI0/
PW45EV0
I
38
41
50
P01/EXI1/
PW67EV0
I
39
42
51
P02/EXI2/
RXD0
I
40
43
52
P03/EXI3/
RXD1
I
41
44
53
P04/EXI4
I
⎯
45
54
P05/EXI5
I
P14/
TEST0
RESET_N
TEST1_N
I
I
I
Description
Negative power
supply pin
Positive power
supply pin
Power supply for
internal logic
(internally generated)
Input port/
Input pin for testing
Reset input pin
Input pin for testing
Input port/
Low-speed clock
oscillation pin
Input/output port/
Low-speed clock
oscillation pin
Reference power
supply pin of
Successive-approxi
mation type ADC
Input port /
External interrupt /
PW45EV0 input
Input port /
External interrupt /
PW67EV0 input
Input port /
External interrupt
UART0 data input
Input port /
External interrupt
UART1 data input
Input port /
External interrupt
Input port /
External interrupt
Secondary function
Pin
name
Tertiary function
I/O
Description
Pin
name
⎯
⎯
⎯
⎯
⎯
⎯
Quaternary function
I/O
Description
Pin
name
I/O
Description
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
PWM4
O
PWM4
output
⎯
⎯
⎯
PWM5
O
PWM5
output
⎯
⎯
⎯
Low-spe
ed clock
output
Low-spe
ed clock
output
42
46
55
P20/
LED0/
O
Output port / LED
drive
LSCLK
O
43
47
56
P21/
LED1/
O
Output port / LED
drive
OUTCLK
O
44
48
57
P22/
LED2/
O
Output port / LED
drive
⎯
⎯
⎯
TMHAO
UT
O
TimerA
output
PWM6
O
PWM6
output
45
49
58
P23/
LED3/
O
⎯
⎯
⎯
TMHBO
UT
O
TimerB
output
PWM7
O
PWM7
output
7
7
7
P30/EXI6
PW45EV1/
AIN0
I/O
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
8
8
8
P31/EXI7
PW67EV1/
AIN1
I/O
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
9
9
9
P32/
PW45EV0/
AIN2
I/O
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
10
10
10
P33/
PW67EV0/
AIN3
I/O
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Output port / LED
drive
Input/output port /
PW45EV1 input /
Successive
approximation type
ADC input
Input/output port /
PW67EV1 input /
Successive
approximation type
ADC input
Input/output port /
PW45EV0 input /
Successive
approximation type
ADC input
Input/output port /
PW67EV0 input /
Successive
approximation type
11/36
FEDL620Q150A-01
ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A
48
Pin
No.
52
Pin
No.
64
Pin
No.
Primary function
Pin
name
I/O
Description
ADC input
Input/output port /
Successive
approximation type
ADC input
Input/output port /
Successive
approximation type
ADC input
Secondary function
Pin
name
Tertiary function
I/O
Description
Pin
name
⎯
⎯
⎯
⎯
⎯
⎯
11
11
11
P34/
AIN4/
I/O
12
12
12
P35/
AIN5/
I/O
⎯
13
13
P36
I/O
Input/output port
LSCLK
O
⎯
⎯
14
P37
I/O
Input/output port
OUTCLK
O
13
14
17
P40/
CMP0M
I/O
Input/output port /
Comparator0
inverting input
SDA
I/O
18
P41/
CMP0P
I/O
Input/output port /
Comparator0
non-inverting input
I/O
Low-spe
ed clock
output
Low-spe
ed clock
output
2
I C data
input/ou
tput
I/O
Pin
name
I/O
Description
PWM4
O
PWM4
output
⎯
⎯
⎯
PWM5
O
PWM5
output
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
SIN0
I
⎯
⎯
⎯
SCK0
I/O
⎯
⎯
⎯
2
14
15
15
16
19
P42/
AIN6
16
17
20
P43/
AIN7
I/O
17
18
21
P44/
T0P4CK/
AIN8
I/O
18
19
22
P45/
T1P5CK/
AIN9
I/O
19
20
23
P46/
T16CK0/
AIN10
I/O
20
21
24
P47/
T16CK1/
AIN11
I/O
⎯
⎯
25
P50
I/O
Input/output port /
Successive
approximation type
ADC input
Input/output port /
Successive
approximation type
ADC input
Input/output port /
PWM4 external clock
input/
Successive
approximation type
ADC input
Input/output port /
PWM5 external clock
input/
Successive
approximation type
ADC input
Input/output port /
Timer8,A /
PWM6 external clock
input /
Successive
approximation type
ADC input
Input/output port /
Timer9,B /
PWM7 external clock
input /
Successive
approximation type
ADC input
Input/output port
Quaternary function
Description
SSIO0
data
input
SSIO0
synchron
ous
clock
input/out
put
SCL
I/O
IC
clock
input/ou
tput
RXD0
I
UART0
data
input
SOUT0
O
SSIO0
data
output
⎯
⎯
⎯
TXD0
O
UART0
data
output
PWM4
O
PWM4
output
TXD1
O
UART1
data
output
⎯
⎯
⎯
SIN0
I
SSIO0
data
input
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
SCK0
I/O
SSIO0
synchron
ous
clock
input/out
put
⎯
⎯
⎯
SOUT0
O
SSIO0
data
output
⎯
⎯
⎯
⎯
⎯
⎯
PWM5
O
PWM5
output
⎯
⎯
⎯
SDA
I/O
I C data
input/ou
tput
SIN0
I
SCK0
I/O
SOUT0
O
2
2
⎯
⎯
26
P51
I/O
Input/output port
SCL
I/O
IC
clock
input/ou
tput
⎯
⎯
27
P52
I/O
Input/output port
RXD1
I
UART1
data
input
SSIO0
data
input
SSIO0
synchron
ous
clock
input/out
put
SSIO0
data
output
12/36
FEDL620Q150A-01
ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A
48
Pin
No.
52
Pin
No.
64
Pin
No.
⎯
22
21
Primary function
Pin
name
I/O
28
P53
23
29
22
24
23
Secondary function
Description
Pin
name
I/O
I/O
Input/output port
TXD1
O
P54
I/O
Input/output port
RXD0
I
30
P55
I/O
Input/output port
TXD0
O
25
31
P56
I/O
Input/output port
⎯
⎯
24
26
32
P57
I/O
Input/output port
⎯
⎯
25
27
33
P60
I/O
Input/output port
SDA
I/O
26
28
34
P61
I/O
Input/output port
SCL
I/O
27
29
35
⎯
⎯
28
30
36
⎯
⎯
Description
UART1
data
output
UART0
data
input
UART0
data
output
Tertiary function
Pin
name
I/O
Pin
name
I/O
Description
PWM6
O
PWM6
output
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
SIN0
I
TXD1
O
UART1
data
output
⎯
SCK0
I/O
⎯
⎯
⎯
⎯
SOUT0
O
PWM7
O
PWM7
output
TMHAO
UT
O
TimerA
output
PWM6
O
PWM6
output
TMHBO
UT
O
TimerB
output
PWM7
O
PWM7
output
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
PWM4
O
PWM4
output
⎯
⎯
⎯
PWM5
O
PWM5
output
⎯
⎯
⎯
PWM6
O
PWM6
output
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
TXD0
O
UART0
data
output
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
2
P62/
PW45EV1
P63/
PW67EV1
I/O
I/O
Input/output port /
PW45EV1 input
Input/output port /
PW67EV1 input
I C data
input/ou
tput
2
IC
clock
input/ou
tput
⎯
⎯
31
37
P64
I/O
Input/output port
⎯
⎯
⎯
⎯
38
P65
I/O
Input/output port
LSCLK
O
⎯
⎯
39
P66
I/O
Input/output port
OUTCLK
O
⎯
⎯
40
P67
I/O
Input/output port
⎯
⎯
Low-spe
ed clock
output
Low-spe
ed clock
output
⎯
⎯
⎯
15
P70
I/O
Input/output port
⎯
⎯
⎯
PWM6
O
⎯
⎯
16
P71
I/O
Input/output port
⎯
⎯
⎯
PWM7
O
⎯
⎯
59
P72
I/O
Input/output port
RXD1
I
UART1
data
input
SIN0
I
⎯
⎯
60
P73
I/O
Input/output port
TXD1
O
UART1
data
output
SCK0
I/O
⎯
⎯
61
P74
I/O
Input/output port
⎯
⎯
⎯
SOUT0
O
I/O
I C data
input/ou
tput
SIN0
I
SCK0
I/O
2
29
32
41
P80
I/O
Input/output port
SDA
Quaternary function
Description
2
30
33
42
P81
I/O
Input/output port
SCL
I/O
IC
clock
input/ou
tput
31
34
43
P82
I/O
Input/output port
⎯
⎯
⎯
SOUT0
O
32
35
44
P83
I/O
Input/output port
⎯
⎯
⎯
PWM5
O
33
36
45
P84
I/O
Input/output port
RXD1
I
UART1
data
SIN0
I
SSIO0
data
input
SSIO0
synchron
ous
clock
input/out
put
SSIO0
data
output
⎯
PWM6
output
PWM7
output
SSIO0
data
input
SSIO0
synchron
ous
clock
input/out
put
SSIO0
data
output
SSIO0
data
input
SSIO0
synchron
ous
clock
input/out
put
SSIO0
data
output
PWM5
output
SSIO0
data
13/36
FEDL620Q150A-01
ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A
48
Pin
No.
52
Pin
No.
64
Pin
No.
34
37
35
36
Primary function
Pin
name
I/O
46
P85
38
47
39
48
Secondary function
Description
Pin
name
I/O
I/O
Input/output port
TXD1
O
P86
I/O
Input/output port
RXD0
I
P87
I/O
Input/output port
TXD0
O
Description
input
UART1
data
output
UART0
data
input
UART0
data
output
Tertiary function
Pin
name
I/O
SCK0
I/O
SOUT0
O
PWM4
O
Description
input
SSIO0
synchron
ous
clock
input/out
put
SSIO0
data
output
PWM4
output
Quaternary function
Pin
name
I/O
Description
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
14/36
FEDL620Q150A-01
ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A
PIN DESCRIPTION
Pin name
I/O
Primary/
Secondary/
Tertiary/
Description
Logic
Quaternary
Power supply
VSS
—
Negative power supply pin
—
—
VDD
—
Positive power supply pin
—
—
VDDL
—
Positive power supply pin for internal logic (internally generated). Connect
capacitors (CL) (see Measuring Circuit 1) between this pin and VSS .
—
—
Test
TEST0
I
Input/output pin for testing.
—
Positive
TEST1_N
I
Input/output pin for testing. This pin has a pull-up resistor built in.
—
Negative
I
Reset input pin. When this pin is set to a “L” level, the device is placed in system
reset mode and the internal circuit is initialized. If after that this pin is set to a “H”
level, program execution starts. This pin has a pull-up resistor built in.
—
Negative
—
—
—
—
System
RESET_N
XT0
I
XT1
O
LSCLK*
O
Low-speed clock output. This function is allocated to the secondary function of the Secondary
P20/P36/P65 pin.
—
OUTCLK*
O
High-speed clock output. This function is allocated to the secondary function of
the P21/P37/P66 pin.
Secondary
—
Primary
Positive
Crystal connection pin for low-speed clock. A 32.768 kHz crystal oscillator (see
measuring circuit 1) is connected to this pin. Capacitors CDL and CGL are
connected across this pin and VSS as required.
General-purpose input port
P00 to P05*
I
P12
I
P13
I/O
P14
I
General-purpose input or output ports.
General-purpose output port
P20 to P23
O
General-purpose output ports. Provided with a secondary or tertiary or quaternary Secondary/
function for each port. Cannot be used as ports if their secondary functions or
Tertiary/
tertiary or quaternary are used.
Quaternary
Positive
General-purpose input/output port
P30 to P37*
P40 to P47
P50 to P57*
I/O General-purpose output ports. Provided with a secondary or tertiary or quaternary Secondary/
function for each port. Cannot be used as ports if their secondary functions or
Tertiary/
tertiary or quaternary are used.
Quaternary
Positive
P60 to P67*
P70 to P74*
P80 to P87
*: ML620Q15XA have a different pin configuration for each package. See “LIST OF PINS” for more details.
Pin name
I/O
Description
Primary/
Secondary/
Tertiary/
Logic
15/36
FEDL620Q150A-01
ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A
Quaternary
UART
O
UART0 data output pin. Allocated to the secondary function of the P43, P55 , Secondary
P87 and the fourthly function of the P73.
Quaternary
Positive
I
UART0 data input pin. Allocated to the secondary function of the P02, P42,
P54 and P86.
Secondary
Positive
O
UART1 data output pin. Allocated to the secondary function of the P53, P73, Secondary
P85, and the fourthly function of the P43, P55.
Quaternary
Positive
I
UART1 data input pin. Allocated to the secondary function of the P03, P52,
P72 and P84.
Secondary
Positive
Secondary
Positive
I2C clock output pin. This pin is used as the secondary function of the P41,
I/O P51, P61 and P81. This pin has an NMOS open drain output. When using this Secondary
pin as a function of the I2C, externally connect a pull-up resistor.
Positive
TXD0*
RXD0*
TXD1*
RXD1*
I2C bus interface
SDA*
SCL*
I2C data input/output pin. This pin is used as the secondary function of the
I/O P40, P50, P60 and P80. This pin has an NMOS open drain output. When
2
using this pin as a function of the I C, externally connect a pull-up resistor.
Synchronous serial (SSIO)
SIN0*
I
SCK0*
I/O
SOUT0*
O
Synchronous serial data input pin. Allocated to the tertiary function of the
P40, P44, P50, P55, P72, P80 and P84.
Synchronous serial clock input/output pin. Allocated to the tertiary function of
the P41, P45, P51, P56, P73, P81 and P85.
Synchronous serial data output pin. Allocated to the tertiary function of the
P42, P46, P52, P57, P74, P82 and P86.
Tertiary
Positive
Tertiary
—
Tertiary
Positive
Tertiary
Positive
Tertiary
Positive
PWM
PWM4*
O
PWM5*
O
PWM4 output pin. Allocated to the tertiary function of the P34, P43, P64 and
P87.
PWM5 output pin. Allocated to the tertiary function of the P35, P47, P65 and
P83.
O
Tertiary
PWM6 output pin. Allocated to the tertiary function of the P53, P66, P70 and
fourthly function of the P22 and P60.
Quaternary
O
PWM7 output pin. Allocated to the tertiary function of the P71 and fourthly
function of the P23, P57, and P61.
I
Control start /stop/clear for PWM4 and PWM5. Allocated to the primary
function of the P00, P30, P32 and P62.
Primary
—
I
Control start /stop/clear pin for PWM6 and PWM7. Allocated to the primary
function of the P01, P31, P33, and P63.
Primary
—
T0P4CK
I
External clock input pin for timer 0 and PWM4. Allocated to the primary
function of the P44 pin.
Primary
—
T1P5CK
I
External clock input pin for timer 1 and PWM5. Allocated to the primary
function of the P45 pin.
Primary
—
PWM6*
PWM7*
PW45EV0
PW45EV1
PW67EV0
PW67EV1
Tertiary
Quaternary
Positive
Positive
*: ML620Q15XA have a different pin configuration for each package. See “LIST OF PINS” for more details.
16/36
FEDL620Q150A-01
ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A
Pin name
Description
Primary/
Secondary
Logic
External maskable interrupt input pins. The interrupt is enabled and interrupt
edge is selectable by the software for each bit. Allocated to the primary
function of the P00 to P05 and P30 to P31.
Primary
Positive/
Negative
Primary
—
I/O
External interrupt
EXI0∼7*
I
Timer
T16CK0
I
T16CK1
TMHAOUT
TMHBOUT
External clock input pin for 16bit timer 8, timer A and PWM6. Allocated to the
primary function of the P46 pin.
I
External clock input pin for 16bit timer 9, timer B and PWM7. Allocated to the
primary function of the P47 pin.
Primary
—
O
16bit timer A output pin. Allocated to the tertiary function of the P22 andn
P60.
Tertiary
Positive
O
16bit timer B output pin. Allocated to the tertiary function of the P23 and P61.
Tertiary
Positive
O
Pins for LED driving. Allocated to the primary function of the P20 to P23 pins.
Primary
Positive/
Negative
LED drive
LED0 to
LED3
Successive-approximation type A/D converter
VREF
I
Reference power supply pin for successive approximation type A/D
converter.
—
—
AIN0 to
AIN11
I
Analog inputs to Ch0–Ch11 of the successive-approximation type A/D
converter. Allocated to the secondary function of the P30 to P35 and P42 to
P47 pins.
—
—
Analog Comparator
CMP0P
I
Non-inverting input for comparator0. This pin is used as the primary function
of the P41 pin.
—
—
CMP0M
I
Inverting input for comparator0. This pin is used as the primary function of
the P40 pin.
—
—
*: ML620Q15XA have a different pin configuration for each package. See “LIST OF PINS” for more details.
17/36
FEDL620Q150A-01
ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A
TERMINATION OF UNUSED PINS
How to Terminate Unused Pins
Pin
RESET_N
P14/TEST0
TEST1_N
VREF
P00 to P05*
P12
P13
P20 to P23
P30 to P37*
P40 to P47
P50 to P57*
P60 to P67*
P70 to P74*
P80 to P87
Recommended pin termination
open
open
open
Connect to VDD
Connect VDD or VSS
Connect VDD or VSS
open
open
open
open
open
open
open
open
*: ML620Q15XA have a different pin configuration for each package. See “LIST OF PINS” for more details.
Note:
For unused input ports or unused input/output ports, if the corresponding pins are configured as high-impedance
inputs and left open, the supply current may become excessively large. Therefore, it is recommended to
configure those pins as either inputs with a pull-down resistor/pull-up resistor or outputs.
18/36
FEDL620Q150A-01
ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(VSS = 0V)
Symbol
Condition
Rating
Unit
Power supply voltage 1
Parameter
VDD
Ta = 25°C
−0.3 to +6.5
V
Power supply voltage 2
VDDL
Ta = 25°C
−0.3 to +2.0
V
Reference voltage
VREF
Ta = 25°C
−0.3 to VDD+0.3
V
VAI
Ta = 25°C
−0.3 to VDD+0.3
V
Analog input voltage
VIN
Ta = 25°C
−0.3 to VDD+0.3
V
Output voltage
VOUT
−0.3 to VDD+0.3
V
Output current 1
IOUT1
−12 to +11
mA
Output current 2
Input voltage
IOUT2
Ta = 25°C
Port3,4,5,6,7,8
Ta = 25°C
Port2 Ta = 25°C
−12 to +20
mA
Power dissipation
PD
Ta = 25°C
1
W
Storage temperature
TSTG
―
−55 to +150
°C
Recommended Operating Conditions
(VSS = 0V)
Parameter
Symbol
Condition
Range
Unit
TOP
―
−40 to +105
°C
Operating voltage
VDD
―
1.8 to 5.5
V
Reference voltage
VREF
―
1.8 to VDD
V
Analog input voltage
Operating frequency (CPU)
Low-speed crystal oscillation frequency
VAI
fOP
fXTL
VSS to VREF
30k to 8.4M
32.768k
V
Hz
Hz
Low-speed crystal oscillation
external capacitor
CDL
CGL
―
―
―
Use 32.768KHz Crystal
Oscillator DT-26
(DAISHINKU CORP.)
CL
―
2.2±30%
Operating temperature
Capacitor externally connected to VDDL pin
12 to 25
12 to 25
pF
µF
19/36
FEDL620Q150A-01
ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A
Flash Memory Operating Conditions
Parameter
Symbol
Operating temperature
TOP
Operating voltage
VDD
CEPD
CEPP
―
Maximum rewrite count
Erase unit
―
―
Erase time
―
Write unit
Write time (Max.)
Data retention period
―
―
YDR
Condition
Data flash memory, At write/erase
Flash ROM, At write/erase
At write/erase
Data Flash
Program Flash
Chip erase
Program Flash
Block erase
Data Flash
Sector erase (Data Flash only)
Chip erase, Block erase, Sector
erase
―
1 word (2 Bytes)
―
(VSS = 0V)
Unit
Range
-40 to +105
0 to +40
1.8 to 5.5
10,000
100
All area
8
2
1
°C
V
times
―
KB
KB
KB
100
ms
1 word (2 Bytes)
40
15
―
µs
years
DC Characteristics (Oscillation, Reset)
Parameter
Low-speed crystal oscillation
1
start time*
Symbol
TXTL
(VDD=1.8 to 5.5V, VSS =0V, Ta=−40 to +105°C, unless otherwise specified)
Measur
Condition
Min.
Typ.
Max.
Unit
ing
circuit
―
―
0.6
Typ
32.768k
-1%
Low-speed RC oscillator
Typ
fLCR
32.768k
Ta= -40 to 85°C
frequency
-2.5%
Typ
32.768k
Ta= -40 to 105°C
-3%
Typ
2.097
Ta= +25°C
-5%
High-speed RC oscillator
fHCR
ferequency
Typ
2.097
Ta= -40°C to +105°C
-15%
LSCLK=32.768kHz
Typ
PLL oscillation frequency
8.192
fPLL
2,048 clock average
-1%
Reset pulse width
PRST
―
100
―
Reset noise rejection pulse width
PNRST
―
―
―
Power On Reset rising time
TPOR
―
―
―
*1: Use 32.768KHz Crystal Oscillator DT-26 (Daishinku) with capacitance CGL/CDL＝12pF.
Ta= +25°C
2
Typ
+1%
Typ
+2.5%
Typ
+3%
Typ
+5%
Typ
+15%
Typ
+1%
―
0.4
10
s
Hz
Hz
Hz
1
MHz
MHz
MHz
µs
ms
20/36
FEDL620Q150A-01
ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A
Reset
VIL1
RESET_N
VIL1
PRST
Reset pulse width (PRST)
VDD
1.8V
0V
TPOR
Power On Reset VDD Rising Time (TPOR)
21/36
FEDL620Q150A-01
ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A
DC Characteristics (LLD)
Parameter
Symbol
VDLLD threshold voltage
VD+
Hysterisis
Vhys
(VDD=2.2 to 5.5V, VSS =0V, Ta=−40 to +105°C, unless otherwise specified)
Meas
Condition
Min.
Typ.
Max.
Unit
uring
circuit
LD1 to 0 = 0H
1.8
1.9
2
LD1 to 0 = 1H
2.45
2.55
2.65
When power falling
LD1 to 0 = 2H
3.6
3.7
3.8
LD1 to 0 = 3H
4.1
4.2
4.3
V
1
LD1 to 0 = 0H
1.85
1.98
2.1
LD1 to 0 = 1H
2.5
2.63
2.75
When power rising
LD1 to 0 = 2H
3.65
3.78
3.9
LD1 to 0 = 3H
4.15
4.28
4.4
―
―
―
80
―
mV
mA
DC Characteristics (Analog Comparator)
Parameter
Symbol
Common mode Input
voltage
Input offset voltage
Response time
CMPnM
VIN
CMPnP
VIN
VCMPOF
TCMP
(VDD=2.2 to 5.5V, VSS =0V, Ta=−40 to +105°C, unless otherwise specified)
Meas
Condition
Min.
Typ.
Max.
Unit
uring
circuit
VDD
―
0
―
-1.4
V
―
0
1
―
VDD
―
CMPnP = CMPnM ± 100mV
―
―
100
1
5
―
mV
µS
DC Characteristics (IDD)
Parameter
Symbol
Supply current
1
IDD1
Supply current
2
Supply current
3
IDD2
IDD3
(VDD=1.8 to 5.5V, VSS =0V, Ta=−40 to +105°C, unless otherwise specified)
Meas
Condition
Min.
Typ.
Max. Unit
uring
circuit
CPU is in STOP state.
Low-speed/high-speed oscillation is
stopped. VDD=3.0V
Crystal Oscillating. CPU is in HALT
*2
state (LTBC,WBC: Operating ).
High-speed oscillation is stopped.
VDD=3.0V
Internal RC Oscillating. CPU is in HALT
*2
state (LTBC,WBC: Operating ).
High-speed oscillation is stopped.
VDD=3.0V
1
CPU: Running at 32kHz*
High-speed oscillation is stopped.
VDD=3.0V
-40 to +35℃
―
1.0
6
-40 to +105℃
―
1.0
22
-40 to +35℃
―
2.5
7
-40 to +105℃
―
2.5
24
-40 to +35℃
―
3.5
9
-40 to +105℃
―
3.5
26
-40 to +35℃
―
13
20
-40 to +105℃
―
13
42
―
0.64
2.0
―
5
8
Supply current
IDD4
CPU: Running at 2MHz RC oscillating mode*2
VDD=5.0V
4
CPU: Running at 8.192MHz PLL oscillating mode*2
Supply current
IDD5
5
VDD=5.0V
*1: Case when the CPU operating rate is 100% (with no HALT state)
*2 : Significant bits of BLKCON0 to BLKCON4 registers are all “1”.
µA
1
mA
22/36
FEDL620Q150A-01
ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A
DC Characteristics (VOHL, IOHL)
Parameter
Output voltage 1
(P20 to P23)
(P30 to P37)*
(P40 to P47)
(P50 to P57)*
(P60 to P67)*
(P70 to P74)*
(P80 to P87)
Output voltage 2
(P20–P23)
Output voltage 3
(P40 to P41)
(P50 to P51)*
(P60 to P61)*
(P80 to P81)
Output leakage
current
(P20 to P23)
(P30 to P37)*
(P40 to P47)
(P50 to P57)*
(P60 to P67)*
(P70 to P74)*
(P80 to P87)
(VDD=1.8 to 5.5V, VSS =0V, Ta=−40 to +105°C, unless otherwise specified)
Measuring
Condition
Min.
Typ.
Max.
Unit
circuit
Symbol
VOH1
IOH1 = −0.5mA
VDD
−0.5
―
―
VOL1
IOL1 = +0.5mA
―
―
0.5
―
―
0.5
―
―
0.5
IOL3 = +3mA
VDD ≥ 2.0V
―
―
0.4
IOL3 = +2mA
2.0V > VDD ≥ 1.8V
―
―
VDD*
0.2
―
―
1
VOL2
When LED drive
mode
is selected
2
VOL3
IOOH
IOOL
When I C mode
is selected
IOL2 = +10mA
VDD ≥ 5.0V
IOL2 = +8mA
VDD ≥ 3.0V
VOH = VDD
(in high-impedance state)
VOL = VSS
(in high-impedance state)
−1
―
V
2
µA
3
―
DC Characteristics (IIHL)
(VDD=1.8 to 5.5V, VSS =0V, Ta=−40 to +105°C, unless otherwise specified)
Measuring
Condition
Min.
Typ.
Max.
Unit
circuit
Parameter
Symbol
Input current 1
(RESET_N)
(TEST1_N)
Input current 2
(P00 to P05)*
(P30 to P37)*
(P40 to P47)
(P50 to P57)*
(P60 to P67)*
(P70 to P74)*
(P80 to P87)
IIH1
VIH1 = VDD
0
―
1
IIL1
VIL1 = VSS
−1500
−300
−20
IIH2
VIH2 = VDD (when pulled down)
2
30
250
IIL2
VIL2 = VSS (when pulled up)
−250
−30
−2
―
―
1
-1
―
―
IIH2Z
IIL2Z
VIH2 = VDD
(in high-impedance state)
VIL2 = VSS
(in high-impedance state)
µA
4
23/36
FEDL620Q150A-01
ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A
DC Characteristics (VIHL)
Parameter
Input voltage 1
(RESET_N)
(P14/TEST0)
(TEST1_N)
(P00 to P05)*
(P12, P13)
(P30 to P37)*
(P40 to P47)
(P50 to P57)*
(P60 to P67)*
(P70 to P74)*
(P80 to P87)
Input pin capacitance
(RESET_N)
(P14/TEST0)
(TEST1_N)
(P00 to P05)*
(P12, P13)
(P30 to P37)*
(P40 to P47)
(P50 to P57)*
(P60 to P67)*
(P70 to P74)*
(P80 to P87)
Symbol
VIH1
(VDD=1.8 to 5.5V, VSS =0V, Ta=−40 to +105°C, unless otherwise specified)
Measuring
Condition
Min.
Typ.
Max.
Unit
circuit
―
0.7×
VDD
―
VDD
VIL1
―
0
―
0.3×
VDD
CIN
f = 10kHz
Vrms = 50mV
Ta = 25°C
―
―
10
V
5
pF
―
*: ML620Q15X have a different pin configuration for each package. See “LIST OF PINS” for more details.
24/36
FEDL620Q150A-01
ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A
Measuring circuit 1
CGL
XT0
CDL
32.768kHz
crystal
XT1
CGH
VDD VREF
VDDL
A
CV
CL
VSS
CV
：2.2µF
CL
：2.2µF
CGL
：12pF
CDL
：12pF
32.768kHz Crystal oscillator
(DT-26 DAISHINKU Corp.)
Measuring circuit 2
(*2)
VIL
VDD VDDL VREF
Output pins
(*1)
Input pins
VIH
V
VSS
(*1) Input logic circuit to determine the specified measuring conditions.
(*2) Measured at the specified output pins.
25/36
FEDL620Q150A-01
ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A
Measuring circuit 3
(*2)
VIL
Input pins
(*1)
Output pins
VIH
VDD VDDL
VREF
A
VSS
(*1) Input logic circuit to determine the specified measuring conditions.
(*2) Measured at the specified output pins.
Measuring circuit 4
Input pins
A
Output pins
(*3)
VDD
VDDL
VREF
VSS
*3: Measured at the specified input pins.
26/36
FEDL620Q150A-01
ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A
VIL
Input pins
(*1)
Output pins
VIH
VDD
VDDL
VREF
Waveform monitoring
Measuring circuit 5
VSS
*1: Input logic circuit to determine the specified measuring conditions.
27/36
FEDL620Q150A-01
ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A
AC Characteristics (External Interrupt)
Parameter
External interrupt disable
period
Symbol
TNUL
(VDD=1.8 to 5.5V, VSS =0V, Ta=−40 to +105°C, unless otherwise specified)
Condition
Min.
Typ.
Max.
Unit
Interrupt: Enabled (MIE = 1),
2.5×
3.5×
―
µs
CPU: NOP operation
LSCLK
LSCLK
EXI0 to EXI7
(Rising-edge interrupt)
tNUL
EXI0 to EXI7
(Falling-edge interrupt)
tNUL
EXI0 to EXI7
(Both-edge interrupt)
tNUL
28/36
FEDL620Q150A-01
ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A
AC Characteristics (Synchronous Serial Port)
Parameter
Symbol
SCK input cycle
(slave mode)
tSCYC
SCK output cycle
(master mode)
tSCYC
SCK input pulse width
(slave mode)
tSW
(VDD=1.8 to 5.5V, VSS =0V, Ta=−40 to +105°C, unless otherwise specified)
Condition
Min.
Typ.
Max.
Unit
High-speed oscillation stopped
10
―
―
µs
500
During high-speed oscillation
―
―
ns
―
―
SCK(*1)
―
sec
High-speed oscillation stopped
4
―
―
µs
During high-speed oscillation
200
SCK(*1)
SCK output pulse width
―
tSW
(master mode)
×0.4
SOUT output delay time
―
―
tSD
(slave mode)
SOUT output delay time
―
―
tSD
(master mode)
SIN input setup time
―
80
tSS
(slave mode)
SIN input setup time
―
240
tSS
(Master mode)
SIN input hold time
―
80
tSH
*1: Clock period selected by SnCK3–0 of the serial port n mode register (SIOnMOD1)
―
―
ns
SCK(*1)
×0.5
SCK(*1)
×0.6
sec
―
180
ns
―
80
ns
―
―
ns
―
―
ns
―
―
ns
tSCYC
tSW
tSW
SCKn*
tSD
tSD
SOUTn
tSS
tSH
SINn*
*: Indicates the secondary function of the corresponding port.
29/36
FEDL620Q150A-01
ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A
AC Characteristics (I2C Bus Interface: Standard Mode 100kHz)
(VDD=1.8 to 5.5V, VSS =0V, Ta=−40 to +105°C, unless otherwise specified)
Rating
Symbol
Condition
Unit
Min.
Typ.
Max.
fSCL
⎯
0
⎯
100
kHz
Parameter
SCL clock frequency
SCL hold time
(start/restart condition)
SCL ”L” level time
SCL ”H” level time
SCL setup time
(restart condition)
SDA hold time
SDA setup time
SDA setup time
(stop condition)
Bus-free time
tHD:STA
⎯
4.0
⎯
⎯
µs
tLOW
tHIGH
⎯
⎯
4.7
4.0
⎯
⎯
⎯
⎯
µs
µs
tSU:STA
⎯
4.7
⎯
⎯
µs
tHD:DAT
tSU:DAT
⎯
⎯
0
0.25
⎯
⎯
⎯
⎯
µs
µs
tSU:STO
⎯
4.0
⎯
⎯
µs
tBUF
⎯
4.7
⎯
⎯
µs
AC Characteristics (I2C Bus Interface: Fast Mode 400kHz)
(VDD=1.8 to 5.5V, VSS =0V, Ta=−40 to +105°C, unless otherwise specified)
Rating
Symbol
Condition
Unit
Min.
Typ.
Max.
fSCL
⎯
0
⎯
400
kHz
Parameter
SCL clock frequency
SCL hold time
(start/restart condition)
SCL ”L” level time
SCL ”H” level time
SCL setup time
(restart condition)
SDA hold time
SDA setup time
SDA setup time
(stop condition)
Bus-free time
tHD:STA
⎯
0.6
⎯
⎯
µs
tLOW
tHIGH
⎯
⎯
1.3
0.6
⎯
⎯
⎯
⎯
µs
µs
tSU:STA
⎯
0.6
⎯
⎯
µs
tHD:DAT
tSU:DAT
⎯
⎯
0
0.1
⎯
⎯
⎯
⎯
µs
µs
tSU:STO
⎯
0.6
⎯
⎯
µs
tBUF
⎯
1.3
⎯
⎯
µs
Start
condition
Restart
condition
Stop
condition
SDA
SCL
tHD:STA
tLOW
tHIGH
tSU:STA tHD:STA
tSU:DAT
tHD:DAT
tSU:STO
tBUF
30/36
FEDL620Q150A-01
ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A
Characteristics of Successive Approximation Type A/D Converter
Parameter
Resolution
Symbol
n
Integral non-linearity error
INL
Differential non-linearity error
DNL
Zero-scale error
Full-scale error
Input impedance
A/D operating voltage
VOFF
FSE
RI
VREF
Conversion time
tCONV
(VDD=1.8 to 5.5V, VSS =0V, Ta=−40 to +105°C, unless otherwise specified)
Condition
Min.
Typ.
Max.
Unit
―
―
―
10
bits
2.7V ≤ VREF ≤ 5.5V
−4
―
+4
2.2V ≤ VREF ＜ 2.7V
−6
―
+6
−10
―
+10
1.8V ≤ VREF ＜ 2.2V
2.7V ≤ VREF ≤ 5.5V
−3
―
+3
LSB
2.2V ≤ VREF ＜ 2.7V
−5
―
+5
−9
―
+9
1.8V ≤ VREF ＜ 2.2V
RI ≤ 5kΩ
−6
―
+6
RI ≤ 5kΩ
−6
―
+6
―
―
―
5k
Ω
VREF ≤ VDD
2.7
―
5.5
V
CPU works in PLL oscillation mode
SACK bit = 0
―
13.5
―
2.7V ≤ VREF ≤ 5.5V
µs
CPU works in PLL oscillation mode
SACK bit = 1
―
43
―
1.8V ≤ VREF ≤ 5.5V
VDD
Reference
voltage
VREF
VDDL
1µF
2.2µF
A
-
2.2µF
Analog input
RI≤5kΩ
+
0.1µF
AIN0
to
AIN11
VSS
31/36
FEDL620Q150A-01
ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A
PACKAGE DIMENSIONS
ML620Q151A/ML620Q152A/ML620Q153A Package Dimension (48pin TQFP)
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact a ROHM sales office for the product name, package name,
pin number, package code and desired mounting conditions (reflow method, temperature and times).
32/36
FEDL620Q150A-01
ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A
ML620Q154A/ML620Q155A/ML620Q156A Package Dimension (52pin TQFP)
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact a ROHM sales office for the product name, package name,
pin number, package code and desired mounting conditions (reflow method, temperature and times).
33/36
FEDL620Q150A-01
ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A
ML620Q157A/ML620Q158A/ML620Q159A PACKAGE DIMENSION (64PIN TQFP)
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact a ROHM sales office for the product name, package name,
pin number, package code and desired mounting conditions (reflow method, temperature and times).
34/36
FEDL620Q150A-01
ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A
REVISION HISTORY
Document
No.
PEDL620Q150-01
PEDL620Q150-02
FEDL620Q150A-01
Date
Jul 15, 2014
Aug 14, 2014
Page
Previous Current
Edition
Edition
Description
–
–
Preliminary First Edition
P2-P4
P2-P4
Changed English expression for some descriptions.
P5-P7
P5-P7
Added notes (*) about some pins.
P10
P10
Corrected pin names of 57pin and 58pin.
P11
P11
Deleted the 2nd function of P02 and P03.
P13
P13
Corrected the tertiary function name of P70 and P71.
P15
P15
Changed English expression for the note(*).
P16
P16
Corrected description about PW45EVn and PW67EVn.
P17
P17
Corrected description about EXI0-7 and TMHnOUT.
P18
P18
Changed English expression for the note(*).
P21
P21
P24
P24
P32
–
P32
–
–
–
1
1
3
4
16
3
4
16
May 7, 2015
Added Power On Reset Rising Time (TPOR).
Corrected pin name and Change English expression for the
note(*).
Added 52pin TQFP package dimension.
Formal First Edition
z Changed the part numbers.
(Old) ML620Q151/152/153/154/155/156/157/158/159
(New)
ML620Q151A/152A/153A/154A/155A/156A/157A/158A/159A
z Made a list of ROM size and rewrite cycle.
z Made a list of the number of interrupt.
Made a list of the number of ports.
Made a list of the kinds of package.
Corrected the port name PWMn assigned.
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FEDL620Q150A-01
ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A
Notes
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