Dear customer
LAPIS Semiconductor Co., Ltd. ("LAPIS Semiconductor"), on the 1st day of October,
2020, implemented the incorporation-type company split (shinsetsu-bunkatsu) in which
LAPIS established a new company, LAPIS Technology Co., Ltd. (“LAPIS
Technology”) and LAPIS Technology succeeded LAPIS Semiconductor’s LSI business.
Therefore, all references to "LAPIS Semiconductor Co., Ltd.", "LAPIS Semiconductor"
and/or "LAPIS" in this document shall be replaced with "LAPIS Technology Co., Ltd."
Furthermore, there are no changes to the documents relating to our products other than
the company name, the company trademark, logo, etc.
Thank you for your understanding.
LAPIS Technology Co., Ltd.
October 1, 2020
FEDL62Q1300-02
Issue Date: Sep 27, 2019
ML62Q1300 Group
16-bit micro controller
GENERAL DESCRIPTION
ML62Q1300 Group is a high performance CMOS 16-bit microcontroller equipped with an 16-bit CPU nX-U16/100 and
integrated with program memory(Flash memory), data memory(RAM), data Flash and rich peripheral functions such as the
multiplier/divider, CRC operator, DMA controller, clock generator, timer, UART, synchronous serial port, I2C bus interface unit,
buzzer, Voltage Level Supervisor(VLS), successive approximation type A/D converter, D/A converter , analog comparator, safety
function(IEC60730/60335 Class B) and etc.
The CPU nX-U16/100 is capable of efficient instruction execution in 1-intruction 1-clock mode by pipeline architecture parallel
processing.
The built-in on-chip debug function enables debugging and programming the software. Also, ISP(In-System Programming)
function supports the Flash programming in production line.
The ML62Q1300 Group has five packages (16pin - 32pin) and five kinds of memory sizes(16Kbyte - 64Kbyte).
Table 1 ML62Q1300 Group Product List
Program
memory
Data memory
(RAM)
Data Flash
64Kbyte
48Kbyte
4Kbyte
32Kbyte
2Kbyte
32Kbyte
24Kbyte
16Kbyte
2Kbyte
16pin
SSOP16
WQFN16
20pin
TSSOP20
24pin
WQFN24
32pin
TQFP32
WQFN32
－
－
ML62Q1347
ML62Q1367
－
－
ML62Q1346
ML62Q1366
－
－
ML62Q1345
ML62Q1365
ML62Q1325
ML62Q1335
－
－
ML62Q1324
ML62Q1334
－
－
ML62Q1323
ML62Q1333
－
－
FEATURES
• CPU
− 16-bit RISC CPU (CPU name: nX-U16/100(A35 core))
− Instruction system: 16-bit length instruction
‒ Instruction set: Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations,
bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on
‒ On-chip debug function built-in (supported by LAPIS on-chip debug emulator EASE1000)
‒ ISP (In-System Programming) function built-in
‒ Minimum instruction execution time
30.5 μs (at 32.768 kHz system clock)
62.5ns/41.6ns (at 16 MHz/24MHz system clock)
• Coprocessor for multiplication and division
− Multiplication: 16bit × 16bit (operation time 4 cycles)
− Division: 32bit / 16bit (operation time 8 cycles)
− Division: 32bit / 32bit (operation time 16 cycles)
− Multiply-accumulate (non-saturating): 16bit × 16bit + 32bit (operation time 4 cycles)
− Multiply-accumulate (saturating): 16bit × 16bit + 32bit (operation time 4 cycles)
− Signed-operation and unsigned-operation are available
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FEDL62Q1300-02
• Operating voltage and temperature
‒ Operating voltage: VDD = 1.6 V to 5.5 V (Need 1.8V or higher at the power on)
‒ Operating temperature: -40°C to +105 °C
• Internal memory
‒ Program Flash memory area
Rewrite count: 100 cycles
Rewrite unit: 32bit(4byte)
Erase unit: 16Kbyte/1Kbyte
Erase/Rewrite temperature: 0°C to +40°C
‒ Data Flash memory area
Rewrite count 10,000 cycles
Rewrite unit: 8bit(1byte)
Erase unit: All area/128byte
Erase/Rewrite temperature: -40°C to +85°C
Back Ground Operation(CPU can work while erasing and rewriting)
This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc.
SuperFlash® is a registered trademark of Silicon Storage Technology, Inc.
‒ Data RAM area
Rewrite unit: 8bit/16bit(1byte/2byte)
Parity check function (Parity error reset or interrupt is generatable)
• Clock
‒ Low-speed clock
Internal low-speed RC oscillation: Approx.32.768 kHz
‒ High-speed clock
PLL oscillation: 24MHz/16MHz is selectable by code option
‒ WDT(Watch Dog Timer) clock
Internal low-speed RC oscillation: Approx. 1kHz
The WDT independent clock or the divided clock of internal low-speed clock is selectable by the code option.
• Reset
‒ RESET_N pin reset
‒ Reset by power-on detection
‒ Reset by the 2nd watchdog timer (WDT) overflow
‒ Reset by WDT counter clear during the clear invalid period
‒ Reset by RAM parity error
‒ Reset by unused ROM access
‒ Reset by voltage level detection (VLS)
‒ The software reset by BRK instruction (reset CPU only)
‒ Reset to the peripheral circuits by Block Reset Control Registers (BRECON 0 to 3)
‒ One-time reset to the all peripheral circuits by Software Reset Control Register (SOFTRCON)
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FEDL62Q1300-02
• Power management
‒ HALT mode: CPU stops executing instruction, clock oscillations and peripheral circuits remain previous states
‒ HALT-H mode: CPU stops executing instruction, high-speed clock oscillation stops and peripheral circuits working with
low-speed clock remain previous states
‒ STOP mode: CPU stops executing instruction, both high-speed oscillation and low-speed oscillation stop.
‒ STOP-D mode: CPU stops executing instruction, both high-speed oscillation and low-speed oscillation stop. The internal
regulator’s output voltage (VDDL) goes down to reduce the current consumption.
‒ Clock gear: The frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, 1/8, 1/16 or 1/32 of the
oscillation clock)
‒ Block Control Function: Powers down the circuits of unused function blocks (reset the block or stop supplying the clock)
• Interrupt controller
− Non-maskable interrupt source: 1 (Internal sources: WDT)
− Maskable interrupt sources: max.32
− Four step interrupt levels
− External interrupt ports : max. 8
• Watchdog timer(WDT)
‒ Operating clock is selectable (1kHz WDT independent clock or divided clock of internal 32.768kHz RC oscillation)
‒ Overflow period: 8 types selectable (7.8ms, 15.6ms, 31.3ms, 62.5ms, 125ms, 500ms, 2000ms and 8000ms @32.768kHz)
‒ Enabling or disabling the window function is selectable (The clear enable period is 50% or 75% of overflow period)
‒ WDT operation is selectable by code option (Enable or Disable)
‒ Readable WDT counter (WDT counter monitor function)
‒ The first overflow generates the WDT interrupt, and the second overflow generates the WDT reset when the counter clear
enable period is 100% of overflow period.
‒ The first overflow generates the WDT reset when the counter clear enable period is 50% or 75% of overflow period.
‒ The invalid clear reset generated when the WDT counter is cleared out of the WDT counter clear enable period.
• DMA(Direct Memory Access) controller
− Channel : 2ch
− Transfer unit: 8bit/16bit
− Max. transfer count: 1024 time
− Transfer type: 2 cycle transfer
− Transfer mode: Single transfer mode
Fixed address, address increments and address decrements
− Transfer target: SFR/RAM SFR/RAM (Transfer from/to Flash is not supported)
− Transfer request: Serial communication units, A/D, 16-bit timers, Functional timers and External interrupts.
• Low-speed Time base counter
− Divide the Low-speed clock(LSCLK) and generate 128Hz to 1Hz internal pulse signals
− Periodical interrupt × 3 selectable from 8 frequencies (128Hz, 64Hz, 32Hz, 16Hz, 8Hz, 4Hz, 2Hz and 1Hz)
− The time base clock output (1Hz or 2Hz) from general purpose ports (TBCOUT1).
• Functional timer(FTM)
− Channel: 4ch
− Timer one shot mode and repeat mode, Capture mode, PWM mode1 and PWM mode 2(complementary output)
− Same start/stop is available with different channels
(This function is not available with 16-bit timers)
− Event trigger (external interrupts, analog comparators, 16-bit timers and Functional timers)
− Dead time is generatable.
− Available to specify division ratio of counter clock channel by channel
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FEDL62Q1300-02
• 16-bit timers
− Channel: Max. 6ch
‒ 8-bits timer mode and 16-bit timer mode (1ch 16-bit timer is configurable as 2ch 8-bit timer)
− Same start/stop is available with different channels
(This function is not available with Functional Timer)
‒ Timer output (toggled by overflow)
− Available to specify division ratio of counter clock channel by channel
• Serial communication unit
− Channel: 2ch
− Synchronous Serial Port or UART is selectable in each channel
< Synchronous Serial Port >
‒ Master/slave selectable
‒ LSB first/MSB first selectable
‒ 8-bit length/16-bit length selectable
< UART >
‒ Full-duplex communication x 1ch(One Full-duplexUART is configurable as two half-duplex UARTs)
‒ 5-8 bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits
‒ Positive logic/negative logic selectable
‒ LSB first/MSB first selectable
‒ Wide range of communication speed
32.768kHz clock: 1bps to 4,800bps
24MHz clock: 600bps to 3Mbps
16MHz clock: 300bps to 2Mbps
‒ Internal baud rate generator
• I2C bus interface unit (Master/Slave)
‒ Channel: 1ch
‒ Master or Slave mode is selectable
< Master function >
‒ Standard mode (100 kbit/s), fast mode (400 kbit/s) and 1Mbps mode(1Mbit/s)
‒ Handshake (Clock synchronization)
‒ 7bit address format (10bit address format is supported)
< Slave function >
‒ Standard mode (100 kbit/s), fast mode (400 kbit/s) and 1Mbps mode(1Mbit/s)
‒ Clock stretch function
‒ 7bit address format
• I2C bus interface (Master only)
‒ Channel: 1ch
‒ Standard mode (100 kbit/s), fast mode (400 kbit/s) and 1Mbps mode(1Mbit/s)
‒ Handshake (Clock synchronization)
‒ 7bit address format (10bit address format is supported)
• General-purpose ports (GPIO)
‒ I/O port: Max. 28 (Including one pin for on-chip debug and pins for other shared functions)
‒ External interrupt function × 8
‒ LED driver port : Max. 27
‒ Carrier frequency output function (used for IR communication)
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FEDL62Q1300-02
• Successive approximation type A/D converter
‒ Channel: Max.8ch
‒ Resolution: 10bit
‒ Conversion time: Selectable 2.25μs (min) /channel (When the conversion clock is 8MHz)
‒ VDD pin input voltage / Internal reference voltage(Approx. 1.55V) / External reference voltage (VREF pin) are selectable
‒ Scan function (repeat conversion)
‒ One result register for each channel
‒ Interrupt by threshold of conversion result
‒ Temperature sensor for low-speed RC oscillation adjustment
• Voltage level supervisor (VLS)
‒ Accuracy: ±4%
‒ Threshold voltage: 12 values selectable (1.85V ~ 4.00V)
‒ Voltage level detection reset (VLS reset)
‒ Voltage level detection interrupt (VLS0 interrupt)
• Analog comparator
‒ Channel: 1ch
‒ Interrupts allow edge selection and sampling selection
‒ An external or an internal reference voltage(0.8V) is selectable
• D/A converter
‒ Channel: Max 1ch
‒ Resolution: 8bit
‒ Output impedance: 6k ohm(Typ.)
‒ R-2R ladder method
• Buzzer
‒ 4 buzzer mode (Repeat sound, Single sound, Intermittent sound 1 and Intermittent sound 2)
‒ 8frequencies (4.096kHz to 293Hz)
‒ 15 step duty (1/16 to 15/16)
‒ Selectable the logic of buzzer output pin (Positive or Negative logic)
• CRC(Cyclic Redundancy Check) operation function
‒ Generation equation: X16+X12+X5+1
‒ LSB first or MSB first is selectable
‒ Automatic CRC mode: Automatic CRC calculation with data of program memory in HALT mode
• Safety Function(IEC60730/60335 Class B)
‒ RAM/SFR guard
‒ Automatic CRC calculation with data of program memory
‒ RAM parity error detection
‒ ROM unused area access reset
‒ Clock mutual check
‒ WDT counter check
‒ Successive approximation type A/D converter test
‒ UART test
‒ Synchronous serial test
‒ I2C test
‒ GPIO test
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FEDL62Q1300-02
• Shipping package
−
−
−
−
−
−
16-pin plastic SSOP
ML62Q1323/1324/1325 - xxxMB (Blank part: ML62Q1323/1324/1325-NNNMB)
16-pin plastic WQFN
ML62Q1323/1324/1325 - xxxGD (Blank part: ML62Q1323/1324/1325-NNNGD)
20-pin plastic TSSOP
ML62Q1333/1334/1335 - xxxTD (Blank part: ML62Q1333/1334/1335-NNNTD)
24-pin plastic WQFN
ML62Q1345/1346/1347 - xxxGD (Blank part: ML62Q1345/1346/1347-NNNGD)
32-pin plastic TQFP
ML62Q1365/1366/1367 - xxxTB (Blank part: ML62Q1365/1366/1367-NNNTB)
32-pin plastic WQFN
ML62Q1365/1366/1367 - xxxGD (Blank part: ML62Q1365/1366/1367-NNNGD)
xxx: ROM code number
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FEDL62Q1300-02
ML62Q1300 Group how to read the part number
ML 62 Q 13 6 7 – xxx TB
Package Type
GD
:WQFN
MB
:SSOP
TB
:TQFP
TD
:TSSOP
ROM Code Number
NNN :Blank
xxx
:Custom Code Number
Program Memory Size
3
:16Kbyte
4
:24Kbyte
5
:32Kbyte
6
:48Kbyte
7
:64Kbyte
Pin Count
2
:16pin
3
:20pin
4
:24pin
6
:32pin
Group Name
13
:1300 Group
Program Memory Type
Q
:Flash Memory
CPU Type
62
:16bit CPU nX-U16/100
LAPIS Semiconductor Logic Product
Figure 1 ML62Q1300 Group Part Number
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FEDL62Q1300-02
ML62Q1300 Group Main Function List
Table 2 ML62Q1300 Group Main Function List
Pin
Interrupt
Serial
Analog
8bit D/A converter [channel]
Analog comparator [input pin]
Analog comparator [channel]
10bit Successive type A/D converter [channel]
I2C bus interface (Master only) [channel]
I2C bus unit (Master/Slave) [channel]
2
Full-duplex UART or Synchronous serial [channel] *
Simplified RTC [channel]
1
16-bit Timer [channel] *
Functional Timer [channel]
External interrupt [port]
LED drive port
11
Internal interrupt [source]
I/O port
Reset Input pin
Power pin counts
Total pin-counts
12
Part number
Timer
ML62Q1323
ML62Q1324
ML62Q1325
ML62Q1333
ML62Q1334
ML62Q1335
ML62Q1345
ML62Q1346
ML62Q1347
ML62Q1365
ML62Q1366
ML62Q1367
16
6
23
20
16
3
24
1
8
20
28
0
15
4
0
19
2
1
1
1
2
8
25
32
4
6
1
27
*1 : One 16-bit timer is configurable as two 8-bit timers.
*2 : Full-duplex UART and Synchronous Serial Port can not be used simultaneously in the same channel.
One Full-duplexUART is configurable as two half-duplex UARTs.
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FEDL62Q1300-02
BLOCK DIAGRAM
CPU (nX-U16/100)
EPSW1~3
GREG
0 ～15
PSW
ALU
Timing
Controller
Instruction
Decoder
LR
DSR/CSR
EA
PC
Multiplier/Divider
(Coprocessor)
Instruction
Register
Data Bus
INT
Power
Circuit
Serial
Commun
ication
Unit
RAM
RESET_N
TEST0*
Reset/
TEST
INT
Interrupt
OUTLSCLK*
OUTHSCLK*
Clock
Generation
Circuit
2
Watch
Dog
Timer
I C Bus
Unit
2
VLS
DMAC
CMP0P*
CMP0M*
IC
Master
I2CM0_SDA*
I2CM0_SCL*
16-bit
Timer
TMH0~5OUT*
INT
INT
RC
Oscillation
(For WDT)
INT
EXTRIG0~7*
Functional
Timer
CRC
FTM0~3P
FTM0~3N
INT
INT
FLASH
Controller
Time-base
Counter
A/D
Converter
Buzzer
INT
Analog
Comparator
I2CU0_SDA*
I2CU0_SCL*
INT
INT
Low-speed
RC
Oscillation
SU0~1_SCK*
SU0~1_SIN*
SU0~1_SOUT*
SU0~1_RXD0*
SU0~1_TXD0*
SU0~1_RXD1*
SU0~1_TXD1*
INT
INT
PLL
Oscillation
VDD
VSS
VREF
AIN0 toAIN5/7*
Program memory
(Flash)
BUS
Controller
Data Flash
VDD
VSS
VREFO*
ECSR1
SP
On-Chip
ICE
VDDL
ELR1～3
INT
Safety
Function
INT
TBCOUT1*
BZ0P*
BZ0N*
PX0～PX7
(X= 0～3)
GPIO
DACOUT0*
D/A
Converter
EXI0~7
Reset
Function
* : indicates the shared function of general ports.
Figure 2 ML62Q1300 Group Block Diagram
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FEDL62Q1300-02
PIN CONFIGURATION
Pin Layout of ML62Q1323/1324/1325 16pin SSOP Package
VDD
1
16
P27/EXI7/EXTRG7/SU1_TXD1/I2CU0_SCL/
FTM3N/TBCOUT1/BZ0N/AIN7
VSS
2
15
P26/EXI6/EXTRG6/SU1_RXD1/SU1_RXD0/
I2CU0_SDA/FTM3P/BZ0P/AIN6
VDDL
3
14
P23/EXI5/EXTRG5/SU1_SCLK/I2CM0_SCL/
TMH2OUT/VREF
13
P22/SU1_TXD0/SU1_SOUT/SU1_TXD1/
I2CM0_SDA/FTM2N/OUTHSCLK/AIN3
12
P21/EXI4/EXTRG4/SU1_RXD0/SU1_SIN/
FTM2P/OUTLSCLK/AIN2
6
11
P20/SU0_TXD1/FTM1N/TBCOUT1/BZ0N/AIN1
7
10
P17/EXI3/EXTRG3/SU0_RXD1/SU0_RXD0/
FTM1P/BZ0P/AIN0
8
9
P13/SU0_TXD0/SU0_SOUT/SU0_TXD1/
TMH1OUT/TMH3OUT
RESET_N
4
P00/TEST0
5
P02/EXI0/EXTRG0/SU0_RXD0/SU0_SIN/
FTM0P/OUTLSCLK/CMP0M
P03/EXI1/EXTRG1/SU0_TXD0/SU0_SOUT/SU0_TXD1
/I2CU0_SDA/FTM0N/OUTHSCLK/CMP0P
P04/EXI2/EXTRG2/SU0_SCLK/I2CU0_SCL/
TMH0OUT
(TOP VIEW)
SSOP16
Figure 3 Pin Layout of 16pin SSOP Package
10/59
FEDL62Q1300-02
P23/EXI5/EXTRG5/SU1_SCLK/I2CM0_SCL/
TMH2OUT/VREF
P22/SU1_TXD0/SU1_SOUT/SU1_TXD1/
I2CM0_SDA/FTM2N/OUTHSCLK/AIN3
P21/EXI4/EXTRG4/SU1_RXD0/SU1_SIN/
FTM2P/OUTLSCLK/AIN2
P20/SU0_TXD1/FTM1N/TBCOUT1/BZ0N/AIN1
P17/EXI3/EXTRG3/SU0_RXD1/SU0_RXD0/
FTM1P/BZ0P/AIN0
Pin Layout of ML62Q1323/1324/1325 16pin WQFN Package
12
11
10
9
13
P26/EXI6/EXTRG6/SU1_RXD1/SU1_RXD0/ 14
I2CU0_SDA/FTM3P/BZ0P/AIN6
(TOP VIEW)
WQFN16
P27/EXI7/EXTRG7/SU1_TXD1/I2CU0_SCL/ 15
FTM3N/TBCOUT1/BZ0N/AIN7
1
2
3
4
VDDL
RESET_N
P00/TEST0
16
VSS
VDD
8
P13/SU0_TXD0/SU0_SOUT/SU0_TXD1/
TMH1OUT/TMH3OUT
7
P04/EXI2/EXTRG2/SU0_SCLK/I2CU0_SCL/
TMH0OUT
6
P03/EXI1/EXTRG1/SU0_TXD0/SU0_SOUT/SU0_TXD1/
I2CU0_SDA/FTM0N/OUTHSCLK/CMP0P
5
P02/EXI0/EXTRG0/SU0_RXD0/SU0_SIN/
FTM0P/OUTLSCLK/CMP0M
Figure 4 Pin Layout of 16pin WQFN Package
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FEDL62Q1300-02
Pin Layout of ML62Q1333/1334/1335 20pin TSSOP Package
RESET_N
1
20
VDDL
P00/TEST0
2
19
VSS
3
18
VDD
4
17
P33/SU1_TXD1/TMH3OUT
16
P27/EXI7/EXTRG7/SU1_TXD1/I2CU0_SCL/
FTM3N/TBCOUT1/BZ0N/AIN7
15
P26/EXI6/EXTRG6/SU1_RXD1/SU1_RXD0/
I2CU0_SDA/FTM3P/BZ0P/AIN6
7
14
P25/SU1_TXD0/SU1_SOUT/SU1_TXD1/AIN
P17/EXI3/EXTRG3/SU0_RXD1/SU0_RXD0/
FTM1P/BZ0P/AIN0
8
13
P24/SU1_RXD0/SU1_SIN/AIN4
P20/SU0_TXD1/FTM1N/TBCOUT1/BZ0N/AIN1
9
12
P23/EXI5/EXTRG5/SU1_SCLK/I2CM0_SCL/
TMH2OUT/VREF
P21/EXI4/EXTRG4/SU1_RXD0/SU1_SIN/
FTM2P/OUTLSCLK/AIN2
10
11
P22/SU1_TXD0/SU1_SOUT/SU1_TXD1/
I2CM0_SDA/FTM2N/OUTHSCLK/AIN3
P02/EXI0/EXTRG0/SU0_RXD0/SU0_SIN/
FTM0P/OUTLSCLK/CMP0M
P03/EXI1/EXTRG1/SU0_TXD0/SU0_SOUT/SU0_TXD1/
I2CU0_SDA/FTM0N/OUTHSCLK/CMP0P
P04/EXI2/EXTRG2/SU0_SCLK/I2CU0_SCL/
TMH0OUT
5
6
P05
P13/SU0_TXD0/SU0_SOUT/SU0_TXD1/
TMH1OUT/TMH3OUT
(TOP VIEW)
TSSOP20
Figure 5 Pin Layout of 20pin TSSOP Package
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FEDL62Q1300-02
P23/EXI5/EXTRG5/SU1_SCLK/I2CM0_SCL/
TMH2OUT/VREF
P22/SU1_TXD0/SU1_SOUT/SU1_TXD1/
I2CM0_SDA/FTM2N/OUTHSCLK/AIN3
P21/EXI4/EXTRG4/SU1_RXD0/SU1_SIN/
FTM2P/OUTLSCLK/AIN2
P20/SU0_TXD1/FTM1N/TBCOUT1/BZ0N/AIN1
P17/EXI3/EXTRG3/SU0_RXD1/SU0_RXD0/
FTM1P/BZ0P/AIN0
P16/SU1_SCLK/I2CU0_SCL/TMH5OUT
Pin Layout of ML62Q1345/1346/1347 24pin WQFN Package
18
17
16
15
14
13
P24/SU1_RXD0/SU1_SIN/AIN4 19
12
P13/SU0_TXD0/SU0_SOUT/SU0_TXD1/
TMH1OUT/TMH3OUT
20
11
P12/SU0_RXD0/SU0_SIN/TMH4OUT
10
P05
9
P04/EXI2/EXTRG2/SU0_SCLK/I2CU0_SCL/
TMH0OUT
P25/SU1_TXD0/SU1_SOUT/SU1_TXD1/AIN
P26/EXI6/EXTRG6/SU1_RXD1/SU1_RXD0
21
I2CU0_SDA/FTM3P/BZ0P/AIN6/
(TOP VIEW)
WQFN24
P27/EXI7/EXTRG7/SU1_TXD1/I2CU0_SCL/ 22
FTM3N/TBCOUT1/BZ0N/AIN7
7
P02/EXI0/EXTRG0/SU0_RXD0/SU0_SIN/
FTM0P/OUTLSCLK/CMP0M
1
2
3
4
5
6
P01/DACOUT0
24
P00/TEST0
P33/SU1_TXD1/TMH3OUT
RESET_N
P03/EXI1/EXTRG1/SU0_TXD0/SU0_SOUT/SU0_TXD1/
I2CU0_SDA/FTM0N/OUTHSCLK/CMP0P
VDDL
8
VSS
23
VDD
P32/SU1_RXD1/SU1_RXD
Figure 6 Pin Layout of 24pin WQFN Package
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FEDL62Q1300-02
21
P14
P20/SU0_TXD1/FTM1N/TBCOUT1/BZ0N/AIN1
22
P15/I2CU0_SDA
P21/EXI4/EXTRG4/SU1_RXD0/SU1_SIN/
FTM2P/OUTLSCLK/AIN2
23
P16/SU1_SCLK/I2CU0_SCL/TMH5OUT
P22/SU1_TXD0/SU1_SOUT/SU1_TXD1/
I2CM0_SDA/FTM2N/OUTHSCLK/AIN3
24
P17/EXI3/EXTRG3/SU0_RXD1/SU0_RXD0/
FTM1P/BZ0P/AIN0
P23/EXI5/EXTRG5/SU1_SCLK/I2CM0_SCL/
TMH2OUT/VREF
Pin Layout of ML62Q1365/1366/1367 32pin TQFP Package
20
1
18
17
25
16
P13/SU0_TXD0/SU0_SOUT/SU0_TXD1/
TMH1OUT/TMH3OUT
P25/SU1_TXD0/SU1_SOUT/SU1_TXD1/AIN5
26
15
P12/SU0_RXD0/SU0_SIN/TMH4OUT
P26/EXI6/EXTRG6/SU1_RXD1/SU1_RXD0/
I2CU0_SDA/FTM3P/BZ0P/AIN6
27
14
P11/SU0_SCLK
13
P10/SU0_TXD1
12
P07/SU0_RXD1/SU0_RXD0/I2CM0_SCL
P24/SU1_RXD0/SU1_SIN/AIN4
P27/EXI7/EXTRG7/SU1_TXD1/I2CU0_SCL/
FTM3N/TBCOUT1/BZ0N/AIN7
28
(TOP VIEW)
TQFP32
31
10
P05
P33/SU1_TXD1/TMH3OUT
32
9
P04/EXI2/EXTRG2/SU0_SCLK/I2CU0_SCL/
TMH0OUT
2
3
4
5
6
7
8
P03/EXI1/EXTRG1/SU0_TXD0/SU0_SOUT/SU0_TXD1/
I2CU0 SDA/FTM0N/OUTHSCLK/CMP0P
1
P02/EXI0/EXTRG0/SU0_RXD0/SU0_SIN/
FTM0P/OUTLSCLK/CMP0M
P32/SU1_RXD1/SU1_RXD0
P01/DACOUT0
P06/I2CM0_SD
P00/TEST0
11
RESET_N
30
VDDL
P31
VSS
29
VDD
P30
Figure 7 Pin Layout of 32pin TQFP Package
14/59
FEDL62Q1300-02
P21/EXI4/EXTRG4/SU1_RXD0/SU1_SIN/
FTM2P/OUTLSCLK/AIN2
P20/SU0_TXD1/FTM1N/TBCOUT1/BZ0N/AIN1
P17/EXI3/EXTRG3/SU0_RXD1/SU0_RXD0/
FTM1P/BZ0P/AIN0
P16/SU1_SCLK/I2CU0_SCL/TMH5OUT
P15/I2CU0_SDA
P14
24
P22/SU1_TXD0/SU1_SOUT/SU1_TXD1/
I2CM0_SDA/FTM2N/OUTHSCLK/AIN3
P23/EXI5/EXTRG5/SU1_SCLK/I2CM0_SCL/
TMH2OUT/VREF
Pin Layout of ML62Q1365/1366/1367 32pin WQFN Package
23
22
21
20
19
18
17
16 P13/SU0_TXD0/SU0_SOUT/SU0_TXD1/
TMH1OUT/TMH3OUT
P24/SU1_RXD0/SU1_SIN/AIN4 25
P25/SU1_TXD0/SU1_SOUT/SU1_TXD1/AIN5
15 P12/SU0_RXD0/SU0_SIN/TMH4OUT
26
P26/EXI6/EXTRG6/SU1_RXD1/SU1_RXD0/ 27
I2CU0_SDA/FTM3P/BZ0P/AIN6
14 P11/SU0_SCLK
(TOP VIEW)
WQFN32
P27/EXI7/EXTRG7/SU1_TXD1/I2CU0_SCL/ 28
FTM3N/TBCOUT1/BZ0N/AIN7
P30
29
13 P10/SU0_TXD1
12 P07/SU0_RXD1/SU0_RXD0/I2CM0_SCL
11 P06/I2CM0_SD
P31 30
P32/SU1_RXD1/SU1_RXD0
10 P05
31
9 P04/EXI2/EXTRG2/SU0_SCLK/I2CU0_SCL/
TMH0OUT
2
3
4
5
6
7
VSS
VDDL
RESET_N
P00/TEST0
P01/DACOUT0
P02/EXI0/EXTRG0/SU0_RXD0/SU0_SIN/
FTM0P/OUTLSCLK/CMP0M
8
P03/EXI1/EXTRG1/SU0_TXD0/SU0_SOUT/SU0_TXD1/
I2CU0_SDA/FTM0N/OUTHSCLK/CMP0P
1
VDD
P33/SU1_TXD1/TMH3OUT 32
Figure 8 Pin Layout of 32pin WQFN Package
15/59
FEDL62Q1300-02
PIN LIST
Table 3 Pin List
Pin No.
16Pin No.(SSOP)
16Pin No.(WQFN)
（ TSSOP
）
20Pin No.
24Pin No.(WQFN)
32Pin No.(TQFP)
(WQFN)
1
16
18
1
1
VDD
-
-
-
-
-
-
-
-
2
3
1
2
19
20
2
3
2
3
VSS
VDDL
-
-
-
-
-
-
-
-
4
3
1
4
4
5
4
2
-
-
-
5
6
5
6
P00
P01
6
5
3
7
7
P02
7
6
4
8
8
P03
8
7
5
9
9
P04
-
-
6
10
-
-
10
11
12
P05
P06
P07
Pin
name
(Primary
function)
RESET_N
nd
rd
th
Primary
function
Others
2
function
Communic
ations
3
function
Communi
cations
4
function
Communic
ations
5
function
Timers
6
function
Others
7
function
Others
8
function
ADC
TEST0
DACOUT0
EXI0
EXTRG0
EXI1
EXTRG1
EXI2
EXTRG2
-
th
th
th
th
-
-
-
-
-
-
-
SU0_RXD0
SU0_SIN
SU0_TXD0
SU0_SOUT
-
-
-
-
-
-
-
-
FTM0P
OUTLSCLK
CMP0M
-
SU0_TXD1
I2CU0_SDA
FTM0N
OUTHSCLK
CMP0P
-
SU0_SCLK
-
I2CU0_SCL
TMH0OUT
-
-
-
SU0_RXD1
SU0_RXD0
I2CM0_SDA
I2CM0_SCL
-
-
-
-
-
-
-
-
13
P10
-
SU0_TXD1
-
-
-
-
-
-
-
-
-
-
14
P11
-
SU0_SCLK
-
-
-
-
-
-
-
-
-
11
15
P12
-
-
-
TMH4OUT
-
-
-
9
8
7
12
16
P13
-
SU0_TXD1
-
TMH1OUT
-
TMH3OUT
-
-
-
-
13
17
18
19
P14
P15
P16
-
I2CU0_SDA
I2CU0_SCL
TMH5OUT
-
-
-
10
9
8
14
20
P17
EXI3
EXTRG3
SU0_RXD0
SU0_SIN
SU0_TXD0
SU0_SOUT
SU1_SCLK
SU0_RXD1
SU0_RXD0
-
FTM1P
-
BZ0P
AIN0
11
10
9
15
21
P20
SU0_TXD1
SU1_RXD0S
U1_SIN
SU1_TXD0
SU1_SOUT
-
-
FTM1N
TBCOUT1
BZ0N
AIN1
-
-
FTM2P
OUTLSCLK
-
AIN2
SU1_TXD1
I2CM0_SDA
FTM2N
OUTHSCLK
-
AIN3
SU1_SCLK
-
I2CM0_SCL
TMH2OUT
-
-
VREFO
SU1_RXD0
SU1_SIN
SU1_TXD0
SU1_SOUT
-
-
-
-
-
AIN4
SU1_TXD1
-
-
-
-
AIN5
SU1_RXD1
SU1_RXD0
I2CU0_SDA
FTM3P
-
BZ0P
AIN6
SU1_TXD1
-
I2CU0_SCL
FTM3N
BZ0N
AIN7
SU1_RXD1
SU1_RXD0
-
-
-
-
-
SU1_TXD1
-
-
-
-
-
EXI4
EXTRG4
12
11
10
16
22
P21
13
12
11
17
23
P22
-
14
13
12
18
24
P23
EXI5
EXTRG5
VREF
-
-
13
19
25
P24
-
-
-
14
20
26
P25
-
15
14
15
21
27
P26
16
15
16
22
28
P27
-
-
-
23
29
30
31
P30
P31
P32
EXI6
EXTRG6
EXI7
EXTRG7
-
-
-
17
24
32
P33
-
TMH3OUT
TBCOUT1
16/59
FEDL62Q1300-02
PIN DESCRIPTION
Table 4 Pin Description (1/4)
Function
Signal name
－
Pin name
VSS
I/O
－
－
VDD
－
－
VDDL
－
Power
Test
TEST0
P00
I/O
VREFO
P23
－
RESET_N
RESET_N
I
System
OUTLSCLK
OUTHSCLK
General port
(GPIO)
P02
P21
P03
P22
P00
P00
P01 – P07
P01 – P07
P10 – P17
P10 – P17
P20 – P27
P20 – P27
P30 – P33
P30 – P33
Description
Negative power supply pin (-)
Positive power supply pin (+).Connect a capacitor CV
between this pin and VSS to stabilize power supply.
Power supply pin for internal logic (internal
regulator’s output). Connect a capacitor CL(1μF)
between this pin and VSS.
Input pin for testing. Also, used for on-chip debug
interface or ISP function. P00 is initialized as pull-up
input mode by the system reset (not high-impedance
mode).
Logic
－
－
－
－
Reference voltage output.
An internal reference voltage in the SA type A/D
－
converter block can be externally used for a reference.
The pin is shared with the SA type A/D converter
external reference voltage input.
Input for reset. Asserting “L” level to this pin enters
the MCU into system reset mode and internal circuits
are initialized, then releasing it to “H” level make CPU
Negative
start running the program. Used for on-chip debug
interface or ISP function. Internal pull-up resistor is
not installed.
O
Low-speed clock output.
－
O
High-speed clock output.
－
I/O
General I/O port
- High-impedance
- Input with Pull-UP (initial value)
- Input without Pull-UP
- CMOS output
Positive
- N-channel open drain output
P00 is only initialized as pulled-up input and other
ports are initialized as high-impedance
Not available to use as I/O pin when using for on-chip
debug interface or ISP function.
I/O
General I/O port
- High-impedance (initial value)
- Input with Pull-UP
- Input without Pull-UP
- CMOS output
- N-channel open drain output
Positive
17/59
FEDL62Q1300-02
Table 4 Pin Description (2/4)
Function
Signal name
SU0_TXD0
SU0_RXD0
SU0_TXD1
UART
SU0_RXD1
SU1_TXD0
SU1_RXD0
SU1_TXD1
SU1_RXD1
SU0_SIN
SU0_SCK
Synchronous
Serial Port
SU0_SOUT
SU1_SIN
SU1_SCK
SU1_SOUT
I2CU0_SDA
2
I C Bus
I2CU0_SCL
I2CM0_SDA
I2CM0_SCL
Pin name
P03
P13
P02
P07
P12
P17
P03
P10
P13
P20
P07
P17
P22
P25
P21
P24
P26
P32
P22
P25
P27
P33
P26
P32
P02
P12
P04
P11
P03
P13
P21
P24
P16
P23
P22
P25
P03
P15
P26
P04
P16
P27
P06
P22
P07
P23
I/O
Description
Logic
O
Serial communication unit0/UART0 data output pin.
Positive
I
Serial communication unit0/UART0 data input pin.
Positive
O
Serial communication unit0/UART1 data output pin.
Positive
I
Serial communication unit0/UART1 data input pin.
Positive
O
Serial communication unit1/UART0 data output pin
Positive
I
Serial communication unit1/UART0 data input pin.
Positive
O
Serial communication unit1/UART1 data output pin.
Positive
I
Serial communication unit1/UART1 data input pin.
Positive
I
Serial communication unit0/Synchronous serial data
input pin.
Positive
I/O
Serial communication unit0/Synchronous serial clock
I/O pin.
Positive
O
Serial communication unit0/Synchronous serial data
output pin.
Positive
I
Serial communication unit1/Synchronous serial data
input pin.
Positive
I/O
Serial communication unit1/Synchronous serial clock
I/O pin.
Positive
O
Serial communication unit1/Synchronous serial data
output pin.
Positive
I/O
I C Unit0 (Master and Salve) Data I/O pin / N-ch open
drain. Connect a pull-up resistor externally.
I/O
I C Unit0 (Master and Salve) Clock I/O pin / N-ch
open drain. Connect a pull-up resistor externally.
I/O
I C Master0 Data I/O pin / N-ch open drain. Connect
a pull-up resistor externally.
2
Positive
2
Positive
2
Positive
2
I/O
I C Master0 Clock I/O pin / N-ch open drain. Connect
a pull-up resistor externally.
Positive
18/59
FEDL62Q1300-02
Table 4 Pin Description (3/4)
Function
Functional Timer
(FTM)
16bit General
Timer
Low-Speed
Time Base
Counter (LTBC)
Signal name
Pin name
I/O
Description
FTM0P
FTM0N
FTM1P
FTM1N
FTM2P
FTM2N
FTM3P
FTM3N
EXTRG0
EXTRG1
EXTRG2
EXTRG3
EXTRG4
EXTRG5
EXTRG6
EXTRG7
TMH0OUT
TMH1OUT
TMH2OUT
P02
P03
P17
P20
P21
P22
P26
P27
P02
P03
P04
P17
P21
P23
P26
P27
P04
P13
P23
P13
P33
P12
P16
P02
P03
P20
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
O
O
O
Functional Timer0 output.
Functional Timer0 output.
Functional Timer1 output.
Functional Timer1 output.
Functional Timer2 output.
Functional Timer2 output.
Functional Timer3 output.
Functional Timer3 output.
Functional Timer event trigger input pin.
Functional Timer event trigger input pin.
Functional Timer event trigger input pin.
Functional Timer event trigger input pin.
Functional Timer event trigger input pin.
Functional Timer event trigger input pin.
Functional Timer event trigger input pin.
Functional Timer event trigger input pin.
16bit General Timer 0 output pin
16bit General Timer 1 output pin
16bit General Timer 2 output pin
O
16bit General Timer 3 output pin
O
O
I
I
16bit General Timer 4 output pin
16bit General Timer 5 output pin
16bit General Timer trigger input pin
16bit General Timer trigger input pin
Positive
Positive
—
—
O
Low-speed Time Base Counter 1Hz/2Hz output pin
Positive
O
Buzzer output (positive phase)
Positive
O
Buzzer output (negative phase)
Negative
TMH3OUT
TMH4OUT
TMH5OUT
EXTRG0
EXTRG1
TBCOUT1
BZ0P
Buzzer
BZ0N
P27
P17
P26
P20
P27
Logic
Positive
Negative
Positive
Negative
Positive
Negative
Positive
Negative
—
—
—
—
—
—
—
—
Positive
Positive
Positive
Positive
19/59
FEDL62Q1300-02
Table 4 Pin Description (4/4)
Function
External Interrupt
Successive
approximation
type A/D
converter
Analog
comparator
D/A converter
Signal name
Pin name
I/O
EXI0
EXI1
EXI2
EXI3
EXI4
EXI5
EXI6
EXI7
P02
P03
P04
P17
P21
P23
P26
P27
I
I
I
I
I
I
I
I
VREF
P23
—
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
CMP0P
CMP0M
DACOUT0
P17
P20
P21
P22
P24
P25
P26
P27
P03
P02
P01
I
I
I
I
I
I
I
I
I
I
O
Description
External interrupt 0 input pin
External interrupt 1 input pin
External interrupt 2 input pin
External interrupt 3 input pin
External interrupt 4 input pin
External interrupt 5 input pin
External interrupt 6 input pin
External interrupt 7 input pin
SA type A/D converter external reference voltage
input. The voltage provided to the pin is used as the
reference voltage for the A/D conversion.
SA type A/D converter channel 0 input pin
SA type A/D converter channel 1 input pin
SA type A/D converter channel 2 input pin
SA type A/D converter channel 3 input pin
SA type A/D converter channel 4 input pin
SA type A/D converter channel 5 input pin
SA type A/D converter channel 6 input pin
SA type A/D converter channel 7 input pin
Comparator input 0 (noninverting input)
Comparator input 0 (inverting input)
D/A converter0 output pin
Logic
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
20/59
FEDL62Q1300-02
TERMINATION OF UNUSED PINS
Table 5 Termination of unused pins
Pin
Recommended pin termination
RESET_N
Connect to VDD through a resistor
Open the pin with the internal initial condition of pulled-up
input mode.
P00/TEST0
P01 to P07
P10 to P17
P20 to P27
P30 to P33
Open the pins with the internal initial condition of
Hi-impedance mode.
Note:
For unused input ports or unused input/output ports, if an unstable middle level voltage is supplied to the corresponding pins which
are configured as inputs without pull-up register or input/output mode, supply current may become excessively large. Therefore, it
is recommended to configure those pins as either input mode with a pull-up resistor or output mode.
21/59
FEDL62Q1300-02
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(VSS = 0V)
Parameter
Symbol
Condition
Rating
Unit
Power supply voltage 1
VDD
Ta = +25°C
-0.3 to +6.5
V
Power supply voltage 2
VDDL
Ta = +25°C
-0.3 to +2.0
VIN
Ta = +25°C
-0.3 to VDD+0.3*
Input voltage
Output voltage
VOUT
Ta = +25°C
“H” level output current
IOUTH
Ta = +25°C
“L” level output current
IOUTL
Ta = +25°C
1pin
Total
1pin
Total
V
1
V
1
V
-0.3 to VDD+0.3*
2
-40*
2
-150*
+40
+150
1
-55 to +150
mA
mA
Power dissipation
PD
Ta = +25°C
W
Storage temperature
TSTG
―
°C
1
* 6.5V or lower
2
* The current flowing out the LSI through the pin is described in the negative number.
The applicable maximum current is the absolute value.
For example, -1mA means the maximum current 1mA flows out the LSI through the pin.
[Note] Use the product within absolute maximum ratings. The absolute maximum ratings are conditions which may physically
deteriorate the quality of product.
Recommended Operating Conditions
(VSS = 0V)
Symbol
Condition
Range
Unit
Operating temperature
Parameter
TOP
―
-40 to +105
°C
Operating voltage 1
VDD
fOP
VDDL pin external capacitance
CL
1.6 to 5.5
30k to 4M
30k to 25M
1.0 ±30%
V
Operating frequency (CPU)
―
VDD = 1.6 to 5.5V
VDD = 1.8 to 5.5V
―
Hz
μF
22/59
FEDL62Q1300-02
Current Consumption 1
Product： ML62Q1323, ML62Q1324, ML62Q1325, ML62Q1333, ML62Q1334, ML62Q1335
o
Parameter
Symbol
Supply current 0
IDD0
Supply current 1
IDD1
Supply current 2
Supply current 3
IDD2
IDD3
(VDD=1.6 to 5.5V, VSS =0V, Ta=-40 to +105 C, unless otherwise specified)
Measuri
3
Condition
Min.
Typ. *
Max.
Unit
ng
circuit
Ta = -40 to
―
17
CPU is in STOP-D state.
o
+85 C
0.60
Low-speed RC1K/RC32K and
µA
Ta = -40 to
PLL oscillation are stopped.
―
36
o
+105 C
Ta = -40 to
―
20
CPU is in STOP state.
o
+85 C
Low-speed RC1K/RC32K and
µA
0.75
Ta = -40 to
PLL oscillation are stopped.
―
42
o
+105 C
Low-speed RC32K Oscillating.
CPU is in HALT state (LTBC
*1
and WDT are operating ). PLL
oscillation is stopped.
CPU: Running with 32kHz RC
1 2
oscillation clock* *
PLL oscillation is stopped.
Ta = -40 to
o
+85 C
―
Ta = -40 to
o
+105 C
―
Ta = -40 to
o
+105 C
―
27
µA
3.6
44
17
CPU: Running with 16MHz PLL
2
Ta = -40 to
oscillating clock*
Supply current 4
―
IDD4
3.1
o
+105 C
PLL 16MHz is oscillating.
VDD=1.8~5.5V
CPU: Running with 24MHz PLL
2
Ta = -40 to
oscillating clock*
Supply current 5
―
4.4
IDD5
o
+105 C
PLL 24MHz is oscillating.
VDD=1.8~5.5V
1
* LTBC and WDT is operating, Significant bits of BLKCON0-3 and BRECON0-3 registers are all “1”
2
* CPU running in wait mode
3
o
* On the condition of VDD=3.0V, Ta=+25 C
66
1
µA
3.8
mA
5.3
23/59
FEDL62Q1300-02
Current Consumption 2
Product： ML62Q1345, ML62Q1346, ML62Q1347, ML62Q1365, ML62Q1366, ML62Q1367
o
Parameter
Symbol
Supply current 0
IDD0
Supply current 1
IDD1
Supply current 2
Supply current 3
IDD2
IDD3
(VDD=1.6 to 5.5V, VSS =0V, Ta=-40 to +105 C, unless otherwise specified)
Measuri
3
Condition
Min.
Typ. *
Max.
Unit
ng
circuit
Ta = -40 to
―
18
CPU is in STOP-D state.
o
+85 C
0.80
Low-speed RC1K/RC32K and
µA
Ta = -40 to
PLL oscillation are stopped.
―
40
o
+105 C
Ta = -40 to
―
21
CPU is in STOP state.
o
+85 C
Low-speed RC1K/RC32K and
µA
0.95
Ta = -40 to
PLL oscillation are stopped.
―
45
o
+105 C
Low-speed RC32K Oscillating.
CPU is in HALT state (LTBC
*1
and WDT are operating ). PLL
oscillation is stopped.
CPU: Running with 32kHz RC
1 2
oscillation clock* *
PLL oscillation is stopped.
Ta = -40 to
o
+85 C
―
Ta = -40 to
o
+105 C
―
Ta = -40 to
o
+105 C
―
33
µA
4.3
50
20
CPU: Running with 16MHz PLL
2
Ta = -40 to
oscillating clock*
Supply current 4
―
IDD4
4.3
o
+105 C
PLL 16MHz is oscillating.
VDD=1.8~5.5V
CPU: Running with 24MHz PLL
2
Ta = -40 to
oscillating clock*
Supply current 5
―
6.4
IDD5
o
+105 C
PLL 24MHz is oscillating.
VDD=1.8~5.5V
1
* LTBC and WDT is operating, Significant bits of BLKCON0-3 and BRECON0-3 registers are all “1”
2
* CPU running in wait mode
3
o
* On the condition of VDD=3.0V, Ta=+25 C
70
1
µA
4.8
mA
7.0
24/59
FEDL62Q1300-02
On-chip Oscillator
(VDD=1.6 to 5.5V, VSS =0V, Ta=−40 to +105οC, unless otherwise specified)
Measur
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
ing
circuit
Ta= +25°C
Typ
VDD = 1.8 to 5.5V
Typ
32.768
+1.0%
-1.0%
Without software
1
adjustment *
Ta= -40 to +85°C
Typ
VDD = 1.8 to 5.5V
Typ
32.768
+2.5%
-2.5%
Without software
Low-speed RC oscillator
1
adjustment *
fRCL1
frequency accuracy 1
Ta= -40 to +105°C
Typ
VDD = 1.8 to 5.5V
Typ
32.768
+3.0%
-3.0%
Without software
1
adjustment *
kHz
VDD = 1.6 to 1.8V
Typ
Typ
32.768
Without software
-3.5%
-3.5%
1
adjustment *
Ta= -40 to +85°C
Typ
VDD = 1.8 to 5.5V
Typ
32.768
+1.0%
-1.0%
With software
1
adjustment *
Low-speed RC oscillator
fRCL2
frequency accuracy 2
Ta= -40 to +105°C
Typ
VDD = 1.8 to 5.5V
Typ
32.768
+1.5%
-1.5%
With software
1
adjustment *
1
Ta= -40 to +85°C
Typ
VDD = 1.8 to 5.5V
Typ
16/24
+2.5%
-2.5%
Without software
1
adjustment *
Ta= -40 to +105°C
PLL oscillation frequency
Typ
fPLL1
VDD = 1.8 to 5.5V
Typ
accuracy 1
16/24
+3.0%
-3.0%
Without software
1
adjustment *
VDD = 1.6 to 1.8V
Typ
Typ
MHz
16/24
Without software
+3.5%
-3.5%
1
adjustment *
Ta= -40 to +85°C
Typ
VDD = 1.8 to 5.5V
Typ
16/24
+1.0%
-1.0%
With software
1
adjustment *
PLL oscillation frequency
fPLL2
accuracy 2
Ta= -40 to +105°C
Typ
VDD = 1.8 to 5.5V
Typ
16/24
+1.5%
-1.5%
With software
1
adjustment *
PLL oscillation start time
TPLL
VDD = 1.6 to 5.5V
―
―
2
ms
Ta= -40 to +105°C
1kHz Low-speed RC oscillator
fRC1K
0.5
1
2.5
kHz
(for WDT) frequency accuracy
VDD = 1.6 to 5.5V
1
* Adjust the frequency by using temperature sensor in ADC and a Specific Function Register (LRCADJ register)
25/59
FEDL62Q1300-02
Input / Output pin 1
(VDD=1.6 to 5.5V, VSS =0V, Ta=−40 to +105οC, unless otherwise specified)
Parameter
Output voltage1
“H”/”L” level
(P00-P07)
(P10-P17)
(P20-P27)
(P30-P33)
Output voltage2
“L” level
(P01-P07)
(P10-P17)
(P20-P27)
(P30-P33)
Symbol
Condition
Min.
Typ.
Max.
VDD
-1.5
VDD
-0.5
―
―
VOH1
IOH1=-10mA
VDD≥4.5V
IOH1=-1mA
VDD≥1.6V
―
―
IOL1=+10mA
VDD≥4.5V
―
―
1.5
IOL1=+1mA
VDD≥1.6V
―
―
0.5
IOL2=+15mA
VDD≥4.5V
IOL2=+8mA
VDD≥3.0V
IOL2=+3mA
VDD≥2.0V
―
―
0.7
―
―
0.5
―
―
0.4
IOL2=+2mA
VDD≥1.6V
―
―
0.4
VOL1
VOL2
When Nch open
drain output
mode is selected
Unit
Measur
ing
circuit
V
2
26/59
FEDL62Q1300-02
Input / Output pin 2
(VDD=1.6 to 5.5V, VSS =0V, Ta=−40 to +105οC, unless otherwise specified)
Parameter
Symbol
“H” level output
6
current1 *
IOH1
“H” level output
1 4
current * *
“L” level output
6
current1 *
“L” level output
6
current2 *
“L” level output
2 4
total current * *
IOH3
IOL1
IOL2
IOL3
Condition
1pin
Total of ‘P00-P07
andP10-P13
or
Total of ‘P14-P17,
P20-P27 and P30-P33
(Duty≤50%)
All pin total
(Duty≤50%)
1pin
(CMOS output mode)
1pin
(Nch open drain output
mode)
Total of P00-P07 and
P10-P13
or
Total of P14-P17,
P20-P27 and P30-P33
(Nch open drain output
mode, duty≤50%)
All pin total
(Nch open drain output
mode, duty≤50%)
Min.
Typ
.
Max.
VDD≥4.5V
VDD≥1.6V
-10* *
3 5
-1* *
3 5
―
―
―
―
VDD≥4.5V
-50*
5
―
―
VDD≥1.6V
-20*
5
―
―
VDD≥4.5V
VDD≥1.6V
VDD≥4.5V
VDD≥1.6V
VDD≥4.5V
VDD≥3.0V
VDD≥2.0V
VDD≥1.6V
-100*
5
-40*
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
3
10*
3
1*
3
15*
3
8*
3
3*
3
2*
VDD≥4.5V
―
―
60
VDD≥3.0V
―
―
40
VDD≥2.0V
―
―
15
VDD≥1.6V
―
―
10
VDD≥4.5V
―
―
120
VDD≥1.6V
―
―
20
5
Output leak
IOOH
VOH=VDD (High impedance mode)
―
―
(P00-P07)
(P10-P17)
5
(P20-P27)
IOOL
VOL=VSS (High impedance mode)
-1*
―
(P30-P33)
1
* Sink-out current from VDD to the output pin, which can guarantee the device operation.
2
* Sink-in current from the output pin to VSS, which can guarantee the device operation.
3
* Do not exceed total current.
4
* The total current is on the condition of Duty≤50%.
When the duty ＞50% the total current is calculated by following formula.
Total current = IOL3 x 50/n (When the duty is n%)
When IOL3=100mA and n=80%,
Total current = IOL3 x 50/80 = 62.5mA
Current allowed per 1pin is independent of the duty and specified as IOL1 and IOL2.
Do not apply current larger than Absolute Maximum Ratings.
5
* The current flowing out the LSI through the pin is described in the negative number.
The applicable maximum current is the absolute value.
For example, -1mA means the maximum current 1mA flows out the LSI through the pin.
6
* VOH1, VOL1, and VOL2 are satisfied with this spec.
Unit
Measu
ring
circuit
mA
3
+1
μA
―
27/59
FEDL62Q1300-02
Input / Output pin 3
(VDD=1.6 to 5.5V, VSS =0V, Ta=−40 to +105οC, unless otherwise specified)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Input current1
(RESET_N)
IIH1
IIL1
IIL2
V/IIL2
IIH2Z
IIL2Z
IIL3
V/IIL3
IIH3Z
VIH1=VDD
VIL1=VSS
*2
VIL2=VSS (pull-up mode)
*2
VIL2=VSS (pull-up mode)
VIH2=VDD (High impedance mode)
VIL2=VSS (High impedance mode)
*2
VIL1=VSS(pull-up mode)
*2
VIL1=VSS (pull-up mode)
VIH1=VDD (High impedance mode)
―
1
-1*
1
-1500*
3.7
―
1
-1*
1
-250*
22
―
―
―
1
-300*
10
―
―
1
-30*
100
―
1
―
1
-20*
80
1
―
1
-2*
800
1
IIL3Z
VIL1=VSS (High impedance mode)
-1*
―
―
VIH1
―
0.7
x VDD
―
VDD
VIL1
―
0
―
0.3
x VDD
VIH2
―
0.7
x VDD
―
VDD
VIL2
―
0
―
0.25
x VDD
CPIN
f = 10kHz
Ta = +25°C
―
―
10
Input current2
(P00/TEST0)
Input current3
(P01-P07)
(P10-P17)
(P20-P27)
(P30-P33)
Input voltage1
(RESET_N)
(P01-P07)
(P10-P17)
(P20-P27)
(P30-P33)
Input voltage2
(P00/TEST0)
Pin capacitance
(RESET_N)
(P00/TEST0)
(P01-P07)
(P10-P17)
(P20-P27)
(P30-P33)
1
Unit
Measur
ing
circuit
μA
kΩ
μA
4
kΩ
μA
V
5
pF
―
1
* The current flowing out the LSI through the pin is described in the negative number.
The applicable maximum current is the absolute value.
For example, -1mA means the maximum current 1mA flows out the LSI through the pin.
*2
Measurement conditions: Typ. : VDD = 3.0V, Max. : VDD = 1.6V, Min. : VDD = 5.5V
28/59
FEDL62Q1300-02
Synchronous Serial Port
Slave mode
Parameter
SCK input cycle
SCK input pulse width
(VDD=1.8 to 5.5V, VSS =0V, Ta=−40 to +105οC, unless otherwise specified)
Condition
Min.
Typ.
Max.
Unit
2
―
1*
―
―
µs
3
―
0.5 *
―
―
µs
100+
VDD=2.4 to 5.5V
―
―
ns
1
HSCLK* ×3
200+
VDD=1.8 to 5.5V
―
―
ns
1
HSCLK* ×3
1
HSCLK*
―
―
―
ns
x1
80+
―
―
―
ns
1
HSCLK* ×3
Symbol
tSCYC
tSW
SOUT output delay time
tSD
SIN input setup time
tSS
SIN input hold time
tSH
1
* Cycle of high speed clock
2
* Need input cycles of HSLCK x8 or longer
3
* Need input cycles of HSLCK x4 or longer
tSCYC
tSW
tSW
70%
SUn_SCLK*
30%
tSD
SUn_SOUT*
tSD
70%
70%
30%
30%
tSS
SUn_SIN*
*2
nd
tSH
70%
70%
30%
30%
th
to 8 function of port, n=0~1
29/59
FEDL62Q1300-02
Master mode
(VDD=1.8 to 5.5V, VSS =0V, Ta=−40 to +105οC, unless otherwise specified)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
1
SCK output cycle
tSCYC
―
―
SCLK*
―
ns
1
1
1
SCLK*
SCLK*
SCLK*
SCK output pulse width
tSW
―
ns
×0.4
×0.5
×0.6
VDD=2.4 to 5.5V
―
―
100
ns
SOUT output delay time
tSD
VDD=1.8 to 5.5V
―
―
160
ns
VDD=2.4 to 5.5V
120
―
―
ns
SIN input setup time
tSS
VDD=1.8 to 5.5V
180
―
―
ns
VDD=2.4 to 5.5V
80
―
―
ns
SIN input hold time
tSH
VDD=1.8 to 5.5V
100
―
―
ns
1
* Clock cycle selected by bit12~8(SnCK4~0) of the serial port n mode register (SIOnMOD)
VDD≥2.4V: min250ns , VDD≥1.8V: min500ns
tSCYC
tSW
tSW
70%
SUn_SCLK*
30%
tSD
SUn_SOUT*
tSD
70%
70%
30%
30%
tSS
SUn_SIN*
*2
nd
tSH
70%
70%
30%
30%
th
to 8 function of port, n=0~1
30/59
FEDL62Q1300-02
I2C Bus Interface
Standard Mode 100kbps
(VDD=1.8 to 5.5V, VSS =0V, Ta=−40 to +105οC, unless otherwise specified)
Symbol
Condition
Min.
Typ.
Max.
Unit
fSCL
―
0
―
100
kHz
Parameter
SCL clock frequency
SCL hold time
tHD:STA
―
4.0
―
―
µs
(start/restart condition)
tLOW
―
4.7
―
―
SCL ”L” level time
µs
tHIGH
―
4.0
―
―
SCL ”H” level time
µs
SCL setup time
tSU:STA
―
4.7
―
―
µs
(restart condition)
SDA hold time
tHD:DAT
―
0
―
―
µs
SDA setup time
tSU:DAT
―
0.25
―
―
µs
SDA setup time
tSU:STO
―
4.0
―
―
µs
(stop condition)
Bus-free time
tBUF
―
4.7
―
―
µs
2
2
2
When using the I C as the master, configure the I C master n mode register (I2MnMOD) and I C bus 0 mode register
(master side, I2UM0MOD) so that meet these specifications.
Start
Condition
I2U0_SDA
I2M0_SDA
Re-start
Condition
Stop
Condition
70% 70%
70% 70%
70%
I2U0_SCL
I2M0_SCL
30%
tHD:STA
30%
tLOW
70%
70%
30%
tHIGH
tSU:STA tHD:STA
70%
70%
30%
30%
30%
tSU:DAT
30%
tHD:DAT
70%
30%
70%
70%
tSU:STO tBUF
31/59
FEDL62Q1300-02
Fast Mode 400kbps
(VDD=1.8 to 5.5V, VSS =0V, Ta=−40 to +105οC, unless otherwise specified)
Symbol
Condition
Min.
Typ.
Max.
Unit
fSCL
―
0
―
400
kHz
Parameter
SCL clock frequency
SCL hold time
tHD:STA
―
0.6
―
―
µs
(start/restart condition)
SCL ”L” level time
tLOW
―
1.3
―
―
µs
SCL ”H” level time
tHIGH
―
0.6
―
―
µs
SCL setup time
tSU:STA
―
0.6
―
―
µs
(restart condition)
tHD:DAT
―
0
―
―
SDA hold time
µs
SDA setup time
tSU:DAT
―
0.1
―
―
µs
SDA setup time
tSU:STO
―
0.6
―
―
µs
(stop condition)
Bus-free time
tBUF
―
1.3
―
―
µs
2
2
2
When using the I C as the master, configure the I C master n mode register(I2MnMOD) and I C bus 0 mode register
(master side, I2UM0MOD) so that meet these specifications.
Start
Condition
I2U0_SDA
I2M0_SDA
Re-start
Condition
Stop
Condition
70% 70%
70% 70%
70%
I2U0_SCL
I2M0_SCL
30%
tHD:STA
30%
tLOW
70%
70%
30%
tHIGH
tSU:STA tHD:STA
70%
70%
30%
30%
30%
tSU:DAT
30%
tHD:DAT
70%
30%
70%
70%
tSU:STO tBUF
32/59
FEDL62Q1300-02
1Mbps Mode
(VDD=2.7 to 5.5V, VSS =0V, Ta=−40 to +105οC, unless otherwise specified)
Symbol
Condition
Min.
Typ.
Max.
Unit
fSCL
―
0
―
1000
kHz
Parameter
SCL clock frequency
SCL hold time
tHD:STA
―
0.26
―
―
µs
(start/restart condition)
SCL ”L” level time
tLOW
―
0.5
―
―
µs
SCL ”H” level time
tHIGH
―
0.26
―
―
µs
SCL setup time
tSU:STA
―
0.26
―
―
µs
(restart condition)
tHD:DAT
―
0
―
―
SDA hold time
µs
SDA setup time
tSU:DAT
―
0.1
―
―
µs
SDA setup time
tSU:STO
―
0.26
―
―
µs
(stop condition)
Bus-free time
tBUF
―
0.5
―
―
µs
2
2
2
When using the I C as the master, configure the I C master n mode register(I2MnMOD) and I C bus 0 mode register
(master side, I2UM0MOD) so that meet these specifications.
Start
Condition
I2U0_SDA
I2M0_SDA
Re-start
Condition
Stop
Condition
70% 70%
70% 70%
70%
I2U0_SCL
I2M0_SCL
30%
tHD:STA
30%
tLOW
70%
70%
30%
tHIGH
tSU:STA tHD:STA
70%
70%
30%
30%
30%
tSU:DAT
70%
70%
30%
30%
tHD:DAT
70%
tSU:STO tBUF
33/59
FEDL62Q1300-02
Reset
(VDD=1.6 to 5.5V, VSS =0V, Ta=−40 to +105οC, unless otherwise specified)
Parameter
Reset pulse width
P00 ”H” level setup time
P00 ”H” level hold time
Symbol
Condition
Min.
Typ.
Max.
Unit
Measur
ing
circuit
PRST
tSP00
tHP00
―
―
―
2
1
1
―
―
―
―
―
―
ms
ms
ms
1
VIL1
RESET_N
VIH1
VIL1
PRST
“H” level input
or “Pull-up”
“H” level or “L” level
P00/TEST0
tSP00
“H” level or “L” level
tHP00
Power On Reset
(VSS =0V, Ta=−40 to +105οC, unless otherwise specified)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
V
Power down(falling)
1.43
1.49
1.58
Power up(rising)
1.47
1.57
1.80
V
1
Power on rising slope
RPOR*
―
―
―
60
V/ms
2
POR response time
PPOR
*
200
―
―
µs
1
* : Rise the VDD to 1.8V or higher when powering on.
2
* : This is the time from the VDD gets 100mV lower than VPOR to the Power-On-Reset internally generates.
Make the power down falling slope 2V/ms or lower(i.e. slower).
POR detect voltage
Measur
ing
circuit
VPOR
1
1.8V
VDD
0V
VPOR
100mV
VPOR
PPOR
[Note for in case of instantaneous power failure]
In case of instantaneous power failure and a pulse shorter than the response time of VLS or POR is asserted to VDD, it is possible to
make the MCU cannot get the reset and make erroneous operation. In that case, please have countermeasures such as preventing
the voltage down using bypass capacitor or making reset pin reset.
34/59
FEDL62Q1300-02
VLS
Parameter
Symbol
VVLSR
VVLSF
VVLSR
VVLSF
VVLSR
VVLSF
VVLSR
VVLSF
VVLSR
VVLSF
VVLSR
VLS threshold
2
voltage *
VVLSF
VVLSR
VVLSF
VVLSR
VVLSF
VVLSR
VVLSF
VVLSR
VVLSF
VVLSR
VVLSF
VVLSR
VVLSF
VLS Current
IVLS
(VDD=1.6 to 5.5V, VSS =0V, Ta=−40 to +105οC, unless otherwise specified)
Condition
Measuring
Min.
Typ.
Max.
Unit
1
circuit
VLS0LV *
Rising
3.86
4.06
4.26
00H
Falling
3.84
4.00
4.16
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
Rising
3.57
3.76
3.95
Falling
3.55
3.70
3.85
Rising
2.94
3.11
3.28
Falling
2.92
3.05
3.18
Rising
2.85
3.01
3.17
Falling
2.83
2.95
3.07
Rising
2.75
2.91
3.07
Falling
2.73
2.85
2.97
Rising
2.66
2.81
2.96
Falling
2.64
2.75
2.86
Rising
2.56
2.71
2.86
Falling
2.54
2.65
2.76
Rising
2.46
2.61
2.76
Falling
2.44
2.55
2.66
Rising
2.37
2.51
2.65
Falling
2.35
2.45
2.55
Rising
1.98
2.11
2.24
Falling
1.96
2.05
2.14
Rising
1.89
2.01
2.13
Falling
1.87
1.95
2.03
Rising
1.79
1.91
2.03
Falling
1.77
1.85
1.93
―
50
―
―
V
1
nA
1
* Bit3~Bit0 of voltage level detection circuit 0 level register (VLS0LV).
2
* The Data VLS0LV = 0CH~0FH is not available to use, if the data is specified it will the same spec as that 0BH is
specified.
Analog Comparator
o
(VDD=1.8 to 5.5V, VSS =0V, Ta=-40 to +105 C, unless otherwise specified)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Comparator same
phase input
voltage range
VCMR
―
0.1
―
VDD
-1.5
V
Comparator0
input offset
VCMOF
Ta=+25 C, VDD=5.0V
―
5
―
mV
Comparator
Reference
Voltage
VCMREF
―
0.75
0.8
0.85
V
O
Measuring
circuit
1
35/59
FEDL62Q1300-02
Successive Approximation Type A/D Converter
o
Parameter
Resolution
Overall error
Symbol
nAD
―
Integral non-linearity
error
INLAD
Differential non-linearity
error
DNLAD
Zero-scale error
Full-scale error
A/D reference voltage
Internal reference voltage
ZSE
FSE
VREF
VREFI
Conversion time
tCONV
(VDD=1.8 to 5.5V, VSS =0V, Ta=-40 to +105 C, unless otherwise specified)
Condition
Min.
Typ.
Max.
Unit
―
―
―
10
bit
1
4.5V≤VREFP * ≤5.5V
-3.5
1.2
3.5
1
2.7V≤VREFP * ≤5.5V
-4
―
4
1
2.2V≤VREFP * ＜2.7V
-6
―
6
1
1.8V≤VREFP * ＜2.2V
-10
―
10
VREFP=Internal reference voltage
-15
―
15
1
2.7V≤VREFP * ≤5.5V
-3
―
3
LSB
1
2.2V≤VREFP * ＜2.7V
-5
―
5
1
1.8V≤VREFP * ＜2.2V
-9
―
9
VREFP=Internal reference voltage
-14
―
14
RI≤1kΩ
-6
―
6
RI≤1kΩ
-6
―
6
―
1.8
―
VDD
V
―
1.5
1.55
1.6
4.5V≤VDD≤5.5V
2.25
―
427
μs
2.2V≤VDD≤5.5V
4.5
―
427
1.8V≤VDD≤5.5V
18
―
427
1
* : VDD or P23/VREF is selected for the reference voltage of Successive Approximation Type A/D Converter by setting
bit5(VREFP1) and bit4(VREFP0) of SA-ADC TEMP/VREF control register(VREFCON).
The current flows during the ADC sampling as it takes charging. Make the output impedance of the anlog signal source 1kΩ
or smaller. Also, putting 0.1uF capacitor on the ADC input pin is recommended to reduce the noise.
VDD
VDDL
1.0μF
A
-
1.0μF
Analog input
RI≤1kΩ
AINn
+
0.1μF
VSS
36/59
FEDL62Q1300-02
D/A Converter
o
Parameter
Resolution
Conversion cycle
Integral non-linearity error
Differential non-linearity
error
Output impedance
Symbol
nDA
tc
INLDA
DNLDA
(VDD=1.8 to 5.5V, VSS =0V, Ta=-40 to +105 C, unless otherwise specified)
Condition
Min.
Typ.
Max.
Unit
―
―
―
8
bit
―
10
―
―
μs
RL=4MΩ
-2
―
2
LSB
RL=4MΩ
-1
―
1
DACEN bit of D/A converter enable
register =1
Ro
3
6
9
kΩ
Reference Voltage Output
o
Parameter
Output voltage
Output impedance
Symbol
VREFO
RVREFO
(VDD=1.8 to 5.5V, VSS =0V, Ta=-40 to +105 C, unless otherwise specified)
Condition
Min.
Typ.
Max.
Unit
―
―
1.55
―
V
―
―
―
500
kΩ
Flash Memory
Parameter
Symbol
Operating temperature
TOP
Operating voltage
VDD
CEPD
CEPP
Maximum rewrite count
―
Erase unit
―
Erase time (Max.)
―
Write unit
―
Write time (Max.)
Data retention period
―
―
YDR
Condition
Data flash memory, At write/erase
Flash ROM, At write/erase
At write/erase
Data Flash (4Kbyte)
Program Flash
Program Flash
Block erase
Data Flash
Program Flash
Sector erase
Data Flash
Block erase /
Sector erase
Program Flash
Data Flash
Program Flash
Data Flash
―
Range
-40 to +85
0 to +40
+1.8 to +5.5
10000
100
16K
All area
1K
128
50
4
1
80
40
15
(VSS= 0V)
Unit
°C
V
times
B
B
ms
B
μs
years
37/59
FEDL62Q1300-02
Measuring circuit
Measuring circuit 1
VDD
VDDL
CV :1.0μF
CL :1.0μF
VSS
A
CV
CL
Measuring circuit 2
(*2)
VIH
Output pins
VIL
Input pins
(*1)
VDD
VDDL
V
Current
load
VSS
(*1) Input logic circuit to determine the specified measuring conditions
(*2) Measured connecting specified pins
Measuring circuit 3
(*2)
VIH
Output pins
VIL
Input pins
(*1)
VDD
VDDL
A
VSS
(*1) Input logic circuit to determine the specified measuring conditions
(*2) Measured connecting specified pins
38/59
FEDL62Q1300-02
Measuring circuit 4
(*2)
Output pins
Input pins
A
VDD
VDDL
VSS
(*2) Measured connecting specified pins
Measuring circuit 5
VIH
Output pins
VIL
Input pins
(*1)
VDD
VDDL
VSS
(*1) Input logic circuit to determine the specified measuring conditions
39/59
FEDL62Q1300-02
Characteristics graphs
These Graphs on the following pages are references for designing an application.
40/59
FEDL62Q1300-02
IOH vs VDD-VOH1 (VDD=5V TYP.)
IOH vs VDD-VOH1 (VDD=5V TYP.)
-40[℃]
25[℃]
85[℃]
105[℃]
5
VDD-VOH[V]
4
3
2
1
0
-60
-50
-40
-30
IOH[mA]
-20
-10
0
IOH vs VDD-VOH1 (VDD=3V TYP.)
IOH vs VDD-VOH1 (VDD=3V TYP.)
-40[℃]
25[℃]
85[℃]
105[℃]
3
VDD-VOH[V]
2.5
2
1.5
1
0.5
0
-30
-25
-20
-15
IOH[mA]
-10
-5
0
41/59
FEDL62Q1300-02
IOL vs VOL1 (VDD=5V TYP.)
IOL vs VOL1 (VDD=5V TYP.)
-40[℃]
25[℃]
85[℃]
105[℃]
5
VOL1[V]
4
3
2
1
0
0
10
20
30
40
50
IOL[mA]
IOL vs VOL1 (VDD=3V TYP.)
IOL vs VOL1 (VDD=3V TYP.)
-40[℃]
25[℃]
85[℃]
105[℃]
3
VOL1[V]
2.5
2
1.5
1
0.5
0
0
5
10
IOL[mA]
15
20
42/59
FEDL62Q1300-02
IOL vs VOL2 (VDD=5V TYP.)
IOL vs VOL2 (VDD=5V TYP.)
-40[℃]
25[℃]
85[℃]
105[℃]
5
VOL2[V]
4
3
2
1
0
0
20
40
60
80
100
IOL[mA]
IOL vs VOL2 (VDD=3V TYP.).
IOL vs VOL2 (VDD=3V TYP.)
-40[℃]
25[℃]
85[℃]
105[℃]
3
VOL2[V]
2.5
2
1.5
1
0.5
0
0
10
20
30
40
50
IOL[mA]
43/59
FEDL62Q1300-02
VDD VS IIL2 (TYP. VIL2=VSS)
VDD vs IIL2 (TYP. VIL2=VSS)
-40℃
25℃
85℃
2
3
4
105℃
0
-100
IIH2[uA]
-200
-300
-400
-500
-600
-700
1
5
6
VDD[V]
Pull-up resistor
VDD VS VDD/IIL2 (TYP. VIL2=VSS)
Pull-up resistor
VDD vs VDD/IIL2 (TYP. VIL2=VSS)
VDD/IIH2[kΩ]
-40℃
14
12
10
8
6
4
2
0
1
2
25℃
85℃
105℃
3
4
5
6
VDD[V]
44/59
FEDL62Q1300-02
VDD VS IIL3 (TYP. VIL3=VSS)
VDD vs IIL3 (TYP. VIL3=VSS)
-40℃
25℃
85℃
2
3
4
105℃
0
IIH3[uA]
-50
-100
-150
-200
1
5
6
VDD[V]
Pull-up resistor
VDD VS VDD/IIL3 (TYP. VIL3=VSS)
VDD/IIH3[kΩ]
Pull-up resistor
VDD vs VDD/IIL3 (TYP. VIL3=VSS)
350
300
250
200
150
100
50
0
1
-40℃
25℃
2
3
85℃
4
105℃
5
6
VDD[V]
45/59
FEDL62Q1300-02
Product： ML62Q1323, ML62Q1324, ML62Q1325, ML62Q1333, ML62Q1334, ML62Q1335
Current consumption VS operating frequency of CPU
VDD=3V, temp=25℃ CPU 16MHz Wait mode (TYP.)
Stop the clock supply to peripherals.
consumption current [mA]
Current consumption VS operating frequency of CPU
VDD=3V, temp=25oC CPU 16MHz Wait mode (TYP.)
Stop the clock supply to peripherals.
3.5
3
2.5
2
1.5
1
0.5
0
0
5
10
15
operating frequency of CPU [MHz]
20
VDD=3V, temp=25℃ CPU 16MHz no Wait mode (TYP.)
consumption current [mA]
Current consumption VS operating frequency of CPU
VDD=3V, temp=25oC CPU 16MHz no Wait mode (TYP.)
Stop the clock supply to peripherals.
2.5
2
1.5
1
0.5
0
0
2
4
6
operating frequency of CPU [MHz]
8
10
46/59
FEDL62Q1300-02
Product： ML62Q1323, ML62Q1324, ML62Q1325, ML62Q1333, ML62Q1334, ML62Q1335
Current consumption VS operating frequency of CPU
VDD=3V, temp=25℃ CPU 24MHz Wait mode (TYP.)
Stop the clock supply to peripherals.
consumption current [mA]
Current consumption VS operating frequency of CPU
VDD=3V, temp=25oC CPU 24MHz Wait mode (TYP.)
Stop the clock supply to peripherals.
5
4
3
2
1
0
0
5
10
15
20
operating frequency of CPU [MHz]
25
30
VDD=3V, temp=25℃ CPU 24MHz no Wait mode (TYP.)
consumption current [mA]
Current consumption VS operating frequency of CPU
VDD=3V, temp=25oC CPU 24MHz no Wait mode (TYP.)
Stop the clock supply to peripherals.
2
1.5
1
0.5
0
0
1
2
3
4
5
operating frequency of CPU [MHz]
6
7
47/59
FEDL62Q1300-02
Product： ML62Q1345, ML62Q1346, ML62Q1347, ML62Q1365, ML62Q1366, ML62Q1367
Current consumption VS operating frequency of CPU
VDD=3V, temp=25°C CPU 16MHz Wait mode (TYP.)
Stop the clock supply to peripherals.
consumption current [mA]
Current consumption VS operating frequency of CPU
VDD=3V, temp=25oC CPU 16MHz Wait mode (TYP.)
Stop the clock supply to peripherals.
5
4
3
2
1
0
0
5
10
15
operating frequency of CPU [MHz]
20
VDD=3V, temp=25°C CPU 16MHz no Wait mode (TYP.)
consumption current [mA]
Current consumption VS operating frequency of CPU
VDD=3V, temp=25oC CPU 16MHz no Wait mode (TYP.)
Stop the clock supply to peripherals.
3
2.5
2
1.5
1
0.5
0
0
2
4
6
operating frequency of CPU [MHz]
8
10
48/59
FEDL62Q1300-02
Product： ML62Q1345, ML62Q1346, ML62Q1347, ML62Q1365, ML62Q1366, ML62Q1367
Current consumption VS operating frequency of CPU
VDD=3V, temp=25 oC CPU 24MHz Wait mode (TYP.)
Stop the clock supply to peripherals.
consumption current [mA]
Current consumption VS operating frequency of CPU
VDD=3V, temp=25oC CPU 24MHz Wait mode (TYP.)
Stop the clock supply to peripherals.
7
6
5
4
3
2
1
0
0
5
10
15
20
operating frequency of CPU [MHz]
25
30
VDD=3V, temp=25 oC CPU 24MHz no Wait mode (TYP.)
consumption current [mA]
Current consumption VS operating frequency of CPU
VDD=3V, temp=25oC CPU 24MHz no Wait mode (TYP.)
Stop the clock supply to peripherals.
2.5
2
1.5
1
0.5
0
0
1
2
3
4
5
operating frequency of CPU [MHz]
6
7
49/59
FEDL62Q1300-02
Consumption current of ADC VS operating voltage
PLL frequency=16MHz temp=25 oC ch0 VREF=VDD
consumption current of ADC
(PLL frequency=16MHz temp=25oC ch0 VREF=VDD )
consumption current of ADC [mA]
1.2
1
0.8
0.6
0.4
0.2
0
2
2.5
3
3.5
4
VDD [V]
4.5
5
5.5
50/59
FEDL62Q1300-02
TEMP VS Low-speed RC oscillator frequency accuracy 1
without software adjustment (Typ.)
Low-speed RC oscillator frequency accuracy 1
without software adjustment (Typ.)
Low-speed RC oscillator
frequency accuracy 1 [%]
VDD=1.8V
4
3
2
1
0
-1
-2
-3
-4
-40
-20
0
VDD=3V
20
40
VDD=5.5V
60
80
100
Temp[oC]
TEMP VS PLL oscillator frequency accuracy 1
without software adjustment (24MHz Typ.)
PLL oscillator frequency accuracy 1
without software adjustment (24MHz Typ.)
PLL oscillator
frequency accuracy 1 [%]
VDD=1.8V
4
3
2
1
0
-1
-2
-3
-4
-40
-20
0
VDD=3V
20
40
o
Temp[ C]
VDD=5.5V
60
80
100
51/59
FEDL62Q1300-02
PACKAGE DIMENSIONS
ML62Q1323/1324/1325
16pin SSOP Package
(Unit: mm)
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore,
before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin number, package
code and desired mounting conditions (reflow method, temperature and times).
52/59
FEDL62Q1300-02
ML62Q1323/1324/1325
16pin WQFN Package
(Unit: mm)
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore,
before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin number, package
code and desired mounting conditions (reflow method, temperature and times).
Note for the package with exposed die pad
The die pad is exposed on the bottom of WQFN package. Make the die pad electrically open when soldering onto the PCB.
53/59
FEDL62Q1300-02
ML62Q1333/1334/1335
20pin TSSOP Package
(Unit: mm)
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore,
before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin number, package
code and desired mounting conditions (reflow method, temperature and times).
54/59
FEDL62Q1300-02
ML62Q1345/1346/1347
24pin WQFN Package
(Unit: mm)
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore,
before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin number, package
code and desired mounting conditions (reflow method, temperature and times).
Note for the package with exposed die pad
The die pad is exposed on the bottom of WQFN package. Make the die pad electrically open when soldering onto the PCB.
55/59
FEDL62Q1300-02
ML62Q1365/1366/1367
32pin TQFP Package
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore,
before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin number, package
code and desired mounting conditions (reflow method, temperature and times).
56/59
FEDL62Q1300-02
ML62Q1365/1366/1367
32pin WQFN Package
(Unit: mm)
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore,
before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin number, package
code and desired mounting conditions (reflow method, temperature and times).
Note for the package with exposed die pad
The die pad is exposed on the bottom of WQFN package. Make the die pad electrically open when soldering onto the PCB.
57/59
FEDL62Q1300-02
REVISION HISTORY
Document
No.
Date
FEDL62Q1300-01
Nov 15, 2018
FEDL62Q1300-02
Sep 27, 2019
Page
Previous Current
Edition
Edition
Description
st
-
-
1 Revision.
1
1
Changed the products status (Table 1 ML62Q1300 Group
Product List)
-
23
Added Current Consumption 1
26
27
Added comment “*6” to the IOHL.
46
49
Updated 24MHz Characteristics graph
-
46,47
*
*
Added ML62Q1323/ML62Q1324/ML62Q1325/ML62Q1333/
ML62Q1334/ML62Q1335 Current consumption VS operating
frequency of CPU
Correction of errors
58/59
FEDL62Q1300-02
Notes
1) The information contained herein is subject to change without notice.
2) Although LAPIS Semiconductor is continuously working to improve product reliability and quality, semiconductors can
break down and malfunction due to various factors. Therefore, in order to prevent personal injury or fire arising from failure,
please take safety measures such as complying with the derating characteristics, implementing redundant and fire prevention
designs, and utilizing backups and fail-safe procedures. LAPIS Semiconductor shall have no responsibility for any damages
arising out of the use of our Products beyond the rating specified by LAPIS Semiconductor.
3) Examples of application circuits, circuit constants and any other information contained herein are provided only to illustrate
the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing
circuits for mass production.
4) The technical information specified herein is intended only to show the typical functions of the Products and examples of
application circuits for the Products. No license, expressly or implied, is granted hereby under any intellectual property rights
or other rights of LAPIS Semiconductor or any third party with respect to the information contained in this document;
therefore LAPIS Semiconductor shall have no responsibility whatsoever for any dispute, concerning such rights owned by
third parties, arising out of the use of such technical information.
5) The Products are intended for use in general electronic equipment (i.e. AV/OA devices, communication, consumer systems,
gaming/entertainment sets) as well as the applications indicated in this document.
6) The Products specified in this document are not designed to be radiation tolerant.
7) For use of our Products in applications requiring a high degree of reliability (as exemplified below), please contact and
consult with a LAPIS Semiconductor representative: transportation equipment (i.e. cars, ships, trains), primary
communication equipment, traffic lights, fire/crime prevention, safety equipment, medical systems, servers, solar cells, and
power transmission systems.
8) Do not use our Products in applications requiring extremely high reliability, such as aerospace equipment, nuclear power
control systems, and submarine repeaters.
9) LAPIS Semiconductor shall have no responsibility for any damages or injury arising from non-compliance with the
recommended usage conditions and specifications contained herein.
10) LAPIS Semiconductor has used reasonable care to ensure the accuracy of the information contained in this document.
However, LAPIS Semiconductor does not warrant that such information is error-free and LAPIS Semiconductor shall have no
responsibility for any damages arising from any inaccuracy or misprint of such information.
11) Please use the Products in accordance with any applicable environmental laws and regulations, such as the RoHS Directive.
For more details, including RoHS compatibility, please contact a ROHM sales office. LAPIS Semiconductor shall have no
responsibility for any damages or losses resulting non-compliance with any applicable laws or regulations.
12) When providing our Products and technologies contained in this document to other countries, you must abide by the
procedures and provisions stipulated in all applicable export laws and regulations, including without limitation the US
Export Administration Regulations and the Foreign Exchange and Foreign Trade Act.
13) This document, in part or in whole, may not be reprinted or reproduced without prior consent of LAPIS Semiconductor.
Copyright 2018-2019 LAPIS Semiconductor Co., Ltd.
2-4-8 Shinyokohama, Kouhoku-ku,
Yokohama 222-8575, Japan
http://www.lapis-semi.com/en/
59/59
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