FEDL62Q1500-07
Issue Date: May 19, 2022
ML62Q1500/1800 Group
16-bit micro controller
GENERAL DESCRIPTION
ML62Q1500/1800 Group is a high performance CMOS 16-bit microcontroller equipped with an 16-bit CPU nX-U16/100 and
integrated with program memory(Flash memory), data memory(RAM), data Flash and rich peripheral functions such as the
multiplier/divider, CRC generator, DMA controller, Clock generator, Simplified RTC, Timer, General Purpose Ports, UART,
Synchronous serial port, I2C bus interface unit (Master, Slave), Buzzer, Voltage Level Supervisor(VLS), Successive
approximation type A/D converter, D/A converter , Analog comparator, Safety function(IEC60730/60335 Class B) and so on.
The CPU nX-U16/100 is capable of efficient instruction execution in 1-instruction 1-clock mode by pipeline architecture parallel
processing.
The built-in on-chip debug function enables debugging and programming the software. Also, ISP(In-System Programming)
function supports the Flash programming in production line.
The ML62Q1500/1800 Group has seven packages (48pin - 100pin) and ten kinds of memory sizes(32Kbyte - 512Kbyte).
Table 1 ML62Q1500/1800 Group Product List
Program
memory
512Kbyte
384Kbyte
Data memory
(RAM)
Data Flash
32Kbyte
8Kbyte
256Kbyte
192Kbyte
16Kbyte
160Kbyte
128Kbyte
96Kbyte
32Kbyte
52pin
TQFP52
64pin
QFP64
TQFP64
80pin
QFP80
100pin
QFP100
TQFP100
－
－
ML62Q1859
ML62Q1869
ML62Q1879
－
－
ML62Q1858
ML62Q1868
ML62Q1878
－
－
ML62Q1557
ML62Q1567
ML62Q1577
－
－
ML62Q1556
ML62Q1566
ML62Q1576
－
－
ML62Q1555
ML62Q1565
ML62Q1575
16Kbyte
－
－
－
ML62Q1564
ML62Q1574
8Kbyte
ML62Q1534
ML62Q1544
ML62Q1554
－
－
16Kbyte
8Kbyte
64Kbyte
48Kbyte
48pin
TQFP48
8Kbyte
4Kbyte
－
－
－
ML62Q1563
ML62Q1573
ML62Q1533
ML62Q1543
ML62Q1553
－
－
ML62Q1532
ML62Q1542
ML62Q1552
－
－
ML62Q1531
ML62Q1541
ML62Q1551
－
－
ML62Q1530
ML62Q1540
ML62Q1550
－
－
Please see the page 70 “Notes for product usage” and the page 71 “Notes” in this document on use with this ML62Q1500/1800
group.
FEATURES
• CPU
− 16-bit RISC CPU: nX-U16/100(A35 core)
− Instruction system: 16-bit length instructions
‒ Instruction set: Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations,
bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on
‒ Built-in On-chip debug function
‒ Built-in ISP (In-System Programming) function
‒ Minimum instruction execution time
Approximately 30.5 μs (at 32.768 kHz system clock)
Approximately 62.5ns/41.6ns (at 16 MHz/24MHz system clock)
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FEDL62Q1500-07
• Coprocessor for multiplication and division
− Multiplication
: 16bit × 16bit (operation time : 4 cycles)
− Division
: 32bit ÷ 16bit (operation time : 8 cycles)
− Division
: 32bit ÷ 32bit (operation time : 16 cycles)
− Multiply-accumulate (non-saturating): 16bit × 16bit + 32bit (operation time : 4 cycles)
− Multiply-accumulate (saturating): 16bit × 16bit + 32bit (operation time : 4 cycles)
− Signed or Unsigned is selectable
• Operating voltage and temperature
‒ Operating voltage: VDD = 1.6 to 5.5 V (VDD should be 1.8V or over at Power-on)
‒ Operating temperature: -40 °C to +105 °C
• Internal memory
‒ Program memory area
Rewrite count: 100 cycles
Write unit: 32bit(4byte)
Erase unit: 16Kbyte/1Kbyte
Erase/Write temperature: 0 °C to +40 °C
‒ Data Flash memory area
Rewrite count 10,000 cycles
Write unit: 8bit(1byte)
Erase unit: all area/128byte
Erase/Write temperature: -40 °C to +85 °C
Back Ground Operation(CPU can work while erasing and rewriting)
This product uses Super Flash® technology licensed from Silicon Storage Technology, Inc.
Super Flash® is a registered trademark of Silicon Storage Technology, Inc.
‒ Data RAM area
Rewrite unit: 8bit/16bit (1byte/2byte)
Parity check function is available (interrupt / reset are generatable at Parity error)
• Clock Generation Circuit
‒ Low-speed clock (LSCLK)
Internal low-speed RC oscillation: Approximately 32.768 kHz
External low-speed clock input: Approximately 32.768 kHz
External low-speed crystal oscillation: 32.768 kHz crystal resonator is connectable
3 selectable crystal oscillation mode (Tough, Normal, and Low current consumption)
⋅ Tough mode: Largest oscillation allowance to make highest resistance against leakage between the pins
⋅ Normal mode: Normal oscillation allowance and current consumption
⋅ Low current consumption mode: Smallest oscillation allowance to make lower current consumption
‒ High-speed clock (HSCLK)
PLL oscillation: 2 selectable oscillation frequency (24MHz and 16MHz) by code option
‒ Watch Dog Timer (WDT): built-in independent clock for WDT (RC1K: Approximately 1kHz)
• Reset
‒ Reset by reset input pin
‒ Reset by Power-On Reset
‒ Reset by WDT overflow
‒ Reset by WDT invalid clear
‒ Reset by RAM parity error
‒ Reset by unused ROM area access (instruction access)
‒ Reset by voltage level supervisor (VLS)
‒ Software reset by BRK instruction (reset CPU only)
‒ Reset the peripherals individually
‒ Collective reset to the all control pins and peripheral circuits
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FEDL62Q1500-07
• Power management
‒ HALT mode: CPU stops executing instruction, peripheral circuits continue working
‒ HALT-H mode: CPU stops executing instruction, high-speed clock oscillation stops and peripheral circuits continue
working with low-speed clock
‒ STOP mode: CPU and peripheral circuits stops executing instruction, both high-speed oscillation and low-speed
oscillation stop.
‒ STOP-D mode: CPU and peripheral circuits stops executing instruction, both high-speed oscillation and low-speed
oscillation stop. The internal logic voltage (VDDL) goes down to reduce the current consumption (RAM data is retained).
‒ Clock gear: High-speed system clock frequency can be changed (1/1, 1/2, 1/4, 1/8, 1/16 or 1/32 of HSCLK)
‒ Block Control Function: Powers down the unused function blocks (reset the block or stop supplying the clock)
• Interrupt controller
− External interrupt ports : max 12
− Non-maskable interrupt source: 1 (Internal source: WDT)
− Maskable interrupt sources: max.51
− Four step interrupt levels
• Watchdog timer(WDT)
‒ Selectable Operating clock : select RC1K or LSCLK by code option
‒ Overflow period: 8selectable (7.8ms, 15.6ms, 31.3ms, 62.5ms, 125ms, 500ms, 2s and 8s)
‒ Selectable window function (enable or disable): configurable clear enable period (50% or 75% of overflow period)
‒ Selectable WDT operation : select Enable or Disable by code option
‒ Readable WDT counter : WDT counter monitor function
• DMA(Direct Memory Access) controller
− Channel: 2channel
− Transfer unit: 8bit/16bit
− Transfer count: 1 to 1024
− Transfer cycle: 2 cycle transfer
− Transfer address: Fixed addressing mode, inclement addressing mode, and decrement addressing mode
− Transfer target: Special Function Register (SFR)/RAM SFR/RAM (Transfer from/to Flash is not supported)
− Transfer request: External pins, Serial communication unit, Successive approximation type A/D converter, 16bit timer,
and Functional timer
• Low-speed Time base counter
− Generate 8 frequency (128Hz to1Hz) internal pulse signals by dividing the Low-speed clock (LSCLK)
− Selectable 3 interrupts from eight frequency internal pulse signals
− 1Hz or 2Hz output from general purpose port
− Built-in Frequency adjust function : Adjust range: Approximately -488ppm to +488ppm, adjust resolution:
Approximately 0.119ppm
• Simplified RTC
− Channel: 1channel
− Count by a unit for one second from "00 min. 00 sec" to "59 min. 59 sec"
− Selectable Periodical interrupt request from four periods (0.5s, 1s, 30s or 60s)
− Built-in minute and second writing error protraction function
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FEDL62Q1500-07
• Functional timer
− Channel: Max. 8 channel
− Built-in timer, capture, and PWM function by 16bit counter
− Built-in Repeat mode, One shot mode is available
− Two types of PWM output with the same period and different duties, and complementary PWM output with the dead time
− Monitor input signal duty and the period by capture function
− Generate periodical interrupts, duty interrupts, and interrupts coincided with set value
− Counter Start, Stop, Counter clear triggered by an external inputs or Timer
− Generate Emergency stop and emergency stop interrupt triggered by an external input
− Same start/stop among different channels of the functional timer
− Selectable counter clock (external clock or divided by 1 to 128 of LSCLK or HSCLK) for each channels
• 16-bit General timers
− Channel: Max. 8channel
‒ 8 bits timer mode and 16-bit timer mode
− Same start/stop among different channels of 16bit (8bit) timer
‒ Timer output (toggled by overflow)
− Selectable counter clock (external clock or divided by 1 to 128 of LSCLK or HSCLK) for each channels
• Serial communication unit
− Synchronous Serial Port (SSIO) mode or UART mode is selectable
− Channel: Max. 6channel
< Synchronous Serial Port mode>
‒ Selectable from Master and Slave
‒ Selectable from LSB first or MSB first
‒ Selectable 8-bit length or 16-bit length
< UART mode>
‒ Full-duplex communication mode and half-duplex communication mode
‒ 5 to 8bit length, parity or no parity, odd parity or even parity, 1 stop bit or 2 stop bits
‒ Selectable from Positive logic or Negative logic
‒ Selectable from LSB first or MSB first
‒ Configurable wide range communication speed
32.768kHz operation clock: 1 bps to 4,800 bps
24MHz operation clock: 600 bps to 3 Mbps
16MHz operation clock: 300 bps to 2 Mbps
‒ Built-in baud rate generator
• I2C bus unit (Master / Slave)
‒ Selectable from Master mode or Slave mode
‒ Channel: 1 channel
< Master function >
‒ Standard mode (100 kbps), fast mode (400 kbps) and 1Mbps mode(1Mbps)
‒ Handshake (Clock synchronization)
‒ 7bit address format (10bit address format is supported)
< Slave function >
‒ Standard mode (100 kbps), fast mode (400 kbps) and 1Mbps mode(1Mbp)
‒ Clock stretch function
‒ 7bit address format
• I2C bus Master
‒ Channel: 2channel
‒ Standard mode (100 kbps), fast mode (400 kbps) and 1Mbps mode(1Mbps)
‒ Handshake (Clock synchronization)
‒ 7bit address format (10bit address format is supported)
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FEDL62Q1500-07
• General-purpose ports (GPIO)
‒ I/O port: Max. 92 (Including one pin for on-chip debug and pins for other shared functions)
‒ Input port: Max. 2(Including a shared function)
‒ External interrupt port: Max. 12
‒ LED driver port: Max. 91
‒ Carrier frequency output function (used for IR communication)
• Successive approximation type A/D converter (SA-ADC)
‒ Channel: Max.16channel
‒ Resolution: 10bit
‒ Conversion time: Min. 2.25μs /channel (When the conversion clock speed is 8MHz)
‒ Reference voltages are selectable
(VDD pin / Internal reference voltage (VREFI = Approximately 1.55V) / External reference voltage (VREF pin))
‒ Selected channel repeat conversion
‒ Dedicated result register for each channel
‒ Interrupt determining by upper limit or lower limit threshold of conversion result
• Voltage Level Supervisor (VLS)
‒ Accuracy: ±4%
‒ Threshold voltage: 12 selectable (from 1.85V to 4.00V)
‒ Functional Voltage level detection reset (VLS reset)
‒ Functional Voltage level detection interrupt (VLS0 interrupt)
• Analog comparator
‒ Channel: Max. 2 channel
‒ Selectable interrupt from the comparator output (rising edge or falling edge)
‒ Selectable from sampling or without sampling
‒ Comparable with external 2 inputs
‒ Comparable with external input and internal reference voltage (0.8V)
• D/A converter
‒ Channel: Max. 2 channel
‒ Resolution: 8bit
‒ Output impedance: 6k ohm (Typ.)
‒ R-2R ladder type
• Buzzer
‒ 4 buzzer mode (Continuous sound, Single sound, Intermittent sound 1 and Intermittent sound 2)
‒ 8frequencies (4.096kHz to 293Hz)
‒ 15 step duty (1/16 to 15/16)
‒ Selectable from positive logic buzzer output or negative logic buzzer output
• CRC (Cyclic Redundancy Check) generator
‒ Generation equation: X16+X12+X5+1
‒ Selectable from LSB first or MSB first
‒ Built-in Automatic program memory CRC calculation mode in HALT mode
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FEDL62Q1500-07
• Safety Function (IEC60730/60335 Class B)
‒ Automatic switching to the internal low-speed RC oscillation in case the low-speed crystal oscillation stopped
‒ RAM/SFR guard
‒ Automatic program memory CRC calculation
‒ RAM parity error detection
‒ ROM unused area access reset (instruction access)
‒ Clock mutual monitoring
‒ WDT counter monitoring
‒ SA-ADC test
‒ UART test
‒ Synchronous serial I/O test
‒ I2C bus test
‒ GPIO test
• Shipping package
−
−
−
−
−
−
−
48 pin plastic TQFP
ML62Q1530/1531/1532/1533/1534 - xxxTB
（Blank part: ML62Q1530/1531/1532/1533/1534-NNNTB）
52 pin plastic TQFP
ML62Q1540/1541/1542/1543/1544 - xxxTB
（Blank part: ML62Q1540/1541/1542/1543/1544-NNNTB）
64 pin plastic TQFP
ML62Q1550/1551/1552/1553/1554/1555/1556/1557/1858/1859 - xxxTB
（Blank part: ML62Q1550/1551/1552/1553/1554/1555/1556/1557/1858/1859-NNNTB）
64 pin plastic QFP
ML62Q1550/1551/1552/1553/1554/1555/1556/1557/1858/1859 - xxxGA
（Blank part: ML62Q1550/1551/1552/1553/1554/1555/1556/1557/1858/1859-NNNGA）
80 pin plastic QFP
ML62Q1563/1564/1565/1566/1567 /1868/1869- xxxGA
（Blank part: ML62Q1563/1564/1565/1566/1567/1868/1869-NNNGA）
100 pin plastic TQFP
ML62Q1573/1574/1575/1576/1577/1878/1879 - xxxTB
（Blank part: ML62Q1573/1574/1575/1576/1577/1878/1879-NNNTB）
100 pin plastic QFP
ML62Q1573/1574/1575/1576/1577/1878/1879 - xxxGA
（Blank part: ML62Q1573/1574/1575/1576/1577/1878/1879-NNNGA）
xxx: ROM code number
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FEDL62Q1500-07
ML62Q1500/1800 Group how to read the part number
ML 62 Q 15 7 7 – xxx TB
Package Type
GA
:QFP
TB
:TQFP
ROM Code Number
NNN :Blank
xxx
:Custom Code Number
Program Memory Size
0
:32Kbyte
1
:48Kbyte
2
:64Kbyte
3
:96Kbyte
4
:128Kbyte
5
:160Kbyte
6
:192Kbyte
7
:256Kbyte
8
:384Kbyte
9
:512Kbyte
Pin Count
3
:48pin
4
:52pin
5
:64pin
6
:80pin
7
:100pin
Group Name
15
:1500 Group
18
:1800 Group
Program Memory Type
Q
:Flash Memory
CPU Type
62
:16bit CPU nX-U16/100
LAPIS Technology Logic Product
Figure 1 ML62Q1500/1800 Group Part Number
7/71
FEDL62Q1500-07
ML62Q1500/1800 Group Main Function List
Table 2 ML62Q1500/1800 Group Main Function List
Pin
Interrupt
1
1
1
2
2
4
71
43
92
D/A converter [channel]
2
72
12
57
4
100
2
Analog comparator [input pin]
80
6
Analog comparator [channel]
1
6
Successive approximation type A/D converter
[channel]
58
10
Analog
I2C bus interface (Master only) [channel]
64
31
I2C bus unit (Master/Slave) [channel]
Input pin count*3
Reset Input pin count
Power pin count
3
Serial communication unit
(Full-duplex UART or Synchronous serial) [channel]*2
45
Serial
Simplified RTC [channel]
46
16bit General l Timer [channel]*1
52
Functional Timer [channel]
41
External interrupt [port]
LED drive port (shared with the I/O port)
42
Total pin-count
ML62Q1530
ML62Q1531
ML62Q1532
ML62Q1533
ML62Q1534
ML62Q1540
ML62Q1541
ML62Q1542
ML62Q1543
ML62Q1544
ML62Q1550
ML62Q1551
ML62Q1552
ML62Q1553
ML62Q1554
ML62Q1555
ML62Q1556
ML62Q1557
ML62Q1858
ML62Q1859
ML62Q1563
ML62Q1564
ML62Q1565
ML62Q1566
ML62Q1567
ML62Q1868
ML62Q1869
ML62Q1573
ML62Q1574
ML62Q1575
ML62Q1576
ML62Q1577
ML62Q1878
ML62Q1879
Internal interrupt [source]
I/O pin count
48
Part number
Timer
12
8
8
6
16
2
91
*1 : One 16bit timer is configurable as two 8bit timers
*2 : Synchronous Communication unit includes UART and Synchronous Serial Port. UART mode and Synchronous
Serial Port can not be used at the same time in the same channel.
*3 : Shared with pins for crystal oscillation
8/71
FEDL62Q1500-07
BLOCK DIAGRAM
CPU（nX-U16/100）
EPSW1～3
ELR1～3
ECSR1～3
LR
DSR/CSR
EA
PC
Multiplier/Divider
(Coprocessor)
GREG
0 ～15
PSW
Timing
Controller
ALU
SP
Instruction
Decoder
On-Chip
ICE
Instruction
Register
VDD
VSS
Program
Memory
（FLASH）
BUS
Controller
INT
SU0~5_SCLK*
SU0~5_SIN*
SU0~5_SOUT0*
RAM
VDDL
VREFO *
RESET_N
TEST0* 2
Serial
Communication
Unit *1
Power
Circuit
Data FLASH
SYSTEM
FLASH
Controller
INT
OUTLSCLK*
OUTHSCLK*
Clock
Generation
Circuit
Interrupt
Low-speed
RC
Oscillation
High-speed
PLL
Oscillation
I2C Bus
Unit
I2CU0_SDA*
I2CU0_SCL*
I2C Bus
Master
I2CM0~1_SDA*
I2CM0~1_SCL*
INT
INT
16-Bit
Timer
INT
VLS
RC
Oscillation
(for WDT)
VDD
VSS
VREF
AIN0 to AIN15*
INT
INT
WDT
XT0
XT1
INT
Functional
Timer
DMA
Controller
Low-speed
Crystal
Oscillation
CRC
Generator
INT
SA-ADC
DACOUT0~1*
Analog
Comparator
Low Speed
Time Base
Counter
Simplified
RTC
D/A
Converter
INT
Safety
Function
EXTRIG0～7
FTM0~7P*
FTM0~7N*
INT
INT
INT
TMH0~7OUT*
INT
Buzzer
CMP0~1P*
CMP0~1M*
SU0~5_RXD0*
SU0~5_TXD0*
SU0~5_RXD1*
SU0~5_TXD1*
INT
Reset
Function
GPIO
(External Interrupt)
TBCOUT0*
TBCOUT1*
BZ0P*
BZ0N*
PX0~PX7
（X= 0~9,A,B)
PI00,PI01*3
EXI0~11
* : Indicates the shared function of general ports.
*1 : Shared UART and Synchronous Serial Port.
*2 : Not available as the input port when connecting to the on-chip debug emulator.
*3 : Not available as the input port when connecting to the crystal resonator.
Figure 2 ML62Q1500/1800 Group Block Diagram
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FEDL62Q1500-07
PIN CONFIGURATION
The port names in the pin-layout indicate 1st-function. Refer to Table-3 or Table-4 about other functions.
24
P30
25
37
36
P14
P15
P16
P17/EXI3/EXTRG3
P20
P21/EXI4/EXTRG4
P22
P23/EXI5/EXTRG5/VREF
P24
P25
P26/EXI6/EXTRG6
P27/EXI7/EXTRG7
Pin Layout of 48pin TQFP Package
P50/EXI8
P31
P13
P32
P12
P33
P11
P60
P10
TOP VIEW
TQFP48
P61
P62
P63
P07
P06
P05
P04/EXI2/EXTRG2
P64/EXI9
P71
P66
P72
P43
P73
13
48
P65
P74
P75
P03/EXI1/EXTRG1
P02/EXI0/EXTRG0
P01/DACOUT0
P00/TEST0
RESET_N
VDDL
VSS
VDD
12
XT1/PI01
XT0/PI00
1
Figure 3 Pin Layout of 48pin TQFP Package
10/71
FEDL62Q1500-07
26
P41
27
40
39
P14
P15
P16
P17/EXI3/EXTRG3
P20
P22
P21/EXI4/EXTRG4
P24
P23/EXI5/EXTRG5/VREF
P25
P26/EXI6/EXTRG6
P27/EXI7/EXTRG7
P56
Pin Layout of 52pin TQFP Package
P51
P30
P50/EXI8
P31
P13
P32
P12
P33
P11
P60
P10
TOP VIEW
TQFP52
P61
P62
P07
P06
P05
P63
P64/EXI9
P04/EXI2/EXTRG2
P72
P43
P73
14
P71
P66
52
P65
P74
P75
P47
P02/EXI0/EXTRG0
P03/EXI1/EXTRG1
P00/TEST0
P01/DACOUT0
RESET_N
VDDL
VSS
VDD
13
XT1/PI01
XT0/PI00
1
Figure 4 Pin Layout of 52pin TQFP52 Package
11/71
FEDL62Q1500-07
32
P40
33
49
48
P54
P55
P14
P15
P16
P17/EXI3/EXTRG3
P20
P21/EXI4/EXTRG4
P22
P23/EXI5/EXTRG5/VREF
P24
P26/EXI6/EXTRG6
P25
P27/EXI7/EXTRG7
P56
P57
Pin Layout of 64pin TQFP/QFP Package
P53
P41
P52
P30
P51
P31
P50/EXI8
P32
P13
P33
P12
P60
P11
TOP VIEW
TQFP64/QFP64
P61
P62
P10
P07
P63
P06
P64/EXI9
P05
P70
P67
P71
P42
P72
P43
P73
17
P04/EXI2/EXTRG2
P66
64
P65
P74
P75
P47
P46
P03/EXI1/EXTRG1
P02/EXI0/EXTRG0
P45
P44/DACOUT1
P01/DACOUT0
RESET_N
P00/TEST0
VDDL
VSS
VDD
16
XT1/PI01
XT0/PI00
1
Figure 5 Pin Layout of 64pin TQFP/QFP Package
12/71
P65
P04/EXI2/EXTRG2
P66
P70
P67
P71
P42
P72
P43
P73
21
40
60
1
P74
P75
P76/EXI10
P47
P46
P03/EXI1/EXTRG1
P02/EXI0/EXTRG0
P45
P44/DACOUT1
P61
P82
P60
P81
P33
P80
P01/DACOUT0
P00/TEST0
RESET_N
VDDL
VSS
VDD
XT1/PI01
XT0/PI00
61
PB2
80
NC
VDD
P54
P55
P14
P15
P16
P17/EXI3/EXTRG3
P20
P21/EXI4/EXTRG4
P22
P23/EXI5/EXTRG5/VREF
P24
P25
P26/EXI6/EXTRG6
P27/EXI7/EXTRG7
P56
P57
PA3/EXI11
PA4
FEDL62Q1500-07
Pin Layout of 80pin QFP Package
41
PB3
TOP VIEW
QFP80
P96
P95
PB4
P94
PB5
P93
P40
P53
P41
P30
P52
P51
P31
P50/EXI8
P32
P13
P12
P10
P11
P62
P07
P63
P06
P64/EXI9
P05
20
Figure 6 Pin Layout of 80pin QFP Package
13/71
26
50
75
1
P74
P75
P76/EXI10
P47
P46
P03/EXI1/EXTRG1
P02/EXI0/EXTRG0
P45
P44/DACOUT1
P87
P86
P85
P84
P61
P83
P60
P82
P81
P80
P01/DACOUT0
P00/TEST0
RESET_N
VDDL
VSS
VDD
XT1/PI01
XT0/PI00
P43
76
PB0
100
NC
VDD
PA1
PA2
P54
P55
P14
P15
P16
P17/EXI3/EXTRG3
P20
P21/EXI4/EXTRG4
P22
P23/EXI5/EXTRG5/VREF
P24
P25
P26/EXI6/EXTRG6
P27/EXI7/EXTRG7
P56
P57
PA3/EXI11
PA4
PA5
PA6
PA7
FEDL62Q1500-07
Pin Layout of 100pin TQFP Package
51
PB1
P32
P52
P33
P51
TOP VIEW
TQFP100
PA0
P97
PB2
P96
PB3
P95
PB4
P94
PB5
P93
P40
P92
P41
P91
P30
P90
P31
P53
P50/EXI8
P62
P13
P12
P63
P11
P64/EXI9
P10
P65
P07
P66
P06
P67
P05
P42
P04/EXI2/EXTRG2
PB6
P70
PB7
P71
P77
P72
P73
25
Figure 7 Pin Layout of 100pin TQFP Package
14/71
31
50
80
1
P71
P72
P73
P74
P75
P76/EXI10
P47
P46
P03/EXI1/EXTRG1
P02/EXI0/EXTRG0
P45
P44/DACOUT1
P87
P86
P61
P85
P60
P84
P33
P83
P82
P81
P80
P01/DACOUT0
P00/TEST0
RESET_N
VDDL
VSS
VDD
XT1/PI01
XT0/PI00
P43
P77
PB7
81
PB3
100
P97
PA0
NC
VDD
PA1
PA2
P54
P55
P14
P15
P16
P17/EXI3/EXTRG3
P20
P21/EXI4/EXTRG4
P22
P23/EXI5/EXTRG5/VREF
P24
P25
P26/EXI6/EXTRG6
P27/EXI7/EXTRG7
P56
P57
PA3/EXI11
PA4
PA5
PA6
PA7
PB0
PB1
PB2
FEDL62Q1500-07
Pin Layout of 100pin QFP Package
51
PB4
TOP VIEW
QFP100
P96
P95
PB5
P94
P40
P93
P41
P30
P92
P91
P31
P90
P32
P53
P52
P51
P62
P50/EXI8
P13
P63
P12
P64/EXI9
P11
P65
P10
P66
P07
P67
P06
P42
P05
PB6
P04/EXI2/EXTRG2
P70
30
Figure 8 Pin Layout of 100pin QFP Package
15/71
FEDL62Q1500-07
PIN LIST
Table 3 Pin List (1/3)
Pin No.
QFP100
64Pin
TQFP100
52Pin
3
4
5
1
2
6
7
3
4
5
1
2
6
7
3 3 3 5
VDD
- 42 52 54
VDD
4 4 4 6
VSS
- 41 51 53
NC
5 5 5 7
VDDL
1 1 1 3
XT0
2 2 2 4
XT1
6 6 6 8 RESET_N
7 7 7 9
P00
8 8
th
th
th
th
th
5 func.
Timer
6 func.
Others
7 func.
Others
8 func.
ADC
-
-
-
-
-
-
DACOUT0
-
-
-
-
TBCOUT0
TBCOUT1
-
FTM0P
OUTLSCLK
CMP0M
-
FTM0N
OUTHSCLK
CMP0P
AIN11
I2CU0_SCL TMH0OUT
-
-
-
I2CM0_SDA
SU0_RXD1 SU0_RXD0 I2CM0_SCL
SU0_TXD1
SU0_SCLK
SU0_RXD0
TMH4OUT
SU0_SIN
SU0_TXD0
SU0_TXD1
TMH1OUT
SU0_SOUT
I2CU0_SDA
SU1_SCLK
I2CU0_SCL TMH5OUT
-
-
-
-
-
-
-
TMH3OUT
-
-
-
-
P02
10 10 12 15 20 22
P03
16 17 21 25 30 32
P04
17
18
19
20
21
33
34
35
36
37
P05
P06
P07
P10
P11
EXI0
EXTRG0
EXI1
EXTRG1
EXI2
EXTRG2
-
22 23 27 31 36 38
P12
-
23 24 28 32 37 39
P13
-
25 27 35 45 57 59
26 28 36 46 58 60
27 29 37 47 59 61
P14
P15
P16
28 30 38 48 60 62
P17
EXI3
EXTRG3
29 31 39 49 61 63
P20
-
30 32 40 50 62 64
P21
EXI4
EXTRG4
31 33 41 51 63 65
P22
-
32 34 42 52 64 66
P23
EXI5
EXTRG5
VREF
33 35 43 53 65 67
P24
-
34 36 44 54 66 68
P25
-
35 37 45 55 67 69
P26
36 38 46 56 68 70
P27
31
32
33
34
35
rd
-
9 9 11 14 19 21
26
27
28
29
30
nd
4 func.
3 func.
2 func.
communica communica communica
tions
tions
tions
PI00
PI01
TEST0
P01
22
23
24
25
26
8
Primary
func.
Others
8 10
18
19
20
21
22
8
80Pin
48Pin
Pin name
(Primary
func.)
EXI6
EXTRG6
EXI7
EXTRG7
SU0_RXD0
SU0_SIN
SU0_TXD0
SU0_TXD1 I2CU0_SDA
SU0_SOUT
SU0_SCLK
-
SU0_RXD1 SU0_RXD0
-
FTM1P
TBCOUT0
BZ0P
AIN0
SU0_TXD1
-
FTM1N
TBCOUT1
BZ0N
AIN1
FTM2P
OUTLSCLK
-
AIN2
FTM2N
OUTHSCLK
-
AIN3
-
-
VREFO
-
SU1_RXD0
SU1_SIN
SU1_TXD0
SU1_TXD1 I2CM0_SDA
SU1_SOUT
SU1_SCLK
-
SU1_RXD0
SU1_SIN
SU1_TXD0
SU1_TXD1
SU1_SOUT
I2CM0_SCL TMH2OUT
-
-
-
-
AIN4
-
-
-
-
AIN5
SU1_RXD1 SU1_RXD0 I2CU0_SDA
FTM3P
TBCOUT0
BZ0P
AIN6
SU1_TXD1
FTM3N
TBCOUT1
BZ0N
AIN7
-
I2CU0_SCL
16/71
FEDL62Q1500-07
Table 3 Pin List (2/3)
Pin No.
nd
rd
th
10
13
14
29
30
31
32
33
34
20
23
24
40
41
42
43
57
58
P45
P46
P47
P50
P51
P52
P53
P54
P55
EXI8
-
- 39 47 57 69 71
P56
-
-
P57
-
90
91
92
93
P60
P61
P62
P63
-
45 49 59 75 92 94
P64
EXI9
46 50 60 76 93 95
P65
-
47
15
14
13
12
11
-
51
16
15
14
13
12
-
61
62
20
19
18
17
16
15
-
77
78
24
23
22
21
20
19
18
-
94
95
29
28
27
26
25
24
23
99
96
97
31
30
29
28
27
26
25
1
P66
P67
P70
P71
P72
P73
P74
P75
P76
P77
EXI10
-
-
-
-
9
9 11
P80
-
-
-
-
10 10 12
P81
-
-
-
-
11
-
P82
P83
P84
P85
P86
P87
-
QFP100
DACOUT1
TQFP100
P44
80Pin
9 12 17 19
64Pin
SU1_RXD1 SU1_RXD0
SU1_TXD1
SU5_TXD1
SU3_TXD1
-
52Pin
-
48Pin
Primary
func.
Others
*1
Pin name
(Primary
func)
37
38
39
40
48
41
42
43
44
40
52
51
52
53
54
49
50
63
64
67
68
69
70
65
66
79
80
84
85
86
87
82
83
96
100
86
87
88
89
84
85
98
2
P30
P31
P32
P33
P40
P41
P42
P43
-
-
24
-
11
25
26
-
41
42
43
44
13
16
17
33
34
35
36
43
44
18
21
22
38
39
40
41
55
56
- 48 58 70 72
45
46
47
48
55
56
57
58
71
72
73
74
88
89
90
91
11
12
13
14
15
16
13
14
15
16
17
18
4 func.
3 func.
2 func.
communica communica communica
tions
tions
tions
*1
*1
th
th
th
th
5 func.
Timer
*1
6 func.
Others
7 func.
Others
8 func.
ADC
*1
-
TMH3OUT
-
TBCOUT0
TBCOUT0
TBCOUT1
TBCOUT1
AIN10
SU4_RXD1 SU4_RXD0
-
-
-
-
-
SU4_TXD1
SU4_RXD1
SU4_TXD1
SU2_RXD1
SU2_TXD1
SU2_RXD0
SU2_SIN
SU2_TXD0
SU2_SOUT
SU3_RXD0
SU3_SIN
SU3_TXD0
SU3_SOUT
SU3_SCLK
SU3_RXD1
SU4_RXD0
SU4_SIN
SU4_TXD0
SU4_SOUT
SU4_SCLK
-
SU2_RXD0
-
-
TMH7OUT
-
-
-
-
-
-
-
-
-
AIN12
SU2_TXD1
-
-
-
-
AIN13
-
I2CM1_SCL
I2CM1_SDA
-
FTM4N
FTM4P
-
CMP1P
CMP1M
-
-
-
FTM5P
-
-
-
SU3_TXD1
-
FTM5N
-
-
AIN8
SU3_RXD0
-
-
TMH6OUT
-
-
-
AIN9
-
-
-
-
-
-
-
SU4_TXD1
-
-
-
-
-
-
-
-
-
-
-
SU4_RXD0
*1: The pins of name with DACOUT1, SU2, SU3, SU4, SU5, TMH6, TMH7, AIN12 or AIN13 are not assigned to products of
48/52/64 PIN-packages.
17/71
FEDL62Q1500-07
Table 3 Pin List (3/3)
Pin No.
42 44
43 45
44 46
P90
P91
P92
-
48Pin
52Pin
64Pin
80Pin
QFP100
Primary
func.
Others
TQFP100
Pin name
(Primary
func)
-
-
-
-
-
-
-
37 45 47
P93
-
-
-
-
38 46 48
P94
-
-
-
-
39
40
59
60
-
49
50
51
52
55
56
73
74
75
76
77
78
79
P95
P96
P97
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PB0
PB1
EXI11
-
-
-
-
61 78 80
PB2
-
-
-
-
62 79 81
PB3
-
-
-
-
63
64
-
PB4
PB5
PB6
PB7
-
47
48
49
50
53
54
71
72
73
74
75
76
77
80
81
97
98
82
83
99
100
nd
rd
th
3 func.
4 func.
2 func.
communica communica communica
tions
tions
tions
SU4_RXD0
SU4_SIN
SU4_TXD0
SU4_TXD1
SU4_SOUT
SU4_SCLK
SU2_SCLK
SU5_RXD0
SU5_SIN
SU5_TXD0
SU5_TXD1
SU5_SOUT
SU5_SCLK
SU5_RXD1 SU5_RXD0
-
th
th
th
th
5 func.
Timers
6 func.
Others
7 func.
Others
8 func.
ADC
-
-
-
-
-
-
FTM6P
-
-
-
-
FTM6N
-
-
-
-
FTM7P
FTM7N
-
-
-
AIN14
AIN15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
18/71
FEDL62Q1500-07
PIN DESCRIPTION
Table 4 Pin Description (1/5)
Function
Signal name
-
Pin name
VSS
I/O
-
-
VDD
-
-
VDDL
-
Test
TEST0
P00
I/O
Un used
NC
VREFO
NC
P23
-
RESET_N
RESET_N
I
XT0
XT0
I
Power
System
XT1
OUTLSCLK
OUTHSCLK
General
purpose port
XT1
P02
P21
P03
P22
Description
Logic
Negative power supply pin (-)
Positive power supply pin (+). Connect a capacitor CV
between this pin and VSS.
Power supply pin for internal logic (internal regulator’s
output). Connect a capacitor CL (1μF) between this pin and
VSS.
Input for testing, is used as on-chip debug interface and ISP
function.
P00 is initialized as pull-up input mode by the system reset.
Connect to VSS.
Reference voltage output
Reset input.
Applying “L” level shifts the MCU in system reset mode.
Applying “H” level shifts the CPU in program running mode. Negative
Used for on-chip debug interface and ISP function.
No pull-up resistor is installed.
O
Low speed crystal oscillation pins
Connect 32.768kHz crystal resonator
capacitors between the pin and VSS.
O
Low-speed clock output.
-
O
High-speed clock output.
-
PI00,PI01
XT0,XT1
I
P00
P00
I/O
P01 to P07
P10 to P17
P20 to P27
P30 to P33
P40 to P47
P50 to P57
P60 to P67
P70 to P77
P80 to P87
P90 to P97
PA0 to PA7
PB0 to PB7
P01 to P07
P10 to P17
P20 to P27
P30 to P33
P40 to P47
P50 to P57
P60 to P67
P70 to P77
P80 to P87
P90 to P97
PA0 to PA7
PB0 to PB7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
and
Connect
-
General purpose input.
Not available as general inputs when using the crystal
Positive
resonator.
General purpose I/O port
- High-impedance
- Input with Pull-UP (initial value)
- Input without Pull-UP
Positive
- CMOS output
- N-channel open drain output
Not available to use as I/O pin when using for on-chip debug
interface or ISP function.
Positive
Positive
Positive
Positive
General purpose I/O
Positive
- High-impedance (initial value)
Positive
- Input with Pull-UP
- Input without Pull-UP
Positive
- CMOS output
Positive
- N-channel open drain output
Positive
Positive
Positive
Positive
19/71
FEDL62Q1500-07
Table 4 Pin Description (2/5)
Function
Signal name
SU0_TXD0
SU0_RXD0
SU0_TXD1
SU0_RXD1
SU1_TXD0
SU1_RXD0
SU1_TXD1
SU1_RXD1
UART
SU2_TXD0
SU2_RXD0
SU2_TXD1
SU2_RXD1
SU3_TXD0
SU3_RXD0
SU3_TXD1
SU3_RXD1
SU4_TXD0
SU4_RXD0
SU4_TXD1
SU4_RXD1
SU5_TXD0
Pin name
P03
P13
P02
P07
P12
P17
P03
P10
P13
P20
P07
P17
P22
P25
P21
P24
P26
P32
P22
P25
P27
P33
P26
P32
P57
P54
P56
P55
P57
P54
P65
P64
P67
P42
P65
P67
P81
P94
P44
P52
P80
P93
P45
P53
P81
P94
P44
P52
I/O
PB3
Description
Logic
O
Serial communication unit0 UART0 data output
Positive
I
Serial communication unit0 Full-duplex data input
Serial communication unit0 UART0 data input
Positive
O
Serial communication unit0 Full-duplex data output
Serial communication unit0 UART1 data output
Positive
I
Serial communication unit0 UART1 data input
Positive
O
Serial communication unit1 UART0 data output
Positive
I
Serial communication unit1 Full-duplex data input
Serial communication unit1 UART0 data input
Positive
O
Serial communication unit1 Full-duplex data output
Serial communication unit1 UART1 data output
Positive
I
Serial communication unit1 UART1 data input
Positive
O
Serial communication unit2 UART0 data output
Positive
I
Serial communication unit2 Full-duplex data input
Serial communication unit2 UART0 data input
Positive
O
Serial communication unit2 Full-duplex data output
Serial communication unit2 UART1 data output
Positive
I
O
Serial communication unit2 UART1 data input
Serial communication unit3 UART0 data output
Positive
Positive
I
Serial communication unit3 Full-duplex data input
Serial communication unit3 UART0 data input
Positive
O
Serial communication unit3 Full-duplex data output
Serial communication unit3 UART1 data output
Positive
I
Serial communication unit3 UART1 data input
Positive
O
Serial communication unit4 UART0 data output
Positive
I
Serial communication unit4 Full-duplex data input
Serial communication unit4 UART0 data input
Positive
O
Serial communication unit4 Full-duplex data output
Serial communication unit4 UART1 data output.
Positive
I
Serial communication unit4 UART1 data input
Positive
O
Serial communication unit5 UART0 data output
Positive
20/71
FEDL62Q1500-07
Table 4 Pin Description (3/5)
Function
Signal name
SU5_RXD0
UART
SU5_TXD1
SU5_RXD1
SU0_SIN
SU0_SCLK
SU0_SOUT
SU1_SIN
SU1_SCLK
SU1_SOUT
Synchronous
Serial Port
SU2_SIN
SU2_SCLK
SU2_SOUT
SU3_SIN
SU3_SCLK
SU3_SOUT
SU4_SIN
SU4_SCLK
SU4_SOUT
SU5_SIN
SU5_SCLK
SU5_SOUT
I2CU0_SDA
2
I C Bus
I2CU0_SCL
I2CM0_SDA
Pin name
PB2
PB5
P40
PB3
PB5
P02
P12
P04
P11
P47
P03
P13
P21
P24
P16
P23
P22
P25
P56
PA3
P57
P64
P66
P65
P80
P93
P95
P82
P81
P94
PB2
PB4
PB3
P03
P15
P26
P46
P02
P04
P16
P27
P47
P06
P22
I/O
Description
Logic
I
Serial communication unit5 Full-duplex data input
Serial communication unit5 UART0 data input
Positive
O
Serial communication unit5 Full-duplex data output
Serial communication unit5 UART1 data output.
Positive
I
Serial communication unit5 UART1 data input
Positive
I
Serial communication unit0 Synchronous serial data input
Positive
I/O
Serial communication unit0 Synchronous serial clock I/O
Positive
O
Serial communication unit0 Synchronous serial data output
I
Serial communication unit1 Synchronous serial data input
Positive
I/O
Serial communication unit1 Synchronous serial clock I/O
Positive
O
Serial communication unit1 Synchronous serial data output
Positive
I
I/O
O
I
I/O
O
Serial communication unit2 Synchronous serial data
Serial communication unit2 Synchronous serial clock I/O
Serial communication unit2 Synchronous serial data output
Serial communication unit3 Synchronous serial data input
Serial communication unit3 Synchronous serial clock I/O
Serial communication unit3 Synchronous serial data output
Positive
Positive
Positive
Positive
Positive
Positive
I
Serial communication unit4 Synchronous serial data input
Positive
I/O
Serial communication unit4 Synchronous serial clock I/O
Positive
O
Serial communication unit4 Synchronous serial data output
Positive
I
I/O
O
Serial communication unit5 Synchronous serial data input
Serial communication unit5 Synchronous serial clock I/O
Serial communication unit5 Synchronous serial data output
Positive
Positive
Positive
I/O
I C Unit0 (Master and Salve) Data I/O
N-channel open drain
Connect a pull-up resistor externally
I/O
I C Unit0 (Master and Salve) Clock I/O
N-channel open drain output
Connect a pull-up resistor externally
I/O
I C Master0 Data I/O pin
N-channel open drain output
Connect a pull-up resistor externally
Positive
2
Positive
2
Positive
2
Positive
21/71
FEDL62Q1500-07
Table 4 Pin Description (4/5)
Function
Signal name
I2CM1_SDA
P61
I/O
I2CM1_SCL
P60
I/O
FTM0P
FTM0N
P02
P03
P17
P47
P20
P46
P21
P22
P01
P26
P27
P44
P63
P62
P64
P65
P93
P94
P86
PA3
P87
PA4
P02
P03
P04
P17
P21
P23
P26
P27
P04
P13
P23
P13
P33
P12
P16
P70
P54
P02
P03
O
O
Description
2
I C Master0 Clock I/O
N-channel open drain output
Connect a pull-up resistor externally
2
I C Master1 Data I/O
N-channel open drain output
Connect a pull-up resistor externally
2
I C Master1 Clock I/O
N-channel open drain output
Connect a pull-up resistor externally
Functional Timer0 P output
Functional Timer0 N output
O
Functional Timer1 P output
Positive
O
Functional Timer1 N output
Negative
O
O
Functional Timer2 P output
Functional Timer2 N output
Positive
Negative
O
Functional Timer3 P output
Positive
O
Functional Timer3 N output
Negative
O
O
O
O
O
O
Functional Timer4 P output
Functional Timer4 N output
Functional Timer5 P output
Functional Timer5 N output
Functional Timer6 P output
Functional Timer6 N output
Positive
Negative
Positive
Negative
Positive
Negative
O
Functional Timer7 P output
Positive
O
Functional Timer7 N output
Negative
I
I
I
I
I
I
I
I
O
O
O
Functional Timer event trigger input
Functional Timer event trigger input
Functional Timer event trigger input
Functional Timer event trigger input
Functional Timer event trigger input
Functional Timer event trigger input
Functional Timer event trigger input
Functional Timer event trigger input
16bit General Timer 0 output
16bit General Timer 1 output
16bit General Timer 2 output
Positive
Positive
Positive
O
16bit General Timer 3 output
Positive
O
O
O
O
I
I
16bit General Timer 4 output
16bit General Timer 5 output
16bit General Timer 6 output
16bit General Timer 7 output
16bit Timer trigger input
16bit Timer trigger input
Positive
Positive
Positive
Positive
-
I2CM0_SCL
2
I C Bus
FTM1P
FTM1N
FTM2P
FTM2N
FTM3P
FTM3N
Functional
Timer
(FTM)
FTM4P
FTM4N
FTM5P
FTM5N
FTM6P
FTM6N
FTM7P
FTM7N
EXTRG0
EXTRG1
EXTRG2
EXTRG3
EXTRG4
EXTRG5
EXTRG6
EXTRG7
TMH0OUT
TMH1OUT
TMH2OUT
TMH3OUT
16 bit Timer
TMH4OUT
TMH5OUT
TMH6OUT
TMH7OUT
EXTRG0
EXTRG1
Pin name
P07
P23
I/O
I/O
Logic
Positive
Positive
Positive
Positive
Negative
22/71
FEDL62Q1500-07
Table 4 Pin Description (5/5)
Function
Signal name
TBCOUT0
Low-speed
Time Base
Counter
TBCOUT1
BZ0P
Buzzer
BZ0N
External
Interrupt
Successive
approximation
type
A/D converter
(SA-ADC)
Analog
comparator
D/A converter
EXI0
EXI1
EXI2
EXI3
EXI4
EXI5
EXI6
EXI7
EXI8
EXI9
EXI10
EXI11
VREF
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
AIN11
AIN12
AIN13
AIN14
AIN15
CMP0P
CMP0M
CMP1P
CMP1M
DACOUT0
DACOUT1
Pin name
P01
P17
P26
P31
P43
P01
P20
P27
P31
P43
P17
P26
P20
P27
P02
P03
P04
P17
P21
P23
P26
P27
P50
P64
P76
PA3
P23
P17
P20
P21
P22
P24
P25
P26
P27
P65
P66
P43
P03
P56
P57
PA3
PA4
P03
P02
P62
P63
P01
P44
I/O
Description
Logic
O
The virtual frequency adjustment signal output or The low
speed time base counter output signal
Positive
O
1Hz/2Hz clock output for the Simplified RTC
Positive
O
Buzzer output (positive phase)
Positive
O
Buzzer output (negative phase)
Negative
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
O
O
External Interrupt 0 Input
External Interrupt 1 Input
External Interrupt 2 Input
External Interrupt 3 Input
External Interrupt 4 Input
External Interrupt 5 Input
External Interrupt 6 Input
External Interrupt 7 Input
External Interrupt 8 Input
External Interrupt 9 Input
External Interrupt 10 Input
External Interrupt 11 Input
SA-ADC external reference voltage input
SA-ADC channel 0 input
SA-ADC channel 1 input
SA-ADC channel 2 input
SA-ADC channel 3 input
SA-ADC channel 4 input
SA-ADC channel 5 input
SA-ADC channel 6 input
SA-ADC channel 7 input
SA-ADC channel 8 input
SA-ADC channel 9 input
SA-ADC channel 10 input
SA-ADC channel 11 input
SA-ADC channel 12 input
SA-ADC channel 13 input
SA-ADC channel 14 input
SA-ADC channel 15 input
Comparator input 0 (noninverting input)
Comparator input 0 (inverting input)
Comparator input 1 (noninverting input)
Comparator input 1 (inverting input)
D/A converter 0 output
D/A converter 1 output
-
23/71
FEDL62Q1500-07
TERMINATION OF UNUSED PINS
Table 5 Termination of unused pins
Pin
NC
RESET_N
P00/TEST0
XT0/PI00, XT1/PI01
P01 to P07
P10 to P17
P20 to P27
P30 to P33
P40 to P47
P50 to P57
P60 to P67
P70 to P77
P80 to P87
P90 to P97
PA0 to PA7
PB0 to PB7
pin termination
Connect to VSS.
Connect to VDD
Connect to VDD with initial state (pulled-up input mode)
Open with initial state (Hi-impedance)
Note:
Terminate unused input pins according to the table 5 in order to avoid unexpected through-current
in the pins.
24/71
FEDL62Q1500-07
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(VSS = 0V)
Parameter
Symbol
Condition
Rating
Unit
Power supply voltage 1
VDD
Ta = +25°C
-0.3 to +6.5
V
Power supply voltage 2
VDDL
Ta = +25°C
-0.3 to +2.0
V
Input voltage
VIN
Ta = +25°C
-0.3 to VDD+0.3*
Output voltage
VOUT
Ta = +25°C
“H” level output current
IOUTH
Ta = +25°C
“L” level output current
IOUTL
Ta = +25°C
-0.3 to VDD+0.3*
2
-40*
2
-180*
+40
+180
1
-55 to +150
1pin
Total
1pin
Total
1
V
1
V
mA
mA
Power dissipation
PD
Ta = +25°C
W
Storage temperature
―
°C
TSTG
1
* 6.5V or lower
2
* The current flowing out the LSI through the pin is described in the negative number.
The applicable maximum current is the absolute value.
For example, -1mA means the maximum current 1mA flows out the LSI through the pin.
[Note]
Stresses above the absolute maximum ratings listed in the above table may cause permanent damage to the device.
These are stress ratings only and functional operation of the device at these conditions is not implied.
Recommended Operating Conditions
(VSS = 0V)
Parameter
Symbol
Condition
Range
Unit
Operating temperature (Ambient)
Ta
―
-40 to +105
°C
Operating temperature (Chip-Junction)
Tj
―
-40 to +115
°C
Operating voltage
VDD
fOP
VDDL pin external capacitance
CL
1.6 to 5.5
30k to 4M
30k to 25M
1.0 ±30%
V
Operating frequency (CPU)
―
VDD = 1.6 to 5.5V
VDD = 1.8 to 5.5V
―
Hz
μF
25/71
FEDL62Q1500-07
Thermal characteristics
The maximum chip-junction temperature, Tjmax, may be calculated using the following equation.
𝑇𝑗 𝑚𝑚𝑚 = 𝑇𝑎 𝑚𝑚𝑚 + 𝑃𝐷 𝑚𝑚𝑚 × 𝜃𝑗𝑗
𝑇𝑎 𝑚𝑚𝑚 : maximum ambient temperature
𝑃𝐷 𝑚𝑚𝑚 : LSI maximum power dissipation
: Package junction to ambient thermal resistance
𝜃𝑗𝑗
Design a Mounting board by considering heat radiation such as power dissipation and ambient temperature to satisfy the
recommended conditions.
The following table shows the each package’s thermal resistance for thermal design reference estimated by simulation based
on the PCB (printed circuit board) conditions define as a below.
Parameter
Symbol
Package type
θja
TQFP48
TQFP52
TQFP64
QFP64
QFP80
TQFP100
QFP100
Thermal
resistance
Value
L1
63.6
61.7
63.2
47.2
55.5
48.0
104.7
L2
57.8
56.7
58.2
43.3
51.6
43.3
101.3
Unit
o
C/W
PCB conditions:
PCB name
L1
L2
Unit
PCB size （L / W / T）
114.3 / 76.2 / 1.6
114.3 / 76.2 / 1.6
mm
Number of layer
1
2
layer
Wiring density
60% (top layer)
60%(top and bottom layer)
―
―
Wind condition
No wind (0m/s)
26/71
FEDL62Q1500-07
Current Consumption 1
Product： ML62Q1530, ML62Q1531, ML62Q1532, ML62Q1533, ML62Q1534, ML62Q1540,
ML62Q1541, ML62Q1542, ML62Q1543, ML62Q1544, ML62Q1550, ML62Q1551,
ML62Q1552, ML62Q1553, ML62Q1554
o
Parameter
Symbol
Supply current 0
IDD0
Supply current 1
IDD1
Supply current 2-1
IDD2-1
(VDD=1.6 to 5.5V, VSS =0V, Ta=-40 to +105 C, unless otherwise specified)
Measuri
3
Condition
Min.
Typ.*
Max.
Unit
ng
circuit
Ta = -40 to
―
23
CPU is in STOP-D state.
o
+85 C
Low-speed RC1K/RC32K and
µA
0.8
Ta = -40 to
PLL oscillation are stopped.
―
75
o
+105 C
Ta = -40 to
―
26
CPU is in STOP state.
o
+85 C
Low-speed RC1K/RC32K and
µA
1.0
Ta = -40 to
PLL oscillation are stopped.
―
80
o
+105 C
Low-speed RC32K Oscillating.
*1
CPU is in HALT state . PLL
oscillation is stopped.
Low-speed Crystal Oscillating.
*4
Supply current 2-2
Supply current 3
IDD2-2
IDD3
*1
Ta = -40 to
o
+85 C
―
Ta = -40 to
o
+105 C
―
85
Ta = -40 to
o
+85 C
―
32
35
µA
4.7
µA
3.0
CPU is in HALT state . PLL
oscillation is stopped.
Ta = -40 to
o
+105 C
―
CPU: Running with low-speed
1 2
RC32K oscillation clock* *
PLL oscillation is stopped.
Ta = -40 to
o
+105 C
―
1
85
17
CPU: Running with 16MHz PLL
1 2
Ta = -40 to
oscillating clock* *
Supply current 4
―
IDD4
3.3
o
+105 C
PLL 16MHz is oscillating.
VDD=1.8~5.5V
CPU: Running with 24MHz PLL
1 2
Ta = -40 to
oscillating clock* *
Supply current 5
―
IDD5
4.7
o
+105 C
PLL 24MHz is oscillating.
VDD=1.8~5.5V
1
* LTBC and WDT is operating, Significant bits of BCKCON0-3 and BRECON0-3 registers are all “1”
2
* CPU running in wait mode
3
o
* On the condition of VDD=3.0V, Ta=+25 C
4
* When the noise filter is not used in the low power consumption mode
105
µA
4.5
mA
6.0
27/71
FEDL62Q1500-07
Current Consumption 2
Product： ML62Q1555, ML62Q1556, ML62Q1557, ML62Q1563, ML62Q1564, ML62Q1565, ML62Q1566,
ML62Q1567, ML62Q1573, ML62Q1574, ML62Q1575, ML62Q1576, ML62Q1577
o
Parameter
Supply current 0
Supply current 1
Supply current 2-1
(VDD=1.6 to 5.5V, VSS =0V, Ta=-40 to +105 C, unless otherwise specified)
Measuri
3
Symbol
Condition
Min.
Typ.*
Max.
Unit
ng
circuit
Ta = -40 to
―
55
CPU is in STOP-D state.
o
+85 C
µA
IDD0 Low-speed RC1K/RC32K and
1.0
Ta = -40 to
PLL oscillation are stopped.
―
110
o
+105 C
Ta = -40 to
―
60
CPU is in STOP state.
o
+85 C
µA
IDD1 Low-speed RC1K/RC32K and
1.3
Ta = -40 to
PLL oscillation are stopped.
―
120
o
+105 C
Ta = -40 to
Low-speed RC32K Oscillating.
o
+85 C
CPU is in HALT state (LTBC and
IDD2-1
*1
WDT are operating ). PLL
Ta = -40 to
o
oscillation is stopped.
+105 C
*4
Supply current 2-2
Supply current 3
Low-speed Crystal Oscillating.
CPU is in HALT state (LTBC and
IDD2-2
*1
WDT are operating ). PLL
oscillation is stopped.
IDD3
CPU: Running with low-speed
1 2
RC32K oscillation clock* *
PLL oscillation is stopped.
Ta = -40 to
o
+85 C
―
76
µA
5.5
―
135
―
76
µA
4.5
Ta = -40 to
o
+105 C
―
Ta = -40 to
o
+105 C
―
1
135
20
CPU: Running with 16MHz PLL
1 2
Ta = -40 to
oscillating clock* *
Supply current 4
―
IDD4
5.0
o
+105 C
PLL 16MHz is oscillating.
VDD=1.8~5.5V
CPU: Running with 24MHz PLL
1 2
Ta = -40 to
oscillating clock* *
Supply current 5
―
IDD5
6.8
o
+105 C
PLL 24MHz is oscillating.
VDD=1.8~5.5V
1
* LTBC and WDT is operating, Significant bits of BCKCON0-3 and BRECON0-3 registers are all “1”
2
* CPU running in wait mode
3
o
* On the condition of VDD=3.0V, Ta=+25 C
4
* When the noise filter is not used in the low power consumption mode
150
µA
6.2
mA
8.5
28/71
FEDL62Q1500-07
Current Consumption 3
Product： ML62Q1858, ML62Q1859, ML62Q1868, ML62Q1869, ML62Q1878, ML62Q1879
o
Parameter
Symbol
Supply current 0
IDD0
Supply current 1
IDD1
Supply current 2-1
IDD2-1
(VDD=1.6 to 5.5V, VSS =0V, Ta=-40 to +105 C, unless otherwise specified)
Measuri
3
Condition
Min.
Typ.*
Max.
Unit
ng
circuit
Ta = -40 to
―
57
CPU is in STOP-D state.
o
+85 C
1.2
Low-speed RC1K/RC32K and
µA
Ta = -40 to
PLL oscillation are stopped.
―
140
o
+105 C
Ta = -40 to
―
62
CPU is in STOP state.
o
+85 C
Low-speed RC1K/RC32K and
µA
1.8
Ta = -40 to
PLL oscillation are stopped.
―
150
o
+105 C
Low-speed RC32K Oscillating.
CPU is in HALT state (LTBC
*1
and WDT are operating ). PLL
oscillation is stopped.
Low-speed Crystal Oscillating.
*4
Supply current 2-2
Supply current 3
IDD2-2
IDD3
Ta = -40 to
o
+85 C
―
78
µA
6.0
Ta = -40 to
o
+105 C
―
165
Ta = -40 to
o
+85 C
―
78
CPU is in HALT state (LTBC
*1
and WDT are operating ). PLL
oscillation is stopped.
Ta = -40 to
o
+105 C
―
CPU: Running with low-speed
1 2
RC32K oscillation clock* *
PLL oscillation is stopped.
Ta = -40 to
o
+105 C
―
µA
4.5
1
165
20
CPU: Running with 16MHz PLL
1 2
Ta = -40 to
oscillating clock* *
Supply current 4
―
IDD4
4.0
o
+105 C
PLL 16MHz is oscillating.
VDD=1.8~5.5V
CPU: Running with 24MHz PLL
1 2
Ta = -40 to
oscillating clock* *
Supply current 5
―
5.7
IDD5
o
+105 C
PLL 24MHz is oscillating.
VDD=1.8~5.5V
1
* LTBC and WDT is operating, Significant bits of BCKCON0-3 and BRECON0-3 registers are all “1”
2
* CPU running in wait mode
3
o
* On the condition of VDD=3.0V, Ta=+25 C
4
* When the noise filter is not used in the low power consumption mode
190
µA
5.0
mA
7.0
29/71
FEDL62Q1500-07
Low speed Crystal Oscillation
o
Parameter
Symbol
(VDD=1.6 to 5.5V, VSS =0V, Ta=-40 to +105 C, unless otherwise specified)
Range
Condition
Unit
Min.
Typ.
Max.
Crystal oscillation
fXTL
―
―
32.768
―
kHz
1 2
frequency * *
Crystal oscillation start
TXTL
―
―
―
2
s
time
1
* : The oscillation frequency is determined by the oscillation circuit, crystal resonator and the external capacitance
(CGL/CDL). As those parameters changes depending the crystal resonator, it requires evaluation on the actual PCB
circuit for matching. Ask crystal resonator makers for matching and confirm the oscillation characteristics.
2
* : The quality of oscillation characteristics might be lost, depending on material of PCB, condition of wiring
capacitance or parasitic capacitance on the external circuits. Note for designing the external circuit.
- Make the wires on the external circuit as short as possible.
- Place the crystal resonator and oscillation circuit as close to the MCU as possible and make the wires between
the external capacitance and crystal resonator as short as possible.
- Ensure no signal line flowing big current runs near the oscillation circuit.
- Ensure no signal line runs under and near the oscillation circuit.
- Make ground of external capacitance the same as MCU ground VSS pin and connect them to the ground that
has low variation of current and voltage.
variation.
- The quality of oscillation characteristics might be lost depending on operating environment due to moisture
absorption of PCB and condensation of PCB surface, recommended to have measures such as covering the
oscillation circuit with resin.
Low speed Crystal Oscillation external circuit example
XT0
XT1
VSS
Crystal resonator
(32.768kHz）
CGL
CDL
External Clock Input
o
Parameter
Symbol
Input Frequency
fEXCK
Input pulse width
tEXCKW
(VDD=1.6 to 5.5V, VSS =0V, Ta=-40 to +105 C, unless otherwise specified)
Range
Condition
Unit
Min.
Typ.
Max.
Typ.
Typ.
―
32.768
kHz
-1.0%
+1.0%
1/fEXCK
1/fEXCK
―
―
s
x 0.4
x 0.6
30/71
FEDL62Q1500-07
On-chip Oscillator
Parameter
Symbol
Low-speed RC oscillator
frequency accuracy 1
Without software adjustment
fRCL1
Low-speed RC oscillator
frequency accuracy 2
With software adjustment
fRCL2
PLL oscillation frequency
accuracy 1
Without software adjustment
fPLL1
PLL oscillation frequency
accuracy 2
With software adjustment
fPLL2
PLL oscillation start time
1kHz Low-speed RC oscillator
(for WDT) frequency accuracy
TPLL
fRC1K
(VDD=1.6 to 5.5V, VSS =0V, Ta=−40 to +105οC, unless otherwise specified)
Measur
Condition
Min.
Typ.
Max.
Unit
ing
circuit
Ta= +25°C
Typ.
Typ.
32.768
VDD = 1.8 to 5.5V
-1.0%
+1.0%
Typ.
Ta= -40 to +85°C
Typ.
32.768
VDD = 1.8 to 5.5V
-2.5%
+2.5%
Typ.
Ta= -40 to +105°C
Typ.
32.768
VDD = 1.8 to 5.5V
-3.0%
+3.0%
kHz
Typ.
Typ.
VDD = 1.6 to 1.8V
32.768
-3.5%
-3.5%
Ta= -40 to +85°C
Typ.
Typ.
32.768
VDD = 1.8 to 5.5V
-1.0%
+1.0%
Typ.
Ta= -40 to +105°C
Typ.
32.768
VDD = 1.8 to 5.5V
-1.5%
+1.5%
Typ.
Typ.
1
Ta= -40 to +85°C
16/24
VDD = 1.8 to 5.5V
-2.5%
+2.5%
Ta= -40 to +105°C
Typ.
Typ.
16/24
VDD = 1.8 to 5.5V
-3.0%
+3.0%
Typ.
Typ.
VDD = 1.6 to 1.8V
16/24
MHz
-3.5%
+3.5%
Typ.
Ta= -40 to +85°C
Typ.
16/24
VDD = 1.8 to 5.5V
-1.0%
+1.0%
Typ.
Ta= -40 to +105°C
Typ.
16/24
VDD = 1.8 to 5.5V
-1.5%
+1.5%
VDD = 1.6 to 5.5V
―
―
2
ms
Ta= -40 to +105°C
0.5
1
2.5
kHz
VDD = 1.6 to 5.5V
31/71
FEDL62Q1500-07
Input / Output pin 1
(VDD=1.6 to 5.5V, VSS =0V, Ta=−40 to +105οC, unless otherwise specified)
Parameter
Output voltage1
“H”/”L” level
(P00-P07)
(P10-P17)
(P20-P27)
(P30-P33)
(P40-P47)
(P50-P57)
(P60-P67)
(P70-P77)
(P80-P87)
(P90-P97)
(PA0-PA7)
(PB0-PB7)
Output voltage2
“L” level
(P01-P07)
(P10-P17)
(P20-P27)
(P30-P33)
(P40-P47)
(P50-P57)
(P60-P67)
(P70-P77)
(P80-P87)
(P90-P97)
(PA0-PA7)
(PB0-PB7)
Symbol
Condition
Min.
Typ.
Max.
IOH1=-10mA
VDD≥4.5V
VDD
-1.5
―
―
IOH1=-1mA
VDD≥1.6V
VDD
-0.5
―
―
IOL1=+10mA
VDD≥4.5V
―
―
1.5
IOL1=+1mA
VDD≥1.6V
―
―
0.5
Unit
Measur
ing
circuit
V
2
VOH1
VOL1
VOL2
When N-ch open
drain output
mode is selected
IOL2=+15mA
VDD≥4.5V
―
―
0.7
IOL2=+8mA
VDD≥3.0V
―
―
0.5
IOL2=+3mA
VDD≥2.0V
―
―
0.4
IOL2=+2mA
VDD≥1.6V
―
―
0.4
32/71
FEDL62Q1500-07
Input / Output pin 2
(VDD=1.6 to 5.5V, VSS =0V, Ta=−40 to +105οC, unless otherwise specified)
Parameter
Symbol
“H” level output
6
current1 *
IOH1
“H” level output total
1 4
current * *
IOH3
Condition
―
―
VDD≥1.6V
3 5
-1* *
―
―
VDD≥4.5V
-90*
5
―
―
VDD≥1.6V
-20*
5
―
―
All pin total
(duty≤50%)
VDD≥4.5V
VDD≥1.6V
-180*
5
-40*
―
―
―
―
VDD≥4.5V
―
―
10*
VDD≥1.6V
VDD≥4.5V
VDD≥3.0V
VDD≥2.0V
VDD≥1.6V
―
―
―
―
―
―
―
―
―
―
3
1*
3
15*
3
8*
3
3*
3
2*
VDD≥4.5V
―
―
90
VDD≥3.0V
―
―
40
VDD≥2.0V
―
―
15
VDD≥1.6V
―
―
10
VDD≥4.5V
―
―
180
VDD≥1.6V
―
―
20
VOH=VDD (High impedance mode)
―
―
+1
Total of ‘P00-P07,
P10-P13, P44-P47,
P50-P53, P70-P76,
P80-P87，P90-P97, PA0’
or ‘P14-P17, P20-P27,
P30-P33, P40-P43,
P54-P57 P60-P67,P77,
PA1-PA7，PB0-PB7’
(duty≤50%)
1pin (CMOS output
mode)
“L” level output
6
current2 *
IOL2
1pin (Nch open drain
output mode)
Total of P00-P07,
P10-P13, P44-P47,
P50-P53, P70-P76,
P80-P87, P90-P97, PA0’
or ‘P14~P17, P20-P27,
P30-P33, P40-P43,
P54-P57 P60-P67,P77,
PA1-PA7, PB0-PB7’
(Nch open drain output
mode,duty≤50%)
All pin total
(Nch open drain output
mode,duty≤50%)
Output leak
(P00-P07)
(P10-P17)
(P20-P27)
(P30-P33)
(P40-P47)
(P50-P57)
(P60-P67)
(P70-P77)
（P80-P87）
（P90-P97）
（PA0-PA7）
（PB0-PB7）
IOOH
Max.
-10* *
IOL1
IOL3
Typ.
VDD≥4.5V
1pin
“L” level output
6
current1 *
“L” level output total
2 4
current * *
Min.
3 5
5
Unit
Measuri
ng
circuit
3
mA
3
μA
IOOL
VOL=VSS (High impedance mode)
5
-1*
―
―
33/71
FEDL62Q1500-07
1
* Sink-out current from VDD to the output pin, which can guarantee the device operation.
2
* Sink-in current from the output pin to VSS, which can guarantee the device operation.
3
* Do not beyond total current.
4
* The total current is on the condition of Duty≤50%(same applies to IOH1).
When the duty>50% the total current is calculated by following formula.
Total current = IOL3 x 50/n (When the duty is n%)
When IOL3=100mA and n=80%,
Total current = IOL3 x 50/80 = 62.5mA
Current allowed per 1pin is independent of the duty and specified as IOL1 and IOL2.
Do not apply current larger than Absolute Maximum Ratings.
5
* The current flowing out the LSI through the pin is described in the negative number.
The applicable maximum current is the absolute value.
For example, -1mA means the maximum current 1mA flows out the LSI through the pin.
6
* VOH1, VOL1, and VOL2 are satisfied with this spec.
34/71
FEDL62Q1500-07
Input / Output pin 3
(VDD=1.6 to 5.5V, VSS =0V, Ta=−40 to +105οC, unless otherwise specified)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Input current1
(RESET_N)
IIH1
IIL1
IIL2
V/IIL2
IIH2Z
IIL2Z
VIH1=VDD
VIL1=VSS
*2
VIL2=VSS (pull-up mode)
*2
VIL2=VSS (pull-up mode)
VIH2=VDD (High impedance mode)
VIL2=VSS (High impedance mode)
―
1
-1*
1
-1500*
3.7
―
1
-1*
―
―
1
-300*
10
―
―
1
―
1
-20*
80
1
―
Input current2
(P00/TEST0)
Input current3
(P01-P07)
(P10-P17)
(P20-P27)
(P30-P33)
(P40-P47)
(P50-P57)
(P60-P67)
(P70-P77)
(P80-P87)
(P90-P97)
(PA0-PA7)
(PB0-PB7)
Input current4
(PI00-PI01)
Input voltage1
(RESET_N)
(P01-P07)
(P10-P17)
(P20-P27)
(P30-P33)
(P40-P47)
(P50-P57)
(P60-P67)
(P70-P77)
(P80-P87)
(P90-P97)
(PA0-PA7)
(PB0-PB7)
(PI00-PI01)
Input voltage2
(P00/TEST0)
IIL3
VIL1=VSS (pull-up mode)
*2
-250*
1
-30*
1
-2*
V/IIL3
VIL1=VSS (pull-up mode)
*2
22
100
800
―
1
Unit
Measur
ing
circuit
μA
kΩ
μA
1
IIH3Z
VIH1=VDD (High impedance mode)
―
IIL3Z
VIL1=VSS (High impedance mode)
-1*
1
―
―
IIH4
IIL4
VIH1=VDD
VIL1=VSS
―
1
-1*
―
―
1
―
VIH1
―
0.7
x VDD
―
VDD
VIL1
―
0
―
0.3
x VDD
VIH2
―
0.7
x VDD
―
VDD
VIL2
―
0
―
0.25
x VDD
kΩ
4
μA
V
5
Pin capacitance
(RESET_N)
(P00/TEST0)
(P01-P07)
(P10-P17)
(P20-P27)
(P30-P33)
f = 10kHz
(P40-P47)
―
―
10
pF
―
CPIN
(P50-P57)
Ta = +25°C
(P60-P67)
(P70-P77)
(P80-P87)
(P90-P97)
(PA0-PA7)
(PB0-PB7)
(PI00-PI01)
1
* The current flowing out the LSI through the pin is described in the negative number. The applicable maximum current is the
absolute value. For example, -1mA means the maximum current 1mA flows out the LSI through the pin.
*2
Measurement conditions: Typ. : VDD = 3.0V, Max. : VDD = 1.6V, Min. : VDD = 5.5V
35/71
FEDL62Q1500-07
Synchronous Serial Port
Slave mode
Parameter
SCK input cycle
SCK input pulse width
(VDD=1.8 to 5.5V, VSS =0V, Ta=−40 to +105οC, unless otherwise specified)
Condition
Min.
Typ.
Max.
Unit
2
―
1*
―
―
µs
3
―
0.5 *
―
―
µs
100+
―
―
ns
VDD=2.4 to 5.5V
1
HSCLK* ×3
200+
VDD=1.8 to 5.5V
―
―
ns
1
HSCLK* ×3
1
HSCLK*
―
―
―
ns
x1
80+
―
―
―
ns
1
HSCLK* ×3
Symbol
tSCYC
tSW
SOUT output delay time
tSD
SIN input setup time
tSS
SIN input hold time
tSH
1
* Cycle of high speed clock
2
* Need input cycles of HSCLK x8 or longer
3
* Need input cycles of HSCLK x4 or longer
tSCYC
tSW
tSW
0.7×VDD
SUn_SCLK*
0.3×VDD
tSD
tSD
0.7×VDD
SUn_SOUT*
0.3×VDD
tSS
0.7×VDD
SUn_SIN*
*2
nd
tSH
0.3×VDD
th
to 8 function of port, n=0 to 5
36/71
FEDL62Q1500-07
Master mode
(VDD=1.8 to 5.5V, VSS =0V, Ta=−40 to +105οC, unless otherwise specified)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
1
SCK output cycle
tSCYC
―
―
SCLK*
―
ns
1
1
1
SCLK*
SCLK*
SCLK*
―
ns
tSW
SCK output pulse width
×0.4
×0.5
×0.6
VDD=2.4 to 5.5V
―
―
100
ns
SOUT output delay time
tSD
VDD=1.8 to 5.5V
―
―
160
ns
VDD=2.4 to 5.5V
120
―
―
ns
SIN input setup time
tSS
VDD=1.8 to 5.5V
180
―
―
ns
VDD=2.4 to 5.5V
80
―
―
ns
SIN input hold time
tSH
VDD=1.8 to 5.5V
100
―
―
ns
1
* Clock cycle selected by bit12~8(SnCK4~0) of the serial port n mode register (SIOnMOD)
VDD≥2.4V: min250ns , VDD≥1.8V: min500ns
tSCYC
tSW
tSW
0.7×VDD
SUn_SCLK*
0.3×VDD
tSD
tSD
0.7×VDD
SUn_SOUT*
0.3×VDD
tSS
0.7×VDD
SUn_SIN*
*2
nd
tSH
0.3×VDD
th
to 8 function of port, n=0 to 5
37/71
FEDL62Q1500-07
I2C Bus Interface
Standard Mode (100kbps)
Parameter
(VDD=1.8 to 5.5V, VSS =0V, Ta=−40 to +105οC, unless otherwise specified)
Symbol
Condition
Min.
Typ.
Max.
Unit
SCL clock frequency
fSCL
―
0
―
100
kHz
SCL hold time
(start/restart condition)
tHD:STA
―
4.0
―
―
µs
SCL ”L” level time
tLOW
―
4.7
―
―
µs
SCL ”H” level time
tHIGH
―
4.0
―
―
µs
SCL setup time
(restart condition)
tSU:STA
―
4.7
―
―
µs
SDA hold time
tHD:DAT
―
0
―
―
µs
SDA setup time
tSU:DAT
―
0.25
―
―
µs
SDA setup time
(stop condition)
tSU:STO
―
4.0
―
―
µs
Bus-free time
tBUF
―
4.7
―
―
µs
2
2
2
When using the I C as the master, configure the I C master n mode register(I2MnMOD) and I C bus 0 mode register
(master side, I2UM0MOD) so that meet these specifications.
Start
Condition
Re-start
Condition
Stop
Condition
I2CUn_SDA
I2CMn_SDA
0.7×VDD
0.3×VDD
0.7×VDD
0.3×VDD
I2CUn_SCL
I2CMn_SCL
tHD:STA
tLOW
tHIGH
tSU:STA tHD:STA
tSU:DAT
tHD:DAT
tSU:STO tBUF
n：0 to 1
38/71
FEDL62Q1500-07
Fast Mode (400 kbps)
Parameter
(VDD=1.8 to 5.5V, VSS =0V, Ta=−40 to +105οC, unless otherwise specified)
Symbol
Condition
Min.
Typ.
Max.
Unit
SCL clock frequency
fSCL
―
0
―
400
kHz
SCL hold time
(start/restart condition)
tHD:STA
―
0.6
―
―
µs
SCL ”L” level time
tLOW
―
1.3
―
―
µs
SCL ”H” level time
tHIGH
―
0.6
―
―
µs
SCL setup time
(restart condition)
tSU:STA
―
0.6
―
―
µs
SDA hold time
tHD:DAT
―
0
―
―
µs
SDA setup time
tSU:DAT
―
0.1
―
―
µs
SDA setup time
(stop condition)
tSU:STO
―
0.6
―
―
µs
Bus-free time
tBUF
―
1.3
―
―
µs
2
2
2
When using the I C as the master, configure the I C master n mode register(I2MnMOD) and I C bus 0 mode register
(master side, I2UM0MOD) so that meet these specifications.
Start
Condition
Re-start
Condition
Stop
Condition
I2CUn_SDA
I2CMn_SDA
0.7×VDD
0.3×VDD
0.7×VDD
0.3×VDD
I2CUn_SCL
I2CMn_SCL
tHD:STA
tLOW
tHIGH
tSU:STA tHD:STA
tSU:DAT
tHD:DAT
tSU:STO tBUF
n：0 to 1
39/71
FEDL62Q1500-07
1Mbps Mode
Parameter
(VDD=2.7 to 5.5V, VSS =0V, Ta=−40 to +105οC, unless otherwise specified)
Symbol
Condition
Min.
Typ.
Max.
Unit
SCL clock frequency
fSCL
―
0
―
1000
kHz
SCL hold time
(start/restart condition)
tHD:STA
―
0.26
―
―
µs
SCL ”L” level time
tLOW
―
0.5
―
―
µs
SCL ”H” level time
tHIGH
―
0.26
―
―
µs
SCL setup time
(restart condition)
tSU:STA
―
0.26
―
―
µs
SDA hold time
tHD:DAT
―
0
―
―
µs
SDA setup time
tSU:DAT
―
0.1
―
―
µs
SDA setup time
(stop condition)
tSU:STO
―
0.26
―
―
µs
Bus-free time
tBUF
―
0.5
―
―
µs
2
2
2
When using the I C as the master, configure the I C master n mode register(I2MnMOD) and I C bus 0 mode register
(master side, I2UM0MOD) so that meet these specifications.
Start
Condition
Re-start
Condition
Stop
Condition
I2CU0_SDA
I2CMn_SDA
0.7×VDD
0.3×VDD
0.7×VDD
0.3×VDD
I2CU0_SCL
I2CMn_SCL
tHD:STA
tLOW
tHIGH
tSU:STA tHD:STA
tSU:DAT
tHD:DAT
tSU:STO tBUF
n：0 to 1
40/71
FEDL62Q1500-07
Reset
(VDD=1.6 to 5.5V, VSS =0V, Ta=−40 to +105οC, unless otherwise specified)
Parameter
Reset pulse width
*2
P00 ”H” level setup time
P00 ”H” level hold time
*1
*2
*1
*1
Symbol
Condition
Min.
Typ.
Max.
Unit
PRST
―
2
―
―
ms
tSP00
―
1
―
―
ms
tHP00*1
―
1
―
―
ms
Measur
ing
circuit
1
： except ISP mode. Refer to the User’s manual “25.4 In-System Programing Function” for the timing in ISP mode.
： VDD=1.6V or over at power on.
VIL1
RESET_N
PRST
P00/TEST0
“H” level or “L” level
VIH1
VIL1
*2
“H” level input
tSP00
“H” level or “L” level
tHP00
Note:
RESET_N input shorter pulse than the Reset pulse width (PRST) valid time should be avoided.
The shorter pulse input may cause unexpected behavior.
41/71
FEDL62Q1500-07
Slope of Power supply and Power On Reset
(VSS =0V, Ta=−40 to +105οC, unless otherwise specified)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Power on rising slope
Power on falling slope
Power on reset detection
voltage
SVR
SVF
VPORR
VPORF
―
―
At Power up (rising)
At Power down (falling)
―
―
1.47
1.33
―
―
1.57
1.49
60
2
1.80
1.58
V/ms
V/ms
V
V
PPOR
―
200
―
―
μs
VINIT
At power on
1.8
―
―
V
tCPUI
―
11
16
―
ms
Power on reset minimum
pulse width
Power on voltage
CPU operation start time
(from the release of reset to
the CPU starts to run）
SVR
At Power supply voltage level change
SVR
SVF
SVF
Measur
ing
circuit
1
―
At Power supply restart
SVR
VDD
VINIT
VPORR
VPORF
0V
PPOR
tCPUI
At power on
At Power off
Note:
If a pulse shorter than the Power on reset minimum pulse width is asserted to VDD, it may cause the
MCU malfunction.
Apply prevent measurement such as bypass capacitors or external reset input, and so on.
Start the high-speed clock when the VDD is within the operating voltage.
42/71
FEDL62Q1500-07
VLS
Parameter
Symbol
VVLSR
VVLSF
VVLSR
VVLSF
VVLSR
VVLSF
VVLSR
VVLSF
VVLSR
VVLSF
VVLSR
VLS threshold
2
voltage *
VVLSF
VVLSR
VVLSF
VVLSR
VVLSF
VVLSR
VVLSF
VVLSR
VVLSF
VVLSR
VVLSF
VVLSR
VVLSF
VLS Current
IVLS
(VDD=1.6 to 5.5V, VSS =0V, Ta=−40 to +105οC, unless otherwise specified)
Condition
Measuring
Min.
Typ.
Max.
Unit
1
circuit
VLS0LV *
Rising
3.86
4.06
4.26
00H
Falling
3.84
4.00
4.16
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
Rising
3.57
3.76
3.95
Falling
3.55
3.70
3.85
Rising
2.94
3.11
3.28
Falling
2.92
3.05
3.18
Rising
2.85
3.01
3.17
Falling
2.83
2.95
3.07
Rising
2.75
2.91
3.07
Falling
2.73
2.85
2.97
Rising
2.66
2.81
2.96
Falling
2.64
2.75
2.86
Rising
2.56
2.71
2.86
Falling
2.54
2.65
2.76
Rising
2.46
2.61
2.76
Falling
2.44
2.55
2.66
Rising
2.37
2.51
2.65
Falling
2.35
2.45
2.55
Rising
1.98
2.11
2.24
Falling
1.96
2.05
2.14
Rising
1.89
2.01
2.13
Falling
1.87
1.95
2.03
Rising
1.79
1.91
2.03
Falling
1.77
1.85
1.93
―
50
―
―
V
1
nA
1
* Bit3~Bit0 of voltage level detection circuit 0 level register (VLS0LV).
2
* The Data VSL0LV = 0CH~0FH is not available to use, if the data is specified it will the same spec as that 0BH is
specified.
Analog Comparator
o
(VDD=1.8 to 5.5V, VSS =0V, Ta=-40 to +105 C, unless otherwise specified)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Comparator same
phase input
voltage range
VCMR
―
0.1
―
VDD
-1.5
V
Comparator0
input offset
VCMOF
Ta=+25 C、VDD=5.0V
―
5
―
mV
Comparator
Reference
Voltage
VCMREF
―
0.75
0.8
0.85
V
o
Measuring
circuit
1
43/71
FEDL62Q1500-07
Successive Approximation Type A/D Converter
o
Parameter
Resolution
Overall error
Symbol
nAD
―
(VDD=1.8 to 5.5V, VSS =0V, Ta=-40 to +105 C, unless otherwise specified)
Condition
Min.
Typ.
Max.
Unit
―
―
―
10
bit
1
4.5V≤ Reference voltage* ≤5.5V
-3.5
1.2
3.5
2.7V≤ Reference voltage* ≤5.5V
-4
―
1
-6
―
6
1.8V≤ Reference voltage*
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