ML62Q1712-NNNTBZ0BX

Dear customer LAPIS Semiconductor Co., Ltd. ("LAPIS Semiconductor"), on the 1st day of October, 2020, implemented the incorporation-type company split (shinsetsu-bunkatsu) in which LAPIS established a new company, LAPIS Technology Co., Ltd. (“LAPIS Technology”) and LAPIS Technology succeeded LAPIS Semiconductor’s LSI business. Therefore, all references to "LAPIS Semiconductor Co., Ltd.", "LAPIS Semiconductor" and/or "LAPIS" in this document shall be replaced with "LAPIS Technology Co., Ltd." Furthermore, there are no changes to the documents relating to our products other than the company name, the company trademark, logo, etc. Thank you for your understanding. LAPIS Technology Co., Ltd. October 1, 2020 FEDL62Q1700-01 Issue Date: May 24, 2019 ML62Q1700 Group 16-bit micro controller GENERAL DESCRIPTION ML62Q1700 Group is a high performance CMOS 16-bit microcontroller equipped with an 16-bit CPU nX-U16/100 and integrated with program memory(Flash memory), data memory(RAM), data Flash and rich peripheral functions such as the multiplier/divider, CRC operator, DMA controller, clock generator, Simplified RTC, timer, UART, synchronous serial port, I2C bus interface unit, buzzer, Voltage Level Supervisor(VLS), successive approximation type A/D converter, D/A converter , analog comparator, LCD driver, safety function(IEC60730/60335 Class B) and etc. The CPU nX-U16/100 is capable of efficient instruction execution in 1-instruction 1-clock mode by pipeline architecture parallel processing. The built-in on-chip debug function enables debugging and programming the software. Also, ISP(In-System Programming) function supports the Flash programming in production line. The ML62Q1700 Group has seven packages (48pin - 100pin) and ten kinds of memory sizes(32Kbyte - 512Kbyte). Table 1 ML62Q1700 Group Product List Program memory 512Kbyte 384Kbyte Data memory (RAM) Data Flash 32Kbyte 8Kbyte 256Kbyte 192Kbyte 16Kbyte 160Kbyte 128Kbyte 96Kbyte 32Kbyte 52pin TQFP52 64pin QFP64 TQFP64 80pin QFP80 100pin QFP100 TQFP100 － － ML62Q1729 ML62Q1739 ML62Q1749 － － ML62Q1728 ML62Q1738 ML62Q1748 － － ML62Q1727 ML62Q1737 ML62Q1747 － － ML62Q1726 ML62Q1736 ML62Q1746 － － ML62Q1725 ML62Q1735 ML62Q1745 16Kbyte － － － ML62Q1734 ML62Q1744 8Kbyte ML62Q1704 ML62Q1714 ML62Q1724 － － 16Kbyte 8Kbyte 64Kbyte 48Kbyte 48pin TQFP48 8Kbyte 4Kbyte － － － ML62Q1733 ML62Q1743 ML62Q1703 ML62Q1713 ML62Q1723 － － ML62Q1702 ML62Q1712 ML62Q1722 － － ML62Q1701 ML62Q1711 ML62Q1721 － － ML62Q1700 ML62Q1710 ML62Q1720 － － FEATURES • CPU − 16-bit RISC CPU Q;8$FRUH − Instruction system: 16-bit length instruction ‒ Instruction set: Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on ‒ On-chip debug function built-in (supported by LAPIS on-chip debug emulator EASE1000) ‒ ISP (In-System Programming) function built-in ‒ Minimum instruction execution time 30.5 μs (at 32.768 kHz system clock) 62.5ns/41.6ns (at 16 MHz/24MHz system clock) 1/71 FEDL62Q1700-01 • Coprocessor for multiplication and division − Multiplication: 16bit × 16bit (operation time 4 cycles) − Division: 32bit / 16bit (operation time 8 cycles) − Division: 32bit / 32bit (operation time 16 cycles) − Multiply-accumulate (non-saturating): 16bit × 16bit + 32bit (operation time 4 cycles) − Multiply-accumulate (saturating): 16bit × 16bit + 32bit (operation time 4 cycles) • Operating voltage and temperature ‒ Operating voltage: VDD = 1.6 to 5.5 V （Need 1.8V or higher at the power on） ‒ Operating temperature: -40 to +105 °C • Internal memory ‒ Program Flash memory area Rewrite count: 100 cycles Rewrite unit: 32bit(4byte) Erase unit: 16Kbyte/1Kbyte Erase/Rewrite temperature: 0°C to +40°C ‒ Data Flash memory area Rewrite count 10,000 cycles Rewrite unit: 8bit(1byte) Erase unit: all area/128byte Erase/Rewrite temperature: -40°C to +85°C Back Ground Operation(BGO) : CPU can work while erasing and rewriting. This product uses Super Flash® technology licensed from Silicon Storage Technology, Inc. Super Flash® is a registered trademark of Silicon Storage Technology, Inc. ‒ Data RAM area Rewrite unit: 8bit/16bit(1byte/2byte) Parity check function (Parity error reset or interrupt is generatable) • Clock ‒ Low-speed clock Internal low-speed RC oscillation: Approx.32.768 kHz External low-speed crystal oscillation: 32.768 kHz crystal resonator is connectable 3 modes is available for the crystal oscillation ⋅ Tough mode: Largest oscillation allowance to make highest resistance against leakage between the pins ⋅ Standard mode: Standard oscillation allowance and current consumption ⋅ Low power current mode: Smaller oscillation allowance than standard mode to make lower current consumption ‒ High-speed clock PLL oscillation: 24MHz/16MHz is selectable by code option ‒ WDT(Watch Dog Timer) clock Internal low-speed RC oscillation: Approx. 1kHz The WDT independent clock or the divided clock of internal low-speed clock is selectable by the code option. • Reset ‒ RESET_N pin reset ‒ Reset by power-on detection ‒ Reset by the 2nd watchdog timer (WDT) overflow ‒ Reset by WDT counter clear during the clear invalid period ‒ Reset by RAM parity error ‒ Reset by unused ROM access ‒ Reset by voltage level detection (VLS) ‒ The software reset by BRK instruction (reset CPU only) ‒ Reset to the peripheral circuits by Block Reset Control Registers (BRECON 0 to 3) ‒ One-time reset to the all peripheral circuits by Software Reset Control Register (SOFTRCON) 2/71 FEDL62Q1700-01 • Power management ‒ HALT mode: CPU stops executing instruction, clock oscillations and peripheral circuits remain previous states ‒ HALT-H mode: CPU stops executing instruction, high-speed clock oscillation stops and peripheral circuits working with low-speed clock remain previous states ‒ STOP mode: CPU stops executing instruction, both high-speed oscillation and low-speed oscillation stop. ‒ STOP-D mode: CPU stops executing instruction, both high-speed oscillation and low-speed oscillation stop. The internal regulator’s output voltage (VDDL) goes down to reduce the current consumption. ‒ Clock gear: The frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, 1/8, 1/16 or 1/32 of the oscillation clock) ‒ Block Control Function: Powers down the circuits of unused function blocks (reset the block or stop supplying the clock) • Interrupt controller − Non-maskable interrupt source: 1 (Internal sources: WDT) − Maskable interrupt sources: max.51 (Internal sources: max.42, External sources: 9) − Four step interrupt levels − External interrupt ports : max 12 • Watchdog timer(WDT) ‒ Operating clock is selectable (1kHz WDT independent clock or divided clock of internal 32.768kHz RC oscillation) ‒ Overflow period: 8 types selectable (7.8ms, 15.6ms, 31.3ms, 62.5ms, 125ms, 500ms, 2000ms and 8000ms@32.768kHz) ‒ Enabling or disabling the window function is selectable (The clear enable period is 50% or 75% of overflow period) ‒ WDT operation is selectable by code option (Enable or Disable) ‒ Readable WDT counter (WDT counter monitor function) ‒ The first overflow generates the WDT interrupt, and the second overflow generates the WDT reset when the counter clear enable period is 100% of overflow period. ‒ The first overflow generates the WDT reset when the counter clear enable period is 50% or 75% of overflow period. ‒ The invalid clear reset generated when the WDT counter is cleared out of the WDT counter clear enable period. • DMA(Direct Memory Access) controller − Channel: 2ch − Transfer unit: 8bit/16bit − Max. transfer count: 1024 time − Transfer type: 2 cycle transfer − Transfer mode: Single transfer mode Fixed address, address increments and address decrements − Transfer target: SFR/RAM  SFR/RAM (Transfer from/to Flash is not supported) − Transfer request: Serial communication units, A/D, 16-bit timers, Functional timers and External interrupts. • Low-speed Time base counter − Divide the Low-speed clock(LSCLK) and generate 128Hz~1Hz internal pulse signals − Periodical interrupt × 3 selectable from 8 frequencies (128Hz, 64Hz, 32Hz, 16Hz, 8Hz, 4Hz, 2Hz and 1Hz) − The time base clock output (1Hz or 2Hz) from general purpose ports (TBCOUT0, TBCOUT1). − Built-in frequency adjustment function (adjustment range: approx.-488ppm ~ +488ppm, adjustment resolution: approx.0.119ppm) • Simplified RTC − Channel: 1ch − Count by one second from “00 min. 00 sec” to “59 min. 59 sec” − One interrupt occurrence is selectable from four periodical interrupt requests (0.5sec, 1sec, 30sec or 60sec) − Protect function for incorrect writing the minutes and second. 3/71 FEDL62Q1700-01 • Functional timer(FTM) − Channel: Max. 8ch − 5HSHDWPRGH2QHVKRWPRGH, Capture mode, PWM mode1 and PWM mode 2(complementary output) − Same start/stop is available with different channels (This function is not available with 16-bit timer) − Event trigger (external interrupts, analog comparators, 16-bit timers and Functional timers) − DeDGWLPHLVJHQHUDWDEOH − Available to specify division ratio of counter clock channel by channel • 16-bit timers − Channel: Max. 8ch ‒ 8-bits timer mode and 16-bit timer mode (1ch 16-bit timer is configurable as 2ch 8-bit timer) − Same start/stop is available with different channels (This function is not available with Functional Timer) ‒ Timer output (toggled by overflow) − Available to specify division ratio of counter clock channel by channel • Serial communication unit − Channel: Max. 6ch − Synchronous Serial Port or UART is selectable in each channel < Synchronous Serial Port > ‒ Master/slave selectable ‒ LSB first/MSB first selectable ‒ 8-bit length/16-bit length selectable < UART > ‒ Full-duplex communication x 2ch(One Full-duplex UART is configurable as two half-duplex UARTs) ‒ 5~8 bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits ‒ Positive logic/negative logic selectable ‒ LSB first/MSB first selectable ‒ Wide range of communication speed 32.768kHz operation clock : 1bps to 4,800bps 24MHz operation clock : 600bps to 3Mbps 16MHz operation clock : 300bps to 2Mbps ‒ Internal baud rate generator • I2C bus interface unit (Master/Slave) ‒ Channel: 1ch ‒ Master or Slave mode is selectable < Master function > ‒ Standard mode (100 kbit/s), fast mode (400 kbit/s) and 1Mbps mode(1Mbit/s) ‒ Handshake (Clock synchronization) ‒ 7bit address format (10bit address format is supported) < Slave function > ‒ Standard mode (100 kbit/s), fast mode (400 kbit/s) and 1Mbps mode(1Mbit/s) ‒ Clock stretch function ‒ 7bit address format • I2C bus interface (Master only) ‒ Channel: 2ch ‒ Standard mode (100 kbit/s), fast mode (400 kbit/s) and 1Mbps mode(1Mbit/s) ‒ Handshake (Clock synchronization) ‒ 7bit address format (10bit address format is supported) 4/71 FEDL62Q1700-01 • General-purpose ports (GPIO) ‒ I/O port: Max. 87 (Including one pin for on-chip debug and pins for other shared functions) ‒ Input port: Max. 2(Including a shared function) ‒ External interrupt function × 12 ‒ LED driver port : Max. 86 ‒ Carrier frequency output function (used for IR communication) • Successive approximation type A/D converter ‒ Channel: Max.16ch ‒ Resolution: 10bit ‒ Conversion time: Selectable 2.25μs (min) /channel (When the conversion clock is 8MHz) ‒ VDD, Internal reference voltage(Approx. 1.55V) or External reference voltage (VREF pin) is selectable. ‒ Scan function (repeat conversion) ‒ One result register for each channel ‒ Interrupt by threshold of conversion result ‒ Temperature sensor for low-speed RC oscillation adjustment • Voltage level supervisor (VLS) ‒ Accuracy: ±4% ‒ Threshold voltage: 12 values selectable (1.85V ~ 4.00V) ‒ Voltage level detection reset (VLS reset) ‒ Voltage level detection interrupt (VLS0 interrupt) • Analog comparator ‒ Channel: 2ch ‒ Interrupts allow edge selection and sampling selection ‒ An external or an internal reference voltage is selectable • D/A converter ‒ Channel: Max 2ch ‒ Resolution: 8bit ‒ Output impedance: 6k ohm(Typ.) ‒ R-2R ladder method • Buzzer ‒ 4 buzzer mode (Repeat sound, Single sound, Intermittent sound 1 and Intermittent sound 2) ‒ 8frequencies (4.096kHz to 293Hz) ‒ 15 step duty (1/16 to 15/16) ‒ Selectable the logic of buzzer output pin (Positive or Negative logic) • CRC(Cyclic Redundancy Check) operation function ‒ Generation equation: X16+X12+X5+1 ‒ LSB first or MSB first is selectable ‒ Automatic CRC mode: Automatic CRC calculation with data of program memory in HALT mode • LCD driver ‒ Max. 480 dots (60seg x 8 com) *1 ML62Q1700/1701/1702/1703/1704： 24seg×8com (com Max.), 29seg×3com (seg Max.) ML62Q1710/1711/1712/1713/1714： 27seg×8com (com Max.), 32seg×3com (seg Max.) ML62Q1720/1721/1722/1723/1724/ 1725/1726/1727/1728/1729： 35seg×8com (com Max.), 40seg×3com (seg Max.) ML62Q1733/1734/1735/1736/1737/1738/1739： 45seg×8com (com Max.), 50seg×3com (seg Max.) ML62Q1743/1744/1745/1746/1747/1748/1749： 60seg×8com (com Max.), 65seg×3com (seg Max.) *1 : Five pins are shared for common or segment, selectable by setting a SFR ‒ 1/3 bias (built-in bias generation circuit) ‒ Frame frequency (Approx. 32Hz，38Hz，64Hz，75Hz，128Hz and 150Hz) ‒ Four bias generation modes (Internal voltage boost, Internal capacitive voltage divide, External supply voltage/capacitive divide, and External supply voltages) ‒ Contrast adjustment (32 steps) is available in the Internal voltage boost mode. 5/71 FEDL62Q1700-01 • Safety Function (IEC60730/60335 Class B) ‒ Automatic switchLQJ to the LQWHUQDOlow-speed RC oscillation LQFDVHWKHORZVSHHGFU\VWDORVFLOODWLRQVWRSSHG ‒ RAM/SFR guard ‒ Automatic CRC calculation with data of program memory ‒ RAM parity error detection ‒ ROM unused area access reset ‒ Clock mutual check ‒ WDT counter check ‒ Successive approximation type A/D converter test ‒ UART test ‒ Synchronous serial test ‒ I2C test ‒ General port test • Shipping package − − − − − − − 48-pin plastic TQFP ML62Q1700/1701/1702/1703/1704 - xxxTB （Blank part: ：ML62Q1700/1701/1702/1703/1704-NNNTB） 52-pin plastic TQFP ML62Q1710/1711/1712/1713/1714 - xxxTB （Blank part: ML62Q1710/1711/1712/1713/1714-NNNTB） 64-pin plastic TQFP ML62Q1720/1721/1722/1723/1724/1725/1726/1727/1728/1729 - xxxTB （Blank part: ML62Q1720/1721/1722/1723/1724/1725/1726/1727/1728/1729-NNNTB） 64-pin plastic QFP ML62Q1720/1721/1722/1723/1724/1725/1726/1727/1728/1729 - xxxGA （Blank part: ML62Q1720/1721/1722/1723/1724/1725/1726/1727/1728/1729-NNNGA） 80-pin plastic QFP ML62Q1733/1734/1735/1736/1737/1738/1739- xxxGA （Blank part: ML62Q1733/1734/1735/1736/1737/1738/1739-NNNGA） 100-pin plastic TQFP ML62Q1743/1744/1745/1746/1747/1748/1749 – xxxTB （Blank part: ML62Q1743/1744/1745/1746/1747/1748/1749-NNNTB） 100-pin plastic QFP ML62Q1743/1744/1745/1746/1747/1748/1749 - xxxGA （Blank part: ML62Q1743/1744/1745/1746/1747/1748/1749-NNNGA） xxx: ROM code number 6/71 FEDL62Q1700-01 ML62Q1700 Group how to read the part number ML 62 Q 17 4 7 – xxx TB Package Type GA :QFP TB :TQFP ROM Code Number NNN :Blank xxx :Custom Code Number Program Memory Size 0 :32Kbyte 1 :48Kbyte 2 :64Kbyte 3 :96Kbyte 4 :128Kbyte 5 :160Kbyte 6 :192Kbyte 7 :256Kbyte 8 :384Kbyte 9 :512Kbyte Pin Count 0 :48pin 1 :52pin 2 :64pin 3 :80pin 4 :100pin Group Name 17 :1700 Group Program Memory Type Q :Flash Memory CPU Type 62 :16bit CPU nX-U16/100 LAPIS Semiconductor Logic Product Figure 1 ML62Q1700 Group Part Number 7/71 FEDL62Q1700-01 ML62Q1700 Group Main Function List Table 2 ML62Q1700 Group Main Function List Pin LCD drive pin 2 12 8bit D/A converter [ch] Analog comparator [input pin] Analog comparator [ch] 2 10bit Successive type A/D converter [ch] I C bus interface (Master only) [ch] 2 3 5 1 1 1 2 2 4 45 43 12 87 86 Analog 35 5 67 66 I C bus unit (Master/Slave) [ch] 2 Serial Full-duplex UART or Synchronous serial 2 [ch] * 1 6 1 53 52 6 Simplified RTC [ch] 31 10 16-bit Timer [ch] * 27 Timer Functional Timer [ch] 41 40 External interrupt [port] 24 Internal interrupt [source] 5 37 36 LCD bias pin *5 LCD segment pin * *4 *5 LCD common pin LED drive port I/O port 3 Input port * Reset Input pin Power pin counts Total pin-counts ML62Q1700 ML62Q1701 ML62Q1702 48 ML62Q1703 ML62Q1704 ML62Q1710 ML62Q1711 ML62Q1712 52 ML62Q1713 ML62Q1714 3 ML62Q1720 ML62Q1721 ML62Q1722 ML62Q1723 ML62Q1724 64 ML62Q1725 ML62Q1726 ML62Q1727 ML62Q1728 ML62Q1729 ML62Q1733 ML62Q1734 ML62Q1735 ML62Q1736 80 ML62Q1737 ML62Q1738 ML62Q1739 4 ML62Q1743 ML62Q1744 ML62Q1745 ML62Q1746 100 ML62Q1747 ML62Q1748 ML62Q1749 LCD common/segment shared pin Part number Interrupt 8 8 6 16 2 60 *1 : One 16bit timer is configurable as two 8bit timers *2 : Full-duplex UART and Synchronous Serial Port can not be used simultaneously in the same channel. One Full-duplex UART is configurable as two half-duplex UARTs. *3 : Shared with pins for crystal oscillation *4 : The LCD common/segment shared pins are shared for common or segment, selectable by setting a SFR *5 : All LCD drive pins are shared with general purpose I/O ports. 8/71 FEDL62Q1700-01 BLOCK DIAGRAM CPU（nX-U16/100） EPSW1～3 GREG 0 ～15 PSW Timing Controller ALU ELR1～3 ECSR1～3 LR DSR/CSR EA PC Multiplier/Divider (Coprocessor) SP Instruction Decoder On-Chip ICE Instruction Register VDD VSS Program Memory （FLASH） BUS Controller SU0~5_SCLK* SU0~5_SIN* SU0~5_SOUT0* INT RAM VDDL VREFO * Power Circuit RESET_N TEST0* 2 TEST Data FLASH FLASH Controller INT OUTLSCLK* OUTHSCLK* Clock Generation Circuit Interrupt Low-speed RC Oscillation WDT CMP0~1P* CMP0~1M* INT Low-speed Crystal Oscillation A/D Converter INT INT VL1,VL2,VL3 C 1,C 2 I2CM0~1_SDA* I2CM0~1_SCL* Functional Timer INT Low Speed Time Base Counter Simplified RTC Buzzer Safety Function D/A Converter LCD Bias I2C Bus Master INT Analog Comparator INT DACOUT0~1* I2CU0_SDA* I2CU0_SCL* INT DMA Controller CRC Generator INT I2C Bus Unit 16-Bit Timer VLS Reset Function SU0~5_RXD0* SU0~5_TXD0* SU0~5_RXD1* SU0~5_TXD1* INT INT RC Oscillation (for WDT) VDD VSS VREF AIN0 to AIN15* INT INT High-speed PLL Oscillation XT0* 3 XT1* 3 Serial Communication Unit *1 INT GPIO (External Interrupt) TMH0~7OUT* EXTRIG0～7 FTM0~7P* FTM0~7N* TBCOUT0* TBCOUT1* BZ0P* BZ0N* PX0~PX7 （X= 0~9,A,B) PI00,PI01 EXI0~11 COM0~COM2 COM3~COM7/ SEG0~SEG4 SEG5~SEG64 LCD Driver * : Indicates the shared function of general ports. 1 * : One channel Full-duplex UART is configurable as two channel Half-duplex UART. 2 * : Not available as the input port when connecting to the on-chip debug emulator(EASE1000). 3 * : Not available as the input port when connecting to the crystal resonator. Figure 2 ML62Q1700 Group Block Diagram 9/71 FEDL62Q1700-01 PIN CONFIGURATION The pin names in the pin-layout indicate 1st-function or LCD function. Refer to Table-3 or Table-4 about other functions. 24 P30/SEG49 25 37 36 P14/SEG22 P15/SEG23 P16/SEG24 P17/EXI3/EXTRG3/SEG25 P20/SEG26 P21/EXI4/EXTRG4/SEG27 P22/SEG28 P23/EXI5/EXTRG5/SEG29 P24/SEG30 P25/SEG31 P26/EXI6/EXTRG6/SEG32 P27/EXI7/EXTRG7/SEG33 Pin Layout of 48pin TQFP Package P50/EXI8/SEG5 P31/SEG50 P13/COM7/SEG4 P32/SEG51 P12/COM6/SEG3 P33/SEG52 P11/COM5/SEG2 P60/SEG53 P10/COM4/SEG1 TOP VIEW TQFP48 P61/SEG54 P62/SEG55 P63/SEG56 P07/COM3/SEG0 P06/COM2 P05/COM1 P04/EXI2/EXTRG2/COM0 P64/EXI9/SEG57 P66/SEG59 VL2 P43 VL1 13 VL3 48 P65/SEG58 C2 C1 P03/EXI1/EXTRG1 P02/EXI0/EXTRG0 P01/DACOUT0 P00/TEST0 RESET_N VDDL VSS VDD 12 XT1/PI01 XT0/PI00 1 Figure 3 Pin Layout of 48pin TQFP Package 10/71 FEDL62Q1700-01 26 P41/SEG48 27 40 39 P14/SEG22 P15/SEG23 P16/SEG24 P17/EXI3/EXTRG3/SEG25 P20/SEG26 P21/EXI4/EXTRG4/SEG27 P22/SEG28 P23/EXI5/EXTRG5/SEG29 P24/SEG30 P25/SEG31 P26/EXI6/EXTRG6/SEG32 P27/EXI7/EXTRG7/SEG33 P56/SEG34 Pin Layout of 52pin TQFP Package P51/SEG6 P30/SEG49 P50/EXI8/SEG5 P31/SEG50 P13/COM7/SEG4 P32/SEG51 P12/COM6/SEG3 P33/SEG52 P11/COM5/SEG2 P60/SEG53 P10/COM4/SEG1 TOP VIEW TQFP52 P61/SEG54 P62/SEG55 P07/COM3/SEG0 P06/COM2 P63/SEG56 P05/COM1 P64/EXI9/SEG57 P04/EXI2/EXTRG2/COM0 VL2 P43 VL1 14 VL3 P66/SEG59 52 P65/SEG58 C2 C1 P47 P03/EXI1/EXTRG1 P02/EXI0/EXTRG0 P01/DACOUT0 P00/TEST0 RESET_N VDDL VSS VDD 13 XT1/PI01 XT0/PI00 1 Figure 4 Pin Layout of 52pin TQFP52 Package 11/71 FEDL62Q1700-01 32 P40/SEG47 33 49 48 P54/SEG20 P55/SEG21 P14/SEG22 P15/SEG23 P16/SEG24 P17/EXI3/EXTRG3/SEG25 P20/SEG26 P21/EXI4/EXTRG4/SEG27 P22/SEG28 P23/EXI5/EXTRG5/SEG29 P24/SEG30 P25/SEG31 P26/EXI6/EXTRG6/SEG32 P27/EXI7/EXTRG7/SEG33 P56/SEG34 P57/SEG35 Pin Layout of 64pin TQFP/QFP Package P53/SEG8 P41/SEG48 P52/SEG7 P30/SEG49 P51/SEG6 P31/SEG50 P50/EXI8/SEG5 P32/SEG51 P13/COM7/SEG4 P33/SEG52 P12/COM6/SEG3 P60/SEG53 P11/COM5/SEG2 TOP VIEW TQFP64/QFP64 P61/SEG54 P62/SEG55 P63/SEG56 P10/COM4/SEG1 P07/COM3/SEG0 P06/COM2 P64/EXI9/SEG57 P05/COM1 P04/EXI2/EXTRG2/COM0 P66/SEG59 P70 P67/SEG60 VL3 P42/SEG61 VL2 P43 VL1 17 64 P65/SEG58 C2 C1 P47 P46 P03/EXI1/EXTRG1 P02/EXI0/EXTRG0 P45 P44/DACOUT1 P01/DACOUT0 P00/TEST0 RESET_N VDDL VSS VDD 16 XT1/PI01 XT0/PI00 1 Figure 5 Pin Layout of 64pin TQFP/QFP Package 12/71 FEDL62Q1700-01 40 PB2/SEG43 41 61 60 NC VDD P54/SEG20 P55/SEG21 P14/SEG22 P15/SEG23 P16/SEG24 P17/EXI3/EXTRG3/SEG25 P21/EXI4/EXTRG4/SEG27 P20/SEG26 P22/SEG28 P23/EXI5/EXTRG5/SEG29 P24/SEG30 P25/SEG31 P26/EXI6/EXTRG6/SEG32 P27/EXI7/EXTRG7/SEG33 P56/SEG34 P57/SEG35 PA3/EXI11/SEG36 PA4/SEG37 Pin Layout of 80pin QFP Package P96/SEG15 PB3/SEG44 P95/SEG14 PB4/SEG45 P94/SEG13 PB5/SEG46 P93/SEG12 P40/SEG47 P53/SEG8 P41/SEG48 P52/SEG7 P30/SEG49 P51/SEG6 P31/SEG50 P50/EXI8/SEG5 P32/SEG51 P13/COM7/SEG4 TOP VIEW QFP80 P33/SEG52 P60/SEG53 P61/SEG54 P12/COM6/SEG3 P11/COM5/SEG2 P10/COM4/SEG1 P62/SEG55 P07/COM3/SEG0 P63/SEG56 P06/COM2 P64/EXI9/SEG57 P05/COM1 P70 P67/SEG60 VL3 P42/SEG61 VL2 P43 VL1 21 P04/EXI2/EXTRG2/COM0 P66/SEG59 80 P65/SEG58 C2 C1 P76/EXI10 P47 P46 P03/EXI1/EXTRG1 P45 P02/EXI0/EXTRG0 P44/DACOUT1 P82 P81 P80 P01/DACOUT0 P00/TEST0 RESET_N VDDL VSS VDD 20 XT1/PI01 XT0/PI00 1 Figure 6 Pin Layout of 80pin QFP Package 13/71 FEDL62Q1700-01 50 PB0/SEG41 51 76 75 NC VDD PA1/SEG18 PA2/SEG19 P54/SEG20 P55/SEG21 P14/SEG22 P15/SEG23 P16/SEG24 P17/EXI3/EXTRG3/SEG25 P20/SEG26 P21/EXI4/EXTRG4/SEG27 P22/SEG28 P23/EXI5/EXTRG5/SEG29 P24/SEG30 P25/SEG31 P26/EXI6/EXTRG6/SEG32 P27/EXI7/EXTRG7/SEG33 P56/SEG34 P57/SEG35 PA3/EXI11/SEG36 PA4/SEG37 PA5/SEG38 PA6/SEG39 PA7/SEG40 Pin Layout of 100pin TQFP Package PA0/SEG17 PB1/SEG42 P97/SEG16 PB2/SEG43 P96/SEG15 PB3/SEG44 P95/SEG14 PB4/SEG45 P94/SEG13 PB5/SEG46 P93/SEG12 P40/SEG47 P92/SEG11 P41/SEG48 P91/SEG10 P30/SEG49 P90/SEG9 P31/SEG50 P53/SEG8 P32/SEG51 P52/SEG7 P33/SEG52 P51/SEG6 TOP VIEW TQFP100 P60/SEG53 P61/SEG54 P50/EXI8/SEG5 P13/COM7/SEG4 P12/COM6/SEG3 P63/SEG56 P11/COM5/SEG2 P64/EXI9/SEG57 P10/COM4/SEG1 P65/SEG58 P07/COM3/SEG0 P66/SEG59 P06/COM2 P67/SEG60 P05/COM1 P42/SEG61 P04/EXI2/EXTRG2/COM0 PB6/SEG62 P70 PB7/SEG63 VL3 P77/SEG64 VL2 26 VL1 C2 C1 P76/EXI10 P47 P46 P03/EXI1/EXTRG1 P02/EXI0/EXTRG0 P45 P44/DACOUT1 P87 P86 P85 P84 P83 P82 P81 P80 P01/DACOUT0 P00/TEST0 RESET_N VDDL VSS VDD 25 XT1/PI01 1 XT0/PI00 P43 100 P62/SEG55 Figure 7 Pin Layout of 100pin TQFP Package 14/71 FEDL62Q1700-01 50 PB3/SEG44 51 81 80 P97/SEG16 PA0/SEG17 NC VDD PA1/SEG18 PA2/SEG19 P54/SEG20 P55/SEG21 P15/SEG23 P14/SEG22 P16/SEG24 P17/EXI3/EXTRG3/SEG25 P20/SEG26 P21/EXI4/EXTRG4/SEG27 P22/SEG28 P23/EXI5/EXTRG5/SEG29 P24/SEG30 P25/SEG31 P26/EXI6/EXTRG6/SEG32 P27/EXI7/EXTRG7/SEG33 P56/SEG34 P57/SEG35 PA3/EXI11/SEG36 PA4/SEG37 PA5/SEG38 PA6/SEG39 PA7/SEG40 PB0/SEG41 PB1/SEG42 PB2/SEG43 Pin Layout of 100pin QFP Package P96/SEG15 PB4/SEG45 P95/SEG14 PB5/SEG46 P94/SEG13 P40/SEG47 P93/SEG12 P41/SEG48 P92/SEG11 P30/SEG49 P91/SEG10 P31/SEG50 P90/SEG9 P32/SEG51 P53/SEG8 P33/SEG52 P52/SEG7 TOP VIEW QFP100 P60/SEG53 P61/SEG54 P62/SEG55 P51/SEG6 P50/EXI8/SEG5 P13/COM7/SEG4 P12/COM6/SEG3 P64/EXI9/SEG57 P11/COM5/SEG2 P65/SEG58 P10/COM4/SEG1 P66/SEG59 P07/COM3/SEG0 P67/SEG60 P06/COM2 P42/SEG61 P05/COM1 PB6/SEG62 P04/EXI2/EXTRG2/COM0 31 P70 VL3 VL2 VL1 C2 C1 P76/EXI10 P47 P46 P03/EXI1/EXTRG1 P02/EXI0/EXTRG0 P45 P44/DACOUT1 P87 P86 P85 P84 P83 P82 P81 P80 P01/DACOUT0 P00/TEST0 RESET_N VDDL VSS VDD XT1/PI01 XT0/PI00 30 P43 1 P77/SEG64 PB7/SEG63 100 P63/SEG56 Figure 8 Pin Layout of 100pin QFP Package 15/71 FEDL62Q1700-01 PIN LIST Table 3 Pin List (1/3) Pin No. th th QFP100 th TQFP100 th 80 pin th 64 Pin rd 52 Pin nd 48 Pin st Pin name st (1 func) 3 3 3 3 3 5 VDD - - - - - - - - - - - 42 52 54 VDD - - - - - - - - 4 4 4 4 6 VSS - - - - - - - - - - - 41 51 53 NC - - - - - - - - 5 5 5 5 5 7 VDDL - - - - - - - - 1 1 1 1 1 3 XT0 PI00 - - - - - - - 2 2 2 2 2 4 XT1 PI01 - - - - - - - 6 6 6 6 6 8 RESET_N RESET_N - - - - - - - 7 7 7 7 7 9 P00 TEST0 - - - - - - 8 8 8 8 8 10 P01 DACOUT0 - - - FTM3P *1 TBCOUT0 TBCOUT1 - 9 9 11 14 19 21 P02 FTM0P OUTLSCLK CMP0M - 10 10 12 15 20 22 P03 FTM0N OUTHSCLK CMP0P AIN11 16 17 21 25 30 32 P04 - - - 17 18 22 26 31 33 P05 18 19 23 27 32 34 P06 19 20 24 28 33 35 P07 20 21 25 29 34 36 P10 21 22 26 30 35 37 P11 22 23 27 31 36 38 P12 23 24 28 32 37 39 P13 25 27 35 45 57 59 P14 SEG22 26 28 36 46 58 60 P15 SEG23 27 29 37 47 59 61 P16 28 30 38 48 60 62 P17 29 31 39 49 61 63 P20 30 32 40 50 62 64 P21 SEG24 EXI3 EXTRG3 SEG25 SEG26 EXI4 EXTRG4 SEG27 31 33 41 51 63 65 P22 SEG28 32 34 42 52 64 66 P23 EXI5 EXTRG5 VREF SEG29 33 35 43 53 65 67 P24 SEG30 34 36 44 54 66 68 P25 SEG31 35 37 45 55 67 69 P26 36 38 46 56 68 70 P27 4 1 func. others EXI0 EXTRG0 EXI1 EXTRG1 EXI2 EXTRG2 COM0 2 func. SIU 3 func. SIU 4 func. I2C 5 func. Timer 6 func. others 7 func. others 8 func. ADC SU0_RXD0 I2CU0_SCL SU0_SIN *1 SU0_TXD0 SU0_TXD1 I2CU0_SDA SU0_SOUT SU0_SCLK - COM1 - - - - - - - COM2 COM3 SEG0 COM4 SEG1 COM5 SEG2 COM6 SEG3 COM7 SEG4 - - I2CM0_SDA - - - - SU0_RXD1 SU0_RXD0 I2CM0_SCL - - - - SU0_TXD1 - - - - - - SU0_SCLK - - - - - - - TMH4OUT - - - - TMH1OUT - TMH3OUT - EXI6 EXTRG6 SEG32 EXI7 EXTRG7 SEG33 SU0_RXD0 SU0_SIN SU0_TXD0 SU0_TXD1 SU0_SOUT - I2CU0_SCL TMH0OUT - - - - - - - I2CU0_SDA - - - SU1_SCLK - I2CU0_SCL TMH5OUT - - - SU0_RXD1 SU0_RXD0 - FTM1P TBCOUT0 BZ0P AIN0 SU0_TXD1 - - FTM1N TBCOUT1 BZ0N AIN1 SU1_RXD0 SU1_SIN - - FTM2P OUTLSCLK - AIN2 FTM2N OUTHSCLK - AIN3 - - VREFO SU1_TXD0 SU1_TXD1 I2CM0_SDA SU1_SOUT SU1_SCLK - SU1_RXD0 SU1_SIN SU1_TXD0 SU1_TXD1 SU1_SOUT I2CM0_SCL TMH2OUT - - - - AIN4 - - - - AIN5 SU1_RXD1 SU1_RXD0 I2CU0_SDA FTM3P TBCOUT0 BZ0P AIN6 SU1_TXD1 FTM3N TBCOUT1 BZ0N AIN7 - I2CU0_SCL *1: No assignment to ML62Q1500 Series. 16/71 FEDL62Q1700-01 Table 3 Pin List (2/3) Pin No. QFP100 TQFP100 80 pin 64 Pin 52 Pin 48 Pin Pin name st (1 func) st 1 func. others 2 nd func. SIU *3 rd th th 3 func. SIU *3 4 func. I2C 5 func. Timer *3 th 6 func. others th th 7 func. others 8 func. ADC *3 37 41 51 67 84 86 P30 SEG49 - - - - - - - 38 42 52 68 85 87 P31 SEG50 - - - - TBCOUT0 TBCOUT1 - 39 43 53 69 86 88 P32 SEG51 SU1_RXD1 SU1_RXD0 - - - - - 40 44 54 70 87 89 P33 SEG52 SU1_TXD1 - - TMH3OUT - - - 49 65 82 84 P40 SEG47 SU5_TXD1 - - - - - - 40 50 66 83 85 P41 SEG48 - - - - - - - 63 79 96 98 P42 SEG61 SU3_TXD1 - - - - - - 48 52 64 80 100 2 P43 - - - - TBCOUT0 TBCOUT1 AIN10 - - - I2CU0_SDA *1 I2CU0_SCL *2 FTM3N *1 FTM1N *1 FTM1P *1 - - - - - - - - - - - - - - - - - - 9 12 17 19 P44 - - 10 13 18 20 P45 - SU4_TXD1 - - - 13 16 21 23 P46 - - - 11 14 17 22 24 P47 - SU0_SCLK *1 - - - - - - DACOUT1 SU4_RXD1 SU4_RXD0 P51 EXI8 SEG5 SEG6 - - 31 35 40 42 P52 SEG7 - - 32 36 41 43 P53 SEG8 SU4_TXD1 - - 33 43 55 57 P54 SEG20 SU2_RXD1 SU2_RXD0 - - 34 44 56 58 P55 SEG21 39 47 57 69 71 P56 SEG34 48 58 70 72 P57 SEG35 SU2_TXD1 SU2_RXD0 SU2_SIN SU2_TXD0 SU2_TXD1 SU2_SOUT 41 45 55 71 88 90 P60 SEG53 - 42 46 56 72 89 91 P61 SEG54 - 43 47 57 73 90 92 P62 SEG55 44 48 58 74 91 93 P63 SEG56 45 49 59 75 92 94 P64 EXI9 SEG57 46 50 60 76 93 95 P65 SEG58 47 51 61 77 94 96 24 25 29 33 38 40 - - 26 30 34 39 41 - P50 - - - - - - - - - - - - - - - - TMH7OUT - - - - - - - - - - - - AIN12 - - - - AIN13 - I2CM1_SCL - - - - - I2CM1_SDA - - - - - - - FTM4N - CMP1P - - - - FTM4P - CMP1M - - FTM5P - - - - FTM5N - - AIN8 SU4_RXD1 SU4_RXD0 - SU3_RXD0 SU3_SIN SU3_TXD0 SU3_TXD1 SU3_SOUT P66 SEG59 SU3_SCLK - - 62 78 95 97 P67 SEG60 SU3_RXD1 SU3_RXD0 - - 20 24 29 31 P70 - - 15 16 19 23 28 30 VL3 - 14 15 18 22 27 29 VL2 13 14 17 21 26 28 VL1 12 13 16 20 25 27 11 12 15 19 24 26 - - - - - - 18 23 25 - 99 1 - - - - - - AIN9 - - - - - - - TMH6OUT - - - - - - - - - - - - - - - - - - - - - - - - - - C2 - - - - - - - - C1 - - - - - - - - P76 EXI10 - - - - - - - P77 SEG64 - - - - - - - *1: No assignment to ML62Q1500 Series. *2: No assignment to ML62Q1500 Series and products of 52 PIN-package. *3: The pins of name with DACOUT1, SU2, SU3, SU4, SU5, TMH6, TMH7, AIN12 or AIN13 are not assigned to products of 48/52/64 PIN-packages. 17/71 FEDL62Q1700-01 Table 3 Pin List (3/3) Pin No. QFP100 64 Pin TQFP100 52 Pin - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 73 75 - - - - - - - - - - - - 76 78 - - - - 77 79 - - - - - - - - - - - - - - - - - - 80 pin 48 Pin - 9 Pin name st (1 func) st 1 func. others - 9 11 P80 10 10 12 P81 11 11 13 - 12 14 13 15 P82 - P83 - 14 16 P84 P85 - - 2 nd func. SIU rd 3 func. SIU SU4_RXD0 SU4_SIN SU4_TXD0 SU4_TXD1 SU4_SOUT SU4_SCLK SU5_RXD0 th th th th th 4 func. I2C 5 func. Timer 6 func. others 7 func. others 8 func. ADC - - - - - - - - - - - - - - - - - - - - - - - - - - - - SU5_TXD1 *1 - - - - - - - - - - - - - - - - - - - - - - - FTM7P *1 FTM7N *1 - - - - SU5_TXD0 15 17 P86 16 18 P87 42 44 P90 SEG9 43 45 P91 SEG10 - - - - - - - - - - - - - - - - - - - - 44 46 P92 SEG11 37 45 47 P93 SEG12 38 46 48 P94 SEG13 39 47 49 P95 SEG14 SU4_RXD0 SU4_SIN SU4_TXD0 SU4_TXD1 SU4_SOUT SU4_SCLK - FTM6P FTM6N - - - - - - - - - - - P96 SEG15 - 49 51 P97 SEG16 - - - - - - - 50 52 PA0 SEG17 - - - - - - - 53 55 PA1 SEG18 - - - - - - - - - - - - - - - - - 40 48 50 54 56 PA2 SEG19 - 59 71 73 PA3 EXI11 SEG36 SU2_SCLK 60 72 74 PA4 SEG37 - - - FTM7N - - AIN15 PA5 SEG38 - - - - - - - 74 76 PA6 SEG39 - - - - - - - 75 77 PA7 SEG40 - - - - - - - PB0 SEG41 - - - - - - - PB1 SEG42 - - 61 78 80 PB2 SEG43 62 79 81 PB3 SEG44 63 80 82 PB4 SEG45 64 81 83 - 97 99 - 98 100 PB5 SEG46 PB6 SEG62 PB7 SEG63 FTM7P AIN14 - - - - - SU5_RXD0 SU5_SIN SU5_TXD0 SU5_TXD1 SU5_SOUT SU5_SCLK - - - - - - - - - - - - - - - SU5_RXD1 SU5_RXD0 - - - - - - - - - - - - - - - - - - *1: No assignment to ML62Q1500 Series. 18/71 FEDL62Q1700-01 PIN DESCRIPTION Table 4 Pin Description (1/7) Function Signal name － Pin name VSS I/O － － VDD － － VDDL － Power Test TEST0 P00 I/O Un used NC NC － System － － Input pin for testing. Also, used for on-chip debug interface or ISP function. P00 is initialized as pull-up input mode by the system reset (not high-impedance mode). － Recommended to connect to VSS. － VREF P23 － RESET_N RESET_N I XT0 XT0 I XT1 XT1 P02 P21 P03 P22 O O Low-speed clock output. － O High-speed clock output. － PI00, PI01 XT0, XT1 I P00 P00 I/O P01 – P07 P10 – P17 P20 – P27 P30 – P33 P40 – P47 P50 – P57 P60 – P67 P70,P76, P77 P80 – P87 P90 – P97 PA0 – PA7 PB0 – PB7 P01 – P07 P10 – P17 P20 – P27 P30 – P33 P40 – P47 P50 – P57 P60 – P67 P70, P76, P77 P80 – P87 P90 – P97 PA0 – PA7 PB0 – PB7 OUTHSCLK General port (GPIO) Logic － Reference voltage output. An internal reference voltage in the SA type A/D － converter block can be externally used for a reference. The pin is shared with the SA type A/D converter external reference voltage input. Input for reset. Asserting “L” level to this pin enters the MCU into system reset mode and internal circuits are initialized, then releasing it to “H” level make CPU Negative start running the program. Used for on-chip debug interface or ISP function. Internal pull-up resistor is not installed. Low speed crystal oscillation pins － Connect 32.768kHz crystal resonator and have － capacitors between the pin and VSS. OUTLSCLK General input port (GPI) Description Negative power supply pin (-) Positive power supply pin (+). Connect a capacitor CV between this pin and VSS to stabilize power supply. Power supply pin for internal logic (internal regulator’s output). Connect a capacitor CL（1μF） between this pin and VSS. I/O General Input port. Not available to use as general Positive inputs when using the crystal resonator. General I/O port - High-impedance - Input with Pull-UP (initial value) - Input without Pull-UP - CMOS output Positive - N-channel open drain output P00 is only initialized as pulled-up input and other ports are initialized as high-impedance Not available to use as I/O pin when using for on-chip debug interface or ISP function. General I/O port - High-impedance (initial value) - Input with Pull-UP - Input without Pull-UP - CMOS output - N-channel open drain output Positive 19/71 FEDL62Q1700-01 Table 4 Pin Description (2/7) Function Signal name SU0_TXD0 SU0_RXD0 SU0_TXD1 SU0_RXD1 SU1_TXD0 SU1_RXD0 SU1_TXD1 SU1_RXD1 SU2_TXD0 SU2_RXD0 UART SU2_TXD1 SU2_RXD1 SU3_TXD0 SU3_RXD0 SU3_TXD1 SU3_RXD1 SU4_TXD0 SU4_RXD0 SU4_TXD1 SU4_RXD1 SU5_TXD0 SU5_RXD0 SU5_TXD1 SU5_RXD1 Pin name P03 P13 P02 P07 P12 P17 P03 P10 P13 P20 P07 P17 P22 P25 P21 P24 P26 P32 P22 P25 P27 P33 P26 P32 P57 P54 P56 P55 P57 P54 P65 P64 P67 P42 P65 P67 P81 P94 P44 P52 P80 P93 P45 P53 P81 P94 P44 P52 P84 PB3 P83 PB2 PB5 P40 P84 PB3 PB5 I/O Description Logic O Serial communication unit0/UART0 data output pin. Positive I Serial communication unit0/UART0 data input pin. Positive O Serial communication unit0/UART1 data output pin. Positive I Serial communication unit0/UART1 data input pin. Positive O Serial communication unit1/UART0 data output pin Positive I Serial communication unit1/UART0 data input pin. Positive O Serial communication unit1/UART1 data output pin. Positive I Serial communication unit1/UART1 data input pin. Positive O Serial communication unit2/UART0 data output pin. Positive I Serial communication unit2/UART0 data input pin. Positive O Serial communication unit2/UART1 data output pin. Positive I O Serial communication unit2/UART1 data input pin. Serial communication unit3/UART0 data output pin. Positive Positive I Serial communication unit3/UART0 data input pin. Positive O Serial communication unit3/UART1 data output pin. Positive I Serial communication unit3/UART1 data input pin. Positive O Serial communication unit4/UART0 data output pin. Positive I Serial communication unit4/UART0 data input pin. Positive O Serial communication unit4/UART1 data output pin. Positive I Serial communication unit4/UART1 data input pin. Positive O Serial communication unit5/UART0 data output pin. Positive I Serial communication unit5/UART0 data input pin. Positive O Serial communication unit5/UART1 data output pin. Positive I Serial communication unit5/UART1 data input pin. Positive 20/71 FEDL62Q1700-01 Table 4 Pin Description (3/7) SU0_SIN SU0_SCLK SU0_SOUT SU1_SIN SU1_SCLK SU1_SOUT Synchronous Serial Port P02 P12 P04 P11 P47 P03 P13 P21 P24 P16 P23 P22 P25 I Serial communication unit0/Synchronous serial data input pin. Positive I/O Serial communication unit0/Synchronous serial clock I/O pin. Positive O Serial communication unit0/Synchronous serial data output pin. Positive I Serial communication unit1/Synchronous serial data input pin. Positive I/O Serial communication unit1/Synchronous serial clock I/O pin. Positive O SU2_SIN P56 I SU2_SCLK PA3 I/O SU2_SOUT P57 O SU3_SIN P64 I SU3_SCLK P66 I/O SU3_SOUT P65 O P80 P93 P82 P95 P81 P94 I/O SU5_SIN PB2 I SU5_SCLK PB4 I/O SU5_SOUT PB3 O SU4_SIN SU4_SCLK SU4_SOUT I2CU0_SDA I2CU0_SCL 2 I C Bus I2CM0_SDA I2CM0_SCL P03 P15 P26 P46 P02 P04 P16 P27 P47 P06 P22 P07 P23 I O Serial communication unit1/Synchronous serial data output pin. Serial communication unit2/Synchronous serial data input pin. Serial communication unit2/Synchronous serial clock I/O pin. Serial communication unit２/Synchronous serial data output pin. Serial communication unit3/Synchronous serial data input pin. Serial communication unit3/Synchronous serial clock I/O pin. Serial communication unit3/Synchronous serial data output pin. Serial communication unit4/Synchronous serial data input pin. Serial communication unit4/Synchronous serial clock I/O pin. Serial communication unit4/Synchronous serial data output pin. Serial communication unit5/Synchronous serial data input pin. Serial communication unit5/Synchronous serial clock I/O pin. Serial communication unit5/Synchronous serial data output pin. 2 I/O I C Unit0 (Master and Salve) Data I/O pin / N-ch open drain. Connect a pull-up resistor externally. I/O I C Unit0 (Master and Salve) Clock I/O pin / N-ch open drain. Connect a pull-up resistor externally. I/O I C Master0 Data I/O pin / N-ch open drain. Connect a pull-up resistor externally. I/O I2CM1_SDA P61 I/O I2CM1_SCL P60 I/O 2 2 2 I C Master0 Clock I/O pin / N-ch open drain. Connect a pull-up resistor externally. 2 I C Master1 Data I/O pin / N-ch open drain. Connect a pull-up resistor externally. 2 I C Master1 Clock I/O pin / N-ch open drain. Connect a pull-up resistor externally. Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive 21/71 FEDL62Q1700-01 Table 4 Pin Description (4/7) Function Signal name Pin name I/O Description FTM0P FTM0N P02 P03 P17 P47 P20 P46 P21 P22 P01 P26 P27 P44 P63 P62 P64 P65 P93 P94 P86 PA3 P87 PA4 P02 P03 P04 P17 P21 P23 P26 P27 P04 P13 P23 P13 P33 P12 P16 P70 P54 P02 P03 P01 P17 P26 P31 P43 P01 P20 P27 P31 P43 P17 P26 P20 P27 O O Functional Timer0 output. Functional Timer0 output. Positive Negative O Functional Timer1 output. Positive O Functional Timer1 output. Negative O O Functional Timer2 output. Functional Timer2 output. Positive Negative O Functional Timer3 output. Positive O Functional Timer3 output. Negative O O O O O O O Functional Timer4 output. Functional Timer4 output. Functional Timer5 output. Functional Timer5 output. Functional Timer6 output. Functional Timer6 output. Positive Negative Positive Negative Positive Negative Functional Timer7 output. Positive Functional Timer7 output. Negative I I I I I I I I O O O Functional Timer event trigger input pin. Functional Timer event trigger input pin. Functional Timer event trigger input pin. Functional Timer event trigger input pin. Functional Timer event trigger input pin. Functional Timer event trigger input pin. Functional Timer event trigger input pin. Functional Timer event trigger input pin. 16-bit Timer 0 output pin 16-bit Timer 1 output pin 16-bit Timer 2 output pin O 16-bit Timer 3 output pin — — — — — — — — Positive Positive Positive Positive O O O O I I 16-bit Timer 4 output pin 16-bit Timer 5 output pin 16-bit Timer 6 output pin 16-bit Timer 7 output pin 16-bit Timer event trigger input pin. 16-bit Timer event trigger input pin. O The virtual frequency adjustment signal or Low-speed Positive Time Base Counter 1Hz/2Hz output pin O Low-speed Time Base Counter 1Hz/2Hz output pin Positive O Buzzer output (positive phase) Positive O Buzzer output (negative phase) Negative FTM1P FTM1N FTM2P FTM2N FTM3P FTM3N Functional Timer (FTM) FTM4P FTM4N FTM5P FTM5N FTM6P FTM6N FTM7P FTM7N EXTRG0 EXTRG1 EXTRG2 EXTRG3 EXTRG4 EXTRG5 EXTRG6 EXTRG7 TMH0OUT TMH1OUT TMH2OUT TMH3OUT 16-bit Timer TMH4OUT TMH5OUT TMH6OUT TMH7OUT EXTRG0 EXTRG1 TBCOUT0 Low-speed Time Base Counter (LTBC) TBCOUT1 Buzzer BZ0P BZ0N O Logic Positive Positive Positive Positive — — 22/71 FEDL62Q1700-01 Table 4 Pin Description (5/7) Function External Interrupt Successive approximation type A/D converter Analog comparator D/A converter Signal name Pin name I/O EXI0 EXI1 EXI2 EXI3 EXI4 EXI5 EXI6 EXI7 EXI8 EXI9 EXI10 EXI11 P02 P03 P04 P17 P21 P23 P26 P27 P50 P64 P76 PA3 I I I I I I I I I I I I VREF P23 — AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11 AIN12 AIN13 AIN14 AIN15 CMP0P CMP0M CMP1P CMP1M DACOUT0 DACOUT1 P17 P20 P21 P22 P24 P25 P26 P27 P65 P66 P43 P03 P56 P57 PA3 PA4 P03 P02 P62 P63 P01 P44 I I I I I I I I I I I I I I I I I I I I O O Description GPIO maskable external interrupt pin GPIO maskable external interrupt pin GPIO maskable external interrupt pin GPIO maskable external interrupt pin GPIO maskable external interrupt pin GPIO maskable external interrupt pin GPIO maskable external interrupt pin GPIO maskable external interrupt pin GPIO maskable external interrupt pin GPIO maskable external interrupt pin GPIO maskable external interrupt pin GPIO maskable external interrupt pin SA type A/D converter external reference voltage input. The voltage provided to the pin is used as the reference voltage for the A/D conversion. SA type A/D converter channel 0 input pin SA type A/D converter channel 1 input pin SA type A/D converter channel 2 input pin SA type A/D converter channel 3 input pin SA type A/D converter channel 4 input pin SA type A/D converter channel 5 input pin SA type A/D converter channel 6 input pin SA type A/D converter channel 7 input pin SA type A/D converter channel 8 input pin SA type A/D converter channel 9 input pin SA type A/D converter channel 10 input pin SA type A/D converter channel 11 input pin SA type A/D converter channel 12 input pin SA type A/D converter channel 13 input pin SA type A/D converter channel 14 input pin SA type A/D converter channel 15 input pin Comparator input 0 (noninverting input) Comparator input 0 (inverting input) Comparator input 1 (noninverting input) Comparator input 1 (inverting input) D/A converter0 output pin D/A converter1 output pin Logic — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 23/71 FEDL62Q1700-01 Table 4 Pin Description (6/7) Function LCD driver Signal name Pin name I/O Description COM0 COM1 COM2 COM3/SEG0 COM4/SEG1 COM5/SEG2 COM6/SEG3 COM7/SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 P04 P05 P06 P07 P10 P11 P12 P13 P50 P51 P52 P53 P90 P91 P92 P93 P94 P95 P96 P97 PA0 PA1 PA2 P54 P55 P14 P15 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 P56 P57 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 － － － － － － － － － － － － － － － － － － － － － － － － － － － － － － － － － － － － － － － － － － － － － － － － － － Common output pin Common output pin Common output pin Common/Segment output shared pin Common/Segment output shared pin Common/Segment output shared pin Common/Segment output shared pin Common/Segment output shared pin Segment output pin Segment output pin Segment output pin Segment output pin Segment output pin Segment output pin Segment output pin Segment output pin Segment output pin Segment output pin Segment output pin Segment output pin Segment output pin Segment output pin Segment output pin Segment output pin Segment output pin Segment output pin Segment output pin Segment output pin Segment output pin Segment output pin Segment output pin Segment output pin Segment output pin Segment output pin Segment output pin Segment output pin Segment output pin Segment output pin Segment output pin Segment output pin Segment output pin Segment output pin Segment output pin Segment output pin Segment output pin Segment output pin Segment output pin Segment output pin Segment output pin Segment output pin Logic — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 24/71 FEDL62Q1700-01 Table 4 Pin Description (7/7) Function LCD driver Signal name Pin name I/O Description SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 P40 P41 P30 P31 P32 P33 P60 P61 P62 P63 P64 P65 P66 P67 P42 PB6 PB7 P77 C1,C2 C1,C2 － － － － － － － － － － － － － － － － － － － VL1~VL3 VL1~VL3 Segment output pin Segment output pin Segment output pin Segment output pin Segment output pin Segment output pin Segment output pin Segment output pin Segment output pin Segment output pin Segment output pin Segment output pin Segment output pin Segment output pin Segment output pin Segment output pin Segment output pin Segment output pin LCD bias power source generation capacitor connection pin LCD bias power source pin. Connect the capacitors (CL1,CL2,CL3) between the pin and Vss. － Logic — — — — — — — — — — — — — — — — — — — — TERMINATION OF UNUSED PINS Table 5 Termination of unused pins Pin Recommended pin termination NC RESET_N Connect to VSS Connect to VDD through a resistor Open the pin with the internal initial condition of pulled-up input mode. P00/TEST0 XT0/PI00, XT1/PI01 P01 to P07 P10 to P17 P20 to P27 P30 to P33 P40 to P47 P50 to P57 P60 to P67 P70, P76 , P77 P80 to P87 P90 to P97 PA0 to PA7 PB0 to PB7 C1,C2 VL1,VL2 VL3 Open the pins with the internal initial condition of Hi-impedance mode. Open Open Connect to VDD through a resistor Note: For unused input ports or unused input/output ports, if an unstable middle level voltage is supplied to the corresponding pins which are configured as inputs without pull-up register or input/output mode, supply current may become excessively large. Therefore, it is recommended to configure those pins as either input mode with a pull-up resistor or output mode. 25/71 FEDL62Q1700-01 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (VSS = 0V) Parameter Symbol Condition Rating Unit Power supply voltage 1 VDD Ta = +25°C -0.3 to +6.5 V Power supply voltage 2 VDDL Ta = +25°C -0.3 to +2.0 V Power supply voltage 3 VL3 Ta = +25°C -0.3 to +6.5 V Power supply voltage 4 VL1 ,VL2 Ta = +25°C -0.3 to VL3+0.3* Input voltage VIN Ta = +25°C -0.3 to VDD+0.3* 1 V 1 V 1 Output voltage1 VOUT1 Ta = +25°C -0.3 to VDD+0.3* V Output voltage2 VOUT2 Ta = +25°C V “H” level output current IOUTH Ta = +25°C “L” level output current IOUTL Ta = +25°C -0.3 to +6.5 2 -40* 2 -10* +40 +10 1 -55 to +150 1pin Total 1pin Total mA mA Power dissipation PD Ta = +25°C W Storage temperature TSTG ― °C 1 * 6.5V or lower 2 * The current flowing out the LSI through the pin is described in the negative number. The applicable maximum current is the absolute value. For example, -1mA means the maximum current 1mA flows out the LSI through the pin. [Note] Use the product within absolute maximum ratings. The absolute maximum ratings are conditions which may physically deteriorate the quality of product. 26/71 FEDL62Q1700-01 Recommended Operating Conditions (VSS = 0V) Parameter Symbol Condition Range Unit Operating temperature TOP ― -40 to +105 °C Operating voltage 1 VDD ― 1.6 to 5.5 V Operating voltage 2 VL3 External supply method 2.7 to 5.5 V Operating voltage 3 VL2 External supply method 2/3 x VL3 V Operating voltage 4 VL1 fOP VDDL pin external capacitance VL1,VL2,VL3 pin external capacitance CL CL1,CL2, CL3 C1 and C2 pin external capacitance C12 1/3 x VL3 30k to 4M 30k to 25M 1.0 ±30% 0.47±30% or 1.0±30% 0.47±30% or 1.0±30% V Operating frequency (CPU) External supply method VDD = 1.6 to 5.5V VDD = 1.8 to 5.5V ― ― ― Hz μF μF μF Operation Confirmed Crystal Unit (32.768kHz) (VDD=1.6 to 5.5V, VSS =0V) manufacturer Kyocera Part number ST3215SB Load Temperature capacitance [°C] CL [pF] -40 to +105 7 9 Oscillation mode Low power Standard Tough ● ● - ● ● - Oscillation circuit *2*3 parameter (Reference data) CDL [pF] CGL [pF] ● ● ● 12 13 20 8 9 10 12 13 20 8 8 10 River-eletec TFX-04 -40 to +105 5 Nihon Dempa Kogyo NX3215SA -40 to +85 9 ● ● ● 15 15 SII VT-200F -40 to +85 DST1610A -40 to +85 6 12.5 6 DT-26 -10 to +60 6 ● ● - ● ● ● ● ● ● ● ● 9 22 10 10 22 9 22 10 10 22 Daishinku * These are crystal units that operation with our reference board has been confirmed. 2 * These include wiring and parasitic capacitance. 3 * These are reference data. Please optimize them on user system. 27/71 FEDL62Q1700-01 Current Consumption 1 Product： ML62Q1700, ML62Q1701, ML62Q1702, ML62Q1703, ML62Q1704, ML62Q1710, ML62Q1711, ML62Q1712, ML62Q1713, ML62Q1714, ML62Q1720, ML62Q1721, ML62Q1722, ML62Q1723, ML62Q1724 o (VDD=1.6 to 5.5V, VSS =0V, Ta=-40 to +105 C, unless otherwise specified) Parameter Supply current 0 Supply current 1 Supply current 2-1 Symbol IDD0 IDD1 IDD2-1 Condition CPU is in STOP-D state. Low-speed RC1K/RC32K and PLL oscillation are stopped. CPU is in STOP state. Low-speed RC1K/RC32K and PLL oscillation are stopped. Low-speed RC32K Oscillating. CPU is in HALT state (LTBC *1 and WDT are operating ). PLL oscillation is stopped. Low-speed Crystal Oscillating. *4 Supply current 2-2 Supply current 3 IDD2-2 IDD3 Min. Ta = -40 to o +85 C Ta = -40 to o +105 C Ta = -40 to o +85 C Ta = -40 to o +105 C 3 Typ.* ― Max. ― μA 75 ― 40 1.0 μA ― 80 Ta = -40 to o +85 C ― 42 Ta = -40 to o +105 C ― 85 Ta = -40 to o +85 C ― 42 μA 4.9 Ta = -40 to o +105 C ― CPU: Running with low-speed 1 2 RC32K oscillation clock* * PLL oscillation is stopped. Ta = -40 to o +105 C ― Measurin g circuit 37 0.8 CPU is in HALT state (LTBC *1 and WDT are operating ). PLL oscillation is stopped. Unit μA 3.3 1 85 17 CPU: Running with 16MHz PLL 2 Ta = -40 to oscillating clock* Supply current 4 ― 3.4 IDD4 o +105 C PLL 16MHz is oscillating. VDD=1.8~5.5V CPU: Running with 24MHz PLL 2 Ta = -40 to oscillating clock* Supply current 5 ― 4.8 IDD5 o +105 C PLL 24MHz is oscillating. VDD=1.8~5.5V 1 * LTBC and WDT is operating, Significant bits of BLKCON0-3 and BRECON0-3 registers are all “1” 2 * CPU running in wait mode 3 * On the condition of VDD=3.0V, Ta=+25°C 4 * When the noise filter is not used in the low power consumption mode 105 μA 4.5 mA 6.0 28/71 FEDL62Q1700-01 Current Consumption 2 Product： ML62Q1725, ML62Q1726, ML62Q1727, ML62Q1733, ML62Q1734, ML62Q1735, ML62Q1736, ML62Q1737, ML62Q1743, ML62Q1744, ML62Q1745, ML62Q1746, ML62Q1747 o (VDD=1.6 to 5.5V, VSS =0V, Ta=-40 to +105 C, unless otherwise specified) Parameter Supply current 0 Supply current 1 Supply current 2-1 Symbol IDD0 IDD1 IDD2-1 Condition CPU is in STOP-D state. Low-speed RC1K/RC32K and PLL oscillation are stopped. CPU is in STOP state. Low-speed RC1K/RC32K and PLL oscillation are stopped. Low-speed RC32K Oscillating. CPU is in HALT state (LTBC *1 and WDT are operating ). PLL oscillation is stopped. Low-speed Crystal Oscillating. *4 Supply current 2-2 Supply current 3 IDD2-2 IDD3 Min. Ta = -40 to o +85 C Ta = -40 to o +105 C Ta = -40 to o +85 C Ta = -40 to o +105 C 3 Typ.* ― ― μA 60 1.5 μA 120 ― Ta = -40 to o +105 C ― 135 Ta = -40 to o +85 C ― 76 76 μA 5.7 Ta = -40 to o +105 C ― CPU: Running with low-speed 1 2 RC32K oscillation clock* * PLL oscillation is stopped. Ta = -40 to o +105 C ― Measurin g circuit 110 Ta = -40 to o +85 C CPU is in HALT state (LTBC *1 and WDT are operating ). PLL oscillation is stopped. Unit 55 1.0 ― ― Max. μA 4.5 1 135 20 CPU: Running with 16MHz PLL 2 Ta = -40 to oscillating clock* Supply current 4 ― IDD4 4.0 o +105 C PLL 16MHz is oscillating. VDD=1.8~5.5V CPU: Running with 24MHz PLL 2 Ta = -40 to oscillating clock* Supply current 5 ― IDD5 5.7 o +105 C PLL 24MHz is oscillating. VDD=1.8~5.5V 1 * LTBC and WDT is operating, Significant bits of BLKCON0-3 and BRECON0-3 registers are all “1” 2 * CPU running in wait mode 3 * On the condition of VDD=3.0V, Ta=+25°C 4 * When the noise filter is not used in the low power consumption mode 150 μA 5.0 mA 7.0 29/71 FEDL62Q1700-01 Current Consumption 3 Product： ML62Q1728, ML62Q1729, ML62Q1738, ML62Q1739, ML62Q1748, ML62Q1749 o (VDD=1.6 to 5.5V, VSS =0V, Ta=-40 to +105 C, unless otherwise specified) Parameter Supply current 0 Supply current 1 Supply current 2-1 Symbol IDD0 IDD1 IDD2-1 Condition CPU is in STOP-D state. Low-speed RC1K/RC32K and PLL oscillation are stopped. CPU is in STOP state. Low-speed RC1K/RC32K and PLL oscillation are stopped. Low-speed RC32K Oscillating. CPU is in HALT state (LTBC *1 and WDT are operating ). PLL oscillation is stopped. Low-speed Crystal Oscillating. *4 Supply current 2-2 Supply current 3 IDD2-2 IDD3 Min. Ta = -40 to o +85 C Ta = -40 to o +105 C Ta = -40 to o +85 C Ta = -40 to o +105 C 3 Typ.* ― Max. ― μA 140 ― 62 1.8 ― μA 150 Ta = -40 to o +85 C ― Ta = -40 to o +105 C ― 165 Ta = -40 to o +85 C ― 78 78 μA 6.0 Ta = -40 to o +105 C ― CPU: Running with low-speed 1 2 RC32K oscillation clock* * PLL oscillation is stopped. Ta = -40 to o +105 C ― Measurin g circuit 57 1.2 CPU is in HALT state (LTBC *1 and WDT are operating ). PLL oscillation is stopped. Unit μA 4.5 1 165 20 CPU: Running with 16MHz PLL 2 Ta = -40 to oscillating clock* Supply current 4 ― 4.0 IDD4 o +105 C PLL 16MHz is oscillating. VDD=1.8~5.5V CPU: Running with 24MHz PLL 2 Ta = -40 to oscillating clock* Supply current 5 ― 5.7 IDD5 o +105 C PLL 24MHz is oscillating. VDD=1.8~5.5V 1 * LTBC and WDT is operating, Significant bits of BLKCON0-3 and BRECON0-3 registers are all “1” 2 * CPU running in wait mode 3 * On the condition of VDD=3.0V, Ta=+25°C 4 * When the noise filter is not used in the low power consumption mode 190 μA 5.0 mA 7.0 30/71 FEDL62Q1700-01 Low speed Crystal Oscillation o Parameter Symbol (VDD=1.6 to 5.5V, VSS =0V, Ta=-40 to +105 C, unless otherwise specified) Range Condition Unit Min. Typ. Max. Crystal oscillation fXTL ― ― 32.768 ― kHz 1 2 frequency * * Crystal oscillation start TXTL ― ― ― 2 s time 1 * : The oscillation frequency is determined by the oscillation circuit, crystal resonator and the external capacitance (CGL/CDL). As those parameters changes depending the crystal resonator, it requires evaluation on the actual PCB circuit for matching. Ask crystal resonator makers for matching and confirm the oscillation characteristics. 2 * : The quality of oscillation characteristics might be lost, depending on material of PCB, condition of wiring capacitance or parasitic capacitance on the external circuits. Note for designing the external circuit. - Make the wires on the external circuit as short as possible. - Place the crystal resonator and oscillation circuit as close to the MCU as possible and make the wires between the external capacitance and crystal resonator as short as possible. - Ensure no signal line flowing big current runs near the oscillation circuit. - Ensure no signal line runs under and near the oscillation circuit. - Make ground of external capacitance the same as MCU ground VSS pin and connect them to the ground that has low variation of current and voltage. variation. - The quality of oscillation characteristics might be lost depending on operating environment due to moisture absorption of PCB and condensation of PCB surface, recommended to have measures such as covering the oscillation circuit with resin. Low speed Crystal Oscillation external circuit example XT0 XT1 VSS Crystal resonator (32.768kHz） CGL CDL External Clock Input o Parameter Symbol Input Frequency fEXCK Input pulse width tEXCKW (VDD=1.6 to 5.5V, VSS =0V, Ta=-40 to +105 C, unless otherwise specified) Range Condition Unit Min. Typ. Max. Typ. Typ. ― 32.768 kHz -1.0% +1.0% 1/fEXCK 1/fEXCK ― s x 0.4 x 0.6 31/71 FEDL62Q1700-01 On-chip Oscillator (VDD=1.6 to 5.5V, VSS =0V, Ta=−40 to +105°C, unless otherwise specified) Measur Parameter Symbol Condition Min. Typ. Max. Unit ing circuit Ta= +25°C Typ. VDD = 1.8 to 5.5V Typ. 32.768 +1.0% -1.0% Without software 1 adjustment * Ta= -40 to +85°C Typ. VDD = 1.8 to 5.5V Typ. 32.768 +2.5% -2.5% Without software Low-speed RC oscillator 1 adjustment * fRCL1 frequency accuracy 1 Ta= -40 to +105°C Typ. VDD = 1.8 to 5.5V Typ. 32.768 +3.0% -3.0% Without software 1 adjustment * kHz VDD = 1.6 to 1.8V Typ. Typ. 32.768 Without software -3.5% -3.5% 1 adjustment * Ta= -40 to +85°C Typ. VDD = 1.8 to 5.5V Typ. 32.768 +1.0% -1.0% With software 1 adjustment * Low-speed RC oscillator fRCL2 frequency accuracy 2 Ta= -40 to +105°C Typ. VDD = 1.8 to 5.5V Typ. 32.768 +1.5% -1.5% With software 1 adjustment * 1 Ta= -40 to +85°C Typ. VDD = 1.8 to 5.5V Typ. 16/24 +2.5% -2.5% Without software 1 adjustment * Ta= -40 to +105°C PLL oscillation frequency Typ. fPLL1 VDD = 1.8 to 5.5V Typ. accuracy 1 16/24 +3.0% -3.0% Without software 1 adjustment * VDD = 1.6 to 1.8V Typ. Typ. MHz 16/24 Without software +3.5% -3.5% 1 adjustment * Ta= -40 to +85°C Typ. VDD = 1.8 to 5.5V Typ. 16/24 +1.0% -1.0% With software 1 adjustment * PLL oscillation frequency fPLL2 accuracy 2 Ta= -40 to +105°C Typ. VDD = 1.8 to 5.5V Typ. 16/24 +1.5% -1.5% With software 1 adjustment * PLL oscillation start time TPLL VDD = 1.6 to 5.5V ― ― 2 ms Ta= -40 to +105°C 1kHz Low-speed RC oscillator fRC1K 0.5 1 2.5 kHz (for WDT) frequency accuracy VDD = 1.6 to 5.5V 1 * Adjust the frequency by using temperature sensor in ADC and a Specific Function Register (LRCADJ register) 32/71 FEDL62Q1700-01 Input / Output pin 1 (VDD=1.6 to 5.5V, VSS =0V, Ta=−40 to +105°C, unless otherwise specified) Parameter Output voltage1 “H”/”L” level (P00-P07) (P10-P17) (P20-P27) (P30-P33) (P40-P47) (P50-P57) (P60-P67) (P70,P76,P77) (P80-P87) (P90-P97) (PA0-PA7) (PB0-PB7) Output voltage2 “L” level (P01-P07) (P10-P17) (P20-P27) (P30-P33) (P40-P47) (P50-P57) (P60-P67) (P70 P76,P77) (P80-P87) (P90-P97) (PA0-PA7) (PB0-PB7) Output voltage 3 LCD COM/SEG (COM0~COM7) (SEG0~SEG64) Symbol Condition Min. Typ. Max. IOH1=-10mA VDD≥4.5V VDD -1.5 ― ― IOH1=-1mA VDD≥1.6V VDD -0.5 ― ― IOL1=+10mA VDD≥4.5V ― ― 1.5 IOL1=+1mA VDD≥1.6V ― ― 0.5 Unit Measur ing circuit V 2 V 2 VOH1 VOL1 IOL2=+15mA VDD≥4.5V IOL2=+8mA VDD≥3.0V IOL2=+3mA VDD≥2.0V ― ― 0.5 ― ― 0.5 ― ― 0.4 IOL2=+2mA VDD≥1.6V ― ― 0.4 VOH3M IOH3M=-0.03mA VL3 output VL3 -0.2 ― ― VOH3P IOMH3P=+0.03mA VL2 output ― ― VL2 +0.2 IOMH3M=-0.03mA VL2 output VL2 -0.2 ― ― VOL2 VOMH3M When Nch open drain output mode is selected VL3 = 3V, VL2 = 2V, VL1 = 1V IOML3P=+0.03mA VL1 output ― ― VL1 +0.2 VOML3M IOML3M=-0.03mA VL1 output VL1 -0.2 ― ― VOL3P IOL3P=+0.03mA VSS output ― ― 0.2 VOML3P 33/71 FEDL62Q1700-01 Input / Output pin 2 (VDD=1.6 to 5.5V, VSS =0V, Ta=−40 to +105°C, unless otherwise specified) Parameter Symbol “H” level output current1 *6 IOH1 “H” level output 1 4 current1 * * IOH3 Condition 1pin Total of ‘P00-P07, P10-P13, P44-P47, P50-P53, P70,P76, P80-P87，P90-P97, PA0’ or Total of ‘P14-P17, P20-P27, P30-P33, P40-P43, P54-P57 P60-P67,P77, PA1-PA7， PB0-PB7’ (duty≤50%) All pin total (duty≤50%) “L” level output current1 *6 “L” level output 6 current2 * “L” level output 2 4 total current * * IOL1 IOL2 IOL3 1pin (CMOS output mode) 1pin (Nch open drain output mode) Total of P00-P07, P10-P13, P44-P47, P50-P53, P70,P76, P80-P87, P90-P97, PA0’ or Total of ‘P14-P17, P20-P27, P30-P33, P40-P43, P54-P57 P60-P67,P77, PA1-PA7, PB0-PB7’ (Nch open drain output mode,duty≤50%) All pin total (Nch open drain output mode,duty≤50%) Output leak (P00-P07) (P10-P17) (P20-P27) (P30-P33) (P40-P47) (P50-P57) (P60-P67) (P70,P76,P77) (P80-P87) (P90-P97) (PA0-PA7) (PB0-PB7) IOOH Min. Typ. Max. VDD≥4.5V VDD≥1.6V -10* * 3 5 -1* * 3 5 ― ― ― ― VDD≥4.5V -90* 5 ― ― VDD≥1.6V -20* 5 ― ― VDD≥4.5V VDD≥1.6V VDD≥4.5V VDD≥1.6V -180* 5 -40* ― ― ― ― ― ― ― ― 3 10* 3 1* VDD≥4.5V VDD≥3.0V VDD≥2.0V VDD≥1.6V ― ― ― ― ― ― ― ― 15* 3 8* 3 3* 3 2* VDD≥4.5V ― ― 90 5 Unit Measu ring circuit 3 mA 3 VDD≥3.0V ― ― 40 VDD≥2.0V ― ― 15 VDD≥1.6V ― ― 10 VDD≥4.5V ― ― 180 VDD≥1.6V ― ― 20 ― ― +1 VOH=VDD (High impedance mode) μA IOOL VOL=VSS (High impedance mode) 5 -1* ― ― 34/71 FEDL62Q1700-01 * Sink-out current from VDD to the output pin, which can guarantee the device operation. 2 * Sink-in current from the output pin to VSS, which can guarantee the device operation. 3 * Do not exceed total current. 4 * The total current is on the condition of Duty≤50%(same applies to IOH1). When the duty ＞50% the total current is calculated by following formula. Total current = IOL3 x 50/n (When the duty is n%) When IOL3=100mA and n=80%, Total current = IOL3 x 50/80 = 62.5mA Current allowed per 1pin is independent of the duty and specified as IOL1 and IOL2. Do not apply current larger than Absolute Maximum Ratings. 5 * The current flowing out the LSI through the pin is described in the negative number. The applicable maximum current is the absolute value. For example, -1mA means the maximum current 1mA flows out the LSI through the pin. 6 * These values are satisfied with VOH1, VOL1 and VOL2. 1 35/71 FEDL62Q1700-01 Input / Output pin 3 (VDD=1.6 to 5.5V, VSS =0V, Ta=−40 to +105°C, unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Input current1 (RESET_N) IIH1 IIL1 IIL2 V/IIL2 IIH2Z IIL2Z VIH1=VDD VIL1=VSS 2 VIL2=VSS (pull-up mode) * 2 VIL2=VSS (pull-up mode) * VIH2=VDD (High impedance mode) VIL2=VSS (High impedance mode) ― 1 -1* 1 -1500* 3.7 ― 1 -1* ― ― 1 -300* 10 ― ― 1 ― 1 -20* 80 1 ― IIL3 VIL1=VSS (pull-up mode) * V/IIL3 Input current2 (P00/TEST0) Input current3 (P01-P07) (P10-P17) (P20-P27) (P30-P33) (P40-P47) (P50-P57) (P60-P67) (P70,P76,P77) (P80-P87) (P90-P97) (PA0-PA7) (PB0-PB7) Input current4 (PI00-PI01) Input voltage1 (RESET_N) (P01-P07) (P10-P17) (P20-P27) (P30-P33) (P40-P47) (P50-P57) (P60-P67) (P70,P76,P77) (P80-P87) (P90-P97) (PA0-PA7) (PB0-PB7) (PI00-PI01) Input voltage2 (P00/TEST0) Pin capacitance (RESET_N) (P00/TEST0) (P01-P07) (P10-P17) (P20-P27) (P30-P33) (P40-P47) (P50-P57) (P60-P67) (P70,P76,P77) (P80-P87) (P90-P97) (PA0-PA7) (PB0-PB7) (PI00-PI01) 2 -250* 1 -30* 1 -2* 1 VIL1= VSS (pull-up mode) * 2 22 100 800 IIH3Z VIH1=VDD (High impedance mode) ― ― 1 IIL3Z VIL1=VSS (High impedance mode) -1* 1 ― ― IIH4 IIL4 VIH1=VDD VIL1=VSS ― *1 -1 ― ― 1 ― VIH1 ― 0.7 x VDD ― VDD VIL1 ― 0 ― 0.3 x VDD VIH2 ― 0.7 x VDD ― VDD VIL2 ― 0 ― 0.25 ×VDD CPIN f = 10kHz Ta = +25°C ― ― 10 Unit Measur ing circuit μA kΩ μA kΩ 4 μA V 5 pF ― 1 * The current flowing out the LSI through the pin is described in the negative number. The applicable maximum current is the absolute value. For example, -1mA means the maximum current 1mA flows out the LSI through the pin. *2 Measurement conditions: Typ. : VDD = 3.0V, Max. : VDD = 1.6V, Min. : VDD = 5.5V 36/71 FEDL62Q1700-01 Synchronous Serial Port Slave mode Parameter SCK input cycle SCK input pulse width Symbol tSCYC tSW SOUT output delay time tSD SIN input setup time tSS SIN input hold time tSH 1 (VDD=1.8 to 5.5V, VSS =0V, Ta=−40 to +105°C, unless otherwise specified) Condition Min. Typ. Max. Unit 2 ― 1* ― ― μs 3 ― 0.5 * ― ― μs 100+ VDD=2.4 to 5.5V ― ― ns 1 HSCLK* ×3 200+ VDD=1.8 to 5.5V ― ― ns 1 HSCLK* ×3 1 HSCLK* ― ― ― ns x1 80+ ― ― ― ns 1 HSCLK* ×3 * Cycle of high speed clock 2 * Need input cycles of HSLCK x8 or longer 3 * Need input cycles of HSLCK x4 or longer tSCYC tSW tSW 70% SUn_SCLK* 30% tSD SUn_SOUT* tSD 70% 70% 30% 30% tSS SUn_SIN* *2 nd tSH 70% 70% 30% 30% th to 8 function of port, n=0~5 37/71 FEDL62Q1700-01 Master mode (VDD=1.8 to 5.5V, VSS =0V, Ta=−40 to +105°C, unless otherwise specified) Condition Min. Typ. Max. Unit 1 tSCYC ― ― SCLK* ― ns 1 1 1 SCLK* SCLK* SCLK* ― ns tSW SCK output pulse width ×0.4 ×0.5 ×0.6 VDD=2.4 to 5.5V ― ― 100 ns SOUT output delay time tSD VDD=1.8 to 5.5V ― ― 160 ns VDD=2.4 to 5.5V 120 ― ― ns SIN input setup time tSS VDD=1.8 to 5.5V 180 ― ― ns VDD=2.4 to 5.5V 80 ― ― ns SIN input hold time tSH VDD=1.8 to 5.5V 100 ― ― ns 1 * Clock cycle selected by bit12~8(SnCK4~0) of the serial port n mode register (SIOnMOD) VDD≥2.4V: min250ns , VDD≥1.8V: min500ns Parameter SCK output cycle Symbol tSCYC tSW tSW 70% SUn_SCLK* 30% tSD SUn_SOUT* tSD 70% 70% 30% 30% tSS SUn_SIN* *2 nd tSH 70% 70% 30% 30% th to 8 function of port, n=0~5 38/71 FEDL62Q1700-01 I2C Bus Interface Standard Mode 100kHz (VDD=1.8 to 5.5V, VSS =0V, Ta=−40 to +105°C, unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Unit SCL clock frequency fSCL ― 0 ― 100 kHz SCL hold time tHD:STA ― 4.0 ― ― μs (start/restart condition) SCL ”L” level time tLOW ― 4.7 ― ― μs SCL ”H” level time tHIGH ― 4.0 ― ― μs SCL setup time tSU:STA ― 4.7 ― ― μs (restart condition) SDA hold time tHD:DAT ― 0 ― ― μs SDA setup time tSU:DAT ― 0.25 ― ― μs SDA setup time tSU:STO ― 4.0 ― ― μs (stop condition) Bus-free time tBUF ― 4.7 ― ― μs 2 2 2 When using the I C as the master, configure the I C master n mode register(I2MnMOD) and I C bus 0 mode register (master side, I2UM0MOD) so that meet these specifications. Start Condition I2Un_SDA I2Mn_SDA Re-start Condition 70% 70% 30% 70% I2Un_SCL I2Mn_SCL tHD:STA 30% 30% tLOW 70% 70% tHIGH Stop Condition 70% tSU:STA tHD:STA 70% 70% 30% 30% 70% 30% tSU:DAT 30% tHD:DAT 70% 30% 70% 70% tSU:STO tBUF n=0~1 39/71 FEDL62Q1700-01 Fast Mode 400kHz (VDD=1.8 to 5.5V, VSS =0V, Ta=−40 to +105°C, unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Unit SCL clock frequency fSCL ― 0 ― 400 kHz SCL hold time tHD:STA ― 0.6 ― ― μs (start/restart condition) tLOW ― 1.3 ― ― μs SCL ”L” level time SCL ”H” level time tHIGH ― 0.6 ― ― μs SCL setup time tSU:STA ― 0.6 ― ― μs (restart condition) SDA hold time tHD:DAT ― 0 ― ― μs SDA setup time tSU:DAT ― 0.1 ― ― μs SDA setup time tSU:STO ― 0.6 ― ― μs (stop condition) Bus-free time tBUF ― 1.3 ― ― μs 2 2 2 When using the I C as the master, configure the I C master n mode register(I2MnMOD) and I C bus 0 mode register (master side, I2UM0MOD) so that meet these specifications. Start Condition I2Un_SDA I2Mn_SDA Re-start Condition 70% 70% 30% 70% I2Un_SCL I2Mn_SCL tHD:STA 30% 30% tLOW 70% 70% tHIGH Stop Condition 70% tSU:STA tHD:STA 70% 70% 30% 30% 70% 30% tSU:DAT 30% tHD:DAT 70% 30% 70% 70% tSU:STO tBUF n=0~1 40/71 FEDL62Q1700-01 1Mbps Mode (VDD=2.7 to 5.5V, VSS =0V, Ta=−40 to +105°C, unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Unit SCL clock frequency fSCL ― 0 ― 1000 kHz SCL hold time tHD:STA ― 0.26 ― ― μs (start/restart condition) tLOW ― 0.5 ― ― μs SCL ”L” level time SCL ”H” level time tHIGH ― 0.26 ― ― μs SCL setup time tSU:STA ― 0.26 ― ― μs (restart condition) SDA hold time tHD:DAT ― 0 ― ― μs SDA setup time tSU:DAT ― 0.1 ― ― μs SDA setup time tSU:STO ― 0.26 ― ― μs (stop condition) Bus-free time tBUF ― 0.5 ― ― μs 2 2 2 When using the I C as the master, configure the I C master n mode register(I2MnMOD) and I C bus 0 mode register (master side, I2UM0MOD) so that meet these specifications. Start Condition I2Un_SDA I2Mn_SDA Re-start Condition 70% 70% 30% 70% I2Un_SCL I2Mn_SCL tHD:STA 30% 30% tLOW 70% 70% tHIGH Stop Condition 70% tSU:STA tHD:STA 70% 70% 30% 30% 70% 30% tSU:DAT 70% 70% 30% 30% tHD:DAT 70% tSU:STO tBUF n=0~1 41/71 FEDL62Q1700-01 Reset (VDD=1.6 to 5.5V, VSS =0V, Ta=−40 to +105°C, unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Unit Measur ing circuit Reset pulse width P00“H” level setup time P00“H” level hold time PRST tSP00 tHP00 ― ― ― 2 1 1 ― ― ― ― ― ― ms ms ms 1 VIL1 RESET_N VIH1 VIL1 PRST P00/TEST0 “H”level input Or “Pull-up” “H” level or “L” level tSP00 “H” level or “L” level tHP00 Power On Reset (VSS =0V, Ta=−40 to +105°C, unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Unit V Power down(falling) 1.43 1.49 1.58 Power up(rising) 1.47 1.57 1.80 V 1 Power on rising slope RPOR* ― ― ― 60 V/ms 2 POR response time PPOR * 200 ― ― μs 1 * : Rise the VDD to 1.8V or higher when powering on. 2 * : This is the time from the VDD gets 100mV lower than VPOR to the Power-On-Reset internally generates. Make the power down falling slope 2V/ms or lower(i.e. slower). POR detect voltage VDD Measur ing circuit VPOR 1 1.8V 0V VPOR 100mV VPOR PPOR [Note for in case of instantaneous power failure] In case of instantaneous power failure and a pulse shorter than the response time of VLS or POR is asserted to VDD, it is possible to make the MCU cannot get the reset and make erroneous operation. In that case, please have countermeasures such as preventing the voltage down using bypass capacitor or making reset pin reset. 42/71 FEDL62Q1700-01 VLS Parameter Symbol VVLSR VVLSF VVLSR VVLSF VVLSR VVLSF VVLSR VVLSF VVLSR VVLSF VVLSR VLS threshold 2 voltage * VVLSF VVLSR VVLSF VVLSR VVLSF VVLSR VVLSF VVLSR VVLSF VVLSR VVLSF VVLSR VVLSF VLS Current IVLS (VDD=1.6 to 5.5V, VSS =0V, Ta=−40 to +105°C, unless otherwise specified) Condition Measuring Min. Typ. Max. Unit 1 circuit VLS0LV * Rising 3.86 4.06 4.26 00H Falling 3.84 4.00 4.16 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH Rising 3.57 3.76 3.95 Falling 3.55 3.70 3.85 Rising 2.94 3.11 3.28 Falling 2.92 3.05 3.18 Rising 2.85 3.01 3.17 Falling 2.83 2.95 3.07 Rising 2.75 2.91 3.07 Falling 2.73 2.85 2.97 Rising 2.66 2.81 2.96 Falling 2.64 2.75 2.86 Rising 2.56 2.71 2.86 Falling 2.54 2.65 2.76 Rising 2.46 2.61 2.76 Falling 2.44 2.55 2.66 Rising 2.37 2.51 2.65 Falling 2.35 2.45 2.55 Rising 1.98 2.11 2.24 Falling 1.96 2.05 2.14 Rising 1.89 2.01 2.13 Falling 1.87 1.95 2.03 Rising 1.79 1.91 2.03 Falling 1.77 1.85 1.93 ― 50 ― ― V 1 nA 1 * Bit3~Bit0 of voltage level detection circuit 0 level register (VLS0LV). 2 * The Data VSL0LV = 0CH~0FH is not available to use, if the data is specified it will the same spec as that 0BH is specified. Analog Comparator o (VDD=1.8 to 5.5V, VSS =0V, Ta=-40 to +105 C, unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Unit Comparator same phase input voltage range VCMR ― 0.1 ― VDD -1.5 V Comparator0 input offset VCMOF Ta=+25 C、VDD=5.0V ― 5 ― mV Comparator Reference Voltage VCMREF ― 0.75 0.8 0.85 V o Measuring circuit 1 43/71 FEDL62Q1700-01 Successive Approximation Type A/D Converter o Parameter Resolution Overall error Symbol nAD ― Integral non-linearity error INLAD Differential non-linearity error DNLAD Zero-scale error Full-scale error A/D reference voltage Internal reference voltage ZSE FSE VREF VREFI Conversion time tCONV (VDD=1.8 to 5.5V, VSS =0V, Ta=-40 to +105 C, unless otherwise specified) Condition Min. Typ. Max. Unit ― ― ― 10 bit 1 4.5V≤VREFP * ≤5.5V -3.5 1.2 3.5 1 2.7V≤VREFP * ≤5.5V -4 ― 4 1 2.2V≤VREFP *