ML62Q1747-NNNGAZ0AX

FEDL62Q1700-04 Issue Date: May 19, 2022 ML62Q1700 Group 16-bit micro controller GENERAL DESCRIPTION ML62Q1700 Group is a high performance CMOS 16-bit microcontroller equipped with an 16-bit CPU nX-U16/100 and integrated with program memory(Flash memory), data memory(RAM), data Flash and rich peripheral functions such as the multiplier/divider, CRC generator, DMA controller, Clock generator, Simplified RTC, Timer, General Purpose Ports, UART, Synchronous serial port, I2C bus interface unit(Master,Slave), Buzzer, Voltage Level Supervisor(VLS), Successive approximation type A/D converter, D/A converter , Analog comparator, LCD driver, Safety function(IEC60730/60335 Class B) and so on. The CPU nX-U16/100 is capable of efficient instruction execution in 1-instruction 1-clock mode by pipeline architecture parallel processing. The built-in on-chip debug function enables debugging and programming the software. Also, ISP(In-System Programming) function supports the Flash programming in production line. The ML62Q1700 Group has seven packages (48pin - 100pin) and ten kinds of memory sizes(32Kbyte - 512Kbyte). Table 1 ML62Q1700 Group Product List Program memory 512Kbyte 384Kbyte Data memory (RAM) Data Flash 32Kbyte 8Kbyte 256Kbyte 192Kbyte 16Kbyte 160Kbyte 128Kbyte 96Kbyte 32Kbyte 52pin TQFP52 64pin QFP64 TQFP64 80pin QFP80 100pin QFP100 TQFP100 － － ML62Q1729 ML62Q1739 ML62Q1749 － － ML62Q1728 ML62Q1738 ML62Q1748 － － ML62Q1727 ML62Q1737 ML62Q1747 － － ML62Q1726 ML62Q1736 ML62Q1746 － － ML62Q1725 ML62Q1735 ML62Q1745 16Kbyte － － － ML62Q1734 ML62Q1744 8Kbyte ML62Q1704 ML62Q1714 ML62Q1724 － － 16Kbyte 8Kbyte 64Kbyte 48Kbyte 48pin TQFP48 8Kbyte 4Kbyte － － － ML62Q1733 ML62Q1743 ML62Q1703 ML62Q1713 ML62Q1723 － － ML62Q1702 ML62Q1712 ML62Q1722 － － ML62Q1701 ML62Q1711 ML62Q1721 － － ML62Q1700 ML62Q1710 ML62Q1720 － － Please see the page 63 “Notes for product usage” and the page 64 “Notes” in this document on use with this ML62Q1700 group. FEATURES • CPU − 16-bit RISC CPU: nX-U16/100(A35 core) − Instruction system: 16-bit length instructions ‒ Instruction set: Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on ‒ Built-in On-chip debug function ‒ Built-in ISP (In-System Programming) function ‒ Minimum instruction execution time Approximately 30.5 μs (at 32.768 kHz system clock) Approximately 62.5ns/41.6ns (at 16 MHz/24MHz system clock) 1/74 FEDL62Q1700-0４ • Coprocessor for multiplication and division − Multiplication − Division − Division − Multiply-accumulate (non-saturating) − Multiply-accumulate (saturating) − Signed or Unsigned is selectable : 16bit × 16bit (operation time : 4 cycles) : 32bit ÷ 16bit (operation time : 8 cycles) : 32bit ÷ 32bit (operation time : 16 cycles) : 16bit × 16bit + 32bit (operation time : 4 cycles) : 16bit × 16bit + 32bit (operation time : 4 cycles) • Operating voltage and temperature ‒ Operating voltage: VDD = 1.6 to 5.5 V (VDD should be 1.8V or over at Power-on) ‒ Operating temperature: -40 °C to +105 °C • Internal memory ‒ Program memory area Rewrite count Write unit Erase unit Erase/Write temperature : 100 cycles : 32bit(4byte) : 16Kbyte/1Kbyte : 0 °C to +40 °C ‒ Data Flash memory area Rewrite count : 10,000 cycles Write unit : 8bit(1byte) Erase unit : all area/128byte Erase/Write temperature : -40 °C to +85 °C Back Ground Operation(CPU can work while erasing and rewriting) This product uses Super Flash® technology licensed from Silicon Storage Technology, Inc. Super Flash® is a registered trademark of Silicon Storage Technology, Inc. ‒ Data RAM area Rewrite unit : 8bit/16bit (1byte/2byte) Parity check function is available (interrupt / reset are generatable at Parity error) • Clock generation circuit ‒ Low-speed clock (LSCLK) Internal low-speed RC oscillation : Approximately 32.768 kHz External low-speed clock input : Approximately 32.768 kHz External low-speed crystal oscillation : 32.768 kHz crystal resonator is connectable 3 selectable crystal oscillation mode (Tough, Normal, and Low current consumption) ⋅ Tough mode : Largest oscillation allowance to make highest resistance against leakage between the pins ⋅ Normal mode : Normal oscillation allowance and current consumption ⋅ Low current consumption mode: Smallest oscillation allowance to make lower current consumption ‒ High-speed clock (HSCLK) PLL oscillation : 2 selectable oscillation frequency (24MHz and 16MHz) by code option ‒ Watch Dog Timer (WDT) : built-in independent clock for WDT (RC1K: Approximately 1kHz ) • Reset ‒ Reset by reset input pin ‒ Reset by Power-On Reset ‒ Reset by WDT overflow ‒ Reset by WDT invalid clear ‒ Reset by RAM parity error ‒ Reset by unused ROM area access (instruction access) ‒ Reset by voltage level supervisor (VLS) ‒ Software reset by BRK instruction (reset CPU only) ‒ Reset the peripherals individually ‒ Collective reset to the all control pins and peripheral circuits 2/74 FEDL62Q1700-0４ • Power management ‒ HALT mode : CPU stops executing instruction, peripheral circuits continue working ‒ HALT-H mode : CPU stops executing instruction, high-speed clock oscillation stops and peripheral circuits continue working with low-speed clock ‒ STOP mode : CPU and peripheral circuits stops executing instruction, both high-speed oscillation and low-speed oscillation stop. ‒ STOP-D mode : CPU and peripheral circuits stops executing instruction, both high-speed oscillation and low-speed oscillation stop. The internal logic voltage (VDDL) goes down to reduce the current consumption (RAM data is retained). ‒ Clock gear : High-speed system clock frequency can be changed (1/1, 1/2, 1/4, 1/8, 1/16 or 1/32 of HSCLK) ‒ Block Control Function: Powers down the unused function blocks (reset the block or stop supplying the clock) • Interrupt controller − External interrupt ports − Non-maskable interrupt source − Maskable interrupt sources − Four step interrupt levels : max. 12 : 1 (Internal sources: WDT) : max. 51 • Watchdog timer(WDT) ‒ Selectable Operating clock : select RC1K or LSCLK by code option ‒ Overflow period : 8selectable (7.8ms, 15.6ms, 31.3ms, 62.5ms, 125ms, 500ms, 2s and 8s) ‒ Selectable window function (enable or disable): configurable clear enable period (50% or 75% of overflow period) ‒ Selectable WDT operation : select Enable or Disable by code option ‒ Readable WDT counter : WDT counter monitor function • DMA(Direct Memory Access) controller − Channel : 2channel − Transfer unit : 8bit/16bit − Transfer count : 1 to 1024 − Transfer cycle : 2 cycle transfer − Transfer address : Fixed addressing mode, inclement addressing mode , and decrement addressing mode − Transfer target : Special Function Register (SFR)/RAM  SFR/RAM (Transfer from/to Flash is not supported) − Transfer request : External pins, Serial communication unit, Successive approximation type A/D converter, 16bit timer, and Functional timer • Low-speed Time base counter − Generate 8 frequency (128Hz to1Hz) internal pulse signals by dividing the Low-speed clock (LSCLK) − Selectable 3 interrupts from eight frequency internal pulse signals − 1Hz or 2Hz output from general purpose port − Built-in Frequency adjust function: Adjust range: Approximately -488ppm to +488ppm, adjust resolution: Approximately 0.119ppm • Simplified RTC − Channel: 1channel − Count by a unit for one second from "00 min. 00 sec" to "59 min. 59 sec" − Selectable Periodical interrupt request from four periods (0.5s, 1s, 30s or 60s) − Built-in minute and second writing error protraction function 3/74 FEDL62Q1700-0４ • Functional timer − Channel: Max. 8channel − Built-in timer, capture, and PWM function by 16 bit counter − One shot mode is available − Two types of PWM output with the same period and different duties, and complementary PWM output with the dead time − Monitor input signal duty and the period by capture function − Generate periodical interrupts, duty interrupts, and interrupts coincided with set value − Counter Start, Stop, Counter clear triggered by an external inputs or Timer − Generate Emergency stop and emergency stop interrupt triggered by an external input − Same start/stop among different channels of the functional timer − Selectable counter clock(external clock or divided by 1 to 128 of LSCLK or HSCLK) for each channels • 16-bit General timers − Channel: Max. 8channel ‒ 8 bits timer mode and 16-bit timer mode − Same start/stop among different channels of 16bit (8bit) timer ‒ Timer output (toggled by overflow) − Selectable counter clock (external clock or divided by 1 to 128 of LSCLK or HSCLK) for each channels • Serial communication unit − Synchronous Serial Port (SSIO) mode or UART mode is selectable − Channel: Max. 6channel < Synchronous Serial Port mode> ‒ Selectable from Master and Slave ‒ Selectable from LSB first or MSB first ‒ Selectable 8-bit length or 16-bit length < UART mode> ‒ Full-duplex communication mode and half-duplex communication mode ‒ 5 to 8 bit length, parity or no parity, odd parity or even parity, 1 stop bit or 2 stop bits ‒ Selectable from Positive logic or Negative logic ‒ Selectable from LSB first or MSB first ‒ Configurable wide range communication speed 32.768kHz operation clock : 1 bit/s to 4,800 bit/s 24MHz operation clock : 600 bit/s to 3M bit/s 16MHz operation clock : 300 bit/s to 2M bit/s ‒ Built-in baud rate generator • I2C bus unit (Master / Slave) ‒ Selectable from Master mode or Slave mode ‒ Channel: 1channel < Master function > ‒ Standard mode (100 kbit/s), fast mode (400 kbit/s) and 1Mbps mode(1Mbit/s) ‒ Handshake (Clock synchronization) ‒ 7bit address format (10bit address format is supported) < Slave function > ‒ Standard mode (100 kbit/s), fast mode (400 kbit/s) and 1Mbps mode(1Mbit/s) ‒ Clock stretch function ‒ 7bit address format • I2C bus Master ‒ Channel: 2channel ‒ Standard mode (100 kbit/s), fast mode (400 kbit/s) and 1Mbps mode(1Mbit/s) ‒ Handshake (Clock synchronization) ‒ 7bit address format (10bit address format is supported) 4/74 FEDL62Q1700-0４ • General-purpose ports (GPIO) ‒ I/O port : Max. 87 (Including one pin for on-chip debug and pins for other shared functions) ‒ Input port : Max. 2(Including a shared function) ‒ External interrupt port : Max. 12 ‒ LED driver por : Max. 86 ‒ Carrier frequency output function (for IR communication) • Successive approximation type A/D converter (SA-ADC) ‒ Channel: Max.16channel ‒ Resolution: 10bit ‒ Conversion time: Min. 2.25μs / channel (When the conversion clock is 8MHz) ‒ Reference voltages are selectable (VDD pin / Internal reference voltage(VREFI = Approximately 1.55V) / External reference voltage (VREF pin)) ‒ Selected channel repeat conversion ‒ dedicated result register for each channel ‒ Interrupt determining by upper limit or lower limit threshold of conversion result • Voltage Level Supervisor (VLS) ‒ Accuracy: ±4% ‒ Threshold voltage: 12 selectable (from 1.85V to 4.00V) ‒ Functional Voltage level detection reset (VLS reset) ‒ Functional Voltage level detection interrupt (VLS0 interrupt) • Analog comparator ‒ Channel: 2channel ‒ Selectable interrupt from the comparator output (rising edge or falling edge) ‒ Selectable from sampling or without sampling ‒ Comparable with external 2 inputs ‒ Comparable with external input and internal reference voltage (0.8V) • D/A converter ‒ Channel ‒ Resolution ‒ Output impedance ‒ R-2R ladder type : Max 2channel : 8bit : 6k ohm (Typ.) • Buzzer ‒ 4 buzzer mode (Continuous sound, Single sound, Intermittent sound 1 and Intermittent sound 2) ‒ 8frequencies (4.096kHz to 293Hz) ‒ 15 step duty (1/16 to 15/16) ‒ Selectable from positive logic buzzer output or negative logic buzzer output • CRC(Cyclic Redundancy Check) generator ‒ Generation equation: X16+X12+X5+1 ‒ Selectable from LSB first or MSB first ‒ Built-in Automatic program memory CRC calculation mode in HALT mode • LCD driver ‒ Max. 480 dots (60seg x 8 com) *1 ML62Q1700/1701/1702/1703/1704： 24seg×8com (com Max.), 29seg×3com (seg Max.) ML62Q1710/1711/1712/1713/1714： 27seg×8com (com Max.), 32seg×3com (seg Max.) ML62Q1720/1721/1722/1723/1724/ 1725/1726/1727/1728/1729： 35seg×8com (com Max.), 40seg×3com (seg Max.) ML62Q1733/1734/1735/1736/1737/1738/1739： 45seg×8com (com Max.), 50seg×3com (seg Max.) ML62Q1743/1744/1745/1746/1747/1748/1749： 60seg×8com (com Max.), 65seg×3com (seg Max.) *1 : Five pins are shared for common or segment, selectable by setting a SFR ‒ 1/3 bias (built-in bias generation circuit) ‒ Frame frequency (Approximately. 32Hz，38Hz，64Hz，75Hz，128Hz and 150Hz) 5/74 FEDL62Q1700-0４ ‒ Four bias generation modes (Internal voltage boost, External capacitive voltage divide, Internal capacitive voltage divide and External supply voltages) ‒ Contrast adjustment (32 steps) is available in the Internal voltage boost mode. • Safety Function (IEC60730/60335 Class B) ‒ Automatic switching to the internal low-speed RC oscillation in case the low-speed crystal oscillation stopped ‒ RAM/SFR guard ‒ Automatic program memory CRC calculation ‒ RAM parity error detection ‒ ROM unused area access reset (instruction access) ‒ Clock mutual monitoring ‒ WDT counter monitoring ‒ SA-ADC test ‒ UART test ‒ Synchronous serial I/O test ‒ I2C bus test ‒ GPIO test • Shipping package − − − − − − − 48-pin plastic TQFP ML62Q1700/1701/1702/1703/1704 - xxxTB (Blank part: ：ML62Q1700/1701/1702/1703/1704-NNNTB) 52-pin plastic TQFP ML62Q1710/1711/1712/1713/1714 - xxxTB (Blank part: ML62Q1710/1711/1712/1713/1714-NNNTB) 64-pin plastic TQFP ML62Q1720/1721/1722/1723/1724/1725/1726/1727/1728/1729 - xxxTB (Blank part: ML62Q1720/1721/1722/1723/1724/1725/1726/1727/1728/1729-NNNTB) 64-pin plastic QFP ML62Q1720/1721/1722/1723/1724/1725/1726/1727/1728/1729 - xxxGA (Blank part: ML62Q1720/1721/1722/1723/1724/1725/1726/1727/1728/1729-NNNGA) 80-pin plastic QFP ML62Q1733/1734/1735/1736/1737/1738/1739- xxxGA (Blank part: ML62Q1733/1734/1735/1736/1737/1738/1739-NNNGA) 100-pin plastic TQFP ML62Q1743/1744/1745/1746/1747/1748/1749 – xxxTB (Blank part: ML62Q1743/1744/1745/1746/1747/1748/1749-NNNTB) 100-pin plastic QFP ML62Q1743/1744/1745/1746/1747/1748/1749 - xxxGA (Blank part: ML62Q1743/1744/1745/1746/1747/1748/1749-NNNGA) xxx: ROM code number 6/74 FEDL62Q1700-0４ ML62Q1700 Group how to read the part number ML 62 Q 17 4 7 – xxx TB Package Type GA :QFP TB :TQFP ROM Code Number NNN :Blank xxx :Custom Code Number Program Memory Size 0 :32Kbyte 1 :48Kbyte 2 :64Kbyte 3 :96Kbyte 4 :128Kbyte 5 :160Kbyte 6 :192Kbyte 7 :256Kbyte 8 :384Kbyte 9 :512Kbyte Pin Count 0 :48pin 1 :52pin 2 :64pin 3 :80pin 4 :100pin Group Name 17 :1700 Group Program Memory Type Q :Flash Memory CPU Type 62 :16bit CPU nX-U16/100 LAPIS Technology Logic Product Figure 1 ML62Q1700 Group Part Number 7/74 FEDL62Q1700-0４ ML62Q1700 Group Main Function List Table 2 ML62Q1700 Group Main Function List Pin LCD drive pin Interrupt 66 3 5 1 43 87 86 1 1 2 2 4 45 45 100 12 35 5 67 2 8bit D/A converter [channel] 80 2 6 Analog comparator [input pin] 1 52 6 Analog comparator [channel] 53 10 Successive approximation type A/D converter [channel] 64 31 Analog I2C bus interface (Master only) [channel] 3 I2C bus unit (Master/Slave) [channel] 27 Serial communication unit (Full-duplex UART or Synchronous serial) [ channel h] *2 40 Serial Simplified RTC [channel] 41 16-bit Timer [channel] *1 52 Functional Timer [channel] 24 External interrupt [port] 36 Internal interrupt [source] 37 LCD bias pin LCD segment pin *5 LCD common pin *5 LED drive port 48 Input port *3 I/O port Reset Input pin Power pin counts Total pin-counts ML62Q1700 ML62Q1701 ML62Q1702 ML62Q1703 ML62Q1704 ML62Q1710 ML62Q1711 ML62Q1712 ML62Q1713 ML62Q1714 ML62Q1720 ML62Q1721 ML62Q1722 ML62Q1723 ML62Q1724 ML62Q1725 ML62Q1726 ML62Q1727 ML62Q1728 ML62Q1729 ML62Q1733 ML62Q1734 ML62Q1735 ML62Q1736 ML62Q1737 ML62Q1738 ML62Q1739 ML62Q1743 ML62Q1744 ML62Q1745 ML62Q1746 ML62Q1747 ML62Q1748 ML62Q1749 LCD common/segment shared pin *4 *5 Part number Timer 12 8 8 6 16 2 60 *1 : One 16bit timer is configurable as two 8bit timers *2 : Synchronous Communication unit includes UART mode and Synchronous Serial Port mode. UART mode and Synchronous Serial Port can not be used at the same time in the same channel. *3 : Shared with pins for crystal oscillation *4 : The LCD common/segment shared pins are shared for common or segment, selectable by setting a SFR *5 : All LCD drive pins are shared with general purpose I/O ports. 8/74 FEDL62Q1700-0４ BLOCK DIAGRAM CPU（nX-U16/100） EPSW1～3 ELR1～3 ECSR1～3 LR DSR/CSR EA PC Multiplier/Divider (Coprocessor) GREG 0 ～15 PSW Timing Controller ALU SP Instruction Decoder On-Chip ICE Instruction Register VDD VSS Program Memory （FLASH） BUS Controller INT SU0~5_SCLK* SU0~5_SIN* SU0~5_SOUT0* RAM VDDL VREFO * RESET_N TEST0* 2 Serial Communication Unit *1 Power Circuit Data FLASH SYSTEM FLASH Controller INT OUTLSCLK* OUTHSCLK* Clock Generation Circuit Interrupt Low-speed RC Oscillation High-speed PLL Oscillation RC Oscillation (for WDT) CMP0~1P* CMP0~1M* VL1,VL2,VL3 C 1,C 2 I2C Bus Master I2CM0~1_SDA* I2CM0~1_SCL* INT 16-Bit Timer CRC Generator INT SA-ADC Functional Timer Low Speed Time Base Counter Simplified RTC Buzzer Analog Comparator Safety Function D/A Converter Reset Function EXTRIG0～7 FTM0~7P* FTM0~7N* INT INT INT TMH0~7OUT* INT DMA Controller Low-speed Crystal Oscillation LCD Bias I2CU0_SDA* I2CU0_SCL* INT INT DACOUT0~1* I2C Bus Unit INT INT VLS VDD VSS VREF AIN0 to AIN15* INT INT WDT XT0 XT1 SU0~5_RXD0* SU0~5_TXD0* SU0~5_RXD1* SU0~5_TXD1* INT GPIO (External Interrupt) TBCOUT0* TBCOUT1* BZ0P* BZ0N* PX0~PX7 （X= 0~9,A,B) PI00,PI01*3 EXI0~11 COM0~COM2 COM3~COM7/ SEG0~SEG4 SEG5~SEG64 LCD Driver * : Indicates the shared function of general ports. *1 : Shared UART and Synchronous Serial Port. *2 : Not available as the input port when connecting to the on-chip debug emulator. *3 : Not available as the input port when connecting to the crystal resonator. Figure 2 ML62Q1700 Group Block Diagram 9/74 FEDL62Q1700-0４ PIN CONFIGURATION The pin names in the pin-layout indicate 1st-function or LCD function. Refer to Table-3 or Table-4 about other functions. 25 24 37 36 P30/SEG49 P14/SEG22 P15/SEG23 P16/SEG24 P17/EXI3/EXTRG3/SEG25 P20/SEG26 P21/EXI4/EXTRG4/SEG27 P22/SEG28 P23/EXI5/EXTRG5/SEG29/VREF P24/SEG30 P25/SEG31 P26/EXI6/EXTRG6/SEG32 P27/EXI7/EXTRG7/SEG33 Pin Layout of 48pin TQFP Package P50/EXI8/SEG5 P31/SEG50 P13/COM7/SEG4 P32/SEG51 P12/COM6/SEG3 P33/SEG52 P11/COM5/SEG2 P60/SEG53 P10/COM4/SEG1 TOP VIEW TQFP48 P61/SEG54 P62/SEG55 P63/SEG56 P07/COM3/SEG0 P06/COM2 P05/COM1 P04/EXI2/EXTRG2/COM0 P64/EXI9/SEG57 P66/SEG59 VL2 P43 VL1 13 VL3 48 P65/SEG58 C2 C1 P03/EXI1/EXTRG1 P02/EXI0/EXTRG0 P01/DACOUT0 P00/TEST0 RESET_N VDDL VSS VDD 12 XT1/PI01 XT0/PI00 1 Figure 3 Pin Layout of 48pin TQFP Package 10/74 FEDL62Q1700-0４ 39 26 27 40 P41/SEG48 P14/SEG22 P15/SEG23 P16/SEG24 P17/EXI3/EXTRG3/SEG25 P20/SEG26 P21/EXI4/EXTRG4/SEG27 P22/SEG28 P24/SEG30 P23/EXI5/EXTRG5/SEG29/VREF P25/SEG31 P26/EXI6/EXTRG6/SEG32 P27/EXI7/EXTRG7/SEG33 P56/SEG34 Pin Layout of 52pin TQFP Package P51/SEG6 P30/SEG49 P50/EXI8/SEG5 P31/SEG50 P13/COM7/SEG4 P32/SEG51 P12/COM6/SEG3 P33/SEG52 P11/COM5/SEG2 P60/SEG53 P10/COM4/SEG1 TOP VIEW TQFP52 P61/SEG54 P62/SEG55 P07/COM3/SEG0 P06/COM2 P63/SEG56 P05/COM1 P64/EXI9/SEG57 P04/EXI2/EXTRG2/COM0 VL2 P43 VL1 14 VL3 P66/SEG59 52 P65/SEG58 C1 P47 P03/EXI1/EXTRG1 P02/EXI0/EXTRG0 P00/TEST0 P01/DACOUT0 RESET_N VDDL VSS VDD XT1/PI01 XT0/PI00 C2 13 1 Figure 4 Pin Layout of 52pin TQFP52 Package 11/74 FEDL62Q1700-0４ 32 P40/SEG47 33 49 48 P54/SEG20 P55/SEG21 P14/SEG22 P16/SEG24 P15/SEG23 P17/EXI3/EXTRG3/SEG25 P20/SEG26 P21/EXI4/EXTRG4/SEG27 P22/SEG28 P23/EXI5/EXTRG5/SEG29/VREF P24/SEG30 P25/SEG31 P26/EXI6/EXTRG6/SEG32 P27/EXI7/EXTRG7/SEG33 P56/SEG34 P57/SEG35 Pin Layout of 64pin TQFP/QFP Package P53/SEG8 P41/SEG48 P52/SEG7 P30/SEG49 P51/SEG6 P31/SEG50 P50/EXI8/SEG5 P32/SEG51 P13/COM7/SEG4 P33/SEG52 P12/COM6/SEG3 P60/SEG53 P11/COM5/SEG2 TOP VIEW TQFP64/QFP64 P61/SEG54 P62/SEG55 P10/COM4/SEG1 P07/COM3/SEG0 P63/SEG56 P06/COM2 P64/EXI9/SEG57 P05/COM1 P70 P67/SEG60 VL3 P42/SEG61 VL2 P43 VL1 17 P04/EXI2/EXTRG2/COM0 P66/SEG59 64 P65/SEG58 C2 C1 P47 P46 P03/EXI1/EXTRG1 P02/EXI0/EXTRG0 P45 P44/DACOUT1 P01/DACOUT0 P00/TEST0 RESET_N VDDL VSS VDD 16 XT1/PI01 XT0/PI00 1 Figure 5 Pin Layout of 64pin TQFP/QFP Package 12/74 FEDL62Q1700-0４ 40 PB2/SEG43 41 61 60 NC VDD P54/SEG20 P55/SEG21 P14/SEG22 P15/SEG23 P16/SEG24 P17/EXI3/EXTRG3/SEG25 P20/SEG26 P21/EXI4/EXTRG4/SEG27 P23/EXI5/EXTRG5/SEG29/VREF P22/SEG28 P24/SEG30 P25/SEG31 P26/EXI6/EXTRG6/SEG32 P27/EXI7/EXTRG7/SEG33 P56/SEG34 P57/SEG35 PA3/EXI11/SEG36 PA4/SEG37 Pin Layout of 80pin QFP Package P96/SEG15 PB3/SEG44 P95/SEG14 PB4/SEG45 P94/SEG13 PB5/SEG46 P93/SEG12 P40/SEG47 P53/SEG8 P41/SEG48 P52/SEG7 P30/SEG49 P51/SEG6 P31/SEG50 P50/EXI8/SEG5 P32/SEG51 P13/COM7/SEG4 TOP VIEW QFP80 P33/SEG52 P60/SEG53 P61/SEG54 P12/COM6/SEG3 P11/COM5/SEG2 P10/COM4/SEG1 P62/SEG55 P07/COM3/SEG0 P63/SEG56 P06/COM2 P64/EXI9/SEG57 P05/COM1 P70 P67/SEG60 VL3 P42/SEG61 VL2 P43 VL1 21 P04/EXI2/EXTRG2/COM0 P66/SEG59 80 P65/SEG58 C2 C1 P76/EXI10 P47 P46 P03/EXI1/EXTRG1 P02/EXI0/EXTRG0 P45 P82 P44/DACOUT1 P81 P80 P01/DACOUT0 P00/TEST0 RESET_N VSS VDDL VDD 20 XT1/PI01 XT0/PI00 1 Figure 6 Pin Layout of 80pin QFP Package 13/74 FEDL62Q1700-0４ 50 PB0/SEG41 51 76 75 NC VDD PA1/SEG18 PA2/SEG19 P54/SEG20 P55/SEG21 P14/SEG22 P15/SEG23 P16/SEG24 P17/EXI3/EXTRG3/SEG25 P20/SEG26 P21/EXI4/EXTRG4/SEG27 P22/SEG28 P24/SEG30 P23/EXI5/EXTRG5/SEG29/VREF P25/SEG31 P26/EXI6/EXTRG6/SEG32 P27/EXI7/EXTRG7/SEG33 P56/SEG34 PA3/EXI11/SEG36 P57/SEG35 PA4/SEG37 PA5/SEG38 PA6/SEG39 PA7/SEG40 Pin Layout of 100pin TQFP Package PA0/SEG17 PB1/SEG42 P97/SEG16 PB2/SEG43 P96/SEG15 PB3/SEG44 P95/SEG14 PB4/SEG45 P94/SEG13 PB5/SEG46 P93/SEG12 P40/SEG47 P92/SEG11 P41/SEG48 P91/SEG10 P30/SEG49 P90/SEG9 P31/SEG50 P53/SEG8 P32/SEG51 P52/SEG7 P33/SEG52 P51/SEG6 TOP VIEW TQFP100 P60/SEG53 P61/SEG54 P50/EXI8/SEG5 P13/COM7/SEG4 P12/COM6/SEG3 P63/SEG56 P11/COM5/SEG2 P64/EXI9/SEG57 P10/COM4/SEG1 P65/SEG58 P07/COM3/SEG0 P66/SEG59 P06/COM2 P67/SEG60 P05/COM1 P42/SEG61 P04/EXI2/EXTRG2/COM0 PB6/SEG62 P70 PB7/SEG63 VL3 P77/SEG64 VL2 26 VL1 C2 C1 P76/EXI10 P47 P46 P03/EXI1/EXTRG1 P02/EXI0/EXTRG0 P45 P44/DACOUT1 P87 P86 P85 P84 P83 P82 P81 P80 P00/TEST0 P01/DACOUT0 RESET_N VDDL VSS VDD 25 XT1/PI01 1 XT0/PI00 P43 100 P62/SEG55 Figure 7 Pin Layout of 100pin TQFP Package 14/74 FEDL62Q1700-0４ 50 PB3/SEG44 51 81 80 P97/SEG16 PA0/SEG17 NC VDD PA1/SEG18 PA2/SEG19 P54/SEG20 P14/SEG22 P55/SEG21 P15/SEG23 P16/SEG24 P17/EXI3/EXTRG3/SEG25 P20/SEG26 P21/EXI4/EXTRG4/SEG27 P22/SEG28 P24/SEG30 P23/EXI5/EXTRG5/SEG29/VREF P25/SEG31 P26/EXI6/EXTRG6/SEG32 P27/EXI7/EXTRG7/SEG33 P56/SEG34 P57/SEG35 PA3/EXI11/SEG36 PA4/SEG37 PA5/SEG38 PA6/SEG39 PA7/SEG40 PB0/SEG41 PB1/SEG42 PB2/SEG43 Pin Layout of 100pin QFP Package P96/SEG15 PB4/SEG45 P95/SEG14 PB5/SEG46 P94/SEG13 P40/SEG47 P93/SEG12 P41/SEG48 P92/SEG11 P30/SEG49 P91/SEG10 P31/SEG50 P90/SEG9 P32/SEG51 P53/SEG8 P33/SEG52 P52/SEG7 TOP VIEW QFP100 P60/SEG53 P61/SEG54 P51/SEG6 P50/EXI8/SEG5 P13/COM7/SEG4 P63/SEG56 P12/COM6/SEG3 P64/EXI9/SEG57 P11/COM5/SEG2 P65/SEG58 P10/COM4/SEG1 P66/SEG59 P07/COM3/SEG0 P67/SEG60 P06/COM2 P42/SEG61 P05/COM1 PB6/SEG62 P04/EXI2/EXTRG2/COM0 31 P70 VL3 VL2 VL1 C2 C1 P47 P76/EXI10 P46 P03/EXI1/EXTRG1 P02/EXI0/EXTRG0 P45 P44/DACOUT1 P87 P86 P85 P84 P83 P82 P81 P80 P01/DACOUT0 P00/TEST0 RESET_N VDDL VSS VDD XT1/PI01 XT0/PI00 30 P43 1 P77/SEG64 PB7/SEG63 100 P62/SEG55 Figure 8 Pin Layout of 100pin QFP Package 15/74 FEDL62Q1700-0４ PIN LIST Table 3 Pin List (1/3) Pin No. 48 Pin 52 Pin 64 Pin 80 pin TQFP100 QFP100 Pin name st (1 func) 3 3 3 3 3 5 VDD st 1 func. others 2 nd func. SIU rd th th th th th 3 func. SIU 4 func. I2C 5 func. Timer 6 func. others 7 func. others 8 func. ADC - - - - - - - - - - - 42 52 54 VDD - - - - - - - - 4 4 4 4 VSS - - - - - - - - 4 6 - - - 41 51 53 NC - - - - - - - - 5 5 5 5 5 7 VDDL - - - - - - - - 1 1 1 1 1 3 XT0 PI00 - - - - - - - 2 2 2 2 2 4 XT1 PI01 - - - - - - - 6 6 6 6 6 8 RESET_N RESET_N - - - - - - - 7 7 7 7 7 9 P00 TEST0 - - - - - - 8 8 8 8 8 10 P01 DACOUT0 - - - FTM3P *1 TBCOUT0 TBCOUT1 - FTM0P OUTLSCLK CMP0M - FTM0N OUTHSCLK CMP0P AIN11 - - - 9 EXI0 EXTRG0 EXI1 EXTRG1 EXI2 EXTRG2 COM0 SU0_RXD0 I2CU0_SCL SU0_SIN *1 SU0_TXD0 SU0_TXD1 I2CU0_SDA SU0_SOUT 9 11 14 19 21 P02 10 10 12 15 20 22 P03 16 17 21 25 30 32 P04 17 18 22 26 31 33 P05 18 19 23 27 32 34 P06 19 20 24 28 33 35 P07 20 21 25 29 34 36 P10 21 22 26 30 35 37 P11 22 23 27 31 36 38 P12 23 24 28 32 37 39 P13 25 27 35 45 57 59 P14 SEG22 - 26 28 36 46 58 60 P15 SEG23 - 27 29 37 47 59 61 P16 SU1_SCLK 28 30 38 48 60 62 P17 29 31 39 49 61 63 P20 30 32 40 50 62 64 P21 SEG24 EXI3 EXTRG3 SEG25 SEG26 EXI4 EXTRG4 SEG27 31 33 41 51 63 65 P22 SEG28 32 34 42 52 64 66 P23 EXI5 EXTRG5 SEG29 VREF 33 35 43 53 65 67 P24 SEG30 34 36 44 54 66 68 P25 SEG31 35 37 45 55 67 69 P26 36 38 46 56 68 70 P27 SU0_SCLK - COM1 - - - - - - - COM2 COM3 SEG0 COM4 SEG1 COM5 SEG2 COM6 SEG3 COM7 SEG4 - - I2CM0_SDA - - - - SU0_RXD1 SU0_RXD0 I2CM0_SCL - - - - SU0_TXD1 - - - - - - SU0_SCLK - - - - - - - TMH4OUT - - - - TMH1OUT - TMH3OUT - - - - - - - - I2CU0_SDA - - - - - I2CU0_SCL TMH5OUT - - - EXI6 EXTRG6 SEG32 EXI7 EXTRG7 SEG33 SU0_RXD0 SU0_SIN SU0_TXD0 SU0_TXD1 SU0_SOUT I2CU0_SCL TMH0OUT SU0_RXD1 SU0_RXD0 - FTM1P TBCOUT0 BZ0P AIN0 SU0_TXD1 - - FTM1N TBCOUT1 BZ0N AIN1 SU1_RXD0 SU1_SIN - - FTM2P OUTLSCLK - AIN2 FTM2N OUTHSCLK - AIN3 - - VREFO SU1_TXD0 SU1_TXD1 I2CM0_SDA SU1_SOUT SU1_SCLK - SU1_RXD0 SU1_SIN SU1_TXD0 SU1_TXD1 SU1_SOUT I2CM0_SCL TMH2OUT - - - - AIN4 - - - - AIN5 SU1_RXD1 SU1_RXD0 I2CU0_SDA FTM3P TBCOUT0 BZ0P AIN6 SU1_TXD1 FTM3N TBCOUT1 BZ0N AIN7 - I2CU0_SCL *1: No assignment to ML62Q1500 Series. 16/74 FEDL62Q1700-0４ Table 3 Pin List (2/3) Pin No. QFP100 80 pin 64 Pin 52 Pin 48 Pin TQFP100 st Pin name st (1 func) 1 func. others 2 nd func. SIU *3 rd th th th th th 3 func. SIU *3 4 func. I2C 5 func. Timer *3 6 func. others 7 func. others 8 func. ADC *3 - - - - - - - - - 37 41 51 67 84 86 P30 SEG49 38 42 52 68 85 87 P31 SEG50 - - TBCOUT0 TBCOUT1 - 39 43 53 69 86 88 P32 SEG51 SU1_RXD1 SU1_RXD0 - - - - - 40 44 54 70 87 89 - P33 SEG52 SU1_TXD1 - - TMH3OUT - - - 49 65 82 84 P40 SEG47 SU5_TXD1 - - - - - - 40 50 66 83 85 - P41 SEG48 - - - - - - - 63 79 96 98 P42 SEG61 SU3_TXD1 - - - - - - 48 52 64 80 100 2 P43 - - - - TBCOUT0 TBCOUT1 AIN10 - - - I2CU0_SDA *1 I2CU0_SCL *2 FTM3N *1 FTM1N *1 FTM1P *1 - - - - - - - - - - - - - - - - - - 9 12 17 19 P44 - - 10 13 18 20 P45 - SU4_TXD1 - - - 13 16 21 23 P46 - - - 11 14 17 22 24 P47 - SU0_SCLK *1 - 24 25 29 33 38 40 P50 - - - - - DACOUT1 SU4_RXD1 SU4_RXD0 P51 EXI8 SEG5 SEG6 - - 31 35 40 42 P52 SEG7 - - 32 36 41 43 P53 SEG8 SU4_TXD1 - - 33 43 55 57 P54 SEG20 SU2_RXD1 SU2_RXD0 - - 34 44 56 58 P55 SEG21 39 47 57 69 71 P56 SEG34 48 58 70 72 P57 SEG35 SU2_TXD1 SU2_RXD0 SU2_SIN SU2_TXD0 SU2_TXD1 SU2_SOUT 41 45 55 71 88 90 P60 SEG53 - 42 46 56 72 89 91 P61 SEG54 43 47 57 73 90 92 P62 SEG55 44 48 58 74 91 93 P63 SEG56 45 49 59 75 92 94 P64 EXI9 SEG57 46 50 60 76 93 95 P65 SEG58 47 51 61 77 94 96 P66 SEG59 SU3_SCLK SU3_RXD1 SU3_RXD0 - - 26 30 34 39 41 - - - 62 78 95 97 P67 SEG60 - - - - - - - - - - - - - - - - - - - TMH7OUT - - - - - - - - - - - - AIN12 - - - - AIN13 - I2CM1_SCL - - - - - - I2CM1_SDA - - - - - - - FTM4N - CMP1P - - - - FTM4P - CMP1M - - FTM5P - - - - FTM5N - - AIN8 - - - - AIN9 - - - - - SU4_RXD1 SU4_RXD0 - SU3_RXD0 SU3_SIN SU3_TXD0 SU3_TXD1 SU3_SOUT - 20 24 29 31 P70 - - - - TMH6OUT - - - 15 16 19 23 28 30 VL3 - - - - - - - - 14 15 18 22 27 29 VL2 - - - - - - - - 13 14 17 21 26 28 VL1 - - - - - - - - 12 13 16 20 25 27 C2 - - - - - - - - 11 12 15 19 24 26 C1 - - - - - - - - P76 EXI10 - - - - - - - P77 SEG64 - - - - - - - - - - - - - 18 23 25 - 99 1 *1: No assignment to ML62Q1500 Series. *2: No assignment to ML62Q1500 Series and products of 52 PIN-package. *3: The pins of name with DACOUT1, SU2, SU3, SU4, SU5, TMH6, TMH7, AIN12 or AIN13 are not assigned to products of 48/52/64 PIN-packages. 17/74 FEDL62Q1700-0４ Table 3 Pin List (3/3) Pin No. th th th - - - 9 9 11 P80 - - - - 10 10 12 P81 - - - - 11 11 13 P82 - SU4_SCLK - - - - 12 14 P83 - SU5_RXD0 - - - - 13 15 P84 - - - - - 14 16 P85 - - - - - 15 17 P86 - - - - - - - - 16 18 P87 - - - - - - - - 42 44 P90 SEG9 - - - - - - - - - - - 43 45 P91 SEG10 - - - - - - - - - - - 44 46 P92 SEG11 - - - - - - - - FTM6P - - - - FTM6N - - - QFP100 TQFP100 th 80 pin th 64 Pin rd 52 Pin nd 48 Pin st Pin name st (1 func) 1 func. others 2 func. SIU 3 func. SIU SU4_RXD0 SU4_SIN SU4_TXD0 SU4_TXD1 SU4_SOUT - SU5_TXD1 SU5_TXD0 *1 - SU4_RXD0 SU4_SIN SU4_TXD0 SU4_TXD1 SU4_SOUT 4 func. I2C 5 func. Timer 6 func. others 7 func. others 8 func. ADC - - - - - - - - - - - - - - - - - - - - - - - - - - FTM7P *1 FTM7N *1 - - - - - - - - - - - - 37 45 47 P93 SEG12 - - - 38 46 48 P94 SEG13 - - - 39 47 49 P95 SEG14 SU4_SCLK - - - - - - - - - 40 48 50 P96 SEG15 - - - - - - - - - - - 49 51 P97 SEG16 - - - - - - - - - - - 50 52 PA0 SEG17 - - - - - - - - - - - 53 55 PA1 SEG18 - - - - - - - - - - - 54 56 PA2 SEG19 - - - - - - - SU2_SCLK - - FTM7P - - AIN14 - - - 59 71 73 PA3 EXI11 SEG36 - - - 60 72 74 PA4 SEG37 - - - FTM7N - - AIN15 - - - - 73 75 PA5 SEG38 - - - - - - - - - - - 74 76 PA6 SEG39 - - - - - - - - - - - 75 77 PA7 SEG40 - - - - - - - - - - - 76 78 PB0 SEG41 - - - - - - - - - - - 77 79 PB1 SEG42 - - - - - - - - 61 78 80 PB2 SEG43 - - - - - - - - 62 79 81 PB3 SEG44 - - - - - - - - 63 80 82 PB4 SEG45 SU5_RXD0 SU5_SIN SU5_TXD0 SU5_TXD1 SU5_SOUT SU5_SCLK - - - - - - - - - 64 81 83 PB5 SEG46 SU5_RXD1 SU5_RXD0 - - - - - - - - - 97 99 PB6 SEG62 - - - - - - - - - - - 98 100 PB7 SEG63 - - - - - - - *1: No assignment to ML62Q1500 Series. 18/74 FEDL62Q1700-0４ PIN DESCRIPTION Table 4 Pin Description (1/7) Function Signal name － Pin name VSS I/O － － VDD － － VDDL － Test TEST0 P00 I/O Un used NC NC － Connect to VSS. VREFO P23 － RESET_N RESET_N I XT0 XT0 I XT1 XT1 P02 P21 P03 P22 O － Reference voltage output Reset input. Applying “L” level shifts the MCU in system reset mode. Applying “H” level shifts the CPU in program running Negative mode. Used for on-chip debug interface and ISP function. No pull-up resistor is installed. Low speed crystal oscillation pins － Connect 32.768kHz crystal resonator and Connect － capacitors between the pin and VSS. O Low-speed clock output. － O High-speed clock output. － PI00, PI01 XT0, XT1 I P00 P00 I/O P01 – P07 P10 – P17 P20 – P27 P30 – P33 P40 – P47 P50 – P57 P60 – P67 P70,P76, P77 P80 – P87 P90 – P97 PA0 – PA7 PB0 – PB7 P01 – P07 P10 – P17 P20 – P27 P30 – P33 P40 – P47 P50 – P57 P60 – P67 P70, P76, P77 P80 – P87 P90 – P97 PA0 – PA7 PB0 – PB7 Power System OUTLSCLK OUTHSCLK General input port (GPI) General port (GPIO) I/O Description Negative power supply pin (-) Positive power supply pin (+). Connect a capacitor CV between this pin and VSS. Power supply pin for internal logic (internal regulator’s output). Connect a capacitor CL (1μF) between this pin and VSS. Input for testing, is used as on-chip debug interface and ISP function. P00 is initialized as pull-up input mode by the system reset. Logic － － － － － General purpose input. Not available as general inputs when using the crystal Positive resonator. General purpose I/O port - High-impedance - Input with Pull-UP (initial value) - Input without Pull-UP Positive - CMOS output - N-channel open drain output Not available to use as I/O pin when using for on-chip debug interface or ISP function. General purpose I/O - High-impedance (initial value) - Input with Pull-UP - Input without Pull-UP - CMOS output - N-channel open drain output Positive 19/74 FEDL62Q1700-0４ Table 4 Pin Description (2/7) Function Signal name SU0_TXD0 SU0_RXD0 SU0_TXD1 SU0_RXD1 SU1_TXD0 SU1_RXD0 SU1_TXD1 SU1_RXD1 SU2_TXD0 SU2_RXD0 UART SU2_TXD1 SU2_RXD1 SU3_TXD0 SU3_RXD0 SU3_TXD1 SU3_RXD1 SU4_TXD0 SU4_RXD0 SU4_TXD1 SU4_RXD1 SU5_TXD0 SU5_RXD0 SU5_TXD1 SU5_RXD1 Pin name P03 P13 P02 P07 P12 P17 P03 P10 P13 P20 P07 P17 P22 P25 P21 P24 P26 P32 P22 P25 P27 P33 P26 P32 P57 P54 P56 P55 P57 P54 P65 P64 P67 P42 P65 P67 P81 P94 P44 P52 P80 P93 P45 P53 P81 P94 P44 P52 P84 PB3 P83 PB2 PB5 P40 P84 PB3 PB5 I/O Description Logic O Serial communication unit0 UART0 data output Positive I Serial communication unit0 Full-duplex data input Serial communication unit0 UART0 data input Positive O Serial communication unit0 Full-duplex data output Serial communication unit0 UART1 data output Positive I Serial communication unit0 UART1 data input Positive O Serial communication unit1 UART0 data output Positive I Serial communication unit1 Full-duplex data input Serial communication unit1 UART0 data input Positive O Serial communication unit1 Full-duplex data output Serial communication unit1 UART1 data output Positive I Serial communication unit1 UART1 data input Positive O Positive I Serial communication unit2 UART0 data output Serial communication unit2 Full-duplex data input Serial communication unit2 UART0 data input Serial communication unit2 Full-duplex data output Serial communication unit2 UART1 data output Serial communication unit2 UART1 data input Serial communication unit3 UART0 data output Serial communication unit3 Full-duplex data input Serial communication unit3 UART0 data input Serial communication unit3 Full-duplex data output Serial communication unit3 UART1 data output Serial communication unit3 UART1 data input O Serial communication unit4 UART0 data output Positive I Serial communication unit4 Full-duplex data input Serial communication unit4 UART0 data input Positive O Serial communication unit4 Full-duplex data output Serial communication unit4 UART1 data output. Positive I Serial communication unit4 UART1 data input Positive O Serial communication unit5 UART0 data output Positive I Serial communication unit5 Full-duplex data input Serial communication unit5 UART0 data input Positive O Serial communication unit5 Full-duplex data output Serial communication unit5 UART1 data output. Positive I Serial communication unit5 UART1 data input Positive I O I O I O Positive Positive Positive Positive Positive Positive Positive 20/74 FEDL62Q1700-0４ Table 4 Pin Description (3/7) Function Signal name Pin name P02 P12 P04 P11 P47 P03 P13 P21 P24 P16 P23 P22 P25 P56 I/O SU2_SCLK PA3 I/O SU2_SOUT P57 O SU3_SIN P64 I SU3_SCLK P66 I/O SU3_SOUT P65 O SU0_SIN SU0_SCLK SU0_SOUT SU1_SIN SU1_SCLK SU1_SOUT SU2_SIN Synchronous Serial Port Positive O Serial communication unit0 Synchronous serial data output Positive I Serial communication unit1 Synchronous serial data input Positive I/O Serial communication unit1 Synchronous serial clock I/O Positive O Serial communication unit1 Synchronous serial data output Positive I SU5_SIN PB2 I SU5_SCLK PB4 I/O SU5_SOUT PB3 O SU4_SOUT I2CU0_SDA I2CU0_SCL 2 I2CM0_SDA P03 P15 P26 P46 P02 P04 P16 P27 P47 P06 P22 I O P23 Serial communication unit2 Synchronous serial data Serial communication unit2 Synchronous serial clock I/O Serial communication unit2 Synchronous serial data output Serial communication unit3 Synchronous serial data input Serial communication unit3 Synchronous serial clock I/O Serial communication unit3 Synchronous serial data output Serial communication unit4 Synchronous serial data input Serial communication unit4 Synchronous serial clock I/O Serial communication unit4 Synchronous serial data output Serial communication unit5 Synchronous serial data input Serial communication unit5 Synchronous serial clock I/O Serial communication unit5 Synchronous serial data output Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive 2 I/O I C Unit0 (Master and Salve) Data I/O N-channel open drain Connect a pull-up resistor externally I/O I C Unit0 (Master and Salve) Clock I/O N-channel open drain output Connect a pull-up resistor externally Positive 2 Positive 2 I/O P07 I2CM0_SCL Positive Serial communication unit0 Synchronous serial clock I/O I/O SU4_SCLK Logic I/O P80 P93 P82 P95 P81 P94 SU4_SIN I C Bus I Description Serial communication unit0 Synchronous serial data input I/O I2CM1_SDA P61 I/O I2CM1_SCL P60 I/O I C Master0 Data I/O pin N-channel open drain output Connect a pull-up resistor externally 2 I C Master0 Clock I/O N-channel open drain output Connect a pull-up resistor externally 2 I C Master1 Data I/O N-channel open drain output Connect a pull-up resistor externally 2 I C Master1 Clock I/O N-channel open drain output Connect a pull-up resistor externally Positive Positive Positive Positive 21/74 FEDL62Q1700-0４ Table 4 Pin Description (4/7) Function Signal name FTM0P FTM0N FTM1P FTM1N FTM2P FTM2N FTM3P FTM3N Functional Timer (FTM) FTM4P FTM4N FTM5P FTM5N FTM6P FTM6N FTM7P FTM7N EXTRG0 EXTRG1 EXTRG2 EXTRG3 EXTRG4 EXTRG5 EXTRG6 EXTRG7 TMH0OUT TMH1OUT TMH2OUT TMH3OUT 16-bit Timer TMH4OUT TMH5OUT TMH6OUT TMH7OUT EXTRG0 EXTRG1 TBCOUT0 Low-speed Time Base Counter (LTBC) TBCOUT1 BZ0P Buzzer BZ0N Pin name P02 P03 P17 P47 P20 P46 P21 P22 P01 P26 P27 P44 P63 P62 P64 P65 P93 P94 P86 PA3 P87 PA4 P02 P03 P04 P17 P21 P23 P26 P27 P04 P13 P23 P13 P33 P12 P16 P70 P54 P02 P03 P01 P17 P26 P31 P43 P01 P20 P27 P31 P43 P17 P26 P20 P27 I/O O O Description Functional Timer0 P output Functional Timer0 N output Logic Positive Negative O Functional Timer1 P output Positive O Functional Timer1 N output Negative O O Functional Timer2 P output Functional Timer2 N output Positive Negative O Functional Timer3 P output Positive O Functional Timer3 N output Negative O O O O O O O Functional Timer4 P output Functional Timer4 N output Functional Timer5 P output Functional Timer5 N output Functional Timer6 P output Functional Timer6 N output Positive Negative Positive Negative Positive Negative Functional Timer7 P output Positive Functional Timer7 N output Negative I I I I I I I I O O O Functional Timer event trigger input Functional Timer event trigger input Functional Timer event trigger input Functional Timer event trigger input Functional Timer event trigger input Functional Timer event trigger input Functional Timer event trigger input Functional Timer event trigger input 16bit General Timer 0 output 16bit General Timer 1 output 16bit General Timer 2 output O 16bit General Timer 3 output — — — — — — — — Positive Positive Positive Positive O O O O I I 16bit General Timer 4 output 16bit General Timer 5 output 16bit General Timer 6 output 16bit General Timer 7 output 16bit Timer trigger input 16bit Timer trigger input Positive Positive Positive Positive — — O The virtual frequency adjustment signal output or The low speed time base counter output signal Positive O 1Hz/2Hz clock output for the Simplified RTC Positive O Buzzer output (positive phase) Positive O Buzzer output (negative phase) Negative O 22/74 FEDL62Q1700-0４ Table 4 Pin Description (5/7) Function External Interrupt Successive approximation type A/D converter (SA-ADC) Analog comparator D/A converter Signal name EXI0 EXI1 EXI2 EXI3 EXI4 EXI5 EXI6 EXI7 EXI8 EXI9 EXI10 EXI11 VREF AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11 AIN12 AIN13 AIN14 AIN15 CMP0P CMP0M CMP1P CMP1M DACOUT0 DACOUT1 Pin name P02 P03 P04 P17 P21 P23 P26 P27 P50 P64 P76 PA3 P23 P17 P20 P21 P22 P24 P25 P26 P27 P65 P66 P43 P03 P56 P57 PA3 PA4 P03 P02 P62 P63 P01 P44 I/O I I I I I I I I I I I I － I I I I I I I I I I I I I I I I I I I I O O Description External Interrupt 0 Input External Interrupt 1 Input External Interrupt 2 Input External Interrupt 3 Input External Interrupt 4 Input External Interrupt 5 Input External Interrupt 6 Input External Interrupt 7 Input External Interrupt 8 Input External Interrupt 9 Input External Interrupt 10 Input External Interrupt 11 Input SA-ADC external reference voltage input SA-ADC channel 0 input SA-ADC channel 1 input SA-ADC channel 2 input SA-ADC channel 3 input SA-ADC channel 4 input SA-ADC channel 5 input SA-ADC channel 6 input SA-ADC channel 7 input SA-ADC channel 8 input SA-ADC channel 9 input SA-ADC channel 10 input SA-ADC channel 11 input SA-ADC channel 12 input SA-ADC channel 13 input SA-ADC channel 14 input SA-ADC channel 15 input Comparator input 0 (noninverting input) Comparator input 0 (inverting input) Comparator input 1 (noninverting input) Comparator input 1 (inverting input) D/A converter 0 output D/A converter 1 output Logic — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 23/74 FEDL62Q1700-0４ Table 4 Pin Description (6/7) Function LCD driver Signal name COM0 COM1 COM2 COM3/SEG0 COM4/SEG1 COM5/SEG2 COM6/SEG3 COM7/SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 Pin name P04 P05 P06 P07 P10 P11 P12 P13 P50 P51 P52 P53 P90 P91 P92 P93 P94 P95 P96 P97 PA0 PA1 PA2 P54 P55 P14 P15 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 P56 P57 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 I/O － － － － － － － － － － － － － － － － － － － － － － － － － － － － － － － － － － － － － － － － － － － － － － － － － － Description Common output Common output Common output Common/Segment output shared Common/Segment output shared Common/Segment output shared Common/Segment output shared Common/Segment output shared Segment output Segment output Segment output Segment output Segment output Segment output Segment output Segment output Segment output Segment output Segment output Segment output Segment output Segment output Segment output Segment output Segment output Segment output Segment output Segment output Segment output Segment output Segment output Segment output Segment output Segment output Segment output Segment output Segment output Segment output Segment output Segment output Segment output Segment output Segment output Segment output Segment output Segment output Segment output Segment output Segment output Segment output Logic — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 24/74 FEDL62Q1700-0４ Table 4 Pin Description (7/7) Function LCD driver Signal name SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 Pin name P40 P41 P30 P31 P32 P33 P60 P61 P62 P63 P64 P65 P66 P67 P42 PB6 PB7 P77 C1,C2 C1,C2 VL1~VL3 VL1~VL3 I/O － － － － － － － － － － － － － － － － － － － － Description Segment output Segment output Segment output Segment output Segment output Segment output Segment output Segment output Segment output Segment output Segment output Segment output Segment output Segment output Segment output Segment output Segment output Segment output LCD bias power source generation capacitor connection LCD bias power source Connect the capacitors (CL1,CL2,CL3) between the pin and Vss. Logic — — — — — — — — — — — — — — — — — — — — 25/74 FEDL62Q1700-0４ TERMINATION OF UNUSED PINS Table 5 Termination of unused pins Pin NC RESET_N P00/TEST0 XT0/PI00, XT1/PI01 P01 to P07 P10 to P17 P20 to P27 P30 to P33 P40 to P47 P50 to P57 P60 to P67 P70, P76 , P77 P80 to P87 P90 to P97 PA0 to PA7 PB0 to PB7 C1,C2 VL1,VL2 VL3 pin termination Connect to VSS Connect to VDD Connect to VDD with initial state (pulled-up input mode) Open the pins with the internal initial condition of Hi-impedance mode. Open Open It is recommended to connect to VDD through a resistor (1kΩ or more). Note:  Terminate unused input pins according to the table 5 in order to avoid unexpected through-current in the pins. 26/74 FEDL62Q1700-0４ ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (VSS = 0V) Parameter Symbol Condition Rating Unit Power supply voltage 1 VDD Ta = +25°C -0.3 to +6.5 V Power supply voltage 2 VDDL Ta = +25°C -0.3 to +2.0 V Power supply voltage 3 VL3 Ta = +25°C -0.3 to +6.5 Power supply voltage 4 VL1 ,VL2 Ta = +25°C -0.3 to VL3+0.3* V 1 V 1 V 1 Input voltage VIN Ta = +25°C -0.3 to VDD+0.3* Output voltage1 Output voltage2 (COM0～COM7, SEG0～SEG64) VOUT1 Ta = +25°C -0.3 to VDD+0.3* V VOUT2 Ta = +25°C -0.3 to +6.5 V “H” level output current IOUTH Ta = +25°C “L” level output current IOUTL Ta = +25°C 1pin Total 1pin Total 2 -40* 2 -180* +40 +180 1 -55 to +150 mA mA Power dissipation PD Ta = +25°C W Storage temperature ― °C TSTG 1 * 6.5V or lower 2 * The current flowing out the LSI through the pin is described in the negative number. The applicable maximum current is the absolute value. For example, -1mA means the maximum current 1mA flows out the LSI through the pin. [Note] Stresses above the absolute maximum ratings listed in the above table may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Recommended Operating Conditions (VSS = 0V) Parameter Symbol Condition Range Operating temperature(Ambient) Operating temperature(Chip-Junction) Ta ― -40 to +105 °C Tj ― -40 to +115 °C Operating voltage 1 VDD ― 1.6 to 5.5 V Operating voltage 2 VL3 External supply method 2.7 to 5.5 V Operating voltage 3 VL2 External supply method 2/3 x VL3 V Operating voltage 4 VL1 fOP VDDL pin external capacitance VL1,VL2,VL3 pin external capacitance CL CL1,CL2, CL3 C1 and C2 pin external capacitance C12 1/3 x VL3 30k to 4M 30k to 25M 1.0 ±30% 0.47±30% or 1.0±30% 0.47±30% or 1.0±30% V Operating frequency (CPU) External supply method VDD = 1.6 to 5.5V VDD = 1.8 to 5.5V ― ― ― Unit Hz μF μF μF 27/74 FEDL62Q1700-0４ Thermal characteristics The maximum chip-junction temperature, Tjmax, may be calculated using the following equation. 𝑇𝑗 𝑚𝑚𝑚 = 𝑇𝑎 𝑚𝑚𝑚 + 𝑃𝐷 𝑚𝑚𝑚 × 𝜃𝑗𝑗 𝑇𝑎 𝑚𝑚𝑚 : maximum ambient temperature 𝑃𝐷 𝑚𝑚𝑚 : LSI maximum power dissipation : Package junction to ambient thermal resistance 𝜃𝑗𝑗 Design a Mounting board by considering heat radiation such as power dissipation and ambient temperature to satisfy the recommended conditions. The following table shows the each package’s thermal resistance for thermal design reference estimated by simulation based on the PCB (printed circuit board) conditions define as a below. Parameter Symbol Package type θja TQFP48 TQFP52 TQFP64 QFP64 QFP80 TQFP100 QFP100 Thermal resistance Value L1 63.6 61.7 63.2 47.2 55.5 48.0 104.7 L2 57.8 56.7 58.2 43.3 51.6 43.3 101.3 Unit o C/W PCB conditions: PCB name L1 L2 Unit PCB size （L / W / T） 114.3 / 76.2 / 1.6 114.3 / 76.2 / 1.6 mm Number of layer 1 2 layer Wiring density 60% (top layer) 60%(top and bottom layer) ― ― Wind condition No wind (0m/s) 28/74 FEDL62Q1700-0４ Current Consumption 1 Product： ML62Q1700, ML62Q1701, ML62Q1702, ML62Q1703, ML62Q1704, ML62Q1710, ML62Q1711, ML62Q1712, ML62Q1713, ML62Q1714, ML62Q1720, ML62Q1721, ML62Q1722, ML62Q1723, ML62Q1724 o (VDD=1.6 to 5.5V, VSS =0V, Ta=-40 to +105 C, unless otherwise specified) Parameter Supply current 0 Supply current 1 Supply current 2-1 Symbol IDD0 IDD1 IDD2-1 Condition CPU is in STOP-D state. Low-speed RC1K/RC32K and PLL oscillation are stopped. CPU is in STOP state. Low-speed RC1K/RC32K and PLL oscillation are stopped. Low-speed RC32K Oscillating. *1 CPU is in HALT state . PLL oscillation is stopped. Low-speed Crystal Oscillating. *4 Supply current 2-2 Supply current 3 IDD2-2 IDD3 Min. CPU: Running with low-speed 1 2 RC32K oscillation clock* * PLL oscillation is stopped. Max. Ta = -40 to o +85 C Ta = -40 to o +105 C Ta = -40 to o +85 C Ta = -40 to o +105 C ― ― 80 Ta = -40 to o +85 C ― 42 Ta = -40 to o +105 C ― 85 Ta = -40 to o +85 C ― 42 ― μA 40 μA 1.0 μA 4.9 μA 3.3 ― Ta = -40 to o +105 C ― Measurin g circuit 75 ― Ta = -40 to o +105 C Unit 37 0.8 *1 CPU is in HALT state . PLL oscillation is stopped. 3 Typ.* 1 85 17 CPU: Running with 16MHz PLL 2 Ta = -40 to oscillating clock* Supply current 4 ― 3.4 IDD4 o +105 C PLL 16MHz is oscillating. VDD=1.8~5.5V CPU: Running with 24MHz PLL 2 Ta = -40 to oscillating clock* Supply current 5 ― 4.8 IDD5 o +105 C PLL 24MHz is oscillating. VDD=1.8~5.5V 1 * LTBC and WDT is operating, Significant bits of BCKCON0-3 and BRECON0-3 registers are all “1” 2 * CPU running in wait mode 3 * On the condition of VDD=3.0V, Ta=+25°C 4 * When the noise filter is not used in the low power consumption mode 105 μA 4.5 mA 6.0 29/74 FEDL62Q1700-0４ Current Consumption 2 Product： ML62Q1725, ML62Q1726, ML62Q1727, ML62Q1733, ML62Q1734, ML62Q1735, ML62Q1736, ML62Q1737, ML62Q1743, ML62Q1744, ML62Q1745, ML62Q1746, ML62Q1747 o (VDD=1.6 to 5.5V, VSS =0V, Ta=-40 to +105 C, unless otherwise specified) Parameter Supply current 0 Supply current 1 Supply current 2-1 Symbol IDD0 IDD1 IDD2-1 Condition Supply current 3 IDD2-2 IDD3 3 Typ.* Max. Ta = -40 to o +85 C Ta = -40 to o +105 C Ta = -40 to o +85 C Ta = -40 to o +105 C ― ― 120 Low-speed RC32K Oscillating. CPU is in HALT state (LTBC *1 and WDT are operating ). PLL oscillation is stopped. Ta = -40 to o +85 C ― 76 Ta = -40 to o +105 C ― 135 Low-speed Crystal Oscillating. Ta = -40 to o +85 C ― 76 CPU is in STOP-D state. Low-speed RC1K/RC32K and PLL oscillation are stopped. CPU is in STOP state. Low-speed RC1K/RC32K and PLL oscillation are stopped. *4 Supply current 2-2 Min. CPU is in HALT state (LTBC *1 and WDT are operating ). PLL oscillation is stopped. CPU: Running with low-speed 1 2 RC32K oscillation clock* * PLL oscillation is stopped. μA ― 110 ― 60 μA 1.5 μA 5.7 μA 4.5 ― Ta = -40 to o +105 C ― Measurin g circuit 55 1.0 Ta = -40 to o +105 C Unit 1 135 20 CPU: Running with 16MHz PLL 2 Ta = -40 to oscillating clock* Supply current 4 ― IDD4 4.0 o +105 C PLL 16MHz is oscillating. VDD=1.8~5.5V CPU: Running with 24MHz PLL 2 Ta = -40 to oscillating clock* Supply current 5 ― IDD5 5.7 o +105 C PLL 24MHz is oscillating. VDD=1.8~5.5V 1 * LTBC and WDT is operating, Significant bits of BCKCON0-3 and BRECON0-3 registers are all “1” 2 * CPU running in wait mode 3 * On the condition of VDD=3.0V, Ta=+25°C 4 * When the noise filter is not used in the low power consumption mode 150 μA 5.0 mA 7.0 30/74 FEDL62Q1700-0４ Current Consumption 3 Product： ML62Q1728, ML62Q1729, ML62Q1738, ML62Q1739, ML62Q1748, ML62Q1749 o (VDD=1.6 to 5.5V, VSS =0V, Ta=-40 to +105 C, unless otherwise specified) Parameter Supply current 0 Supply current 1 Supply current 2-1 Symbol IDD0 IDD1 IDD2-1 Condition CPU is in STOP-D state. Low-speed RC1K/RC32K and PLL oscillation are stopped. CPU is in STOP state. Low-speed RC1K/RC32K and PLL oscillation are stopped. Low-speed RC32K Oscillating. *1 CPU is in HALT state . PLL oscillation is stopped. Low-speed Crystal Oscillating. *4 Supply current 2-2 Supply current 3 IDD2-2 IDD3 Min. CPU: Running with low-speed 1 2 RC32K oscillation clock* * PLL oscillation is stopped. Max. Ta = -40 to o +85 C Ta = -40 to o +105 C Ta = -40 to o +85 C Ta = -40 to o +105 C ― ― 150 Ta = -40 to o +85 C ― 78 Ta = -40 to o +105 C ― 165 Ta = -40 to o +85 C ― 78 ― μA 62 μA 1.8 μA 6.0 μA 4.5 ― Ta = -40 to o +105 C ― Measurin g circuit 140 ― Ta = -40 to o +105 C Unit 57 1.2 *1 CPU is in HALT state . PLL oscillation is stopped. 3 Typ.* 1 165 20 CPU: Running with 16MHz PLL 2 Ta = -40 to oscillating clock* Supply current 4 ― 4.0 IDD4 o +105 C PLL 16MHz is oscillating. VDD=1.8~5.5V CPU: Running with 24MHz PLL 2 Ta = -40 to oscillating clock* Supply current 5 ― 5.7 IDD5 o +105 C PLL 24MHz is oscillating. VDD=1.8~5.5V 1 * LTBC and WDT is operating, Significant bits of BCKCON0-3 and BRECON0-3 registers are all “1” 2 * CPU running in wait mode 3 * On the condition of VDD=3.0V, Ta=+25°C 4 * When the noise filter is not used in the low power consumption mode 190 μA 5.0 mA 7.0 31/74 FEDL62Q1700-0４ Low speed Crystal Oscillation o Parameter Symbol (VDD=1.6 to 5.5V, VSS =0V, Ta=-40 to +105 C, unless otherwise specified) Range Condition Unit Min. Typ. Max. Crystal oscillation fXTL ― ― 32.768 ― kHz 1 2 frequency * * Crystal oscillation start TXTL ― ― ― 2 s time 1 * : The oscillation frequency is determined by the oscillation circuit, crystal resonator and the external capacitance (CGL/CDL). As those parameters changes depending the crystal resonator, it requires evaluation on the actual PCB circuit for matching. Ask crystal resonator makers for matching and confirm the oscillation characteristics. 2 * : The quality of oscillation characteristics might be lost, depending on material of PCB, condition of wiring capacitance or parasitic capacitance on the external circuits. Note for designing the external circuit. - Make the wires on the external circuit as short as possible. - Place the crystal resonator and oscillation circuit as close to the MCU as possible and make the wires between the external capacitance and crystal resonator as short as possible. - Ensure no signal line flowing big current runs near the oscillation circuit. - Ensure no signal line runs under and near the oscillation circuit. - Make ground of external capacitance the same as MCU ground VSS pin and connect them to the ground that has low variation of current and voltage. variation. - The quality of oscillation characteristics might be lost depending on operating environment due to moisture absorption of PCB and condensation of PCB surface, recommended to have measures such as covering the oscillation circuit with resin. Low speed Crystal Oscillation external circuit example XT0 XT1 VSS Crystal resonator (32.768kHz) CGL CDL External Clock Input o Parameter Symbol Input Frequency fEXCK Input pulse width tEXCKW (VDD=1.6 to 5.5V, VSS =0V, Ta=-40 to +105 C, unless otherwise specified) Range Condition Unit Min. Typ. Max. Typ. Typ. ― 32.768 kHz -1.0% +1.0% 1/fEXCK 1/fEXCK ― s x 0.4 x 0.6 32/74 FEDL62Q1700-0４ On-chip Oscillator Parameter Symbol Low-speed RC oscillator frequency accuracy 1 Without software adjustment fRCL1 Low-speed RC oscillator frequency accuracy 2 With software adjustment fRCL2 PLL oscillation frequency accuracy 1 Without software adjustment fPLL1 PLL oscillation frequency accuracy 2 With software adjustment fPLL2 PLL oscillation start time 1kHz Low-speed RC oscillator (for WDT) frequency accuracy TPLL fRC1K (VDD=1.6 to 5.5V, VSS =0V, Ta=−40 to +105°C, unless otherwise specified) Measur Condition Min. Typ. Max. Unit ing circuit Ta= +25°C Typ. Typ. 32.768 VDD = 1.8 to 5.5V -1.0% +1.0% Ta= -40 to +85°C Typ. Typ. 32.768 VDD = 1.8 to 5.5V -2.5% +2.5% Ta= -40 to +105°C Typ. Typ. 32.768 VDD = 1.8 to 5.5V -3.0% +3.0% kHz Typ. Typ. VDD = 1.6 to 1.8V 32.768 -3.5% -3.5% Typ. Ta= -40 to +85°C Typ. 32.768 VDD = 1.8 to 5.5V -1.0% +1.0% Ta= -40 to +105°C Typ. Typ. 32.768 VDD = 1.8 to 5.5V -1.5% +1.5% Ta= -40 to +85°C Typ. Typ. 1 16/24 VDD = 1.8 to 5.5V -2.5% +2.5% Typ. Ta= -40 to +105°C Typ. 16/24 VDD = 1.8 to 5.5V -3.0% +3.0% Typ. Typ. VDD = 1.6 to 1.8V 16/24 MHz -3.5% +3.5% Ta= -40 to +85°C Typ. Typ. 16/24 VDD = 1.8 to 5.5V -1.0% +1.0% Ta= -40 to +105°C Typ. Typ. 16/24 VDD = 1.8 to 5.5V -1.5% +1.5% VDD = 1.6 to 5.5V ― ― 2 ms Ta= -40 to +105°C 0.5 1 2.5 kHz VDD = 1.6 to 5.5V 33/74 FEDL62Q1700-0４ Input / Output pin 1 (VDD=1.6 to 5.5V, VSS =0V, Ta=−40 to +105°C, unless otherwise specified) Parameter Output voltage1 “H”/”L” level (P00-P07) (P10-P17) (P20-P27) (P30-P33) (P40-P47) (P50-P57) (P60-P67) (P70,P76,P77) (P80-P87) (P90-P97) (PA0-PA7) (PB0-PB7) Output voltage2 “L” level (P01-P07) (P10-P17) (P20-P27) (P30-P33) (P40-P47) (P50-P57) (P60-P67) (P70 P76,P77) (P80-P87) (P90-P97) (PA0-PA7) (PB0-PB7) Output voltage 3 LCD COM/SEG (COM0~COM7) (SEG0~SEG64) Symbol Condition Min. Typ. Max. IOH1=-10mA VDD≥4.5V VDD -1.5 ― ― IOH1=-1mA VDD≥1.6V VDD -0.5 ― ― IOL1=+10mA VDD≥4.5V ― ― 1.5 IOL1=+1mA VDD≥1.6V ― ― 0.5 Unit Measur ing circuit V 2 V 2 VOH1 VOL1 IOL2=+15mA VDD≥4.5V ― ― 0.5 IOL2=+8mA VDD≥3.0V ― ― 0.5 IOL2=+3mA VDD≥2.0V ― ― 0.4 IOL2=+2mA VDD≥1.6V ― ― 0.4 VOH3M IOH3M=-0.03mA VL3 output VL3 -0.2 ― ― VOH3P IOMH3P=+0.03mA VL2 output ― ― VL2 +0.2 IOMH3M=-0.03mA VL2 output VL2 -0.2 ― ― IOML3P=+0.03mA VL1 output ― ― VL1 +0.2 VOML3M IOML3M=-0.03mA VL1 output VL1 -0.2 ― ― VOL3P IOL3P=+0.03mA VSS output ― ― 0.2 VOL2 VOMH3M VOML3P When N-ch open drain output mode is selected VL3 = 3V, VL2 = 2V, VL1 = 1V 34/74 FEDL62Q1700-0４ Input / Output pin 2 (VDD=1.6 to 5.5V, VSS =0V, Ta=−40 to +105°C, unless otherwise specified) Parameter Symbol “H” level output 6 current1 * IOH1 “H” level output 1 4 current1 * * IOH3 Condition 1pin Total of ‘P00-P07, P10-P13, P44-P47, P50-P53, P70,P76, P80-P87，P90-P97, PA0’ or Total of ‘P14-P17, P20-P27, P30-P33, P40-P43, P54-P57 P60-P67,P77, PA1-PA7， PB0-PB7’ (duty≤50%) All pin total (duty≤50%) “L” level output 6 current1 * IOL1 1pin (CMOS output mode) “L” level output 6 current2 * IOL2 1pin (N-ch open drain output mode) “L” level output 2 4 total current * * IOL3 Total of P00-P07, P10-P13, P44-P47, P50-P53, P70,P76, P80-P87, P90-P97, PA0’ or Total of ‘P14-P17, P20-P27, P30-P33, P40-P43, P54-P57 P60-P67,P77, PA1-PA7, PB0-PB7’ (N-ch open drain output mode,duty≤50%) All pin total (N-ch open drain output mode,duty≤50%) Output leak (P00-P07) (P10-P17) (P20-P27) (P30-P33) (P40-P47) (P50-P57) (P60-P67) (P70,P76,P77) (P80-P87) (P90-P97) (PA0-PA7) (PB0-PB7) IOOH Min. Typ. Max. VDD≥4.5V VDD≥1.6V -10* * 3 5 -1* * 3 5 ― ― ― ― VDD≥4.5V -90* 5 ― ― VDD≥1.6V -20* 5 ― ― VDD≥4.5V VDD≥1.6V VDD≥4.5V -180* 5 -40* ― ― ― ― ― ― 3 10* VDD≥1.6V VDD≥4.5V VDD≥3.0V VDD≥2.0V VDD≥1.6V ― ― ― ― ― ― ― ― ― ― 1* 3 15* 3 8* 3 3* 3 2* VDD≥4.5V ― ― 90 VDD≥3.0V ― ― 40 VDD≥2.0V ― ― 15 VDD≥1.6V ― ― 10 VDD≥4.5V ― ― 180 VDD≥1.6V ― ― 20 ― ― +1 5 Unit Measu ring circuit 3 mA 3 VOH=VDD (High impedance mode) μA IOOL VOL=VSS (High impedance mode) 5 -1* ― ― 35/74 FEDL62Q1700-0４ 1 * Sink-out current from VDD to the output pin, which can guarantee the device operation. 2 * Sink-in current from the output pin to VSS, which can guarantee the device operation. 3 * Do not exceed total current. 4 * The total current is on the condition of Duty≤50%(same applies to IOH1). When the duty ＞50% the total current is calculated by following formula. Total current = IOL3 x 50/n (When the duty is n%) When IOL3=100mA and n=80%, Total current = IOL3 x 50/80 = 62.5mA Current allowed per 1pin is independent of the duty and specified as IOL1 and IOL2. Do not apply current larger than Absolute Maximum Ratings. 5 * The current flowing out the LSI through the pin is described in the negative number. The applicable maximum current is the absolute value. For example, -1mA means the maximum current 1mA flows out the LSI through the pin. 6 * VOH1, VOL1, and VOL2 are satisfied with this spec. 36/74 FEDL62Q1700-0４ Input / Output pin 3 (VDD=1.6 to 5.5V, VSS =0V, Ta=−40 to +105°C, unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Input current1 (RESET_N) IIH1 IIL1 IIL2 V/IIL2 IIH2Z IIL2Z VIH1=VDD VIL1=VSS 2 VIL2=VSS (pull-up mode) * 2 VIL2=VSS (pull-up mode) * VIH2=VDD (High impedance mode) VIL2=VSS (High impedance mode) ― 1 -1* 1 -1500* 3.7 ― 1 -1* ― ― 1 -300* 10 ― ― 1 ― 1 -20* 80 1 ― Input current2 (P00/TEST0) Input current3 (P01-P07) (P10-P17) (P20-P27) (P30-P33) (P40-P47) (P50-P57) (P60-P67) (P70,P76,P77) (P80-P87) (P90-P97) (PA0-PA7) (PB0-PB7) Input current4 (PI00-PI01) Input voltage1 (RESET_N) (P01-P07) (P10-P17) (P20-P27) (P30-P33) (P40-P47) (P50-P57) (P60-P67) (P70,P76,P77) (P80-P87) (P90-P97) (PA0-PA7) (PB0-PB7) (PI00-PI01) Input voltage2 (P00/TEST0) Pin capacitance (RESET_N) (P00/TEST0) (P01-P07) (P10-P17) (P20-P27) (P30-P33) (P40-P47) (P50-P57) (P60-P67) (P70,P76,P77) (P80-P87) (P90-P97) (PA0-PA7) (PB0-PB7) (PI00-PI01) 2 1 1 -250* -30* -2* 2 Unit Measur ing circuit μA kΩ μA 1 IIL3 VIL1=VSS (pull-up mode) * V/IIL3 VIL1= VSS (pull-up mode) * 22 100 800 IIH3Z VIH1=VDD (High impedance mode) ― ― 1 IIL3Z VIL1=VSS (High impedance mode) -1* 1 ― ― IIH4 IIL4 VIH1=VDD VIL1=VSS ― *1 -1 ― ― 1 ― VIH1 ― 0.7 x VDD ― VDD 4 VIL1 ― 0 ― 0.3 x VDD VIH2 ― 0.7 x VDD ― VDD VIL2 ― 0 ― 0.25 ×VDD CPIN f = 10kHz Ta = +25°C ― ― 10 kΩ μA V 5 pF ― 1 * The current flowing out the LSI through the pin is described in the negative number. The applicable maximum current is the absolute value. For example, -1mA means the maximum current 1mA flows out the LSI through the pin. *2 Measurement conditions: Typ. : VDD = 3.0V, Max. : VDD = 1.6V, Min. : VDD = 5.5V 37/74 FEDL62Q1700-0４ Synchronous Serial Port Slave mode Parameter SCK input cycle SCK input pulse width Symbol tSCYC tSW SOUT output delay time tSD SIN input setup time tSS SIN input hold time tSH (VDD=1.8 to 5.5V, VSS =0V, Ta=−40 to +105°C, unless otherwise specified) Condition Min. Typ. Max. Unit 2 ― 1* ― ― μs 3 ― 0.5 * ― ― μs 100+ VDD=2.4 to 5.5V ― ― ns 1 HSCLK* ×3 200+ VDD=1.8 to 5.5V ― ― ns 1 HSCLK* ×3 1 HSCLK* ― ― ― ns x1 80+ ― ― ― ns 1 HSCLK* ×3 1 * Cycle of high speed clock 2 * Need input cycles of HSCLK x8 or longer 3 * Need input cycles of HSCLK x4 or longer tSCYC tSW tSW 0.7×VDD SUn_SCLK* 0.3×VDD tSD tSD 0.7×VDD SUn_SOUT* 0.3×VDD tSS 0.7×VDD SUn_SIN* *2 nd tSH 0.3×VDD th to 8 function of port, n=0~5 38/74 FEDL62Q1700-0４ Master mode Parameter Symbol SCK output cycle tSCYC SCK output pulse width tSW SOUT output delay time tSD SIN input setup time (VDD=1.8 to 5.5V, VSS =0V, Ta=−40 to +105°C, unless otherwise specified) Condition Min. Typ. Max. Unit ― ― 1 SCLK* 1 1 ― ns 1 ― SCLK* ×0.4 SCLK* ×0.5 SCLK* ×0.6 ns VDD=2.4 to 5.5V ― ― 100 ns VDD=1.8 to 5.5V ― ― 160 ns VDD=2.4 to 5.5V 120 ― ― ns VDD=1.8 to 5.5V 180 ― ― ns VDD=2.4 to 5.5V 80 ― ― ns VDD=1.8 to 5.5V 100 ― ― ns tSS SIN input hold time tSH 1 * Clock cycle selected by bit12~8(SnCK4~0) of the serial port n mode register (SIOnMOD) VDD≥2.4V: min250ns , VDD≥1.8V: min500ns tSCYC tSW tSW 0.7×VDD SUn_SCLK* 0.3×VDD tSD tSD 0.7×VDD SUn_SOUT* 0.3×VDD tSS 0.7×VDD SUn_SIN* *2 nd tSH 0.3×VDD th to 8 function of port, n=0~5 39/74 FEDL62Q1700-0４ I2C Bus Interface Standard Mode (100k bps) (VDD=1.8 to 5.5V, VSS =0V, Ta=−40 to +105°C, unless otherwise specified) Condition Min. Typ. Max. Unit Parameter Symbol SCL clock frequency fSCL ― 0 ― 100 kHz SCL hold time (start/restart condition) tHD:STA ― 4.0 ― ― μs SCL ”L” level time tLOW ― 4.7 ― ― μs SCL ”H” level time tHIGH ― 4.0 ― ― μs SCL setup time (restart condition) tSU:STA ― 4.7 ― ― μs SDA hold time tHD:DAT ― 0 ― ― μs SDA setup time tSU:DAT ― 0.25 ― ― μs SDA setup time (stop condition) tSU:STO ― 4.0 ― ― μs Bus-free time tBUF ― 4.7 ― ― μs 2 2 2 When using the I C as the master, configure the I C master n mode register(I2MnMOD) and I C bus 0 mode register (master side, I2UM0MOD) so that meet these specifications. Start Condition Re-start Condition Stop Condition I2CUn_SDA I2CMn_SDA 0.7×VDD 0.3×VDD 0.7×VDD 0.3×VDD I2CUn_SCL I2CMn_SCL tHD:STA tLOW tHIGH tSU:STA tHD:STA tSU:DAT tHD:DAT tSU:STO tBUF n：0 to 1 40/74 FEDL62Q1700-0４ Fast Mode (400k bps) (VDD=1.8 to 5.5V, VSS =0V, Ta=−40 to +105°C, unless otherwise specified) Condition Min. Typ. Max. Unit Parameter Symbol SCL clock frequency fSCL ― 0 ― 400 kHz SCL hold time (start/restart condition) tHD:STA ― 0.6 ― ― μs SCL ”L” level time tLOW ― 1.3 ― ― μs SCL ”H” level time tHIGH ― 0.6 ― ― μs SCL setup time (restart condition) tSU:STA ― 0.6 ― ― μs SDA hold time tHD:DAT ― 0 ― ― μs SDA setup time tSU:DAT ― 0.1 ― ― μs SDA setup time (stop condition) tSU:STO ― 0.6 ― ― μs Bus-free time tBUF ― 1.3 ― ― μs 2 2 2 When using the I C as the master, configure the I C master n mode register(I2MnMOD) and I C bus 0 mode register (master side, I2UM0MOD) so that meet these specifications. Start Condition Re-start Condition Stop Condition I2CUn_SDA I2CMn_SDA 0.7×VDD 0.3×VDD 0.7×VDD 0.3×VDD I2CUn_SCL I2CMn_SCL tHD:STA tLOW tHIGH tSU:STA tHD:STA tSU:DAT tHD:DAT tSU:STO tBUF n：0 to 1 41/74 FEDL62Q1700-0４ 1Mbps Mode (1M bps) (VDD=2.7 to 5.5V, VSS =0V, Ta=−40 to +105°C, unless otherwise specified) Condition Min. Typ. Max. Unit Parameter Symbol SCL clock frequency fSCL ― 0 ― 1000 kHz SCL hold time (start/restart condition) tHD:STA ― 0.26 ― ― μs SCL ”L” level time tLOW ― 0.5 ― ― μs SCL ”H” level time tHIGH ― 0.26 ― ― μs SCL setup time (restart condition) tSU:STA ― 0.26 ― ― μs SDA hold time tHD:DAT ― 0 ― ― μs SDA setup time tSU:DAT ― 0.1 ― ― μs SDA setup time (stop condition) tSU:STO ― 0.26 ― ― μs Bus-free time tBUF ― 0.5 ― ― μs 2 2 2 When using the I C as the master, configure the I C master n mode register(I2MnMOD) and I C bus 0 mode register (master side, I2UM0MOD) so that meet these specifications. Start Condition Re-start Condition Stop Condition I2CUn_SDA I2CMn_SDA 0.7×VDD 0.3×VDD 0.7×VDD 0.3×VDD I2CUn_SCL I2CMn_SCL tHD:STA tLOW tHIGH tSU:STA tHD:STA tSU:DAT tHD:DAT tSU:STO tBUF n：0 to 1 42/74 FEDL62Q1700-0４ Reset (VDD=1.6 to 5.5V, VSS =0V, Ta=−40 to +105οC, unless otherwise specified) Parameter Reset pulse width *2 P00 ”H” level setup time P00 ”H” level hold time *1 *2 *1 *1 Symbol Condition Min. Typ. Max. Unit PRST ― 2 ― ― ms tSP00 ― 1 ― ― ms tHP00*1 ― 1 ― ― ms Measur ing circuit 1 ： except ISP mode. Refer to the User’s manual “25.4 In-System Programing Function” for the timing in ISP mode. ： VDD=1.6V or over at power on. VIL1 RESET_N PRST P00/TEST0 “H” level or “L” level VIH1 VIL1 *2 “H” level input tSP00 “H” level or “L” level tHP00 Note:  RESET_N input shorter pulse than the Reset pulse width (PRST) valid time should be avoided. The shorter pulse input may cause unexpected behavior. 43/74 FEDL62Q1700-0４ Slope of Power supply and Power On Reset (VSS =0V, Ta=−40 to +105οC, unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Unit Power on rising slope SVR ― ― ― 60 V/ms Power on falling slope SVF ― ― ― 2 V/ms VPORR At Power up (rising) 1.47 1.57 1.80 V VPORF At Power down (falling) 1.33 1.49 1.58 V Power on reset minimum pulse width PPOR ― 200 ― ― μs Power on voltage VINIT At power on 1.8 ― ― V CPU operation start time (from the release of reset to the CPU starts to run） tCPUI ― 11 16 ― ms Power on reset detection voltage SVR At Power supply voltage level change SVR SVF SVF Measur ing circuit 1 ― At Power supply restart SVR VDD VINIT VPORR VPORF 0V PPOR tCPUI At power on At Power off Note:  If a pulse shorter than the Power on reset minimum pulse width is asserted to VDD, it may cause the MCU malfunction. Apply prevent measurement such as bypass capacitors or external reset input, and so on.  Start the high-speed clock when the VDD is within the operating voltage. 44/74 FEDL62Q1700-0４ VLS Parameter Symbol VVLSR VVLSF VVLSR VVLSF VVLSR VVLSF VVLSR VVLSF VVLSR VVLSF VVLSR VLS threshold 2 voltage * VVLSF VVLSR VVLSF VVLSR VVLSF VVLSR VVLSF VVLSR VVLSF VVLSR VVLSF VVLSR VVLSF VLS Current IVLS (VDD=1.6 to 5.5V, VSS =0V, Ta=−40 to +105°C, unless otherwise specified) Condition Measuring Min. Typ. Max. Unit 1 circuit VLS0LV * Rising 3.86 4.06 4.26 00H Falling 3.84 4.00 4.16 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH Rising 3.57 3.76 3.95 Falling 3.55 3.70 3.85 Rising 2.94 3.11 3.28 Falling 2.92 3.05 3.18 Rising 2.85 3.01 3.17 Falling 2.83 2.95 3.07 Rising 2.75 2.91 3.07 Falling 2.73 2.85 2.97 Rising 2.66 2.81 2.96 Falling 2.64 2.75 2.86 Rising 2.56 2.71 2.86 Falling 2.54 2.65 2.76 Rising 2.46 2.61 2.76 Falling 2.44 2.55 2.66 Rising 2.37 2.51 2.65 Falling 2.35 2.45 2.55 Rising 1.98 2.11 2.24 Falling 1.96 2.05 2.14 Rising 1.89 2.01 2.13 Falling 1.87 1.95 2.03 Rising 1.79 1.91 2.03 Falling 1.77 1.85 1.93 ― 50 ― ― V 1 nA 1 * Bit3~Bit0 of voltage level detection circuit 0 level register (VLS0LV). 2 * The Data VSL0LV = 0CH~0FH is not available to use, if the data is specified it will the same spec as that 0BH is specified. Analog Comparator o (VDD=1.8 to 5.5V, VSS =0V, Ta=-40 to +105 C, unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Unit Comparator same phase input voltage range VCMR ― 0.1 ― VDD -1.5 V Comparator0 input offset VCMOF Ta=+25 C, VDD=5.0V ― 5 ― mV Comparator Reference Voltage VCMREF ― 0.75 0.8 0.85 V o Measuring circuit 1 45/74 FEDL62Q1700-0４ Successive Approximation Type A/D Converter o Parameter Resolution Overall error Symbol nAD ― Integral non-linearity error INLAD Differential non-linearity error DNLAD Zero-scale error Full-scale error A/D reference voltage Internal reference voltage ZSE FSE VREF VREFI Conversion time tCONV (VDD=1.8 to 5.5V, VSS =0V, Ta=-40 to +105 C, unless otherwise specified) Condition Min. Typ. Max. Unit ― ― ― 10 bit 1 4.5V≤ Reference voltage* ≤5.5V -3.5 1.2 3.5 1 2.7V≤ Reference voltage* ≤5.5V -4 ― 4 1 2.2V≤ Reference voltage*