ML9477TBZAMX

Dear customer LAPIS Semiconductor Co., Ltd. ("LAPIS Semiconductor"), on the 1st day of October, 2020, implemented the incorporation-type company split (shinsetsu-bunkatsu) in which LAPIS established a new company, LAPIS Technology Co., Ltd. (“LAPIS Technology”) and LAPIS Technology succeeded LAPIS Semiconductor’s LSI business. Therefore, all references to "LAPIS Semiconductor Co., Ltd.", "LAPIS Semiconductor" and/or "LAPIS" in this document shall be replaced with "LAPIS Technology Co., Ltd." Furthermore, there are no changes to the documents relating to our products other than the company name, the company trademark, logo, etc. Thank you for your understanding. LAPIS Technology Co., Ltd. October 1, 2020 FEDL9477-01 Issue Date: Mar. 1, 2010 ML9477 1/3 or 1/4 Duty, 32-Output LCD Driver GENERAL DESCRIPTION The ML9477 is an LCD driver for dynamic display. It has a function to switch between 1/3 and 1/4 duty. When 1/4 duty is selected, an LCD of up to 128 segments can be driven directly; when 1/3 duty is selected, an LCD of up to 96 segments can be driven directly. FEATURES         Logic power supply voltage : 2.7 to 3.6 V, 4.5 to 5.5 V Driver power supply voltage : 3.5 to 5.5 V Operating temperature : 40 to +105°C 32 segment outputs 1/4 duty : Up to 128 segments can be displayed. 1/3 duty : Up to 96 segments can be displayed. Serially interfaces with the CPU using the three signal lines of LOAD, DATA_IN, and CLOCK Built-in RC oscillator circuit for LCD AC drive (the CLKSEL pin allows selecting an external clock input) Built-in voltage-dividing resistor for bias voltage generation Package : 48-pin plastic TQFP (TQFP48-P-0707-0.50-K) 1/20 FEDL9477-01 ML9477 BLOCK DIAGRAM SEG1 SEG32 DVDD 32-Dot Segment Driver Bias Res.. 32-Ch Data Selector 32 TEST 32-Bit Latch4 LOAD 32 32-Bit Latch3 32 32-Bit Latch2 32 32-Bit Latch1 LATCH SELECTOR 32 DATA_IN 38(32 + 6)-bit Shift Register CLOCK OSC OSC TIMING GENERATOR COM1 CLKSEL 3/4SEL COMMON Driver COM2 COM3 COM4 RESET LVDD VSS 2/20 FEDL9477-01 ML9477 COM3 COM4 CLKSEL VSS OSC LVDD 3/4SEL TEST RESET NC DATA_IN CLOCK 48 47 46 45 44 43 42 41 40 39 38 37 PIN CONFIGURATION (TOP VIEW) SEG5 7 30 SEG27 SEG6 8 29 SEG26 SEG7 9 28 SEG25 SEG8 10 27 SEG24 SEG9 11 26 SEG23 SEG10 12 25 SEG22 24 SEG28 SEG21 31 23 6 SEG20 SEG4 22 SEG29 SEG19 32 21 5 SEG18 SEG3 20 SEG30 SEG17 33 19 4 DVDD SEG2 18 SEG31 SEG16 34 17 3 SEG15 SEG1 16 SEG32 SEG14 35 15 2 SEG13 COM1 14 LOAD SEG12 36 13 1 SEG11 COM2 48-Pin Plastic TQFP 3/20 FEDL9477-01 ML9477 PIN DESCRIPTION Symbol I/O OSC I/O DATA_IN I CLOCK I LOAD I TEST I CLKSEL I 3/4SEL I RESET I COM1 COM2 COM3 COM4 O SEG1 to SEG32 O LVDD DVDD VSS    Description Pin for oscillation. Has a Schmitt circuit built in. An oscillator circuit can be configured by connecting one external resistor and one external capacitor. Since an oscillator circuit is susceptible to external noise, make the wiring between this pin and external components as short as possible. An external clock input can be selected by CLKSEL. The relationship between oscillation frequency fOSC and frame frequency fFRM is: (*1) fFRM = fOSC/24 Serial data input pin. Has a Schmitt circuit built in. The LCD display is turned on when the input data signal is at a “H” level and turned off when the input data signal is at a “L” level. Shift clock input pin. Has a Schmitt circuit built in. Data to the DATA_IN pin is shifted in sync with the rising edges of the shift clock pulses. Load pulse input pin. Has a Schmitt circuit built in. Used to transfer serially input data to the display latch or write commands. IC test pin. Has a pull-down resistor built in. Leave this pin open or connect it to VSS when not used. OSC pin input switching pin. When using the built-in oscillator circuit, set this pin to a “L” level; when inputting an external clock, set this pin to a “H” level. While this pin is at a “H” level, the oscillator circuit connected is disabled. 1/3- or 1/4-duty switching input pin. When “H” level is input, 1/3 duty is selected and when “L” level is input, 1/4 duty is selected. Reset signal input pin for initializing the IC. Has a Schmitt circuit built in. This pin is enabled by setting it to “L” level. This pin has a built-in pull-up resistor. Normally, this pin, when connected with an external capacitor, performs power-on (*2) reset. Output pins for LCD display. Connect to the common pins of the LCD panel. - When 1/3 duty is selected: Common signals are outputted through the COM1, COM2, and COM3 pins. Leave the COM4 pin open. - When 1/4 duty is selected: Common signals are outputted through the COM1, COM2, COM3, and COM4 pins. Output pins for LCD display. Connect to the segment pins of the LCD panel. For the relationship between each output of these pins and data, see the section on “Data Structure.” Logic power supply pin. LCD driver power supply pin. Ground pin. 4/20 FEDL9477-01 ML9477 *1: Oscillator circuit configuration LVDD RO OSC CO *2: Reset circuit configuration LVDD CRST RESET 5/20 FEDL9477-01 ML9477 ABSOLUTE MAXIMUM RATINGS Parameter Power supply voltage Symbol Condition Rating Unit LVDD, DVDD Ta = 25°C –0.3 to +6.5 V Input voltage VI Ta = 25°C –0.3 to LVDD+0.3 V Power dissipation Output current PD Ta  105°C 350 mW IO Ta = 25°C –2.0 to +2.0 mA TSTG  –55 to +150 °C Storage temperature RECOMMENDED OPERATING CONDITIONS Parameter Symbol Condition Range Unit V Logic power supply voltage LCD drive voltage LVDD VSS= 0 V 2.7 to 3.6, 4.5 to 5.5 DVDD VSS= 0 V 3.5 to 5.5 V CLOCK frequency fcp  0.01 to 2 MHz Operating temperature Ta  –40 to +105 °C Recommended setting range for external parts (for oscillator circuit) Parameter Min. Max. (LVDD = 4.5 to 5.5 V) Unit Symbol Condition Oscillator resistor RO  20 82 k Oscillator capacitor CO  0.01 0.047 F Frame frequency fFRM  14.6 451.0 Hz The relationship between external oscillator resistor value, external oscillator capacitor value, and frame frequency is as follows: fFRM = fOSC / 24 fOSC = 1 / (device coefficient  external oscillator resistor value RO  external oscillator capacitor value CO) Device coefficient = 0.623% Parameter (LVDD = 2.7 to 3.6 V) Unit Symbol Condition Min. Max. RO  20 82 Oscillator capacitor CO  0.01 0.047 F Frame frequency fFRM  14.6 451.0 Hz Oscillator resistor k The relationship between external oscillator resistor value, external oscillator capacitor value, and frame frequency is as follows: fFRM = fOSC / 24 fOSC = 1 / (device coefficient  external oscillator resistor value RO  external oscillator capacitor value CO) Device coefficient = 0.623% 6/20 FEDL9477-01 ML9477 ELECTRICAL CHARACTERISTICS DC Characteristics Parameter Symbol VIH “H” input voltage VIHOSC VIL “L” input voltage VILOSC IIH1 “H” input current IIHOSC IIL1 “L” input current IIL2 IILOSC VOS0 Segment output voltage VOS1 VOS2 VOS3 VOC0 Common output voltage VOC1 VOC2 VOC3 Dynamic supply current *1 *2 *3 IDVDD+IL VDD (LVDD = 2.7 to 3.6 V, 4.5 to 5.5 V, DVDD = 3.5 to 5.5, Ta = –40 to +105°C) Applicable Condition Min. Max. Unit pin LVDD = 4.5 to 5.5V 0.8LVDD *1 LVDD = 2.7 to 3.6V 0.85LVDD LVDD = 4.5 to 5.5V LVDD V 0.8LVDD CLKSEL = ”H” OSC LVDD = 2.7 to 3.6V 0.85LVDD CLKSEL = ”H” LVDD = 4.5 to 5.5V 0.2LVDD *1 LVDD = 2.7 to 3.6V 0.15LVDD LVDD = 4.5 to 5.5V 0 V 0.2LVDD CLKSEL = ”H” OSC LVDD = 2.7 to 3.6V 0.15LVDD CLKSEL = ”H” VI = LVDD  1 A *2 VI = LVDD  1 A OSC CLKSEL = ”H” VI = 0V –1  A *2 LVDD = 5V –0.009 –0.045 mA VI = 0V RESET LVDD = 3V –0.004 –0.030 mA VI = 0V VI = 0V –1  A OSC CLKSEL = ”H” DVDD = 4.5V DVDD – 0.8  V IO = –10A DVDD = 4.5V 2/3DVDD – 0.8 2/3DVDD + 0.8 V IO = 10A SEG1 to SEG32 DVDD = 4.5V 1/3DVDD – 0.8 1/3DVDD + 0.8 V IO = 10A DVDD = 4.5V  0.8 V IO = 10A DVDD = 4.5V DVDD – 0.77  V IO = –10A DVDD = 4.5V 2/3DVDD – 2/3DVDD+0.77 V IO = 10A COM1 to 0.77 COM4 DVDD = 4.5V 1/3DVDD – 1/3DVDD+0.77 V IO = 10A 0.77 DVDD = 4.5V  0.77 V IO = 10A LVDD, *3  0.5 mA DVDD CLOCK, LOAD, DATA_IN, RESET, 3/4SEL, and CLKSEL CLOCK, LOAD, DATA_IN, 3/4SEL, and CLKSEL CO = 0.022 F, RO = 33 k, no load 7/20 FEDL9477-01 ML9477 Switching Characteristics (Serial Interface) (LVDD = 2.7 to 3.6 V, 4.5 to 5.5 V, DVDD = 3.5 to 5.5 V, Ta = 40 to +105°C) Symbol Condition Min. Max. Unit fCP — 0.01 2.0 MHz Parameter Clock frequency Clock pulse width tWCP — Rise time, Fall time *4 t r , tf — Data setup time tDSU — Data hold time tDHD — Load pulse width tWLD — Clock to load time tCL — Load to clock time tLC — *4 70 — ns — 3 s 50 — ns 50 — ns 100 — ns 100 — ns 100 — ns Applied to CLOCK pin tWCP tr VIH CLOCK tWCP tf VIH VIL VIL 1/fCP tDSU tDHD DATA_IN VIH VIL tWLD tCL LOAD VIH tLC VIL 8/20 FEDL9477-01 ML9477 Switching Characteristics (External Clock Input to OSC) Parameter OSC input frequency (LVDD = 2.7 to 3.6 V, 4.5 to 5.5 V, DVDD = 3.5 to 5.5 V, Ta = 40 to +105°C) Symbol Condition Min. Max. Unit fosc CLKSEL = ”H” 0.5 10 kHz OSC rise time, fall time *5 trosc, tfOSC CLKSEL = ”H” — OSC “H” period tWHOSC CLKSEL = ”H” OSC “L” period tWLOSC CLKSEL = ”H” *5 1 s 4 — s 4 — s Applied to OSC pin 1/fOSC trosc OSC VIHOSC VILOSC tfosc tWHOSC VILOSC VIHOSC VILOSC tWLOSC 9/20 FEDL9477-01 ML9477 POWER-ON/OFF TIMING Voltage DVDD LVDD t t Time If LVDD is in the range of 0 V to LVDDmin, make sure that LVDD  DVDD and t  0[ns] are satisfied. When performing power-on reset with a capacitor connected to the RESET pin, be careful about the relationship between the capacitance value and the rise time of the power supply. INITIALIZATION TIMING LVDD LVDDmin RESET VIL t1 Drive the RESET pin Low and hold it Low under the condition “t1  0[ns]” until LVDD reaches LVDDmin. The value of the current of the pull-up resistor is specified for RESET pin. The customer needs to select an external capacitor that meets the timing requirements shown above. 10/20 FEDL9477-01 ML9477 FUNCTIONAL DESCRIPTION Description of Operation  Display data input As described in the section on “Data Structure,” display data consists of a data field, which corresponds to the LCD segments ON and OFF, and a command field, which indicates the input of display data. Set a value in each of bits C0 and C1 in the command field according to the common output that corresponds to the display data, and set a display data input command in the remaining four bits. Data that has been input to the DATA_IN pin is loaded into the shift register on the rising edges of the CLOCK pulses, transferrred to the display data latch during the “H” level period of the LOAD pulse, and then output via the segment driver. CLOCK DATA_IN D1 D2 D3 D4 D30 D31 D32 C0 C1 C2 C3 C4 C5 LOAD Display output Old data New data 11/20 FEDL9477-01 ML9477  Display ON, display OFF Display goes off when power-on reset is executed; therefore, to turn display on, write the display ON command (F5). The display OFF command (F4) is a command that makes all segments go off. By writing the display OFF command, the segments go off irrespective of display data. The display ON command (F5) is a command that clears a display off state. By writing the display ON command, display goes back to the previous state. CLOCK DATA_IN D1 D2 C4 C5 C2 C3 C4 C5 C2 C3 C4 C5 LOAD Display ON/OFF RESET Input of display data Write display ON command Write display OFF command 12/20 FEDL9477-01 ML9477 List of Commands Command name F0 F0’ F1 C5 0 0 0 C4 0 0 0 C3 0 0 1 C2  1 0 C1   0 1 F2 F3 0 0 1 1 0 1  0  0 1 F3’ F4 F5 F6 F7 F8 0 1 1 1 1 1 1 0 0 1 0 1 1 1 1 0 0 1 1 0 1          C0   0 1 0 1  0 1 0 1       Description Disabled Disabled Display data input (corresponds to COM1) Display data input (corresponds to COM2) Display data input (corresponds to COM3) Display data input (corresponds to COM4) Disabled Disabled Disabled Disabled Disabled Disabled Display OFF Display ON Disabled Disabled Disabled : Don't care If a “Disabled” command is executed, no transfer is carried out from the shift register to the latch; however, data within the shift register will be rewritten. To transfer correct data to the latch, it is necessary to transfer data again using the F1 command. 13/20 FEDL9477-01 ML9477 Data Structure [Input data] First bit Corresponds to SEG32 Corresponds to SEG1 C5 C4 C3 C2 Command C1 C0 D32 D31 D30 D3 D2 D1 LCD display data Note 1: The setting of command F4 or F5 becomes enabled by inputting only the four bits of C2 to C5. (No need to input D1 to D32, C0, or C1.) Note 2: If any dummy bits are required because of the transfer bit count, add them before the first bit. Note 3: Command execution depends on the value of bits C5 to C0 stored immediately before LOAD goes to a “H” level. 14/20 FEDL9477-01 ML9477 Common and Segment Output Waveforms  1/3 duty COM1 DVDD V1 V2 VSS COM2 DVDD V1 V2 VSS COM3 DVDD V1 V2 VSS SEG1 DVDD V1 V2 VSS SEG2 DVDD V1 V2 VSS Display S E G 1 S E G 2 COM1 COM2 COM3 15/20 FEDL9477-01 ML9477  1/4 duty COM1 DVDD V1 V2 VSS COM2 DVDD V1 V2 VSS COM3 DVDD V1 V2 VSS COM4 DVDD V1 V2 VSS SEG1 DVDD V1 V2 VSS Display S E G 1 S E G 2 COM1 COM2 COM3 COM4 DVDD SEG2 V1 V2 VSS 16/20 FEDL9477-01 ML9477 APPLICATION CIRCUIT COM1 1/4 duty LCD COM2 COM3 COM4 SEG1 SEG32 SEG1 SEG32 COM1 COM2 COM3 LOAD DATA_IN CPU CLOCK CLKSEL ML9477 COM4 DVDD +5 V LVDD +5 V OSC 3/4SEL VSS RESET TEST 17/20 FEDL9477-01 ML9477 PACKAGE DIMENSIONS (Unit: mm) Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact ROHM's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 18/20 FEDL9477-01 ML9477 REVISION HISTORY Document No. Date Previous Edition FEDL9477-01 Mar. 1, 2010 – Page Current Edition – Description Final edition 1 19/20 FEDL9477-01 ML9477 NOTICE No copying or reproduction of this document, in part or in whole, is permitted without the consent of LAPIS Semiconductor Co., Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing LAPIS Semiconductor's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from LAPIS Semiconductor upon request. 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