MR44V100AMAZAATL

Dear customer LAPIS Semiconductor Co., Ltd. ("LAPIS Semiconductor"), on the 1st day of October, 2020, implemented the incorporation-type company split (shinsetsu-bunkatsu) in which LAPIS established a new company, LAPIS Technology Co., Ltd. (“LAPIS Technology”) and LAPIS Technology succeeded LAPIS Semiconductor’s LSI business. Therefore, all references to "LAPIS Semiconductor Co., Ltd.", "LAPIS Semiconductor" and/or "LAPIS" in this document shall be replaced with "LAPIS Technology Co., Ltd." Furthermore, there are no changes to the documents relating to our products other than the company name, the company trademark, logo, etc. Thank you for your understanding. LAPIS Technology Co., Ltd. October 1, 2020 FEDR44V100A-01 Issue Date: Sep. 04, 2017 MR44V100A 1M Bit(131,072-Word -Word × 8-Bit) FeRAM (Ferroelectric Random Access Memory) I2C GENERAL DESCRIPTION The MR44V100A is a nonvolatile 131,072-word x 8-bit ferroelectric random access memory (FeRAM) developed in the ferroelectric process and silicon-gate CMOS technology. The MR44V100A is accessed using Two-wire Serial Interface ( I2C BUS ).Unlike SRAMs, this device, whose cells are nonvolatile, eliminates battery backup required to hold data. This device has no mechanisms of erasing and programming memory cells and blocks, such as those used for various EEPROMs. Therefore, the write cycle time can be equal to the read cycle time and the power consumption during a write can be reduced significantly. The MR44V100A can be used in various applications, because the device is guaranteed for the write/read tolerance of 1012 cycles per bit and the rewrite count can be extended significantly. FEATURES • 131,072-word × 8-bit configuration I2C BUS Interface • A single 3.3 V typ. (1.8V to 3.6V) power supply • Operating frequency: 3.4MHz(Max) HS-mode 1MHz(Max) F/S-mode Plus • Read/write tolerance 1012 cycles/bit • Data retention 10 years • Guaranteed operating temperature range −40 to 85°C • Low power consumption Power supply current (@3.4MHz) 1.1mA(Max.) Standby mode supply current 10μA(Typ.), 50μA(Max.) Sleep mode supply current 0.1μA(Typ.), 2μA(Max.) • Package options: 8-pin plastic SOP (P-SOP8-200-1.27-T2K) • RoHS (Restriction of hazardous substances) compliant 1/18 FEDR44V100A-01 MR44V100A PIN CONFIGURATION 8-pin plastic SOP 1 A1 2 A2 3 VSS 4 MR44V100A NC 8 VCC 7 WP 6 SCL 5 SDA PIN DESCRIPTIONS Pin Name NC A1 – A2 Description Not Connected Pin (open) It should always be left open or connected to any potential (ground, power supply) Address ( input ) Address pin indicates device address. When Address value is match the device address code from SDA, the device will be selected. The address pins are pulled down internally. Serial data input serial data output ( input / output ) SDA SDA is a bi-directional line for I2C interface. The output driver is open-drain. A pull-up resistor is required. Serial Clock ( input ) SCL Serial Clock is the clock input pin for setting for serial data timing. Inputs are latched on the rising edge and outputs occur on the falling edge. Write protect ( input ) WP VCC, VSS Write Protect pin controls write-operation to the memory. When WP is high, all address in the memory will be protected. When WP is low, all address in the memory will be written. WP pin is pulled down internally. Power supply Apply the specified voltage to VCC. Connect VSS to ground. 2/18 FEDR44V100A-01 MR44V100A I2C BUS The MR44V100A employs a bi-directional two-wire I2C BUS interface, works as a slave device. An example of I2C interface system with MR44V100A Pull-up resistor SCL SDA SCL SDA I2C BUS master SCL SDA SCL SDA MR44V100A MR44V100A (slave) (slave) A2 A1 A2 A1 00 01 I2C BUS COMUNICATION I2C BUS data communication starts by start condition input, and ends by stop condition input. Data is always 8bit long, acknowledge is always required after each byte. I2C BUS carries out data transmission with plural devices connected by 2 communication lines of serial data ( SDA ) and serial clock ( SCL ). 1-7 SCL 8 9 1-7 8 9 1-7 8 9 SDA ADDRESS START condition R/W ACK DATA ACK DATA ACK STOP condition START CONDITION Before executing each command, start condition ( start bit ) where SDA goes from “HIGH” down to “LOW” when SCL is “HIGH” is necessary. MR44V100A always detects whether SDA and SCL are in start condition ( start bit ) or not, therefore, unless this condition is satisfied, any command is not executed. STOP CONDITION Each command can be ended by SDA rising from “LOW” to “HIGH” when stop condition ( stop bit ), namely, SCL is “HIGH”. 3/18 FEDR44V100A-01 MR44V100A ACKNOWLEDGE ( ACK ) SIGNAL This acknowledge ( ACK ) signal is a software rule to show whether data transfer has been made normally or not. In master and slave, the device (μ-COM at slave address input of write command, read command, and this IC at data output of read command) at the transmitter (sending) side releases the bus after output of 8bit data. The device (this IC at slave address input of write command, read command, and μ-COM at data output of read command) at the receiver (receiving) side sets SDA “LOW” during 9 clock cycles, and outputs acknowledge signal ( ACK signal) showing that it has received the 8bit data. This IC, after recognizing start condition and slave address (8bit), outputs acknowledge signal ( ACK signal) “LOW”. Each write action outputs acknowledge signal ( ACK signal ) “LOW”, at receiving 8bit data ( word address and write data ). Each read action outputs 8bit data ( read data ), and detects acknowledge signal ( ACK signal ) “LOW”. When acknowledge signal ( ACK signal ) is detect, and stop condition is not sent from the master (μ-COM) side, this IC continues data output. When acknowledge signal ( ACK signal ) is not detected, this IC stops data transfer, and recognizes stop condition ( stop bit ), and ends read action. And this IC gets in status. SLAVE ADDRESS Output a slave address after start condition from master. The significant 4 bits of slave address are used for recognizing a device type. The device code of this IC is fixed to “1010”. Next slave addresses (A2 A1 … device address) are for selecting devices, and plural ones can be used on a same bus according to the number of device addresses, and next comes most significant bit (WA16). The most insignificant bit (R/W…READ/WRITE) of slave address is used for designating write or read action, and is as shown below. Setting R/W to 0 Setting R/W to 1 SCL SDA START condition write (setting 0 to word address setting of random read) read 1 2 3 4 5 1 0 1 0 A2 6 7 8 9 1 2 A1 WA16 R/W ACK WRITE PROTECT When WP terminal is set Vcc(H level), data rewrite of all addresses is prohibited. When it is set Vss(L level), data rewrite of all address is enabled. Be sure to connect this terminal to Vcc or Vss, or control it to H level or L level. Because this terminal is pulled down internally, in the case of Open the terminal will be recognized as L level During write cycle WP terminal must be always “L” level. WP terminal must be fixed from start condition to stop condition. 4/18 FEDR44V100A-01 MR44V100A COMMAND BYTE WRITE CYCLE Arbitrary data is written to FeRAM. When to write only 1 byte, byte write is normally used. start condition slave address with LSB is 0 (write) 1st and 2nd word address byte of write data. stop condition S T A R T W R I T E Slave address 1 0 1 0 A2 A1 st 1 WORD address W A 16 W A 15 2 W A 8 A C K nd WORD address W A 7 S T O P Write data W A 0 A C K D 7 D 0 A C K A C K PAGE WRITE CYCLE When to write continuous data of 2 bytes or more, simultaneous write is possible by page write cycle. The address reaches the final address, the address will be rolled over to the first address. By page write cycle, up to 128K bytes data can be written. When data above the maximum bytes are sent, data from the first byte will be overwritten. S T A R T W R I T E Slave address 1 0 1 0 A2 A1 st 1 WORD address W A 16 W A 15 2 W A 8 A C K nd WORD address W A 7 Write data W A 0 A C K D 7 S T O P Write data D 0 A C K D 7 D 0 A C K A C K RANDOM READ CYCLE Random read cycle is a command to read data by designating address. Random read sequence 3. 1. Next to Start condition, slave address with LSB is 0 (write) 2. 1st and 2nd word address Next to Start condition, slave address with LSB is 1 (read) The bit of equivalent to WA16 is ignored. 4. read out byte of data. 5. ACK to “H” 6. Send Stop condition and finish the sequence. S T A R T W R I T E Slave address 1 0 1 0 A2 A1 st 1 WORD address W A 16 W A 15 A C K 2 W A 8 W A 7 A C K nd S T A R T WORD address W A 0 Slave address R E A D Read data 1 0 1 0 A2 A1 X A C K S T O P D 7 A C K D 0 N A C K 5/18 FEDR44V100A-01 MR44V100A SEQUENTIAL READ CYCLE When ACK signal “L” after D0 is detected, and stop condition is not sent from master side, the next address data can be read in succession. The address reaches the final address, the address will be rolled over to the first address. S T A R T W R I T E Slave address 1 0 1 0 A2 A1 1st WORD address W A 16 W A 15 S T A R T 2nd WORD address W A 8 A C K W A 7 W A 0 Slave address R E A D Read data 1 0 1 0 A2 A1 X A C K D 0 A C K A C K S T O P D 7 D 0 A C K N A C K CURRENT ADDRESS READ CYCLE Current address read cycle is a command to read data of internal address register without designating address. When the last read or write address is (n)-th address just before current read cycle, the current address read command outputs data of (n+1)-th address. The previous read or write sequence should be complete up to stop condition. Just after POWER ON or after recovering from SLEEP mode, the internal address resister is unstable. S T A R T Slave address R E A D S T O P Read data 1 0 1 0 A2 A1 X D0 D7 N A C K A C K HS-MODE The MR44V100A support a maximum 3.4MHz high speed mode. When HS-mode operation is needed, the HS-mode command is required before any command. After the HS-mode command is issued, MR44V100A will be the HS-mode, until stop condition is issued. CURRENT ADDRESS READ CYCLE ( HS-MODE ) S T A R T S T A R T HS-mode command 0 0 0 0 1 X X X R E A D Slave address S T O P Read data 1 0 1 0 A2 A1 X D7 D0 A C K N A C K N A C K HS mode BYTE WRITE CYCLE ( HS-MODE ) S T A R T S T A R T HS-mode command 0 0 0 0 1 X X X Slave address 1 0 1 0 A2 A1 N A C K W R I T E st 1 WORD address W A 16 W A 15 A C K 2 W A 8 nd WORD address W A 7 A C K S T O P Write data W A 0 D 7 A C K D 0 A C K HS mode 6/18 FEDR44V100A-01 MR44V100A DEVICE ID The device ID can be read out. The ID is constructed with 12bit Manufacture ID and 12bit Device type. Device ID Read Sequence 1. Next to Start condition, send 0xF8. MR44V100A responds ACK signal. 2. Send the Slave address (WA16 and R/W are “Don’t care”). MR44V100A responds ACK signal. 3. Again next to Start condition, send 0xF9. MR44V100A responds ACK signal, then outputs 3 bytes of Device ID. 4. Send Stop condition and finish the sequence. 1st Byte 0x01 Manufacture ID ( LAPIS ) S T A R T 0xF8 S T A R T Slave address 1 1 1 1 1 0 0 0 0xF9 3rd Byte 0x00 Device Type ( MR44V100A ) Read data 1 1 1 1 1 0 0 1 1 0 1 0 A2 A1 X X A C K 2nd Byte 0xb0 A C K D 7 Read data Read data D 0 D 7 A C K A C K Manufacture ID S T O P D 7 D 0 A C K Device type D 0 N D A 7 C D K 7 SLEEP MR44V100A can provide SLEEP Mode which suppresses the current consumption more than Standby status. Transition to SLEEP Mode and Return from SLEEP mode are the following sequences. Transition to SLEEP Mode 1. Next to Start condition, send 0xF8. MR44V100A responds ACK signal. 2. Send the Slave address (WA16 and R/W are ”Don’t care”). MR44V100A responds ACK signal. 3. Again Next to Start condition, send 0xF8. MR44V100A responds ACK signal and transits to SLEEP Mode. 4. Send Stop condition, finish the sequence. S T A R T 0xF8 S T A R T Slave address 1 1 1 1 1 0 0 0 S T O P 0x86 1 0 0 0 0 1 1 0 1 0 1 0 A2 A1 X X A C K A C K A C K Return from SLEEP Mode 1. Next to Start condition, send the Slave address (WA16 and R/W are “Don’t care”）. 2. When the device address is matched, Start the operation of returning from SLEEP Mode at the falling edge of 6th clocks of SCL after Start condition. When the device address is not matched, SLEEP mode will continue. . 3. Return to standby after the Returning time from SLEEP. After that, as sending the Slave address and responding ACK signal, MR44V100A is returning from SLEEP. S T A R T S T A R T Slave address 1 0 1 0 A2 A1 X X X Returning ↑Start returning Slave address 1 0 1 0 A2 A1 WA 16 R/ W A C K Caution : When to input Slave address for returning from SLEEP mode, Stop condition is not recognized. 7/18 FEDR44V100A-01 MR44V100A Software Reset Software reset is executed to avoid malfunction after power ON, and during command input. SCL 1 2 3 4 5 6 7 8 9 SDA Start condition x 9 Normal command 8/18 FEDR44V100A-01 MR44V100A ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS The application of stress (voltage, current, or temperature) that exceeds the absolute maximum rating may damage the device. Therefore, do not allow actual characteristics to exceed any one parameter ratings PIN VOLTAGES Parameter Pin Voltage (Input Signal) Pin Voltage (Input/Output Voltage) Power Supply Voltage Symbol Rating Unit Min. Max. VIN –0.5 VCC + 0.5 V VINQ, VOUTQ –0.5 VCC + 0.5 V VCC –0.5 4.0 V Note TEMPERATURE RANGE Parameter Symbol Rating Min. Max. Unit Storage Temperature Tstg –55 125 °C Operating Temperature Topr –40 85 °C Note OTHERS Parameter Power Dissipation Symbol Rating Note PD 1,000mW Ta=25°C 9/18 FEDR44V100A-01 MR44V100A RECOMMENDED OPERATING CONDITIONS POWER SUPPLY VOLTAGE Symbol Min. Typ. Max. Unit Power Supply Voltage VCC 1.8 3.3 3.6 V Ground Voltage VSS 0 0 0 V Parameter Note DC INPUT VOLTAGE Symbol Min. Max. Unit Input High Voltage VIH VCC x 0.7 VCC + 0.3 V Input Low Voltage VIL –0.3 VCC x 0.3 V Parameter Note 10/18 FEDR44V100A-01 MR44V100A DC CHARACTERISTICS DC INPUT/OUTPUT CHARACTERISTICS Symbol Condition Min. Max. Unit VOL IOL =3mA ― 0.4 V Input Leakage Current ILI ― –10 10 µA Output Leakage Current ILO ― –10 10 µA Parameter Output Low Voltage Note POWER SUPPLY CURRENT VCC=Max.to Min, Ta=Topr Parameter Power Supply Current (Standby) Power Supply Current (Sleep) Power Supply Current (Operating) Symbol ICCS IZZ ICCA Condition SCL,SDA= VCC, A2,A1= VCC or VSS SCL,SDA= VCC, A2,A1,WP= VCC or VSS VIN=0.3V or VCC－0.3V, fSCL=3.4MHz fSCL=1MHz Typ.* Max. Unit 10 50 µA 0.1 2 µA 0.7 350 1.1 450 mA µA Note Note: Typical condition Vcc=3.3V, Ta=Room temperature. 11/18 FEDR44V100A-01 MR44V100A AC CHARACTERISTICS VCC=Max. to Min., Ta=Topr. F/S-mode Parameter Symbol F/S-mode Plus HS-mode Unit Min. Max. Min. Max. Min. Max. Note Clock frequency fSCL D.C. 400 D.C. 1000 DC 3400 KHz Clock Low time tLOW 1300 — 500 — 160 — ns Clock High time tHIGH 600 — 300 — 60 — ns tAA — 900 — 450 — 130 ns tBUF 1300 — 500 — 300 — ns Start condition hold time tHD:STA 600 — 250 — 160 — ns Start condition setup time tSU:STA 600 — 250 — 160 — ns Input data hold time tHD:DAT 0 — 0 — 0 — ns Input data setup time tSU:DAT 100 — 100 — 10 — ns SDA, SCL rise time tR — 300 — 300 — 80 ns 1 SDA, SCL fall time tF — 300 — 120 — 80 ns 1 tSU:STO 600 — 250 — 160 — ns Output data hold time tDH 0 — 0 — 0 — ns Noise removal time (SDA, SCL) tSP — 50 — 50 — 5 ns tREC — 100 — 100 — 100 µs Output Data delay time BUS release time before transfer start Stop condition setup time Sleep mode recovery time Note: 1. Not 100% tested Equivalent AC Load Circuit 3.3V 1kΩ Output 100pF 12/18 FEDR44V100A-01 MR44V100A TIMING 1/fSCL tR tF SCL VIL tF SDA (input) SDA (output) SCL SDA (input) tHIGH VIH VIH VIH VIL VIL VIH VIL tLOW tSP VIH VIL VIL tHD:DAT VIH VIL tR tSU:DAT tSP VIH VIH VIH VIL VIL tBUF tAA VIH VIH tSU:STA tHD:STA tDH VIH VIH VIL VIL VIH tSU:STO VIH VIL START BIT VIL STOP BIT 13/18 FEDR44V100A-01 MR44V100A •POWER-ON AND POWER-OFF CHARACTERISTICS Parameter Power-On SCL,SDA High Hold Time Power-Off SCL, SDA High Hold Time Power-On Interval Time VCC Power-On ramp rate VCC Power-Off ramp rate Symbol tVHEL tEHVL tVLVH tr tf (Under recommended operating conditions) Min. 100 0 0 30 30 Max. ⎯ ⎯ ⎯ Unit ns ns μs μs/V μs/V Note 1, 2 1 2 Notes: 1. To prevent an erroneous operation, be sure to maintain SCL=SDA="H", and set the FeRAM in an inactive state (standby mode) before and after power-on and power-off. 2. Powering on at the intermediate voltage level will cause an erroneous operation; thus, be sure to power up from 0 V. 3. Enter all signals at the same time as power-on or enter all signals after power-on. •Power-On and Power-Off Sequences tEHVL tVHEL VCC VCC VCC Min. VIH Min. VCC Min. tf tr VIH Min. tVLVH VIL Max. SCL,SDA 0V VIL Max. SCL,SDA 0V ・After Power-Off, terminal state When MR44V100A only goes power-off while the other IC’s on I2C bus are active, all the input pins including I/O pin of MR44V100A must be GND level. (When to reduce stand-by current while SCL or SDA bus are active, recommend the use of SLEEP mode.) 14/18 FEDR44V100A-01 MR44V100A READ/WRITE CYCLES AND DATA RETENTION Ta=Topr (Under recommended operating conditions) Parameter Min. 12 10 10 Read/Write Cycle Data Retention Max. ⎯ ⎯ Unit Cycle Year Note CAPACITANCE VCC =3.3V, VIN = VOUT = GND, f = 1MHz, and Ta = 25°C Signal Input Capacitance Input/Output Capacitance Symbol CIN COUT Min. ⎯ ⎯ Max. 10 10 Unit pF pF Note 1 1 Note1: Sampling value. 15/18 FEDR44V100A-01 MR44V100A PACKAGE DIMENSIONS (Unit: mm) Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 16/18 FEDR44V100A-01 MR44V100A REVISION HISTORY Page Document No. FEDR44V100A-01 Date Sep. 04, 2017 Previous Edition Current Edition – – Description Final edition 1 17/18 FEDR44V100A-01 MR44V100A Notes 1) The information contained herein is subject to change without notice. 2) Although LAPIS Semiconductor is continuously working to improve product reliability and quality, semiconductors can break down and malfunction due to various factors. Therefore, in order to prevent personal injury or fire arising from failure, please take safety measures such as complying with the derating characteristics, implementing redundant and fire prevention designs, and utilizing backups and fail-safe procedures. LAPIS Semiconductor shall have no responsibility for any damages arising out of the use of our Products beyond the rating specified by LAPIS Semiconductor. 3) Examples of application circuits, circuit constants and any other information contained herein are provided only to illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. 4) The technical information specified herein is intended only to show the typical functions of the Products and examples of application circuits for the Products. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of LAPIS Semiconductor or any third party with respect to the information contained in this document; therefore LAPIS Semiconductor shall have no responsibility whatsoever for any dispute, concerning such rights owned by third parties, arising out of the use of such technical information. 5) The Products are intended for use in general electronic equipment (i.e. AV/OA devices, communication, consumer systems, gaming/entertainment sets) as well as the applications indicated in this document. 6) The Products specified in this document are not designed to be radiation tolerant. 7) For use of our Products in applications requiring a high degree of reliability (as exemplified below), please contact and consult with a LAPIS Semiconductor representative: transportation equipment (i.e. cars, ships, trains), primary communication equipment, traffic lights, fire/crime prevention, safety equipment, medical systems, servers, solar cells, and power transmission systems. 8) Do not use our Products in applications requiring extremely high reliability, such as aerospace equipment, nuclear power control systems, and submarine repeaters. 9) LAPIS Semiconductor shall have no responsibility for any damages or injury arising from non-compliance with the recommended usage conditions and specifications contained herein. 10) LAPIS Semiconductor has used reasonable care to ensure the accuracy of the information contained in this document. However, LAPIS Semiconductor does not warrant that such information is error-free and LAPIS Semiconductor shall have no responsibility for any damages arising from any inaccuracy or misprint of such information. 11) Please use the Products in accordance with any applicable environmental laws and regulations, such as the RoHS Directive. For more details, including RoHS compatibility, please contact a ROHM sales office. LAPIS Semiconductor shall have no responsibility for any damages or losses resulting non-compliance with any applicable laws or regulations. 12) When providing our Products and technologies contained in this document to other countries, you must abide by the procedures and provisions stipulated in all applicable export laws and regulations, including without limitation the US Export Administration Regulations and the Foreign Exchange and Foreign Trade Act. 13) This document, in part or in whole, may not be reprinted or reproduced without prior consent of LAPIS Semiconductor. Copyright 2017 LAPIS Semiconductor Co., Ltd. 2-4-8 Shinyokohama, Kouhoku-ku, Yokohama 222-8575, Japan http://www.lapis-semi.com/en/ 18/18