MR45V200BRAZAARL

Dear customer LAPIS Semiconductor Co., Ltd. ("LAPIS Semiconductor"), on the 1st day of October, 2020, implemented the incorporation-type company split (shinsetsu-bunkatsu) in which LAPIS established a new company, LAPIS Technology Co., Ltd. (“LAPIS Technology”) and LAPIS Technology succeeded LAPIS Semiconductor’s LSI business. Therefore, all references to "LAPIS Semiconductor Co., Ltd.", "LAPIS Semiconductor" and/or "LAPIS" in this document shall be replaced with "LAPIS Technology Co., Ltd." Furthermore, there are no changes to the documents relating to our products other than the company name, the company trademark, logo, etc. Thank you for your understanding. LAPIS Technology Co., Ltd. October 1, 2020 FEDR45V200B-02 Issue Date: Oct. 2, 2018 MR45V200B 2M(262,144-Word  8-Bit) FeRAM (Ferroelectric Random Access Memory) SPI GENERAL DESCRIPTION The MR45V200B is a nonvolatile 262,144-word x 8-bit ferroelectric random access memory (FeRAM) developed in the ferroelectric process and silicon-gate CMOS technology. The MR45V200B is accessed using Serial Peripheral Interface. Unlike SRAMs, this device, whose cells are nonvolatile, eliminates battery backup required to hold data. This device has no mechanisms of erasing and programming memory cells and blocks, such as those used for various EEPROMs. Therefore, the write cycle time can be equal to the read cycle time and the power consumption during a write can be reduced significantly. The MR45V200B can be used in various applications, because the device is guaranteed for the write/read tolerance of 1013 cycles per bit and the rewrite count can be extended significantly. FEATURES 262,144-word  8-bit configuration (Serial Peripheral Interface: SPI) A single 2.7V to 3.6V power supply Operating frequency: 34MHz Read/write tolerance 1013 cycles/bit Data retention 10 years Guaranteed operating temperature range 40 to 85C Package: 8-pin plastic DIP • RoHS (Restriction of hazardous substances) compliant • • • • • • • 1/20 FEDR45V200B-02 MR45V200B PIN CONFIGURATION (TOP VIEW) 8-pin plastic DIP 1 SO 2 WP# 3 VSS 4 MR45V200B CS# 8 VCC 7 HOLD# 6 SCK 5 SI Note: Signal names that end with # indicate that the signals are negative-true logic. PIN DESCRIPTIONS Pin Name CS# Description Chip Select (input, negative logic) Latches an address by low input, activates the FeRAM, and enables read or write operation. High input goes the device disable state. Write Protect( input , negative logic ) WP# Write Protect pin controls write-operation to the status-register(BP0,BP1). This pin should be fixed low or high in write-operations. HOLD( input , negative logic ) HOLD# Hold pin is used when the serial-communication suspended without disable the chip select. When HOLD# is low, the serial-output is in High-Z status and serial-input/serial-clock are “Don’t Care”. CS# should be low in hold operation. Serial Clock SCK SI SO VCC, VSS Serial Clock is the clock input pin for setting for serial data timing. Inputs are latched on the rising edge and outputs occur on the falling edge. Serial input SI pins are serial input pins for Operation-code, addresses, and data-inputs. Serial output SO pins are serial output pins. Power supply Apply the specified voltage to VCC. Connect VSS to ground. 2/20 FEDR45V200B-02 MR45V200B SPI SPI mode0（CPOL=0, CPHA=0） CS# SCK SI MSB LSB SPI mode3（CPOL=1, CPHA=1） CS# SCK SI MSB LSB Status Register b7 b0 SRWD 0 0 0 BP1 BP0 WEL WIP Status Register Write Disable Block Protect Bits Write Enable Latch Write In Progress (Always 0) Name WIP WEL BP0,BP1 SRWD 0 Function Fixed to 0. WEL indicates internal Write Enable Latch status. The WEL is set after WREN command. After WRDI command, WRSR command, WRITE command, or Power on, the WEL can be reset. Block Protect: These bits can change protected area. This is the software protect. Status Register Write Disable （ SRWD ） : SRWD controls the effect of the hardware WP# pin. This device will be in hardware-protect by combination of SRWD and WP#. Fixed to 0. Reserved for future use. (RFU) 3/20 FEDR45V200B-02 MR45V200B Operation-Code Operation codes are listed in the table below. If the device receives invalid operation code, the device will be deselected. Instruction Description Instruction format WREN WRDI RDSR WRSR READ WRITE RDID Write Enable Write Disable Read Status Register Write Status Register Read from Memory Array Write to Memory Array Read Device ID 0000 0110 0000 0100 0000 0101 0000 0001 0000 0011 0000 0010 1001 1111 COMMANDS WREN(Write Enable) It is necessary to set Write Enable Latch(WEL)bit before write-operation (WRITE and WRSR). WREN command sets WEL bit. CS# WP# Fixed “H” 0 1 2 3 4 5 6 7 2 3 4 5 6 7 SCK SI SO High-Z WRDI(Write Disable) WRDI command resets WEL bit. CS# WP# Fixed “H” 0 1 SCK SI SO High-Z 4/20 FEDR45V200B-02 MR45V200B RDSR(READ Status Register) The RDSR command allows reading data of status register. The Status Register can be read anytime and any number of times. CS# WP# Fixed “H” 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 7 6 5 4 3 2 1 0 SRWD 0 0 0 SCK SI SO High-Z 7 BP1 BP0 WEL WIP SRWD WRSR(WRITE Status Register） WRSR command allows to write data to status register(SRWD,BP0,BP1). It is necessary to set Write Enable Latch（WEL）bit by WREN command before executing WRSR. WRSR command cannot write RFU(b6,b5,b4), WEL(b1), WIP(b0) of Status Resistor.. CS# 0 1 2 3 4 5 6 7 8 9 10 11 7 6 5 4 SRWD X X X 12 13 14 15 3 2 1 0 X X SCK SI SO BP1 BP0 High-Z Note: WP#=Fixed ”H” 5/20 FEDR45V200B-02 MR45V200B READ(Read from Memory Array) READ command can be valid when CS# goes “L”, then the op-code and 24bit-adresses are inputted to serial input ”SI”. The inputted addresses are loaded to internal register, then the data from corresponded address is output at serial-output “SO”. If CS# will keep “L”, the internal address will be increased automatically after 8 clocks and will output the data from new-address. When it reaches the most significant address, the address counter rolls over to starting address and reading cycle can be continued infinitely. To finish read cycle, make the CS# “H” during LSB output clock. CS# 0 1 2 3 4 5 6 7 8 9 23 22 X X 14 15 16 17 16 15 28 29 30 31 SCK SI SO A17 A16 A15 3 2 1 0 A3 A2 A1 A0 24bit Address (An) High-Z CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 m-2 m-1 m Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Q2 Q1 Q0 SCK SI SO Data Out (An) Data Out (An+1) Note : WP# = fixed ”H” 6/20 FEDR45V200B-02 MR45V200B WRITE(Write to Memory Array) Write command can be valid when CS# goes “L”, then the op-code and 24bit-adresses are inputted to serial input ”SI”. Writing is terminated when CS# goes high after data-input. If CS# will keep “L”, the internal address will be increased automatically. When it reaches the most significant address, the address counter rolls over to starting address 0000h, and writing cycle (overwriting) can be continued infinitely. To finish write cycle, make CS# “H” during LSB input clock. WRITE(1Byte) CS# 0 1 2 3 4 5 6 7 8 9 23 22 X X 14 15 16 17 16 15 28 29 30 31 SCK SI 3 2 1 0 A3 A2 A1 A0 16 28 29 30 31 17 15 16 A17 A16 A15 3 A3 2 A2 1 A1 0 A0 A17 A16 A15 24bit Address An CS# 32 33 34 35 36 37 38 39 D7 D6 D5 D4 D3 D2 D1 D0 SCK SI Data In (An) Note : WP# = Fixed ”H” , SO=High-Z WRITE(Page) CS# 0 1 2 3 4 5 6 7 8 9 23 X 22 X 14 15 SCK SI 24bit Ad CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D5 D4 D3 SCK SI Data In (An) Data In (An+1) CS# 48 49 50 51 52 53 54 55 D7 D6 D5 D4 D3 D2 D1 D0 SCK SI Data In (An+2) D7 D6 D2 D1 D0 Data In (An+m) Note : WP# = Fixed ”H” , SO=High-Z 7/20 FEDR45V200B-02 MR45V200B RDID (Read device ID) RDID command can be valid when CS# goes “L”, then the op-code are inputted to serial input ”SI”. Then 3bytes of device ID is output at serial-output “SO”. Manufacture ID ( LAPIS ) 1st Byte AEh 2nd Byte 83h Device type ( MR45V200B ) 3rd Byte 1Ah CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 1 1 0 SCK SI 1st Byte SO 1 0 1 0 CS# 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 0 SCK SI nd 2 Byte SO 1 0 0 0 rd 3 Byte 0 0 1 1 0 0 0 1 1 Note : WP# = Fixed ”H” 8/20 FEDR45V200B-02 MR45V200B Write Protection Writing protection block is shown as follows: When Status Resister Write Disable(SRWD) bit is reset to “0”, Status Resister number can be changed Protect Block size Block Protect BIT BP1 BP0 0 0 1 1 0 1 0 1 Protected Block None Upper 1/4 block Upper 1/2 block All Protected Address Area None 30000h – 3FFFFh 20000h – 3FFFFh 00000h – 3FFFFh Writing Protect WP# SRWD 1 0 0 0 1 1 0 1 Protection status in memory Unprotected Protected blocks blocks mode Writing protection status in status register Software protection (SPM) Status register is unprotected when WEL-bit is set by WREN command. BP0 and BP1 are unprotected. Protected Unprotected Hardware protection (HPM) Status register is protected. BP0 and BP1 are protected. Protected Unprotected HOLD Hold status is used for suspending serial communication without disable the chip. SO becomes “High-Z” and SI is “Don’t care” during the hold status. It is necessary to keep CS#=L in hold status. Hold status Hold status SCK HOLD# 9/20 FEDR45V200B-02 MR45V200B ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings The application of stress (voltage, current, or temperature) that exceeds the absolute maximum rating may damage the device. Therefore, do not allow actual characteristics to exceed any one parameter ratings Pin voltages Parameter Symbol Rating Min. Max. Unit Pin Voltage (Input Signal) VIN –0.5 VCC + 0.5 V Pin Voltage (Input/Output Voltage) VINQ, VOUTQ –0.5 VCC + 0.5 V Power Supply Voltage VCC –0.5 4.0 V Temperature Range Parameter Symbol Storage Temperature (Extended Temperature Version) Operating Temperature (Extended Temperature Version) Rating Unit Min. Max. Tstg –55 125 °C Topr –40 85 °C Others Symbol Rating Power Dissipation PD 1,000mW Allowable Input Current IIN +/- 20mA Ta=25°C IOUT +/- 20mA Ta=25°C Parameter Allowable Output Current Unit 10/20 FEDR45V200B-02 MR45V200B Recommended Operating Conditions Power Supply Voltage Symbol Min. Typ. Max. Unit Power Supply Voltage VCC 2.7 3.3 3.6 V Ground Voltage VSS 0 0 0 V Parameter DC Input Voltage Symbol Min. Max. Unit Input High Voltage VIH VCC x 0.8 VCC＋0.3 V Input Low Voltage VIL –0.3 VCC x 0.15 V Parameter 11/20 FEDR45V200B-02 MR45V200B DC Characteristics DC Input/Output Characteristics Parameter Symbol Condition Min. Max. Unit Output High Voltage VOH IOH =－2mA VCC  0.85 ― V Output Low Voltage VOL IOL =2mA ― VCC  0.15 V Input Leakage Current ILI ― –10 10 µA Output Leakage Current ILO ― –10 10 µA Power Supply Current VCC=Max.to Min, Ta=Topr Parameter Symbol Power Supply Current (Standby) ICCS Power Supply Current (Operating) ICCA Min. Max. Unit CS#= VCC ,VIN=0V or VCC ― 100 µA VIN=0.2V or VCC－0.2V, SCK=Max., IOUT=0mA ― 10 mA Condition Note 1 Note1: average current. 12/20 FEDR45V200B-02 MR45V200B AC Characteristics VCC=Max. to Min., Ta=Topr. MR45V200B Parameter Symbol Unit Note Min. Max. fC D.C. 34 MHz CS# Active setup time tSLCH 10 ― ns CS# In-active setup-time tSHCH 10 ― ns CS# De-select time tSHSL 10 ― ns CS# Active hold time tCHSH 10 ― ns CS# In-active hold-time tCHSL 10 ― ns SCK High time tCH 13 ― ns 1 SCK Low time tCL 13 ― ns 1 SCK Rise time tCLCH ― 50 ns 2 SCK Fall time tCHCL ― 50 ns 2 Data Setup time tDVCH 5 ― ns Data Hold time tCHDX 5 ― ns SCK Low Hold time after HOLD# inactive tHHCH 10 ― ns SCK Low Hold time after HOLD# active tHLCH 10 ― ns SCK High Setup time before HOLD# active SCK High Setup time before HOLD# inactive tCHHL 10 ― ns tCHHH 10 ― ns Output disable time tSHQZ ― 12 ns SCK Low to Output Valid time tCLQV ― 12 ns Output Hold time tCLQX 0 ― ns tHHQX ― 20 ns 2 tHLQZ ― 20 ns 2 Clock frequency HOLD# High to Output Low impedance time HOLD# High to Output High impedance time Note: 1. tCH＋tCL≧1/fC 2. sample value 2 13/20 FEDR45V200B-02 MR45V200B Timing Diagrams tSHSL Serial Input Timing CS# tCHSL tSLCH tSHCH tCHSH SCK tDVCH SI tCHCL tCLCH tCHDX MSB IN LSB IN High Impedance SO Hold Timing CS# tCHHL tHLCH tHHCH SCK tCHHH tHLQZ tHHQX SO SI HOLD Output Timing CS# tCH SCK tCLQV tCLQX tCLQV tCL tSHQZ tCLQX SO LSB OUT Address, LSB IN tQLQH tQHQL SI 14/20 FEDR45V200B-02 MR45V200B Power-On and Power-Off Characteristics (Under recommended operating conditions) Parameter Symbol Min. Max. Unit Note Power-On CS# High Hold Time tVHEL 50  s 1, 2 Power-Off CS# High Hold Time tEHVL 100  ns 1 Power-On Interval Time tVLVH 1  s 2 Power-On Rise time tR 50 100,000 μs/V Power-down Fall time tF 100 μs/V Notes: 1. To prevent an erroneous operation, be sure to maintain CS#="H", and set the FeRAM in an inactive state (standby mode) before and after power-on and power-off. 2. Powering on at the intermediate voltage level will cause an erroneous operation; thus, be sure to power up from 0 V. 3. Enter all signals at the same time as power-on or enter all signals after power-on. Power-On and Power-Off Sequences tEHVL tVHEL VCC VCC VCC Min. VCC Min. VIH Min. VIH Min. tF VIL Max. CS# 0V tVLVH tR VIL Max. CS# 0V 15/20 FEDR45V200B-02 MR45V200B Read/Write Cycles and Data Retention (Under recommended operating conditions) Parameter Read/Write Cycle Data Retention Min. 13 10 10 Max.   Unit Cycle Year Note 1 Min.   Max. 10 10 Unit pF pF Note 1 1 Note: 1. Total power on time ≤ 10 years Capacitance Signal Input Capacitance Input/Output Capacitance Symbol CIN COUT Note: Sampling value. Measurement conditions are VIN = VOUT = GND, Vcc=3.3V, f = 1MHz, and Ta = 25°C 16/20 FEDR45V200B-02 MR45V200B ORDERING INFORMATION Product No. Package Type (Package Code) Packing Temp. Range MR45V200BRAZAARL 8-pin plastic DIP (P-DIP8-300-2.54-T6) Plastic Tube 40 to 85C 17/20 FEDR45V200B-02 MR45V200B PACKAGE DIMENSIONS (Unit: mm) 18/20 FEDR45V200B-02 MR45V200B REVISION HISTORY Page Document No. Date Previous Edition Current Edition Description FEDR45V200B-01 Sep. 14, 2018 – – Final edition 1 FEDR45V200B-02 Oct. 02, 2018 9 – 8 17 Moved RDID to page8 Added ordering information 19/20 FEDR45V200B-02 MR45V200B Notes 1) The information contained herein is subject to change without notice. 2) Although LAPIS Semiconductor is continuously working to improve product reliability and quality, semiconductors can break down and malfunction due to various factors. Therefore, in order to prevent personal injury or fire arising from failure, please take safety measures such as complying with the derating characteristics, implementing redundant and fire prevention designs, and utilizing backups and fail-safe procedures. LAPIS Semiconductor shall have no responsibility for any damages arising out of the use of our Products beyond the rating specified by LAPIS Semiconductor. 3) Examples of application circuits, circuit constants and any other information contained herein are provided only to illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. 4) The technical information specified herein is intended only to show the typical functions of the Products and examples of application circuits for the Products. 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However, LAPIS Semiconductor does not warrant that such information is error-free and LAPIS Semiconductor shall have no responsibility for any damages arising from any inaccuracy or misprint of such information. 11) Please use the Products in accordance with any applicable environmental laws and regulations, such as the RoHS Directive. For more details, including RoHS compatibility, please contact a ROHM sales office. LAPIS Semiconductor shall have no responsibility for any damages or losses resulting non-compliance with any applicable laws or regulations. 12) When providing our Products and technologies contained in this document to other countries, you must abide by the procedures and provisions stipulated in all applicable export laws and regulations, including without limitation the US Export Administration Regulations and the Foreign Exchange and Foreign Trade Act. 13) This document, in part or in whole, may not be reprinted or reproduced without prior consent of LAPIS Semiconductor. Copyright 2018 LAPIS Semiconductor Co., Ltd. 2-4-8 Shinyokohama, Kouhoku-ku, Yokohama 222-8575, Japan http://www.lapis-semi.com/en/ 20/20