MSM5412222B-25TK-MTL 数据手册
FEDS5412222B-02
Issue Date: Nov 01, 2012
MSM5412222B
262,214-Word 12-Bit Field Memory
GENERAL DESCRIPTION
The LAPIS Semiconductor MSM5412222B is a high performance 3-Mbit, 256K 12-bit, Field Memory. It is
especially designed for high-speed serial access applications such as HDTVs, conventional NTSC TVs, VTRs,
digital movies and Multi-media systems. MSM5412222B is a FRAM for wide or low end use in general
commodity TVs and VTRs exclusively. MSM5412222B is not designed for the other use or high end use in
medical systems, professional graphics systems which require long term picture storage, data storage systems and
others. More than two MSM5412222Bs can be cascaded directly without any delay devices among the
MSM5412222Bs. (Cascading of MSM5412222B provides larger storage depth or a longer delay).
Each of the 12-bit planes has separate serial write and read ports. These employ independent control clocks to
support asynchronous read and write operations. Different clock rates are also supported that allow alternate data
rates between write and read data streams.
The MSM5412222B provides high speed FIFO, First-In First-Out, operation without external refreshing:
MSM5412222B refreshes its DRAM storage cells automatically, so that it appears fully static to the users.
Moreover, fully static type memory cells and decoders for serial access enable the refresh free serial access
operation, so that serial read and/or write control clock can be halted high or low for any duration as long as the
power is on. Internal conflicts of memory access and refreshing operations are prevented by special arbitration
logic.
The MSM5412222B’s function is simple, and similar to a digital delay device whose delay-bit-length is easily set
by reset timing. The delay length, number of read delay clocks between write and read, is determined by externally
controlled write and read reset timings.
Additional SRAM serial registers, or line buffers for the initial access of 256 12-bit enable high speed
first-bit-access with no clock delay just after the write or read reset timings.
Additionally, the MSM5412222B has write mask function or input enable function (IE), and read-data skipping
function or output enable function (OE) . The differences between write enable (WE) and input enable (IE), and
between read enable (RE) and output enable (OE) are that WE and RE can stop serial write/read address
increments, but IE and OE cannot stop the increment, when write/read clocking is continuously applied to
MSM5412222B. The input enable (IE) function allows the user to write into selected locations of the memory
only, leaving the rest of the memory contents unchanged. This facilitates data processing to display a “picture in
picture” on a TV screen.
The MSM5412222B is similar in operation and functionality to LAPIS Semiconductor 1-Mbit Field Memory
MSM514222C and 2-Mbit Field Memory MSM518222A. Three MSM514222Cs or one MSM514222C plus one
MSM518222A can be replaced simply by one MSM5412222B.
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FEDS5412222B-02
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MSM5412222B
FEATURES
Single power supply: 5.0 V ±0.5 V
262,214 words 12 bits
Fast FIFO (First-In First-Out) operation
High speed asynchronous serial access
Read/write cycle time 20 ns/25 ns
Access time
18 ns/23 ns
Direct cascading capability
Write mask function (Input enable control)
Data skipping function (Output enable control)
Self refresh (No refresh control is required)
Package options:
44-pin 400 mil plastic TSOP (Type 2)
(TSOP(2)44-P-400-0.80-K) (Product:MSM5412222B-xxT3-K)
xx indicates speed rank.
PRODUCT FAMILY
Family
Access Time (Max.)
Cycle Time (Min.)
MSM5412222B-25
23 ns
25 ns
MSM5412222B-30
25 ns
30 ns
Package
400 mil 44-pin TSOP (2)
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FEDS5412222B-02
LAPIS Semiconductor
MSM5412222B
PIN CONFIGURATION (TOP VIEW)
VSS
DIN11
DIN10
NC
DIN9
DIN8
DIN7
DIN6
NC
DIN5
DIN4
DIN3
DIN2
NC
DIN1
DIN0
SWCK
RSTW
NC
WE
IE
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
VSS
DOUT11
DOUT10
NC
DOUT9
DOUT8
DOUT7
DOUT6
VCC
DOUT5
DOUT4
DOUT3
DOUT2
VSS
DOUT1
DOUT0
SRCK
RSTR
NC
RE
OE
VCC
44-Pin Plastic TSOP (2)
(K Type)
Pin Name
SWCK
SRCK
WE
Function
Serial Write Clock
Serial Read Clock
Write Enable
RE
Read Enable
IE
Input Enable
OE
Output Enable
RSTW
Write Reset Clock
RSTR
Read Reset Clock
DIN0 to 11
DOUT0 to 11
Data Input
Data Output
VCC
Power Supply (5.0 V)
VSS
Ground (0 V)
NC
No Connection
Note: The same power supply voltage must be provided to every VCC pin, and the same GND voltage
level must be provided to every VSS pin.
3/16
IE
RSTR
Write Line Buffer
( 12)
Array
Memory
262,144 12
( 12)
Read Line Buffer
WE
RSTW SWCK
Serial Write Controller
X
Decoder
SRCK
Serial Read Register ( 12)
Serial Read Controller
RE
Serial Write Register ( 12)
OE
VBB
Generator
Clock
Oscillator
Read/Write
and Refresh
Controller
LAPIS Semiconductor
DIN ( 12)
Data-In
Buffer ( 12)
71-Word
Sub-Register ( 12)
71-Word
Sub-Register ( 12)
Data-Out
Buffer ( 12)
DOUT ( 12)
FEDS5412222B-02
MSM5412222B
BLOCK DIAGRAM
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FEDS5412222B-02
LAPIS Semiconductor
MSM5412222B
OPERATION
Write Operation
The write operation is controlled by three clocks, SWCK, RSTW, and WE. Write operation is accomplished by
cycling SWCK, and holding WE high after the write address pointer reset operation or RSTW.
Each write operation, which begins after RSTW, must contain at least 150 active write cycles, i.e. SWCK cycles
while WE is high. To transfer the last data to the DRAM array, which at that time is stored in the serial data
registers attached to the DRAM array, an RSTW operation is required after the last SWCK cycle.
Note that every write timing of MSM5412222B is delayed by one clock compared with read timings for easy
cascading without any interface delay devices.
Write Reset: RSTW
The first positive transition of SWCK after RSTW becomes high resets the write address counters to zero. RSTW
setup and hold times are referenced to the rising edge of SWCK. Because the write reset function is solely
controlled by the SWCK rising edge after the high level of RSTW, the states of WE and IE are ignored in the write
reset cycle.
Before RSTW may be brought high again for a further reset operation, it must be low for at least two SWCK
cycles.
Data Inputs: DIN0 to 11
Write Clock: SWCK
The SWCK latches the input data on chip when WE is high, and also increments the internal write address pointer.
Data-in setup time tDS, and hold time tDH are referenced to the rising edge of SWCK.
Write Enable: WE
WE is used for data write enable/disable control. WE high level enables the input, and WE low level disables the
input and holds the internal write address pointer. There are no WE disable time (low) and WE enable time (high)
restrictions, because the MSM5412222B is in fully static operation as long as the power is on. Note that WE setup
and hold times are referenced to the rising edge of SWCK.
Input Enable: IE
IE is used to enable/disable writing into memory. IE high level enables writing. The internal write address pointer
is always incremented by cycling SWCK regardless of the IE level. Note that IE setup and hold times are
referenced to the rising edge of SWCK.
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MSM5412222B
Read Operation
The read operation is controlled by three clocks, SRCK, RSTR, and RE. Read operation is accomplished by
cycling SRCK, and holding RE high after the read address pointer reset operation or RSTR.
Each read operation, which begins after RSTR, must contain at least 150 active read cycles, i.e. SRCK cycles while
RE is high.
Read Reset: RSTR
The first positive transition of SRCK after RSTR becomes high resets the read address counters to zero. RSTR
setup and hold times are referenced to the rising edge of SRCK. Because the read reset function is solely controlled
by the SRCK rising edge after the high level of RSTR, the states of RE and OE are ignored in the read reset cycle.
Before RSTR may be brought high again for a further reset operation, it must be low for at least *two SRCK
cycles.
Data Out: DOUT0 to 11
Read Clock: SRCK
Data is shifted out of the data registers. It is triggered by the rising edge of SRCK when RE is high during a read
operation. The SRCK input increments the internal read address pointer when RE is high.
The three-state output buffer provides direct TTL compatibility (no pullup resistor required). Data out is the same
polarity as data in. The output becomes valid after the access time interval tAC that begins with the rising edge of
SRCK. *There are no output valid time restriction on MSM5412222B.
Read Enable: RE
The function of RE is to gate of the SRCK clock for incrementing the read pointer. When RE is high before the
rising edge of SRCK, the read pointer is incremented. When RE is low, the read pointer is not incremented. RE
setup times (tRENS and tRDSS) and RE hold times (tRENH and tRDSH) are referenced to the rising edge of the SRCK
clock.
Output Enable: OE
OE is used to enable/disable the outputs. OE high level enables the outputs. The internal read address pointer is
always incremented by cycling SRCK regardless of the OE level. Note that OE setup and hold times are referenced
to the rising edge of SRCK.
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FEDS5412222B-02
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MSM5412222B
Power-up and Initialization
On power-up, the device is designed to begin proper operation after at least 100 s after VCC has stabilized to a
value within the range of recommended operating conditions. After this 100 s stabilization interval, the following
initialization sequence must be performed.
Because the read and write address counters are not valid after power-up, a minimum of 80 dummy write
operations (SWCK cycles) and read operations (SRCK cycles) must be performed, followed by an RSTW
operation and an RSTR operation, to properly initialize the write and the read address pointer. Dummy write
cycles/RSTW and dummy read cycles/RSTR may occur simultaneously.
If these dummy read and write operations start while VCC and/or the substrate voltage has not stabilized, it is
necessary to perform an RSTR operation plus a minimum of 80 SRCK cycles plus another RSTR operation, and an
RSTW operation plus a minimum of 80 SRCK cycles plus another RSTW operation to properly initialize read and
write address pointers.
Old/New Data Access
There must be a minimum delay of 150 SWCK cycles between writing into memory and reading out from memory.
If reading from the first field starts with an RSTR operation, before the start of writing the second field (before the
next RSTW operation), then the data just written will be read out.
The start of reading out the first field of data may be delayed past the beginning of writing in the second field of
data for as many as 20 SWCK cycles. If the RSTR operation for the first field read-out occurs less than 20 SWCK
cycles after the RSTW operation for the second field write-in, then the internal buffering of the device assures that
the first field will still be read out. The first field of data that is read out while the second field of data is written is
called “old data”.
In order to read out “new data”, i.e., the second field written in, the delay between an RSTW operation and an
RSTR operation must be at least 150 SRCK cycles. If the delay between RSTW and RSTR operations is more than
21 but less than 150 cycles, then the data read out will be undetermined. It may be “old data” or “new” data, or a
combination of old and new data. Such a timing should be avoided.
Cascade Operation
The MSM5412222B is designed to allow easy cascading of multiple memory devices. This provides higher
storage depth, or a longer delay than can be achieved with only one memory device.
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MSM5412222B
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Symbol
Conditon
Rating
Unit
Input Output Voltage
VT
at Ta = 25C, VSS
–1.0 to +7.0
V
Output Current
IOS
Ta = 25C
50
mA
Power Dissipation
PD
Ta = 25C
1
W
Operating Temperature
Topr
—
0 to 70
C
Storage Temperature
Tstg
—
–55 to +150
C
Recommended Operating Conditions
Parameter
Symbol
Min.
Typ
Max.
Unit
Power Supply Voltage
VCC
4.5
5.0
5.5
V
Input High Voltage
VIH
2.4
VCC
VCC +1
V
Input Low Voltage
VIL
–0.1
0
+0.8
V
DC Characteristics
Parameter
Symbol
Condition
Min.
Max.
Unit
ILI
0 < VI < VCC + 1 V, Other Pins Tested at V = 0 V
–10
+10
µA
Output Leakage Current
ILO
0 < VO < VCC
–10
+10
µA
Output “H” Level Voltage
VOH
IOH = –1 mA
2.4
—
V
Output “L” Level Voltage
VOL
IOL = 2 mA
—
0.4
V
Operating Current
ICC1
Minimum Cycle Time, Output Open
—
60
mA
Standby Current
ICC2
Input Pin = VIH/VIL
—
5
mA
Input Leakage Current
Capacitance
(Ta = 25°C, f = 1 MHz)
Parameter
Symbol
Max.
Unit
Input Capacitance (DIN, SWCK, SRCK, RSTW, RSTR, WE, RE, IE, OE)
CI
6
pF
Output Capacitance (DOUT)
CO
7
pF
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MSM5412222B
AC Characteristics
(VCC = 5.0 V ±0.5 V, Ta = 0 to 70°C)
Parameter
Symbol
Access Time from SRCK
DOUT Hold Time from SRCK
DOUT Enable Time from SRCK
SWCK “H” Pulse Width
SWCK “L” Pulse Width
Input Data Setup Time
Input Data Hold Time
WE Enable Setup Time
WE Enable Hold Time
WE Disable Setup Time
WE Disable Hold Time
IE Enable Setup Time
IE Enable Hold Time
IE Disable Setup Time
IE Disable Hold Time
WE “H” Pulse Width
WE “L” Pulse Width
IE “H” Pulse Width
IE “L” Pulse Width
RSTW Setup Time
RSTW Hold Time
SRCK “H” Pulse Width
SRCK “L” Pulse Width
RE Enable Setup Time
RE Enable Hold Time
RE Disable SetupTime
RE Disable Hold Time
OE Enable Setup Time
OE Enable Hold Time
OE Disable SetupTime
OE Disable Hold Time
Output Buffer Turn-off Delay Time from OE
RE “H” Pulse Width
RE “L” Pulse Width
OE “H” Pulse Width
OE “L” Pulse Width
RSTR Setup Time
RSTR Hold Time
SWCK Cycle Time
SRCK Cycle Time
Transition Time (Rise and Fall)
MSM5412222B-25
MSM5412222B-30
Unit
Min.
Max.
Min.
Max.
tAC
tDDCK
tDECK
tWSWH
tWSWL
tDS
tDH
tWENS
tWENH
tWDSS
tWDSH
tIENS
tIENH
tIDSS
tIDSH
tWWEH
tWWEL
tWIEH
tWIEL
tRSTWS
tRSTWH
tWSRH
tWSRL
tRENS
tRENH
tRDSS
tRDSH
tOENS
tOENH
tODSS
tODSH
tOEZ
tWREH
tWREL
—
6
6
9
10
2
4
0
3
0
3
0
3
0
3
5
5
5
5
0
3
9
10
0
3
0
3
0
3
0
3
17
5
5
23
—
23
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
6
6
12
12
2
4
0
3
0
3
0
3
0
3
10
10
10
10
0
3
12
12
0
3
0
3
0
3
0
3
17
10
10
25
—
25
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWOEH
tWOEL
tRSTRS
tRSTRH
tSWC
tSRC
tT
5
5
0
3
25
25
3
—
—
—
—
—
—
30
10
10
0
3
30
30
3
—
—
—
—
—
—
30
ns
ns
ns
ns
ns
ns
ns
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FEDS5412222B-02
LAPIS Semiconductor
MSM5412222B
Notes: 1. Input signal reference levels for the parameter measurement are VIH = 3.0 V and VIL = 0 V. The
transition time tT is defined to be a transition time that signal transfers between VIH = 3.0 V and
VIL = 0 V.
2. AC measurements assume tT = 3 ns.
3. Read address must have more than a 150 address delay than write address in every cycle
when asynchronous read/write is performed.
4. Read must have more than a 150 address delay than write in order to read the data written in
a current series of write cycles which has been started at last write reset cycle: this is called
“new data read”.
When read has less than a 20 address delay than write, the read data are the data written in a
previous series of write cycles which had been written before at last write reset cycle: this is
called “old data read”.
5. When the read address delay is between more than 21 and less than 149, read data will be
undetermined. However, normal write is achieved in this address condition.
6. Outputs are measured with a load equivalent to 1 TTL load and 30 pF.
Output reference levels are VOH = 2.0 V and VOL = 0.8 V.
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MSM5412222B
TIMING WAVEFORM
Write Cycle Timing (Write Reset)
n cycle
0 cycle
2 cycle
1 cycle
–VIH
–VIL
SWCK
tT
tWSWH
tRSTWH
tRSTWS
tWSWL
tSWC
–VIH
–VIL
RSTW
tDH
tDS
DIN
n–1
n
0
1
–VIH
–VIL
2
WE
–VIH
–VIL
IE
–VIH
–VIL
Write Cycle Timing (Write Enable)
n cycle
Disable cycle
Disable cycle
n + 1 cycle
–VIH
–VIL
SWCK
tWDSH
tWENH
tWDSS
tWENS
–VIH
–VIL
WE
tWWEL
DIN
IE
RSTW
n–1
tWWEH
n
n+1
–VIH
–VIL
–VIH
–VIL
–VIH
–VIL
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FEDS5412222B-02
LAPIS Semiconductor
MSM5412222B
Write Cycle Timing (Input Enable)
n cycle
n + 1 cycle
n + 2 cycle
n + 3 cycle
–VIH
–VIL
SWCK
tIENH
tIENS
tIDSS
tIDSH
–VIH
–VIL
IE
tWIEL
DIN
tWIEH
n
n–1
n+3
–VIH
–VIL
WE
–VIH
–VIL
RSTW
–VIH
–VIL
Read Cycle Timing (Read Reset)
n cycle
0 cycle
2 cycle
1 cycle
–VIH
–VIL
SRCK
tT
tWSRH
tRSTRH
tRSTRS
tWSRL
tSRC
–VIH
–VIL
RSTR
tAC
DOUT
n–1
tDDCK
n
0
1
2
–VOH
–VOL
RE
–VIH
–VIL
OE
–VIH
–VIL
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FEDS5412222B-02
LAPIS Semiconductor
MSM5412222B
Read Cycle Timing (Read Enable)
n cycle
Disable cycle
Disable cycle
n + 1 cycle
–VIH
–VIL
SRCK
tRDSH
tRENH
tRDSS
tRENS
–VIH
–VIL
RE
tWREL
DOUT
tWREH
n–1
n+1
n
–VOH
–VOL
OE
–VIH
–VIL
RSTR
–VIH
–VIL
Read Cycle Timing (Output Enable)
n cycle
n + 1 cycle
n + 2 cycle
n + 3 cycle
–VIH
–VIL
SRCK
tODSH
tOENH
tODSS
tOENS
–VIH
–VIL
OE
tWOEH
tWOEL
DOUT
n–1
n
tDECK
Hi-Z
n+3
–VOH
–VOL
tOEZ
RE
RSTR
–VIH
–VIL
–VIH
–VIL
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FEDS5412222B-02
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MSM5412222B
NOTES FOR MOUNTING THE SURFACE MOUNT TYPE PACKAGES
The surface mount type packages are very susceptible to heat in reflow mounting and humidity
absorbed in storage.
Therefore, before you perform reflow mounting, contact LAPIS Semiconductor’s responsible sales
person for the product name, package name, pin number, package code and desired mounting
conditions (reflow method, temperature and times).
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FEDS5412222B-02
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MSM5412222B
REVISION HISTORY
Document
No.
Date
Page
Previous
Current
Edition
Edition
PEDS5412222B-01
Aug 16, 2002
–
–
PEDS5412222B-02
Jan. 13, 2012
1
2,3,
14,15
1
2,3,
14
FPEDS5412222B-02
Nov. 01, 2012
–
–
Description
First edition
Changed Company name and logo
Deleted the 40-pin SOJ package
information and PACKAGE DIMENSION
Released formal edition 02
15/16
FEDS5412222B-02
LAPIS Semiconductor
MSM5412222B
NOTICE
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