74ABT125DB,118

74ABT125 Quad buffer; 3-state Rev. 7 — 25 November 2015 Product data sheet 1. General description The 74ABT125 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The 74ABT125 device is a quad buffer that is ideal for driving bus lines. The device features four output enable inputs (1OE, 2OE, 3OE, 4OE), each controlling one of the 3-state outputs. 2. Features and benefits         Quad bus interface 3-state buffers Live insertion and extraction permitted Output capability: HIGH 32 mA; LOW +64 mA Power-up 3-state Inputs are disabled during 3-state mode Latch-up protection exceeds 500 mA per JESD78 class II level A ESD protection:  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115-A exceeds 200 V  Multiple package options  Specified from 40 C to +85 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74ABT125D 40 C to +85 C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 74ABT125DB 40 C to +85 C SSOP14 plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 74ABT125PW 40 C to +85 C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 74ABT125BQ 40 C to +85 C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5  3  0.85 mm SOT762-1 74ABT125 Nexperia Quad buffer; 3-state 4. Functional diagram  $ <  2(  $  2(   <     (1     $ <    2(  $    <  Q< Q$   2(  Q2( PQD Fig 1. PQD Logic symbol Fig 2. PQD IEC logic symbol Fig 3. Logic diagram (one buffer) 5. Pinning information 5.1 Pinning  WHUPLQDO LQGH[DUHD $%7  9&& 2( $%7 $   2( 2(   9&& <   $ $   2( 2(   < <   $    < $ 2( $   2( <  <   $ *1'   < *1'  2(   *1' <  $ DDL 7UDQVSDUHQWWRSYLHZ DDL (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to GND. Fig 4. Pin configuration SO14 and (T)SSOP14 74ABT125 Product data sheet Fig 5. Pin configuration DHVQFN14 All information provided in this document is subject to legal disclaimers. Rev. 7 — 25 November 2015 © Nexperia B.V. 2017. All rights reserved 2 of 15 74ABT125 Nexperia Quad buffer; 3-state 5.2 Pin description Table 2. Pin description Symbol Pin Description 1OE to 4OE 1, 4, 10, 13 output enable input (active LOW) 1A to 4A 2, 5, 9, 12 data input 1Y to 4Y 3, 6, 8, 11 data output GND 7 ground (0 V) VCC 14 supply voltage 6. Functional description Table 3. Function selection[1] Inputs Output nOE nA L L L L H H H X Z [1] nY H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. 7. Limiting values Table 4. Limiting values[1] In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VCC supply voltage 0.5 +7.0 V VI input voltage 1.2 +7.0 V VO output voltage output in OFF-state or HIGH-state 0.5 +5.5 V IIK input clamping current VI < 0 V 18 - IOK output clamping current VO < 0 V 50 - mA IO output current output in LOW-state - 128 mA Tj junction temperature - 150 C Tstg storage temperature 65 +150 C - 500 mW total power dissipation Ptot [2] Tamb = 40 C to +85 C [3] mA [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. [3] SO14 packages: above 70 C Ptot derate linearly with 8 mW/K SSOP14 and TSSOP14 packages: above 60 C Ptot derate linearly with 5.5 mW/K DHVQFN14 packages: above 60 C Ptot derate linearly with 4.5 mW/K 74ABT125 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 25 November 2015 © Nexperia B.V. 2017. All rights reserved 3 of 15 74ABT125 Nexperia Quad buffer; 3-state 8. Recommended operating conditions Table 5. Operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions VCC supply voltage VI input voltage VIH HIGH-level input voltage VIL LOW-level Input voltage IOH HIGH-level output current Min Max Unit 4.5 5.5 V 0 VCC V 2.0 - V - 0.8 V 32 - mA IOL LOW-level output current - 64 mA t/V input transition rise and fall rate - 10 ns/V Tamb ambient temperature 40 +85 C in free air 9. Static characteristics Table 6. Static characteristics Symbol Parameter 25 C Conditions 40 C to +85 C Unit Min Typ Max Min Max - 0.9 1.2 - 1.2 V VCC = 4.5 V; IOH = 3 mA 2.5 2.9 - 2.5 - V VCC = 5.0 V; IOH = 3 mA 3.0 3.4 - 3.0 - V VCC = 4.5 V; IOH = 32 mA VIK input clamping voltage VCC = 4.5 V; IIK = 18 mA VOH HIGH-level output voltage VI = VIL or VIH 2.0 2.4 - 2.0 - V VOL LOW-level output voltage VCC = 4.5 V; IOL = 64 mA; VI = VIL or VIH - 0.35 0.55 - 0.55 V II input leakage current VCC = 5.5 V; VI = GND or 5.5 V - 0.01 1.0 - 1.0 A IOFF power-off leakage current VCC = 0.0 V; VI or VO  4.5 V - 5.0 100 - 100 A IO(pu/pd) power-up/power-down VCC = 2.1 V; VO = 0.5 V; output current VI = GND or VCC; OE = don’t care - 5.0 50 - 50 A IOZ OFF-state output current VO = 2.7 V - 1.0 50 - 50 A VO = 0.5 V - 1.0 50 - 50 A - 5.0 50 - 50 A 50 100 180 50 180 mA - 65 250 - 250 A [1] VCC = 5.5 V; VI = VIL or VIH ICEX output high leakage current HIGH-state; VO = 5.5 V; VCC = 5.5 V; VI = GND or VCC IO output current VCC = 5.5 V; VO = 2.5 V ICC supply current VCC = 5.5 V; VI = GND or VCC [2] outputs HIGH-state 74ABT125 Product data sheet outputs LOW-state - 12 15 - 30 mA outputs disabled - 65 250 - 50 A All information provided in this document is subject to legal disclaimers. Rev. 7 — 25 November 2015 © Nexperia B.V. 2017. All rights reserved 4 of 15 74ABT125 Nexperia Quad buffer; 3-state Table 6. Static characteristics …continued Symbol Parameter ICC additional supply current 25 C Conditions 40 C to +85 C Unit Min Typ Max Min Max outputs enabled - 0.5 1.5 - 1.5 mA outputs disabled - 50 250 - 250 mA one enable input at 3.4 V and other inputs at VCC or GND; outputs disabled - 0.5 1.5 - 1.5 mA per control pin; VCC = 5.5 V; one control input at 3.4 V, other inputs at VCC or GND [3] CI input capacitance VI = 0 V or VCC - 4 - - - pF CO output capacitance outputs disabled; VO = 0 V or VCC - 7 - - - pF [1] This parameter is valid for any VCC between 0 V and 2.1 V, with a transition time of up to 10 ms. From VCC = 2.1 V to VCC = 5 V  10 %, a transition time of up to 100 s is permitted. [2] Not more than one output should be tested at a time, and the duration of the test should not exceed one second. [3] This is the increase in supply current for each input at 3.4 V. 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V. Test circuit is shown in Figure 8. Symbol Parameter 25 C; VCC = 5.0 V Conditions 40 C to +85 C; Unit VCC = 5.0 V  0.5 V Min Typ Max Min Max tPLH LOW to HIGH propagation delay nA to nY, see Figure 6 1.0 2.8 4.1 1.0 4.6 ns tPHL HIGH to LOW propagation delay nA to nY; see Figure 6 1.0 3.1 4.6 1.0 4.9 ns tPZH OFF-state to HIGH propagation delay nOE to nY; see Figure 7 1.0 3.2 5.0 1.0 5.9 ns tPZL OFF-state to LOW propagation delay nOE to nY; see Figure 7 1.0 4.2 6.2 1.0 6.8 ns tPHZ HIGH to OFF-state propagation delay nOE to nY; see Figure 7 1.0 4.1 5.4 1.0 6.2 ns tPLZ LOW to OFF-state propagation delay nOE to nY; see Figure 7 1.5 2.8 5.0 1.5 5.5 ns 74ABT125 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 25 November 2015 © Nexperia B.V. 2017. All rights reserved 5 of 15 74ABT125 Nexperia Quad buffer; 3-state 11. Waveforms 9, 90 Q$LQSXW *1' W3+/ W3/+ 92+ 90 Q