74AHC02BQ,115

74AHC02; 74AHCT02 Quad 2-input NOR gate Rev. 5 — 11 May 2020 Product data sheet 1. General description The 74AHC02; 74AHCT02 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC02; 74AHCT02 provides a quad 2-input NOR function. 2. Features and benefits • • • • • • • Balanced propagation delays All inputs have a Schmitt-trigger action Inputs accept voltages higher than VCC Input levels: • For 74AHC02: CMOS level • For 74AHCT02: TTL level ESD protection: • HBM EIA/JESD22-A114E exceeds 2000 V • MM EIA/JESD22-A115-A exceeds 200 V • CDM EIA/JESD22-C101C exceeds 1000 V Multiple package options Specified from -40 °C to +85 °C and from -40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package 74AHC02D Temperature range Name Description Version -40 °C to +125 °C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 -40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 -40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 × 3 × 0.85 mm SOT762-1 74AHCT02D 74AHC02PW 74AHCT02PW 74AHC02BQ 74AHCT02BQ 74AHC02; 74AHCT02 Nexperia Quad 2-input NOR gate 4. Functional diagram 2 1A 3 1B 5 2A 6 2B 8 3A 9 3B 11 4A 12 4B 2 1Y 1 2Y 4 3Y 10 4Y 3 5 6 8 9 11 13 12 1 ≥1 4 ≥1 10 ≥1 13 A Y B 001aah084 mna216 Fig. 1. ≥1 Logic symbol Fig. 2. IEC logic symbol Fig. 3. mna215 Logic diagram (one gate) 5. Pinning information 1 1Y terminal 1 index area 2 1B 3 2Y 4 2A 5 10 3Y 2B 6 9 3B GND 7 8 3A 12 4B 02 11 4A 2A 5 2B 6 13 4Y 12 4B 02 GND(1) 11 4A 10 3Y 9 3B 001aac920 Transparent top view (1) This is not a ground pin. There is no electrical or mechanical requirement to solder the pad. In case soldered, the solder land should remain floating or connected to GND. 001aac919 Fig. 4. 4 8 1A 3 2Y 3A 14 VCC 13 4Y 1B 7 1 2 GND 1Y 1A 14 VCC 5.1. Pinning Pin configuration SOT108-1 (SO14) and SOT402-1 (TSSOP14) Fig. 5. Pin configuration SOT762-1 (DHVQFN14) 5.2. Pin description Table 2. Pin description Symbol Pin Description 1Y, 2Y, 3Y, 4Y 1, 4, 10, 13 data output 1A, 2A, 3A, 4A 2, 5, 8, 11 data input 1B, 2B, 3B, 4B 3, 6, 9, 12 data input GND 7 ground (0 V) VCC 14 supply voltage 74AHC_AHCT02 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 11 May 2020 © Nexperia B.V. 2020. All rights reserved 2 / 12 74AHC02; 74AHCT02 Nexperia Quad 2-input NOR gate 6. Functional description Table 3. Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care. Output Input nA nB nY L L H X H L H X L 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC supply voltage -0.5 +7.0 V VI input voltage -0.5 +7.0 V IIK input clamping current VI < -0.5 V [1] -20 - mA IOK output clamping current VO < -0.5 V or VO > VCC + 0.5 V [1] -20 +20 mA IO output current VO = -0.5 V to (VCC + 0.5 V) -25 +25 mA ICC supply current - +75 mA IGND ground current -75 - mA Tstg storage temperature -65 +150 °C Ptot total power dissipation - 500 mW [1] [2] Tamb = -40 °C to +125 °C [2] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For SOT108-1 (SO14) package: Ptot derates linearly with 10.1 mW/K above 100 °C. For SOT402-1 (TSSOP14) package: Ptot derates linearly with 7.3 mW/K above 81 °C. For SOT762-1 (DHVQFN14) package: Ptot derates linearly with 9.6 mW/K above 98 °C. 8. Recommended operating conditions Table 5. Operating conditions Symbol Parameter Conditions 74AHC02 Unit 74AHCT02 Min Typ Max Min Typ Max VCC supply voltage 2.0 5.0 5.5 4.5 5.0 5.5 V VI input voltage 0 - 5.5 0 - 5.5 V VO output voltage 0 - VCC 0 - VCC V Tamb ambient temperature -40 +25 +125 -40 +25 Δt/ΔV input transition rise and fall rate VCC = 3.0 V to 3.6 V - - 100 - - - ns/V VCC = 4.5 V to 5.5 V - - 20 - - 20 ns/V 74AHC_AHCT02 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 11 May 2020 © +125 °C Nexperia B.V. 2020. All rights reserved 3 / 12 74AHC02; 74AHCT02 Nexperia Quad 2-input NOR gate 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max VCC = 2.0 V 1.5 - - 1.5 - 1.5 - V VCC = 3.0 V 2.1 - - 2.1 - 2.1 - V VCC = 5.5 V 3.85 - - 3.85 - 3.85 - V VCC = 2.0 V - - 0.5 - 0.5 - 0.5 V VCC = 3.0 V - - 0.9 - 0.9 - 0.9 V VCC = 5.5 V - - 1.65 - 1.65 - 1.65 V IO = -50 μA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = -50 μA; VCC = 3.0 V 2.9 3.0 - 2.9 - 2.9 - V IO = -50 μA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = -4.0 mA; VCC = 3.0 V 2.58 - - 2.48 - 2.40 - V IO = -8.0 mA; VCC = 4.5 V 3.94 - - 3.80 - 3.70 - V IO = 50 μA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 50 μA; VCC = 3.0 V - 0 0.1 - 0.1 - 0.1 V IO = 50 μA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 3.0 V - - 0.36 - 0.44 - 0.55 V IO = 8.0 mA; VCC = 4.5 V - - 0.36 - 0.44 - 0.55 V 74AHC02 VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VI = VIH or VIL VI = VIH or VIL II input leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V - - 0.1 - 1.0 - 2.0 μA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 2.0 - 20 - 40 μA CI input capacitance - 3 10 - 10 - 10 pF 74AHCT02 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 - - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - - 0.8 - 0.8 - 0.8 V VOH HIGH-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = -50 μA 4.4 4.5 - 4.4 - 4.4 - V IO = -8.0 mA 3.94 - - 3.80 - 3.70 - V LOW-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = 50 μA - 0 0.1 - 0.1 - 0.1 V IO = 8.0 mA - - 0.36 - 0.44 - 0.55 V VOL 74AHC_AHCT02 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 11 May 2020 © Nexperia B.V. 2020. All rights reserved 4 / 12 74AHC02; 74AHCT02 Nexperia Quad 2-input NOR gate Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Min Typ Max Min Max Min Max Unit II input leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V - - 0.1 - 1.0 - 2.0 μA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 2.0 - 20 - 40 μA ΔICC additional supply current per input pin; VI = VCC - 2.1 V; other pins at VCC or GND; IO = 0 A; VCC = 4.5 V to 5.5 V - - 1.35 - 1.5 - 1.5 mA CI input capacitance - 3 10 - 10 - 10 pF 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 7. Symbol Parameter Conditions 25 °C Min -40 °C to +85 °C Typ[1] Max -40 °C to +125 °C Min Max Min Max Unit 74AHC02 propagation nA, nB to nY; see Fig. 6 delay VCC = 3.0 V to 3.6 V; CL = 15 pF tpd CPD [2] - 3.9 7.9 1.0 9.5 1.0 10.0 ns VCC = 3.0 V to 3.6 V; CL = 50 pF - 5.5 11.4 1.0 13 1.0 14.5 ns VCC = 4.5 V to 5.5 V; CL = 15 pF - 2.9 5.5 1.0 6.5 1.0 7.0 ns VCC = 4.5 V to 5.5 V; CL = 50 pF - 4.2 7.5 1.0 8.5 1.0 9.5 ns - 7.0 - - - - - pF - 3.8 5.5 1.0 6.5 1.0 7.0 ns - 5.1 7.5 1.0 8.5 1.0 9.5 ns - 8.0 - - - - - pF power CL = 50 pF; fi = 1 MHz; dissipation VI = GND to VCC capacitance [3] 74AHCT02 propagation nA, nB to nY; see Fig. 6 delay VCC = 4.5 V to 5.5 V; CL = 15 pF tpd [2] VCC = 4.5 V to 5.5 V; CL = 50 pF CPD [1] [2] [3] power CL = 50 pF; fi = 1 MHz; dissipation VI = GND to VCC capacitance [3] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V). tpd is the same as tPLH and tPHL. CPD is used to determine the dynamic power dissipation (PD in μW). 2 2 PD = CPD × VCC × fi × N + Σ(CL × VCC × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; 2 Σ(CL × VCC × fo) = sum of the outputs. 74AHC_AHCT02 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 11 May 2020 © Nexperia B.V. 2020. All rights reserved 5 / 12 74AHC02; 74AHCT02 Nexperia Quad 2-input NOR gate 10.1. Waveforms VI VM nA, nB input GND tPLH tPHL VOH VM nY output VOL 001aah085 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 6. Input to output propagation delays Table 8. Measurement points Type Input Output VM VM 74AHC02 0.5 × VCC 0.5 × VCC 74AHCT02 1.5 V 0.5 × VCC VI negative pulse VM VI GND VM 10 % GND positive pulse tW 90 % tf tr tr tf 90 % VM VM 10 % tW VCC G VI DUT VO RT CL 001aah768 Test data is given in Table 9. Definitions test circuit: RT = termination resistance should be equal to output impedance Zo of the pulse generator. CL = load capacitance including jig and probe capacitance. Fig. 7. Test circuit for measuring switching times Table 9. Test data Type Load Input Test VI tr, tf CL 74AHC02 VCC ≤ 3.0 ns 15 pF, 50 pF tPLH, tPHL 74AHCT02 3.0 V ≤ 3.0 ns 15 pF, 50 pF tPLH, tPHL 74AHC_AHCT02 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 11 May 2020 © Nexperia B.V. 2020. All rights reserved 6 / 12 74AHC02; 74AHCT02 Nexperia Quad 2-input NOR gate 11. Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 inches 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.05 0.01 0.01 0.004 0.028 0.012 0.244 0.039 0.028 0.041 0.228 0.016 0.024 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06 MS-012 Fig. 8. JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Package outline SOT108-1 (SO14) 74AHC_AHCT02 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 11 May 2020 © Nexperia B.V. 2020. All rights reserved 7 / 12 74AHC02; 74AHCT02 Nexperia Quad 2-input NOR gate TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm D SOT402-1 E A X c y HE v M A Z 8 14 Q A2 pin 1 index (A 3 ) A1 A θ Lp 1 L 7 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 Fig. 9. REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Package outline SOT402-1 (TSSOP14) 74AHC_AHCT02 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 11 May 2020 © Nexperia B.V. 2020. All rights reserved 8 / 12 74AHC02; 74AHCT02 Nexperia Quad 2-input NOR gate DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 x 3 x 0.85 mm B D SOT762-1 A A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e v w b 2 6 C A B C y y1 C L 1 7 14 8 Eh e k 13 9 Dh X k 0 2 Dimensions (mm are the original dimensions) Unit max nom min mm A(1) 1 A1 b 0.05 0.30 0.02 0.25 0.00 0.18 4 mm scale c D(1) Dh E(1) Eh e e1 0.2 3.1 3.0 2.9 1.65 1.50 1.35 2.6 2.5 2.4 1.15 1.00 0.85 0.5 2 k L v 0.2 0.5 0.4 0.3 0.1 w y 0.05 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. Outline version SOT762-1 References IEC JEDEC JEITA sot762-1_po European projection Issue date 15-04-10 15-05-05 MO-241 Fig. 10. Package outline SOT762-1 (DHVQFN14) 74AHC_AHCT02 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 11 May 2020 © Nexperia B.V. 2020. All rights reserved 9 / 12 74AHC02; 74AHCT02 Nexperia Quad 2-input NOR gate 12. Abbreviations Table 10. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model LSTTL Low-power Schottky Transistor-Transistor Logic MM Machine Model TTL Transistor-Transistor Logic 13. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74AHC_AHCT02_5 20200511 Product data sheet - Modifications: • • • • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Table 4: Derating values for Ptot total power dissipation updated. Package outline drawing SOT762-1 (DHVQFN14) updated. 74AHC_AHCT02_4 20080521 Modifications: • • • 74AHC_AHCT02_4 Product data sheet - 74AHC_AHCT02_3 The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Table 6: the conditions for input leakage current have been changed. 74AHC_AHCT02_3 20080107 Product data sheet - 74AHC_AHCT02_2 74AHC_AHCT02_2 19990923 Product specification - 74AHC_AHCT02_1 74AHC_AHCT02_1 19981218 Product specification - - 74AHC_AHCT02 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 11 May 2020 © Nexperia B.V. 2020. All rights reserved 10 / 12 74AHC02; 74AHCT02 Nexperia Quad 2-input NOR gate 14. Legal information injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Data sheet status Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". 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In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 5 — 11 May 2020 © Nexperia B.V. 2020. All rights reserved 11 / 12 74AHC02; 74AHCT02 Nexperia Quad 2-input NOR gate Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................1 4. Functional diagram.......................................................2 5. Pinning information......................................................2 5.1. Pinning.........................................................................2 5.2. Pin description............................................................. 2 6. Functional description................................................. 3 7. Limiting values............................................................. 3 8. Recommended operating conditions..........................3 9. Static characteristics....................................................4 10. Dynamic characteristics............................................ 5 10.1. Waveforms.................................................................6 11. Package outline.......................................................... 7 12. Abbreviations............................................................ 10 13. Revision history........................................................10 14. Legal information......................................................11 © Nexperia B.V. 2020. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 11 May 2020 74AHC_AHCT02 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 11 May 2020 © Nexperia B.V. 2020. All rights reserved 12 / 12