74AHC00-Q100; 74AHCT00-Q100
Quad 2-input NAND gate
Rev. 2 — 26 May 2020
Product data sheet
1. General description
The 74AHC00-Q100; 74AHCT00-Q100 are quad 2-input NAND gates. Inputs are overvoltage
tolerant. This feature allows the use of these devices as translators in mixed voltage environments.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100
(Grade 1) and is suitable for use in automotive applications.
2. Features
•
•
•
•
•
•
•
•
•
•
•
•
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
• Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Wide supply voltage range from 2.0 V to 5.5 V
Input levels:
• For 74AHC00-Q100: CMOS level
• For 74AHCT00-Q100: TTL level
Balanced propagation delays
All inputs have Schmitt-trigger actions
Overvoltage tolerant inputs to 5.5 V
High noise immunity
CMOS low power dissipation
ESD protection:
• MIL-STD-883, method 3015 exceeds 2000 V
• HBM EIA/JESD22-A114F exceeds 2000 V
• MM EIA/JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)
Latch-up performance exceeds 100 mA per JESD 78 Class II Level A
Multiple package options
DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of
solder joints
3. Ordering information
Table 1. Ordering information
Type number
Package
74AHC00D-Q100
Temperature range Name
Description
Version
-40 °C to +125 °C
SO14
plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
-40 °C to +125 °C
TSSOP14
plastic thin shrink small outline package; 14 leads; SOT402-1
body width 4.4 mm
-40 °C to +125 °C
DHVQFN14 plastic dual in-line compatible thermal
enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 × 3 × 0.85 mm
74AHCT00D-Q100
74AHC00PW-Q100
74AHCT00PW-Q100
74AHC00BQ-Q100
74AHCT00BQ-Q100
SOT762-1
74AHC00-Q100; 74AHCT00-Q100
Nexperia
Quad 2-input NAND gate
4. Functional diagram
1
1 1A
2 1B
1Y 3
4 2A
5 2B
2Y 6
9 3A
10 3B
3Y 8
12 4A
13 4B
2
4
5
9
10
12
4Y 11
13
mna212
Fig. 1.
&
3
&
6
&
8
&
11
A
Y
B
mna246
Logic symbol
Fig. 2.
IEC logic symbol
Fig. 3.
mna211
Logic diagram (one gate)
5. Pinning information
1
1A
terminal 1
index area
1Y
3
12 4A
2A
4
2B
5
2Y
6
9
3A
GND
7
8
3Y
00
11 4Y
10 3B
13 4B
4
00
11 4Y
2B
5
GND (1)
10 3B
2Y
6
12 4A
9
3A
001aac939
Transparent top view
(1) This is not a ground pin. There is no electrical or
mechanical requirement to solder the pad. In case
soldered, the solder land should remain floating or
connected to GND
001aac938
Fig. 4.
3
2A
8
2
1Y
3Y
1B
14 VCC
13 4B
2
7
1
1B
GND
1A
14 VCC
5.1. Pinning
Pin configuration SOT108-1 (SO14) and
SOT402-1 (TSSOP14)
Fig. 5.
Pin configuration SOT762-1 (DHVQFN14)
5.2. Pin description
Table 2. Pin description
Symbol
Pin
Description
1A, 2A, 3A, 4A
1, 4, 9, 12
data inputs
1B, 2B, 3B, 4B
2, 5, 10, 13
data inputs
1Y, 2Y, 3Y, 4Y
3, 6, 8, 11
data outputs
GND
7
ground (0 V)
VCC
14
supply voltage
74AHC_AHCT00_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 26 May 2020
©
Nexperia B.V. 2020. All rights reserved
2 / 12
74AHC00-Q100; 74AHCT00-Q100
Nexperia
Quad 2-input NAND gate
6. Functional description
Table 3. Function selection
H = HIGH voltage level; L = LOW voltage level; X = don’t care.
Output
Input
nA
nB
nY
L
X
H
X
L
H
H
H
L
7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Min
Max
Unit
VCC
VI
supply voltage
-0.5
+7.0
V
input voltage
-0.5
+7.0
V
IIK
input clamping current
VI < -0.5 V
[1]
-20
-
mA
IOK
output clamping current
VO < -0.5 V or VO > VCC + 0.5 V
[1]
-20
+20
mA
IO
output current
VO = -0.5 V to (VCC + 0.5 V)
-25
+25
mA
ICC
IGND
supply current
-
+75
mA
ground current
-75
-
mA
Tstg
storage temperature
-65
+150
°C
Ptot
total power dissipation
-
500
mW
[1]
[2]
Conditions
Tamb = -40 °C to +125 °C
[2]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For SOT108-1 (SO14) package: Ptot derates linearly with 10.1 mW/K above 100 °C.
For SOT402-1 (TSSOP14) package: Ptot derates linearly with 7.3 mW/K above 81 °C.
For SOT762-1 (DHVQFN14) package: Ptot derates linearly with 9.6 mW/K above 98 °C.
8. Recommended operating conditions
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
74AHC00-Q100
74AHCT00-Q100
Min
Typ
Max
Min
Typ
Max
Unit
VCC
supply voltage
2.0
5.0
5.5
4.5
5.0
5.5
V
VI
input voltage
0
-
5.5
0
-
5.5
V
VO
output voltage
0
-
VCC
0
-
VCC
V
Tamb
ambient temperature
-40
+25
+125
-40
+25
+125
°C
Δt/ΔV
input transition rise and VCC = 3.3 V ± 0.3 V
fall rate
VCC = 5.0 V ± 0.5 V
-
-
100
-
-
-
ns/V
-
-
20
-
-
20
ns/V
74AHC_AHCT00_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 26 May 2020
©
Nexperia B.V. 2020. All rights reserved
3 / 12
74AHC00-Q100; 74AHCT00-Q100
Nexperia
Quad 2-input NAND gate
9. Static characteristics
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 °C
-40 °C to +85 °C -40 °C to +125 °C Unit
Min
Typ
Max
Min
Max
Min
Max
VCC = 2.0 V
1.5
-
-
1.5
-
1.5
-
V
VCC = 3.0 V
2.1
-
-
2.1
-
2.1
-
V
VCC = 5.5 V
3.85
-
-
3.85
-
3.85
-
V
VCC = 2.0 V
-
-
0.5
-
0.5
-
0.5
V
VCC = 3.0 V
-
-
0.9
-
0.9
-
0.9
V
74AHC00-Q100
VIH
VIL
VOH
VOL
HIGH-level
input voltage
LOW-level
input voltage
VCC = 5.5 V
-
-
1.65
-
1.65
-
1.65
V
VI = VIH or VIL
HIGH-level
output voltage
IO = -50 μA; VCC = 2.0 V
1.9
2.0
-
1.9
-
1.9
-
V
IO = -50 μA; VCC = 3.0 V
2.9
3.0
-
2.9
-
2.9
-
V
IO = -50 μA; VCC = 4.5 V
4.4
4.5
-
4.4
-
4.4
-
V
IO = -4.0 mA; VCC = 3.0 V
2.58
-
-
2.48
-
2.40
-
V
IO = -8.0 mA; VCC = 4.5 V
3.94
-
-
3.80
-
3.70
-
V
VI = VIH or VIL
LOW-level
output voltage
IO = 50 μA; VCC = 2.0 V
-
0
0.1
-
0.1
-
0.1
V
IO = 50 μA; VCC = 3.0 V
-
0
0.1
-
0.1
-
0.1
V
IO = 50 μA; VCC = 4.5 V
-
0
0.1
-
0.1
-
0.1
V
IO = 4.0 mA; VCC = 3.0 V
-
-
0.36
-
0.44
-
0.55
V
IO = 8.0 mA; VCC = 4.5 V
-
-
0.36
-
0.44
-
0.55
V
-
-
0.1
-
1.0
-
2.0
μA
II
input leakage
current
VI = 5.5 V or GND;
VCC = 0 V to 5.5 V
ICC
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
2.0
-
20
-
40
μA
CI
input
capacitance
-
3.0
10
-
10
-
10
pF
VI = VCC or GND
74AHCT00-Q100
VIH
HIGH-level
input voltage
VCC = 4.5 V to 5.5 V
2.0
-
-
2.0
-
2.0
-
V
VIL
LOW-level
input voltage
VCC = 4.5 V to 5.5 V
-
-
0.8
-
0.8
-
0.8
V
VOH
VI = VIH or VIL; VCC = 4.5 V
HIGH-level
output voltage
IO = -50 μA
4.4
4.5
-
4.4
-
4.4
-
V
3.94
-
-
3.80
-
3.70
-
V
IO = -8.0 mA
VOL
VI = VIH or VIL; VCC = 4.5 V
LOW-level
output voltage
IO = 50 μA
-
0
0.1
-
0.1
-
0.1
V
IO = 8.0 mA
-
-
0.36
-
0.44
-
0.55
V
VI = 5.5 V or GND;
VCC = 0 V to 5.5 V
-
-
0.1
-
1.0
-
2.0
μA
-
-
2.0
-
20
-
40
μA
II
input leakage
current
ICC
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
74AHC_AHCT00_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 26 May 2020
©
Nexperia B.V. 2020. All rights reserved
4 / 12
74AHC00-Q100; 74AHCT00-Q100
Nexperia
Quad 2-input NAND gate
Symbol Parameter
Conditions
25 °C
-40 °C to +85 °C -40 °C to +125 °C Unit
Min
Typ
Max
Min
Max
Min
Max
ΔICC
additional
per input pin;
supply current VI = VCC - 2.1 V; IO = 0 A;
other pins at VCC or GND;
VCC = 4.5 V to 5.5 V
-
-
1.35
-
1.5
-
1.5
mA
CI
input
capacitance
-
3.0
10
-
10
-
10
pF
VI = VCC or GND
10. Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 7.
Symbol Parameter
Conditions
25 °C
-40 °C to +85 °C -40 °C to +125 °C Unit
Min Typ[1] Max
Min
Max
Min
Max
74AHC00-Q100
tpd
propagation
delay
nA, nB to nY; see Fig. 6
[2]
VCC = 3.0 V to 3.6 V
CL = 15 pF
-
4.5
7.9
1.0
9.5
1.0
10.0
ns
CL = 50 pF
-
6.0
11.4
1.0
13.0
1.0
14.5
ns
CL = 15 pF
-
3.2
5.5
1.0
6.5
1.0
7.0
ns
CL = 50 pF
-
4.5
7.5
1.0
8.5
1.0
9.5
ns
-
7.0
-
-
-
-
-
pF
CL = 15 pF
-
3.3
6.9
1.0
8.0
1.0
9.0
ns
CL = 50 pF
-
4.5
7.9
1.0
9.0
1.0
10.0
ns
-
7.0
-
-
-
-
-
pF
VCC = 4.5 V to 5.5 V
CPD
power
dissipation
capacitance
CL = 50 pF; fi = 1 MHz;
VI = GND to VCC
[3]
nA, nB to nY; see Fig. 6
[2]
74AHCT00-Q100
tpd
CPD
[1]
[2]
[3]
propagation
delay
power
dissipation
capacitance
VCC = 4.5 V to 5.5 V
CL = 50 pF; fi = 1 MHz;
VI = GND to VCC
[3]
Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V).
tpd is the same as tPLH and tPHL.
CPD is used to determine the dynamic power dissipation (PD in μW).
2
2
PD = CPD x VCC x fi x N + Σ(CL x VCC x fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
2
Σ(CL x VCC x fo) = sum of the outputs.
74AHC_AHCT00_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 26 May 2020
©
Nexperia B.V. 2020. All rights reserved
5 / 12
74AHC00-Q100; 74AHCT00-Q100
Nexperia
Quad 2-input NAND gate
10.1. Waveforms
VI
VM
nA, nB input
GND
tPLH
tPHL
VOH
VM
nY output
VOL
001aah088
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig. 6.
Input to output propagation delays
Table 8. Measurement points
Type
Input
Output
VM
VM
74AHC00-Q100
0.5 × VCC
0.5 × VCC
74AHCT00-Q100
1.5 V
0.5 × VCC
VI
negative
pulse
VM
VI
GND
VM
10 %
GND
positive
pulse
tW
90 %
tf
tr
tr
tf
90 %
VM
VM
10 %
tW
VCC
G
VI
DUT
VO
RT
CL
001aah768
Test data is given in Table 9.
Definitions test circuit:
RT = termination resistance should be equal to output impedance Zo of the pulse generator.
CL = load capacitance including jig and probe capacitance.
Fig. 7.
Test circuit for measuring switching times
Table 9. Test data
Type
Load
Input
Test
VI
tr, tf
CL
74AHC00-Q100
VCC
≤ 3.0 ns
15 pF, 50 pF
tPLH, tPHL
74AHCT00-Q100
3.0 V
≤ 3.0 ns
15 pF, 50 pF
tPLH, tPHL
74AHC_AHCT00_Q100
Product data sheet
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Rev. 2 — 26 May 2020
©
Nexperia B.V. 2020. All rights reserved
6 / 12
74AHC00-Q100; 74AHCT00-Q100
Nexperia
Quad 2-input NAND gate
11. Package outline
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
D
E
A
X
c
y
HE
v M A
Z
8
14
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
7
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
inches
0.069
0.010 0.057
0.004 0.049
0.01
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.05
0.01
0.01
0.004
0.028
0.012
0.244
0.039 0.028
0.041
0.228
0.016 0.024
θ
o
8
o
0
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
Fig. 8.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT108-1
076E06
MS-012
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Package outline SOT108-1 (SO14)
74AHC_AHCT00_Q100
Product data sheet
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Rev. 2 — 26 May 2020
©
Nexperia B.V. 2020. All rights reserved
7 / 12
74AHC00-Q100; 74AHCT00-Q100
Nexperia
Quad 2-input NAND gate
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
D
SOT402-1
E
A
X
c
y
HE
v M A
Z
8
14
Q
A2
pin 1 index
(A 3 )
A1
A
θ
Lp
1
L
7
detail X
w M
bp
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.72
0.38
8o
0o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT402-1
Fig. 9.
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
MO-153
Package outline SOT402-1 (TSSOP14)
74AHC_AHCT00_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 26 May 2020
©
Nexperia B.V. 2020. All rights reserved
8 / 12
74AHC00-Q100; 74AHCT00-Q100
Nexperia
Quad 2-input NAND gate
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 x 3 x 0.85 mm
B
D
SOT762-1
A
A
A1
E
c
detail X
terminal 1
index area
terminal 1
index area
C
e1
e
v
w
b
2
6
C A B
C
y
y1 C
L
1
7
14
8
Eh
e
k
13
9
Dh
X
k
0
2
Dimensions (mm are the original dimensions)
Unit
mm
max
nom
min
A(1)
1
A1
b
0.05 0.30
0.02 0.25
0.00 0.18
4 mm
scale
c
D(1)
Dh
E(1)
Eh
e
e1
0.2
3.1
3.0
2.9
1.65
1.50
1.35
2.6
2.5
2.4
1.15
1.00
0.85
0.5
2
k
L
v
0.2
0.5
0.4
0.3
0.1
w
y
0.05 0.05
y1
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
Outline
version
SOT762-1
References
IEC
JEDEC
JEITA
sot762-1_po
European
projection
Issue date
15-04-10
15-05-05
MO-241
Fig. 10. Package outline SOT762-1 (DHVQFN14)
74AHC_AHCT00_Q100
Product data sheet
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Rev. 2 — 26 May 2020
©
Nexperia B.V. 2020. All rights reserved
9 / 12
74AHC00-Q100; 74AHCT00-Q100
Nexperia
Quad 2-input NAND gate
12. Abbreviations
Table 10. Abbreviations
Acronym
Description
CDM
Charge Device Model
CMOS
Complementary Metal-Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MIL
Military
MM
Machine Model
TTL
Transistor-Transistor Logic
13. Revision history
Table 11. Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74AHC_AHCT00_Q100 v.2
20200526
Product data sheet
-
74AHC_AHCT00_Q100 v.1
Modifications:
•
•
•
•
•
74AHC_AHCT00_Q100 v.1
74AHC_AHCT00_Q100
Product data sheet
The format of this data sheet has been redesigned to comply with the identity guidelines
of Nexperia.
Legal texts have been adapted to the new company name where appropriate.
Section 1 and Section 2 updated.
Table 4: Derating values for Ptot total power dissipation have been updated.
Package outline drawing of SOT762-1 (Fig. 10) updated.
20130416
Product specification -
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 26 May 2020
-
©
Nexperia B.V. 2020. All rights reserved
10 / 12
74AHC00-Q100; 74AHCT00-Q100
Nexperia
Quad 2-input NAND gate
equipment, nor in applications where failure or malfunction of an Nexperia
product can reasonably be expected to result in personal injury, death or
severe property or environmental damage. Nexperia and its suppliers accept
no liability for inclusion and/or use of Nexperia products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
14. Legal information
Data sheet status
Document status
[1][2]
Product
status [3]
Definition
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Objective [short]
data sheet
Development
This document contains data from
the objective specification for
product development.
Preliminary [short]
data sheet
Qualification
This document contains data from
the preliminary specification.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification.
Product [short]
data sheet
Production
This document contains the product
specification.
[1]
[2]
[3]
Please consult the most recently issued document before initiating or
completing a design.
The term 'short data sheet' is explained in section "Definitions".
The product status of device(s) described in this document may have
changed since this document was published and may differ in case of
multiple devices. The latest product status information is available on
the internet at https://www.nexperia.com.
Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included herein
and shall have no liability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the relevant
full data sheet, which is available on request via the local Nexperia sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
Nexperia and its customer, unless Nexperia and customer have explicitly
agreed otherwise in writing. In no event however, shall an agreement be
valid in which the Nexperia product is deemed to offer functions and qualities
beyond those described in the Product data sheet.
Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, Nexperia does not give any
representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for the
consequences of use of such information. Nexperia takes no responsibility
for the content in this document if provided by an information source outside
of Nexperia.
In no event shall Nexperia be liable for any indirect, incidental, punitive,
special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia accepts no liability for
any assistance with applications or customer product design. It is customer’s
sole responsibility to determine whether the Nexperia product is suitable
and fit for the customer’s applications and products planned, as well as
for the planned application and use of customer’s third party customer(s).
Customers should provide appropriate design and operating safeguards to
minimize the risks associated with their applications and products.
Nexperia does not accept any liability related to any default, damage, costs
or problem which is based on any weakness or default in the customer’s
applications or products, or the application or use by customer’s third party
customer(s). Customer is responsible for doing all necessary testing for the
customer’s applications and products using Nexperia products in order to
avoid a default of the applications and the products or of the application or
use by customer’s third party customer(s). Nexperia does not accept any
liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — Nexperia products are
sold subject to the general terms and conditions of commercial sale, as
published at http://www.nexperia.com/profile/terms, unless otherwise agreed
in a valid written individual agreement. In case an individual agreement is
concluded only the terms and conditions of the respective agreement shall
apply. Nexperia hereby expressly objects to applying the customer’s general
terms and conditions with regard to the purchase of Nexperia products by
customer.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’s aggregate and cumulative liability towards customer
for the products described herein shall be limited in accordance with the
Terms and conditions of commercial sale of Nexperia.
Right to make changes — Nexperia reserves the right to make changes
to information published in this document, including without limitation
specifications and product descriptions, at any time and without notice. This
document supersedes and replaces all information supplied prior to the
publication hereof.
Suitability for use in automotive applications — This Nexperia product
has been qualified for use in automotive applications. Unless otherwise
agreed in writing, the product is not designed, authorized or warranted to
be suitable for use in life support, life-critical or safety-critical systems or
74AHC_AHCT00_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 26 May 2020
©
Nexperia B.V. 2020. All rights reserved
11 / 12
74AHC00-Q100; 74AHCT00-Q100
Nexperia
Quad 2-input NAND gate
Contents
1. General description...................................................... 1
2. Features.........................................................................1
3. Ordering information....................................................1
4. Functional diagram.......................................................2
5. Pinning information......................................................2
5.1. Pinning.........................................................................2
5.2. Pin description............................................................. 2
6. Functional description................................................. 3
7. Limiting values............................................................. 3
8. Recommended operating conditions..........................3
9. Static characteristics....................................................4
10. Dynamic characteristics............................................ 5
10.1. Waveforms.................................................................6
11. Package outline.......................................................... 7
12. Abbreviations............................................................ 10
13. Revision history........................................................10
14. Legal information......................................................11
©
Nexperia B.V. 2020. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 26 May 2020
74AHC_AHCT00_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 26 May 2020
©
Nexperia B.V. 2020. All rights reserved
12 / 12