74AHCT595D,112

74AHC595; 74AHCT595 8-bit serial-in/serial-out or parallel-out shift register with output latches Rev. 6 — 26 May 2020 Product data sheet 1. General description The 74AHC595; 74AHCT595 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset MR input. A LOW on MR will reset the shift register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the shift register is transferred to the storage register on a LOW-to-HIGH transition of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. Data in the storage register appears at the output whenever the output enable input (OE) is LOW. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the registers. The 74AHCT595 features TTL compatible inputs. Both 74AHC595 and 74AHCT595 inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments. 2. Features and benefits • • • • • • • • • • • Wide supply voltage range from 2.0 V to 5.5 V Balanced propagation delays All inputs have Schmitt-trigger action Overvoltage tolerant inputs to 5.5 V High noise immunity CMOS low power dissipation Input levels: • The 74AHC595 operates with CMOS input levels • The 74AHCT595 operates with TTL input levels ESD protection: • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-A exceeds 200 V • CDM JESD22-C101E exceeds 1000 V Latch-up performance exceeds 100 mA per JESD 78 Class II Level A Multiple package options Specified from -40 °C to +85 °C and from -40 °C to +125 °C 3. Applications • • Serial-to-parallel data conversion Remote control holding register 74AHC595; 74AHCT595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register with output latches 4. Ordering information Table 1. Ordering information Type number Package 74AHC595D Temperature range Name Description Version -40 °C to +125 °C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 -40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 -40 °C to +125 °C DHVQFN16 plastic dual in-line compatible thermal enhanced SOT763-1 very thin quad flat package; no leads; 16 terminals; body 2.5 × 3.5 × 0.85 mm 74AHCT595D 74AHC595PW 74AHCT595PW 74AHC595BQ 74AHCT595BQ 5. Functional diagram 14 DS 11 SHCP 10 MR 8-STAGE SHIFT REGISTER Q7S 12 STCP 13 OE 9 8-BIT STORAGE REGISTER 3-STATE OUTPUTS Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 15 1 Fig. 1. 2 3 4 5 6 7 mna554 Functional diagram 13 11 12 SHCP STCP Q7S Q0 Q1 14 Q2 Q3 DS Q4 Q5 Q6 Q7 MR 10 Fig. 2. Logic symbol 74AHC_AHCT595 Product data sheet EN3 12 10 11 9 15 14 1 C2 SRG8 R C1/ 1D 2D 3 2 1 2 3 3 4 4 5 5 6 6 7 7 OE 13 15 9 mna553 mna552 Fig. 3. IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 6 — 26 May 2020 © Nexperia B.V. 2020. All rights reserved 2 / 19 74AHC595; 74AHCT595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register with output latches STAGE 0 DS D STAGES 1 TO 6 Q STAGE 7 D Q D CP Q7S Q FF7 FF0 CP R R SHCP MR D Q D Q LATCH LATCH CP CP STCP OE Q0 Fig. 4. Q1 Q2 Q3 Q4 Q5 Q6 Q7 mna555 Logic diagram 6. Pinning information 6.1. Pinning 1 Q1 terminal 1 index area Q2 2 15 Q0 Q3 3 14 DS Q4 4 13 OE Q5 5 12 STCP Q6 6 11 SHCP Q7 7 10 MR GND 8 9 Product data sheet Q4 4 13 OE Q5 5 12 STCP Q6 6 Q7 7 GND(1) 11 SHCP 10 MR 001aae483 Transparent top view Q7S Pin configuration SOT109-1 (SO16) and SOT403-1 (TSSOP16) 74AHC_AHCT595 14 DS (1) This is not a ground pin. There is no electrical or mechanical requirement to solder the pad. In case soldered, the solder land should remain floating or connected to GND. 001aae538 Fig. 5. Q3 9 16 VCC 15 Q0 3 Q7S 1 2 8 Q1 Q2 GND 74AHC595 74AHCT595 16 VCC 74AHC595 74AHCT595 Fig. 6. Pin configuration SOT763-1 (DHVQFN16) All information provided in this document is subject to legal disclaimers. Rev. 6 — 26 May 2020 © Nexperia B.V. 2020. All rights reserved 3 / 19 74AHC595; 74AHCT595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register with output latches 6.2. Pin description Table 2. Pin description Symbol Pin Description Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7 15, 1, 2, 3, 4, 5, 6, 7 parallel data output GND 8 ground (0 V) Q7S 9 serial data output MR 10 master reset (active LOW) SHCP 11 shift register clock input STCP 12 storage register clock input OE 13 output enable input (active LOW) DS 14 serial data input VCC 16 supply voltage 7. Functional description Table 3. Function table H = HIGH voltage state; L = LOW voltage state; ↑ = LOW-to-HIGH transition; X = don’t care; NC = no change; Z = high-impedance OFF-state. Control Input Output Function SHCP STCP OE MR DS Q7S Qn X X L L X L NC a LOW-level on MR only affects the shift registers X ↑ L L X L L empty shift register loaded into storage register X X H L X L Z shift register clear; parallel outputs in high-impedance OFF-state ↑ X L H H Q6S NC logic HIGH-level shifted into shift register stage 0. Contents of all shift register stages shifted through, e.g. previous state of stage 6 (internal Q6S) appears on the serial output (Q7S). X ↑ L H X NC QnS contents of shift register stages (internal QnS) are transferred to the storage register and parallel output stages ↑ ↑ L H X Q6S QnS contents of shift register shifted through; previous contents of the shift register is transferred to the storage register and the parallel output stages 74AHC_AHCT595 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 26 May 2020 © Nexperia B.V. 2020. All rights reserved 4 / 19 74AHC595; 74AHCT595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register with output latches SHCP DS STCP MR OE Z-state Q0 Z-state Q1 Z-state Q6 Z-state Q7 Q7S mna556 Fig. 7. Timing diagram 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC supply voltage -0.5 +7.0 V VI input voltage -0.5 +7.0 V IIK input clamping current VI < -0.5 V [1] -20 - mA IOK output clamping current VO < -0.5 V or VO > VCC + 0.5 V [1] -20 +20 mA IO output current VO = -0.5 V to (VCC + 0.5 V) -25 +25 mA ICC supply current - +75 mA IGND ground current -75 - mA Tstg storage temperature -65 +150 °C Ptot total power dissipation - 500 mW [1] [2] Tamb = -40 °C to +125 °C [2] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For SOT109-1 (SO16) package: Ptot derates linearly with 12.4 mW/K above 110 °C. For SOT403-1 (TSSOP16) package: Ptot derates linearly with 8.5 mW/K above 91 °C. For SOT763-1 (DHVQFN16) package: Ptot derates linearly with 11.2 mW/K above 106 °C. 74AHC_AHCT595 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 26 May 2020 © Nexperia B.V. 2020. All rights reserved 5 / 19 74AHC595; 74AHCT595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register with output latches 9. Recommended operating conditions Table 5. Operating conditions Symbol Parameter VCC supply voltage VI input voltage VO output voltage Tamb ambient temperature Δt/ΔV Conditions 74AHC595 74AHCT595 Unit Min Typ Max Min Typ Max 2.0 5.0 5.5 4.5 5.0 5.5 V 0 - 5.5 0 - 5.5 V VCC V 0 - VCC 0 - -40 +25 +125 -40 +25 input transition rise and fall rate VCC = 3.0 V to 3.6 V - - 100 - - - ns/V VCC = 4.5 V to 5.5 V - - 20 - - 20 ns/V +125 °C 10. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max VCC = 2.0 V 1.5 - - 1.5 - 1.5 - V VCC = 3.0 V 2.1 - - 2.1 - 2.1 - V VCC = 5.5 V 3.85 - - 3.85 - 3.85 - V VCC = 2.0 V - - 0.5 - 0.5 - 0.5 V VCC = 3.0 V - - 0.9 - 0.9 - 0.9 V VCC = 5.5 V - - 1.65 - 1.65 - 1.65 V VI = VIH or VIL HIGH-level output voltage IO = -50 μA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = -50 μA; VCC = 3.0 V 2.9 3.0 - 2.9 - 2.9 - V IO = -50 μA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = -4.0 mA; VCC = 3.0 V 2.58 - - 2.48 - 2.40 - V IO = -8.0 mA; VCC = 4.5 V 3.94 - - 3.80 - 3.70 - V VI = VIH or VIL LOW-level output voltage IO = 50 μA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 50 μA; VCC = 3.0 V - 0 0.1 - 0.1 - 0.1 V IO = 50 μA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 3.0 V - - 0.36 - 0.44 - 0.55 V IO = 8.0 mA; VCC = 4.5 V - - 0.36 - 0.44 - 0.55 V - - 0.1 - 1.0 - 2.0 μA 74AHC595 VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage II input leakage current IOZ OFF-state VI = VIH or VIL; output current VO = VCC or GND; VCC = 5.5 V - - ±0.25 - ±2.5 - ±10 μA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 4.0 - 40 - 80 μA CI input capacitance - 3 10 - 10 - 10 pF 74AHC_AHCT595 Product data sheet VI = 5.5 V or GND; VCC = 0 V to 5.5 V All information provided in this document is subject to legal disclaimers. Rev. 6 — 26 May 2020 © Nexperia B.V. 2020. All rights reserved 6 / 19 74AHC595; 74AHCT595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register with output latches Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Min Typ Max Min Max Min Max Unit 74AHCT595 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 - - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - - 0.8 - 0.8 - 0.8 V VOH VI = VIH or VIL; VCC = 4.5 V HIGH-level output voltage IO = -50 μA 4.4 4.5 - 4.4 - 4.4 - V 3.94 - - 3.80 - 3.70 - V IO = -8.0 mA VOL VI = VIH or VIL; VCC = 4.5 V LOW-level output voltage IO = 50 μA - 0 0.1 - 0.1 - 0.1 V IO = 8.0 mA - - 0.36 - 0.44 - 0.55 V VI = 5.5 V or GND; VCC = 0 V to 5.5 V - - 0.1 - 1.0 - 2.0 μA II input leakage current IOZ OFF-state VI = VIH or VIL; output current VO = VCC or GND; VCC = 5.5 V - - ±0.25 - ±2.5 - ±10 μA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 4.0 - 40 - 80 μA ΔICC additional per input pin; VI = VCC - 2.1 V; supply current other inputs at VCC or GND; IO = 0 A; VCC = 4.5 V to 5.5 V - - 1.35 - 1.5 - 1.5 mA CI input capacitance - 3 10 - 10 - 10 pF 11. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 13. Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ [1] Max Min Max Min Max - 5.7 13.0 1.0 15.0 1.0 16.5 ns VCC = 3.0 V to 3.6 V; CL = 50 pF - 7.7 16.5 1.0 18.5 1.0 20.1 ns VCC = 4.5 V to 5.5 V; CL = 15 pF - 4.0 8.2 1.0 9.4 1.0 10.5 ns VCC = 4.5 V to 5.5 V; CL = 50 pF - 5.4 10.0 1.0 11.4 1.0 12.5 ns VCC = 3.0 V to 3.6 V; CL = 15 pF - 5.9 11.9 1.0 13.5 1.0 15.0 ns VCC = 3.0 V to 3.6 V; CL = 50 pF - 7.7 15.4 1.0 17.0 1.0 18.5 ns VCC = 4.5 V to 5.5 V; CL = 15 pF - 4.2 7.4 1.0 8.5 1.0 9.5 VCC = 4.5 V to 5.5 V; CL = 50 pF - 5.5 9.0 1.0 10.5 1.0 11.5 ns 74AHC595 tpd [2] propagation SHCP to Q7S; see Fig. 8 delay VCC = 3.0 V to 3.6 V; CL = 15 pF STCP to Qn; see Fig. 9 74AHC_AHCT595 Product data sheet [2] All information provided in this document is subject to legal disclaimers. Rev. 6 — 26 May 2020 © ns Nexperia B.V. 2020. All rights reserved 7 / 19 74AHC595; 74AHCT595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register with output latches Symbol Parameter Conditions tPHL 25 °C tdis fmax tW Unit Typ [1] Max Min Max Min Max - 5.9 12.8 1.0 13.7 1.0 15.0 ns - 7.4 16.3 1.0 17.2 1.0 18.7 ns - 4.4 8.0 1.0 9.1 1.0 10.0 ns - 5.6 10.0 1.0 11.1 1.0 12.0 ns VCC = 3.0 V to 3.6 V; CL = 15 pF - 5.6 11.5 1.0 13.5 1.0 15.0 ns VCC = 3.0 V to 3.6 V; CL = 50 pF - 7.4 15.0 1.0 17.0 1.0 18.5 ns VCC = 4.5 V to 5.5 V; CL = 15 pF - 4.0 8.6 1.0 10.0 1.0 11.0 ns VCC = 4.5 V to 5.5 V; CL = 50 pF - 5.3 10.6 1.0 12.0 1.0 13.0 ns VCC = 3.0 V to 3.6 V; CL = 15 pF - 5.4 11.0 1.0 13.0 1.0 14.5 ns VCC = 3.0 V to 3.6 V; CL = 50 pF - 8.7 15.7 1.0 16.2 1.0 17.5 ns VCC = 4.5 V to 5.5 V; CL = 15 pF - 3.8 8.0 1.0 9.5 1.0 10.5 ns VCC = 4.5 V to 5.5 V; CL = 50 pF - 5.8 10.3 1.0 11.0 1.0 12.0 ns VCC = 3.0 V to 3.6 V 80 125 - 60 - 40 - MHz VCC = 4.5 V to 5.5 V 130 170 - 110 - 90 - MHz VCC = 3.0 V to 3.6 V 5.0 - - 5.0 - 5.0 - ns VCC = 4.5 V to 5.5 V 5.0 - - 5.0 - 5.0 - ns VCC = 3.0 V to 3.6 V 5.0 - - 5.0 - 5.0 - ns VCC = 4.5 V to 5.5 V 5.0 - - 5.0 - 5.0 - ns VCC = 3.0 V to 3.6 V 5.0 - - 5.0 - 5.0 - ns VCC = 4.5 V to 5.5 V 5.0 - - 5.0 - 5.0 - ns VCC = 3.0 V to 3.6 V 3.5 - - 3.5 - 3.5 - ns VCC = 4.5 V to 5.5 V 3.0 - - 3.0 - 3.0 - ns VCC = 3.0 V to 3.6 V 8.5 - - 8.5 - 8.5 - ns VCC = 4.5 V to 5.5 V 5.0 - - 5.0 - 5.0 - ns VCC = 3.0 V to 3.6 V 1.5 - - 1.5 - 1.5 - ns VCC = 4.5 V to 5.5 V 2.0 - - 2.0 - 2.0 - ns VCC = 3.0 V to 3.6 V 3.0 - - 3.0 - 3.0 - ns VCC = 4.5 V to 5.5 V 2.5 - - 2.5 - 2.5 - ns - 180 - - - - - pF MR to Q7S; see Fig. 11 HIGH to LOW VCC = 3.0 V to 3.6 V; CL = 15 pF propagation VCC = 3.0 V to 3.6 V; CL = 50 pF delay VCC = 4.5 V to 5.5 V; CL = 15 pF enable time OE to Qn; see Fig. 12 [3] disable time OE to Qn; see Fig. 12 maximum frequency -40 °C to +125 °C Min VCC = 4.5 V to 5.5 V; CL = 50 pF ten -40 °C to +85 °C [4] SHCP or STCP; see Fig. 8 and Fig. 9 pulse width SHCP HIGH or LOW; see Fig. 8 STCP HIGH or LOW; see Fig. 9 MR LOW; see Fig. 11 tsu set-up time DS to SHCP; see Fig. 10 SHCP to STCP; see Fig. 9 th trec CPD hold time recovery time DS to SHCP; see Fig. 10 MR to SHCP; see Fig. 11 power fi = 1 MHz; VI = GND to VCC dissipation capacitance 74AHC_AHCT595 Product data sheet [5] [6] All information provided in this document is subject to legal disclaimers. Rev. 6 — 26 May 2020 © Nexperia B.V. 2020. All rights reserved 8 / 19 74AHC595; 74AHCT595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register with output latches Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ [1] Max Min Max Min Max - 3.8 8.2 1.0 9.0 1.0 10.0 ns - 5.2 10.0 1.0 11.0 1.0 12.0 ns VCC = 4.5 V to 5.5 V; CL = 15 pF - 4.0 7.4 1.0 8.5 1.0 9.5 VCC = 4.5 V to 5.5 V; CL = 50 pF - 5.3 9.0 1.0 10.5 1.0 11.5 ns MR to Q7S; see Fig. 11 HIGH to LOW VCC = 4.5 V to 5.5 V; CL = 15 pF propagation VCC = 4.5 V to 5.5 V; CL = 50 pF delay - 4.6 8.2 1.0 9.5 1.0 10.5 ns - 5.8 10.5 1.0 11.5 1.0 12.5 ns - 4.8 9.0 1.0 11.0 1.0 12.0 ns - 6.2 11.6 1.0 13.0 1.0 14.5 ns VCC = 4.5 V to 5.5 V; CL = 15 pF - 3.6 6.9 1.0 8.0 1.0 9.0 VCC = 4.5 V to 5.5 V; CL = 50 pF - 5.8 10.3 1.0 11.0 1.0 12.0 ns 130 170 - 110 - 90 - MHz 74AHCT595 tpd [2] propagation SHCP to Q7S; see Fig. 8 delay VCC = 4.5 V to 5.5 V; CL = 15 pF VCC = 4.5 V to 5.5 V; CL = 50 pF STCP to Qn; see Fig. 9 tPHL ten [2] enable time OE to Qn; see Fig. 12 [3] VCC = 4.5 V to 5.5 V; CL = 15 pF VCC = 4.5 V to 5.5 V; CL = 50 pF tdis ns disable time OE to Qn; see Fig. 12 [4] fmax maximum frequency tW pulse width SHCP HIGH or LOW; VCC = 4.5 V to 5.5 V; see Fig. 8 5.0 - - 5.0 - 5.0 - ns STCP HIGH or LOW; VCC = 4.5 V to 5.5 V; see Fig. 9 5.0 - - 5.0 - 5.0 - ns MR LOW; VCC = 4.5 V to 5.5 V; see Fig. 11 5.0 - - 5.0 - 5.0 - ns 3.0 - - 3.0 - 3.0 - ns SHCP to STCP; VCC = 4.5 V to 5.5 V; see Fig. 9 5.0 - - 5.0 - 5.0 - ns tsu SHCP and STCP; VCC = 4.5 V to 5.5 V; see Fig. 8 and Fig. 9 ns set-up time DS to SHCP; VCC = 4.5 V to 5.5 V; see Fig. 10 th hold time DS to SHCP; VCC = 4.5 V to 5.5 V; see Fig. 10 2.0 - - 2.0 - 2.0 - ns trec recovery time MR to SHCP; VCC = 4.5 V to 5.5 V; see Fig. 11 3.0 - - 3.0 - 3.0 - ns CPD power fi = 1 MHz; VI = GND to VCC dissipation capacitance - 190 - - - - - pF [1] [2] [3] [4] [5] [6] [5] [6] Typical values are measured at nominal supply voltage. tpd is the same as tPHL and tPLH. ten is the same as tPZL and tPZH. tdis is the same as tPLZ and tPHZ. CPD is used to determine the dynamic power dissipation (PD in μW). 2 2 PD = CPD × VCC × fi + Σ(CL × VCC × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; 2 Σ(CL × VCC × fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in V. All 9 outputs switching. 74AHC_AHCT595 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 26 May 2020 © Nexperia B.V. 2020. All rights reserved 9 / 19 74AHC595; 74AHCT595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register with output latches 11.1. Waveforms and test circuit 1/fmax VI SHCP input VM GND tW t PHL t PLH VOH VM Q7S output VOL mna557 Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig. 8. Shift clock pulse, maximum frequency and input to output propagation delays VI SHCP input VM GND 1/fmax t su VI STCP input VM GND tW t PHL t PLH VOH VM Qn output VOL mna558 Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig. 9. Storage clock to output propagation delays 74AHC_AHCT595 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 26 May 2020 © Nexperia B.V. 2020. All rights reserved 10 / 19 74AHC595; 74AHCT595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register with output latches VI VM SHCP input GND t su t su th th VI VM DS input GND VOH VM Q7S output VOL mna560 Measurement points are given in Table 8. The shaded areas indicate when the input is permitted to change for predictable output performance. VOL and VOH are typical output voltage levels that occur with the output load. Fig. 10. Data set-up and hold times VI VM MR input GND tW t rec VI SHCP input VM GND t PHL VOH VM Q7S output VOL mna561 Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig. 11. Master reset to output propagation delays 74AHC_AHCT595 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 26 May 2020 © Nexperia B.V. 2020. All rights reserved 11 / 19 74AHC595; 74AHCT595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register with output latches VI VM OE input GND tPLZ output LOW-to-OFF OFF-to-LOW VCC VM VOL + 0.3 V VOL VOH output HIGH-to-OFF OFF-to-HIGH tPZL tPHZ tPZH VOH - 0.3 V VM GND outputs enabled outputs enabled outputs disabled mna450 Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig. 12. Enable and disable times Table 8. Measurement points Type Input Output VM VM 74AHC595 0.5VCC 0.5VCC 74AHCT595 1.5 V 0.5VCC 74AHC_AHCT595 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 26 May 2020 © Nexperia B.V. 2020. All rights reserved 12 / 19 74AHC595; 74AHCT595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register with output latches VI negative pulse tW 90 % VM 0V VI positive pulse 0V VM 10 % tf tr tr tf 90 % VM VM 10 % tW VCC G VI DUT VCC VO RL RT S1 open CL 001aad983 Test data is given in Table 9. Definitions for test circuit: CL = load capacitance including jig and probe capacitance. RL = load resistance. RT = termination resistance should be equal to the output impedance Zo of the pulse generator. S1 = test selection switch. Fig. 13. Test circuit for measuring switching times Table 9. Test data Type Input Load S1 position VI tr, tf CL RL tPHL, tPLH tPZH, tPHZ tPZL, tPLZ 74AHC595 VCC ≤ 3.0 ns 15 pF, 50 pF 1 kΩ open GND VCC 74AHCT595 3.0 V ≤ 3.0 ns 15 pF, 50 pF 1 kΩ open GND VCC 74AHC_AHCT595 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 26 May 2020 © Nexperia B.V. 2020. All rights reserved 13 / 19 74AHC595; 74AHCT595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register with output latches 12. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e w M bp 0 2.5 detail X 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 inches 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.16 0.15 0.05 0.039 0.016 0.028 0.020 0.01 0.01 0.004 0.028 0.012 0.244 0.041 0.228 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig. 14. Package outline SOT109-1 (SO16) 74AHC_AHCT595 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 26 May 2020 © Nexperia B.V. 2020. All rights reserved 14 / 19 74AHC595; 74AHCT595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register with output latches TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm D SOT403-1 E A X c y HE v M A Z 9 16 Q A2 pin 1 index (A 3 ) A1 A θ Lp 1 L 8 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig. 15. Package outline SOT403-1 (TSSOP16) 74AHC_AHCT595 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 26 May 2020 © Nexperia B.V. 2020. All rights reserved 15 / 19 74AHC595; 74AHCT595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register with output latches DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT763-1 16 terminals; body 2.5 x 3.5 x 0.85 mm B D A A E A1 c detail X terminal 1 index area terminal 1 index area C e1 e b 2 7 y y1 C v M C A B w M C L 1 8 Eh e 16 9 15 10 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b c D (1) Dh E (1) Eh e e1 L v w y y1 mm 1 0.05 0.00 0.30 0.18 0.2 3.6 3.4 2.15 1.85 2.6 2.4 1.15 0.85 0.5 2.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT763-1 --- MO-241 --- EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig. 16. Package outline SOT763-1 (DHVQFN16) 74AHC_AHCT595 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 26 May 2020 © Nexperia B.V. 2020. All rights reserved 16 / 19 74AHC595; 74AHCT595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register with output latches 13. Abbreviations Table 10. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74AHC_AHCT595 v.6 20200526 Product data sheet - Modifications: • • • • • • 74AHC_AHCT595 v.5 The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Section 1 and Section 2 updated. Fig. 7: Timing diagram updated with SHCP waveform. Table 4: Derating values for Ptot total power dissipation updated. Table 7: Propagation delay symbol and parameter corrected (Errata). 74AHC_AHCT595 v.5 20120704 Modifications: • 74AHC_AHCT595 v.4 20090811 Product data sheet - 74AHC_AHCT595 v.3 74AHC_AHCT595 v.3 20080425 Product data sheet - 74AHC_AHCT595 v.2 74AHC_AHCT595 v.2 20060323 Product data sheet - 74AHC_AHCT595 v.1 74AHC_AHCT595 v.1 20000315 Product specification - - 74AHC_AHCT595 Product data sheet Product data sheet - 74AHC_AHCT595 v.4 Added GND in the pin configuration drawing DHVQFN16 (errata) All information provided in this document is subject to legal disclaimers. Rev. 6 — 26 May 2020 © Nexperia B.V. 2020. All rights reserved 17 / 19 74AHC595; 74AHCT595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register with output latches 15. Legal information injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Data sheet status Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the internet at https://www.nexperia.com. Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Nexperia does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. 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Nexperia takes no responsibility for the content in this document if provided by an information source outside of Nexperia. In no event shall Nexperia be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, Nexperia’s aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of Nexperia. Right to make changes — Nexperia reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal 74AHC_AHCT595 Product data sheet Applications — Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 6 — 26 May 2020 © Nexperia B.V. 2020. All rights reserved 18 / 19 74AHC595; 74AHCT595 Nexperia 8-bit serial-in/serial-out or parallel-out shift register with output latches Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Applications.................................................................. 1 4. Ordering information....................................................2 5. Functional diagram.......................................................2 6. Pinning information......................................................3 6.1. Pinning.........................................................................3 6.2. Pin description............................................................. 4 7. Functional description................................................. 4 8. Limiting values............................................................. 5 9. Recommended operating conditions..........................6 10. Static characteristics..................................................6 11. Dynamic characteristics.............................................7 11.1. Waveforms and test circuit.......................................10 12. Package outline........................................................ 14 13. Abbreviations............................................................ 17 14. Revision history........................................................17 15. Legal information......................................................18 © Nexperia B.V. 2020. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 26 May 2020 74AHC_AHCT595 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 26 May 2020 © Nexperia B.V. 2020. All rights reserved 19 / 19