74ALVCH16500
18-bit universal bus transceiver; 3-state
Rev. 3 — 11 December 2017
1
Product data sheet
General description
The 74ALVCH16500 is a high-performance CMOS product. This device is an 18-bit
universal transceiver featuring non-inverting 3-state bus compatible outputs in both
send and receive directions. Data flow in each direction is controlled by output enable
(OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CPBA) inputs.
For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH.
When LEAB is LOW, the A data is latched if CPAB is held at a HIGH or LOW logic level.
If LEAB is LOW, the A data is stored in the latch/flip-flop on the HIGH-to-LOW transition
of CPAB. When OEAB is HIGH, the outputs are active. When OEAB is LOW, the outputs
are in the high-impedance state.
Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA.
The output enables are complimentary (OEAB is active HIGH, and OEBA is active LOW).
To ensure the high impedance state during power up or power down, OEBA
should be tied to VCC through a pullup resistor and OEAB should be tied to GND
through a pulldown resistor; the minimum value of the resistor is determined by the
current-sinking/current-sourcing capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic
level.
2
Features and benefits
•
•
•
•
•
•
•
•
CMOS low power consumption
MultiByte flow-through standard pin-out architecture
Low inductance multiple VCC and GND pins for minimum noise and ground bounce
Direct interface with TTL levels (2.7 V to 3.6 V)
Bus hold on data inputs
Output drive capability 50 Ω transmission lines at 85 °C
Current drive ±24 mA at 3.0 V
Complies with JEDEC standards:
– JESD8-5 (2.3 V to 2.7 V)
– JESD8B/JESD36 (2.7 V to 3.6 V)
• ESD protection:
– HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V
– CDM JESD22-C101E exceeds 1000 V
74ALVCH16500
Nexperia
18-bit universal bus transceiver; 3-state
3
Ordering information
Table 1. Ordering information
Type number
Package
Temperature range
74ALVCH16500DGG -40 °C to +85 °C
4
Name
Description
Version
TSSOP56
plastic thin shrink small outline package;
56 leads; body width 6.1 mm
SOT364-1
Functional diagram
OEAB
CPBA
1
55
2
LEAB
OEBA
3
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
26
1
2
55
A0
B0
A1
B1
A2
B2
A3
B3
A4
B4
A5
B5
A6
B6
A7
B7
A8
B8
A9
B9
A10
B10
A11
B11
A12
B12
A13
B13
A14
B14
A15
B15
A16
B16
A17
B17
OEAB
OEBA
LEAB
LEBA
CPAB
CPBA
CPBA
54
LEBA
52
27
30
28
51
49
3
A0
48
47
A1
45
A2
44
A3
43
A4
42
A5
41
A6
40
A7
38
A8
37
A9
36
A10
34
A11
33
A12
31
A13
A14
27
A15
28
A16
30
A17
5
EN1
2C3
C3
G2
EN4
5C6
C6
G5
3D
1
1
4
1
6D
54
52
6
51
8
49
9
48
10
47
12
45
13
44
14
43
15
42
16
41
17
40
19
38
20
37
21
36
23
34
24
33
26
31
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
aaa-027849
aaa-027848
Figure 1. Logic symbol
Figure 2. IEC logic symbol
VCC
data input
to internal circuit
001aal733
Figure 3. Bus hold circuit
74ALVCH16500
Product data sheet
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2 / 17
74ALVCH16500
Nexperia
18-bit universal bus transceiver; 3-state
OEAB
CPBA
LEBA
CPAB
LEAB
OEBA
An
C1
C1
1D
1D
C1
C1
1D
1D
Bn
18 IDENTICAL CHANNELS
to 17 other channels
aaa-027850
Figure 4. Logic diagram (one section)
74ALVCH16500
Product data sheet
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Rev. 3 — 11 December 2017
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3 / 17
74ALVCH16500
Nexperia
18-bit universal bus transceiver; 3-state
5
Pinning information
5.1 Pinning
74ALVCH16500
OEAB
1
56 GND
LEAB
2
55 CPAB
A0
3
54 B0
GND
4
53 GND
A1
5
52 B1
A2
6
51 B2
VCC
7
A3
8
50 VCC
49 B3
A4
9
48 B4
A5 10
47 B5
GND 11
46 GND
A6 12
45 B6
A7 13
44 B7
A8 14
43 B8
A9 15
42 B9
A10 16
41 B10
A11 17
40 B11
GND 18
39 GND
A12 19
38 B12
A13 20
37 B13
A14 21
36 B14
VCC 22
A15 23
35 VCC
34 B15
A16 24
33 B16
GND 25
32 GND
A17 26
31 B17
OEBA 27
30 CPBA
LEBA 28
29 GND
aaa-027851
Figure 5. Pin configuration for TSSOP56
74ALVCH16500
Product data sheet
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Rev. 3 — 11 December 2017
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4 / 17
74ALVCH16500
Nexperia
18-bit universal bus transceiver; 3-state
5.2 Pin description
Table 2. Pin description
Symbol
Pin
Description
A0, A1, A2, A3, A4, A5, A6, A7, A8,
A9, A10, A11, A12, A13, A14, A15, A16, A17
3, 5, 6, 8, 9, 10, 12, 13, 14,
15, 16, 17, 19, 20, 21, 23, 24, 26
data inputs/outputs
B0, B1, B2, B3, B4, B5, B6, B7, B8,
B9, B10, B11, B12, B13, B14, B15, B16, B17
54, 52, 51, 49, 48, 47, 45, 44, 43,
42, 41, 40, 38, 37, 36, 34, 33, 31
data outputs/inputs
OEAB
1
A to B output enable input
(active HIGH)
OEBA
27
B to A output enable input
(active LOW)
LEAB, LEBA
2, 28
A to B / B to A latch enable inputs
(active HIGH)
CPBA, CPAB
30, 55
B to A / A to B clock inputs
(active LOW)
GND
4, 11, 18, 25, 29, 32, 39, 46, 53, 56
ground (0 V)
VCC
7, 22, 35, 50
supply voltage
6
Functional description
Table 3. Function selection
Operating mode
[1] [2]
Inputs
Outputs
OEAB
LEAB
CPAB
An
Bn
Disabled
L
H
X
X
Z
Transparent
H
H
X
H
H
H
H
X
L
L
H
↓
X
h
H
H
↓
X
l
L
H
L
↓
h
H
H
L
↓
l
L
H
L
H or L
X
H
H
L
H or L
X
L
Latch data & display
Clock data & display
Hold data & display
[1] A-to-B data flow is shown; B-to-A flow is similar but uses OEBA, LEBA, and CPBA.
[2] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the enable or clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the enable or clock transition;
X = don’t care;
↓ = HIGH-to-LOW enable or clock transition;
Z = high-impedance OFF-state.
74ALVCH16500
Product data sheet
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5 / 17
74ALVCH16500
Nexperia
18-bit universal bus transceiver; 3-state
7
Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
VI
Conditions
input voltage
Min
Max
Unit
-0.5
+4.6
V
data inputs
[1]
-0.5
control inputs
[1]
-0.5
[1]
-0.5
VO
output voltage
IIK
input clamping current
VI < 0 V
IOK
output clamping current
IO
output current
ICC
VCC + 0.5 V
+4.6
V
VCC + 0.5 V
-50
-
mA
VO > VCC or VO < 0 V
-
±50
mA
VO = 0 V to VCC
-
±50
mA
supply current
-
100
mA
IGND
ground current
-100
-
mA
Tstg
storage temperature
-65
+150
°C
-
600
mW
Ptot
total power dissipation
Tamb = -40 °C to +85 °C
[2]
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For TSSOP56 packages: above 55 °C derate linearly with 8 mW/K.
8
Recommended operating conditions
Table 5. Recommended operating conditions
Symbol
Parameter
Conditions
Min
Max
Unit
VCC
supply voltage
for maximum speed performance at CL = 30 pF
2.3
2.7
V
for maximum speed performance at CL = 50 pF
3.0
3.6
V
VI
input voltage
0
VCC
V
VO
output voltage
0
VCC
V
Tamb
ambient temperature
in free air
-40
+85
°C
Δt/ΔV
input transition rise and fall rate
VCC = 2.3 V to 3.0 V
-
20
ns/V
VCC = 3.0 V to 3.6 V
-
10
ns/V
74ALVCH16500
Product data sheet
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74ALVCH16500
Nexperia
18-bit universal bus transceiver; 3-state
9
Static characteristics
Table 6. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Parameter
Conditions
Min
VIH
HIGH-level input
voltage
VCC = 2.3 to 2.7 V
1.7
1.2
-
V
VCC = 2.7 to 3.6 V
2.0
1.5
-
V
LOW-level input
voltage
VCC = 2.3 to 2.7 V
-
1.2
0.7
V
VCC = 2.7 to 3.6 V
-
1.5
0.8
V
HIGH-level output
voltage
VI = VIH or VIL
IO = -100 μA; VCC = 2.3 V to 3.6 V
VCC - 0.2
VCC
-
V
IO = -6 mA; VCC = 2.3 V
VCC - 0.3
VCC - 0.08
-
V
IO = -12 mA; VCC = 2.3 V
VCC - 0.6
VCC - 0.26
-
V
IO = -12 mA; VCC = 2.7 V
VCC - 0.5
VCC - 0.14
-
V
IO = -12 mA; VCC = 3.0 V
VCC - 0.6
VCC - 0.09
-
V
IO = -24 mA; VCC = 3.0 V
VCC - 1.0
VCC - 0.28
-
V
IO = 100 μA; VCC = 2.3 V to 3.6 V
-
GND
0.20
V
IO = 6 mA; VCC = 2.3 V
-
0.07
0.40
V
IO = 12 mA; VCC = 2.3 V
-
0.15
0.70
V
IO = 12 mA; VCC = 2.7 V
-
0.14
0.40
V
IO = 24 mA; VCC = 3.0 V
-
0.27
0.55
V
-
0.1
5
μA
VIL
VOH
VOL
LOW-level output
voltage
Typ
[1]
Symbol
Max
Unit
VI = VIH or VIL
II
input leakage current VI = VCC or GND; VCC = 2.3 V to 3.6 V
IBHL
bus hold LOW
current
VCC = 2.3 V; VI = 0.7 V
45
-
-
μA
VCC = 3.0 V; VI = 0.8 V
75
150
-
μA
bus hold HIGH
current
VCC = 2.3 V; VI = 1.7 V
-45
-
-
μA
VCC = 3.0 V; VI = 2.0 V
-75
-175
-
μA
IBHLO
bus hold LOW
overdrive current
VCC = 3.6 V
500
-
-
μA
IBHHO
bus hold HIGH
overdrive current
VCC = 3.6 V
-500
-
-
μA
IOZ
OFF-state output
current
VCC = 2.7 V to 3.6 V; VI = VIH or VIL;
VO = VCC or GND
-
0.1
10
μA
ICC
supply current
VCC = 2.3 to 3.6 V; VI = VCC or GND; IO = 0 A
-
0.2
40
μA
ΔICC
additional supply
current
VI = VCC - 0.6 V; IO = 0 A;
VCC = 2.3 V to 3.6 V
-
150
750
μA
CI
input capacitance
-
4.0
-
pF
CI/O
input/output
capacitance
-
8.0
-
pF
IBHH
[1] All typical values are measured at Tamb = 25 °C.
74ALVCH16500
Product data sheet
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74ALVCH16500
Nexperia
18-bit universal bus transceiver; 3-state
10 Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit, see Figure 10.
Symbol
tpd
Parameter
propagation delay
Conditions
An to Bn; Bn to An; Figure 6
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
enable time
OEBA to An; Figure 8
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
disable time
OEBA to An; Figure 8
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 11 December 2017
ns
-
3.1
4.7
ns
1.0
2.9
4.2
ns
1.0
3.6
6.2
ns
-
3.4
5.5
ns
1.0
3.1
4.9
ns
1.0
3.7
6.6
ns
-
3.8
6.6
ns
1.1
3.3
5.5
ns
1.0
3.1
6.2
ns
-
3.3
6.2
ns
1.0
2.8
5.2
ns
ns
1.0
2.7
5.7
ns
-
2.7
5.4
ns
1.0
2.5
4.6
ns
1.0
2.8
5.4
ns
-
3.3
4.6
ns
1.0
3.2
4.3
ns
[2]
VCC = 2.3 V to 2.7 V
74ALVCH16500
5.2
[2]
VCC = 2.3 V to 2.7 V
OEAB to Bn; Figure 8
3.1
[2]
VCC = 2.3 V to 2.7 V
tdis
Unit
[2]
VCC = 2.3 V to 2.7 V
OEAB to Bn; Figure 8
Max
[2]
VCC = 2.3 V to 2.7 V
ten
1.0
[1]
[2]
VCC = 2.3 V to 2.7 V
CPAB to Bn; CPBA to An; Figure 7
Typ
[2]
VCC = 2.3 V to 2.7 V
LEAB to Bn; LEBA to An; Figure 7
Min
ns
1.0
2.7
6.1
ns
-
3.6
5.7
ns
1.5
3.2
5.0
ns
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74ALVCH16500
Nexperia
18-bit universal bus transceiver; 3-state
Symbol
Parameter
Conditions
tw
pulse width
LEAB HIGH; LEBA HIGH; Figure 7
[1]
Min
Typ
Max
Unit
VCC = 2.3 V to 2.7 V
3.3
0.8
-
ns
VCC = 2.7 V
3.3
0.7
-
ns
VCC = 3.0 V to 3.6 V
3.3
0.9
-
ns
VCC = 2.3 V to 2.7 V
3.3
2.0
-
ns
VCC = 2.7 V
3.3
1.4
-
ns
VCC = 3.0 V to 3.6 V
3.3
1.1
-
ns
VCC = 2.3 V to 2.7 V
1.7
0.1
-
ns
VCC = 2.7 V
1.4
0.1
-
ns
VCC = 3.0 V to 3.6 V
1.3
0.2
-
ns
VCC = 2.3 V to 2.7 V
1.9
0.1
-
ns
VCC = 2.7 V
1.6
−0.2
-
ns
VCC = 3.0 V to 3.6 V
1.4
0.3
-
ns
VCC = 2.3 V to 2.7 V
1.7
0.2
-
ns
VCC = 2.7 V
1.6
0.3
-
ns
VCC = 3.0 V to 3.6 V
1.3
−0.1
-
ns
VCC = 2.3 V to 2.7 V
2.0
0.2
-
ns
VCC = 2.7 V
1.8
0.1
-
ns
VCC = 3.0 V to 3.6 V
1.5
0.1
-
ns
VCC = 2.3 V to 2.7 V
150
333
-
MHz
VCC = 2.7 V
150
333
-
MHz
150
340
-
MHz
output enabled
-
21
-
pF
output disabled
-
3
-
pF
CPAB, CPBA HIGH or LOW; Figure 7
tsu
set-up time
An to CPAB; Bn to CPBA; Figure 9
An to LEAB; Bn to LEBA; Figure 9
th
hold time
An to CPAB; Bn to CPBA; Figure 9
An to LEAB; Bn to LEBA; Figure 9
fmax
maximum frequency
CPAB, CPBA; Figure 7
VCC = 3.0 V to 3.6 V
CPD
power dissipation
capacitance
per latch; VI = GND to VCC
[3]
[1] Typical values are measured at Tamb = 25 °C
Typical values for VCC = 2.3 V to 2.7 V are measured at VCC = 2.5 V
Typical values for VCC = 3.0 V to 3.6 V are measured at VCC = 3.3 V
[2] tpd is the same as tPHL and tPLH; ten is the same as tPZH and tPZL; tdis is the same as tPHZ and tPLZ.
[3] CPD is used to determine the dynamic power dissipation (PD in μW):
2
2
PD = CPD × VCC × fi × N + ∑(CL × VCC × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
2
∑(CL × VCC × fo) = sum of outputs.
74ALVCH16500
Product data sheet
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74ALVCH16500
Nexperia
18-bit universal bus transceiver; 3-state
10.1 Waveforms and test circuit
VI
An, Bn
input
VM
VM
tPHL
tPLH
GND
VOH
Bn, An
output
VM
VM
VOL
001aal734
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Figure 6. The input An, Bn to output Bn, An propagation delay times.
CPBA, CPAB
input
1/fmax
VI
VM
LEBA, LEAB
GND
input
VM
VM
tW
tPHL
tPLH
VOH
VM
An, Bn output
VM
VOL
aaa-027852
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Figure 7. Latch enable input LEAB, LEBA and clock input CPAB, CPBA to output Bn, An propagation delay times;
pulse width and fmax of CPAB and CPBA
OEAB
input
VI
VM
OEBA
input
An, Bn output
LOW-to-OFF
OFF-to-LOW
VM
GND
tPLZ
tPZL
VCC
VM
VX
VOL
tPHZ
An, Bn output
HIGH-to-OFF
OFF-to-HIGH
VOH
tPZH
VY
VM
GND
outputs
enabled
outputs
disabled
outputs
enabled
aaa-027853
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Figure 8. 3-state enable and disable times.
74ALVCH16500
Product data sheet
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10 / 17
74ALVCH16500
Nexperia
18-bit universal bus transceiver; 3-state
An, Bn
input
VI
VM
GND
tsu
VI
CPBA, CPAB,
LEBA, LEAB
input GND
VM
th
VM
tsu
VM
VM
th
VM
aaa-027854
The shaded areas indicate when the input is permitted to change for predictable output performance.
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Figure 9. Data set-up and hold times for An, Bn inputs to LEAB, LEBA, CPAB and CPBA inputs.
Table 8. Measurement points
Supply voltage
Input
VCC
VI
VM
VM
VX
VY
2.3 V to 2.7 V
VCC
0.5 VCC
0.5 VCC
VOL + 0.15 V
VOH - 0.15 V
2.7 V
2.7 V
1.5 V
1.5 V
VOL + 0.3 V
VOH - 0.3 V
3.0 V to 3.6 V
2.7 V
1.5 V
1.5 V
VOL + 0.3 V
VOH - 0.3 V
74ALVCH16500
Product data sheet
Output
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11 / 17
74ALVCH16500
Nexperia
18-bit universal bus transceiver; 3-state
VI
negative
pulse
tW
90 %
VM
0V
VI
positive
pulse
0V
VM
10 %
tf
tr
tr
tf
90 %
VM
VM
10 %
tW
VEXT
VCC
G
VI
RL
VO
DUT
RT
CL
RL
001aae331
Test data is given in Table 9.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Figure 10. Test circuit for measuring switching times
Table 9. Test data
Supply voltage
Input
VCC
VI
tr, tf
CL
RL
tPLH, tPHL
tPLZ, tPZL
tPHZ, tPZH
2.3 V to 2.7 V
VCC
≤ 2.0 ns
30 pF
500 Ω
open
2 × VCC
GND
2.7 V
2.7 V
≤2.5 ns
50 pF
500 Ω
open
2 × VCC
GND
3.0 V to 3.6 V
2.7 V
≤2.5 ns
50 pF
500 Ω
open
2 × VCC
GND
74ALVCH16500
Product data sheet
Load
VEXT
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 11 December 2017
© Nexperia B.V. 2017. All rights reserved.
12 / 17
74ALVCH16500
Nexperia
18-bit universal bus transceiver; 3-state
11 Package outline
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm
SOT364-1
E
D
A
X
c
HE
y
v M A
Z
56
29
Q
A2
(A 3 )
A1
pin 1 index
A
θ
Lp
L
1
28
w M
bp
e
detail X
2.5
0
5 mm
scale
DIMENSIONS (mm are the original dimensions).
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z
θ
mm
1.2
0.15
0.05
1.05
0.85
0.25
0.28
0.17
0.2
0.1
14.1
13.9
6.2
6.0
0.5
8.3
7.9
1
0.8
0.4
0.50
0.35
0.25
0.08
0.1
0.5
0.1
8
o
0
o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT364-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
MO-153
Figure 11. Package outline SOT364-1 (TSSOP56)
74ALVCH16500
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 11 December 2017
© Nexperia B.V. 2017. All rights reserved.
13 / 17
74ALVCH16500
Nexperia
18-bit universal bus transceiver; 3-state
12 Abbreviations
Table 10. Abbreviations
Acronym
Description
CMOS
Complementary Metal-Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
TTL
Transistor-Transistor Logic
13 Revision history
Table 11. Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74ALVCH16500 v.3
20171211
Product data sheet
-
74ALVCH16500 v.2
Modifications:
• The format of this data sheet has been redesigned to comply with the identity guidelines of
Nexperia.
• Legal texts have been adapted to the new company name where appropriate.
• Figure 2: IEC logic symbol updated
74ALVCH16500 v.2
19980924
Product specification
-
74ALVCH16500 v.1
74ALVCH16500 v.1
19980831
Product specification
-
-
74ALVCH16500
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 11 December 2017
© Nexperia B.V. 2017. All rights reserved.
14 / 17
74ALVCH16500
Nexperia
18-bit universal bus transceiver; 3-state
14 Legal information
14.1 Data sheet status
Document status
[1][2]
Product status
[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term 'short data sheet' is explained in section "Definitions".
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple
devices. The latest product status information is available on the Internet at URL http://www.nexperia.com.
14.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included herein
and shall have no liability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the
relevant full data sheet, which is available on request via the local Nexperia
sales office. In case of any inconsistency or conflict with the short data sheet,
the full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
Nexperia and its customer, unless Nexperia and customer have explicitly
agreed otherwise in writing. In no event however, shall an agreement be
valid in which the Nexperia product is deemed to offer functions and qualities
beyond those described in the Product data sheet.
14.3 Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, Nexperia does not give any
representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for the
consequences of use of such information. Nexperia takes no responsibility
for the content in this document if provided by an information source outside
of Nexperia. In no event shall Nexperia be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory. Notwithstanding any damages that
customer might incur for any reason whatsoever, Nexperia's aggregate and
cumulative liability towards customer for the products described herein shall
be limited in accordance with the Terms and conditions of commercial sale of
Nexperia.
Right to make changes — Nexperia reserves the right to make changes
to information published in this document, including without limitation
specifications and product descriptions, at any time and without notice. This
document supersedes and replaces all information supplied prior to the
publication hereof.
Suitability for use — Nexperia products are not designed, authorized or
warranted to be suitable for use in life support, life-critical or safety-critical
74ALVCH16500
Product data sheet
systems or equipment, nor in applications where failure or malfunction
of an Nexperia product can reasonably be expected to result in personal
injury, death or severe property or environmental damage. Nexperia and its
suppliers accept no liability for inclusion and/or use of Nexperia products in
such equipment or applications and therefore such inclusion and/or use is at
the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification. Customers are responsible for the
design and operation of their applications and products using Nexperia
products, and Nexperia accepts no liability for any assistance with
applications or customer product design. It is customer’s sole responsibility
to determine whether the Nexperia product is suitable and fit for the
customer’s applications and products planned, as well as for the planned
application and use of customer’s third party customer(s). Customers should
provide appropriate design and operating safeguards to minimize the risks
associated with their applications and products. Nexperia does not accept
any liability related to any default, damage, costs or problem which is based
on any weakness or default in the customer’s applications or products, or
the application or use by customer’s third party customer(s). Customer is
responsible for doing all necessary testing for the customer’s applications
and products using Nexperia products in order to avoid a default of the
applications and the products or of the application or use by customer’s third
party customer(s). Nexperia does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — Nexperia products are
sold subject to the general terms and conditions of commercial sale, as
published at http://www.nexperia.com/profile/terms, unless otherwise agreed
in a valid written individual agreement. In case an individual agreement is
concluded only the terms and conditions of the respective agreement shall
apply. Nexperia hereby expressly objects to applying the customer’s general
terms and conditions with regard to the purchase of Nexperia products by
customer.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or
the grant, conveyance or implication of any license under any copyrights,
patents or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 11 December 2017
© Nexperia B.V. 2017. All rights reserved.
15 / 17
74ALVCH16500
Nexperia
18-bit universal bus transceiver; 3-state
Non-automotive qualified products — Unless this data sheet expressly
states that this specific Nexperia product is automotive qualified, the
product is not suitable for automotive use. It is neither qualified nor tested in
accordance with automotive testing or application requirements. Nexperia
accepts no liability for inclusion and/or use of non-automotive qualified
products in automotive equipment or applications. In the event that customer
uses the product for design-in and use in automotive applications to
automotive specifications and standards, customer (a) shall use the product
without Nexperia's warranty of the product for such automotive applications,
use and specifications, and (b) whenever customer uses the product for
automotive applications beyond Nexperia's specifications such use shall be
solely at customer’s own risk, and (c) customer fully indemnifies Nexperia
for any liability, damages or failed product claims resulting from customer
74ALVCH16500
Product data sheet
design and use of the product for automotive applications beyond Nexperia's
standard warranty and Nexperia's product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
14.4 Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 11 December 2017
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16 / 17
74ALVCH16500
Nexperia
18-bit universal bus transceiver; 3-state
Contents
1
2
3
4
5
5.1
5.2
6
7
8
9
10
10.1
11
12
13
14
General description ............................................ 1
Features and benefits .........................................1
Ordering information .......................................... 2
Functional diagram ............................................. 2
Pinning information ............................................ 4
Pinning ............................................................... 4
Pin description ................................................... 5
Functional description ........................................5
Limiting values .................................................... 6
Recommended operating conditions ................ 6
Static characteristics .......................................... 7
Dynamic characteristics .....................................8
Waveforms and test circuit .............................. 10
Package outline .................................................13
Abbreviations .................................................... 14
Revision history ................................................ 14
Legal information .............................................. 15
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section 'Legal information'.
© Nexperia B.V. 2017.
All rights reserved.
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 11 December 2017
Document identifier: 74ALVCH16500