74HC10-Q100; 74HCT10-Q100
Triple 3-input NAND gate
Rev. 1 — 21 February 2013
Product data sheet
1. General description
The 74HC10-Q100; 74HCT10-Q100 is a triple 3-input NAND gate. Inputs include clamp
diodes. This enables the use of current limiting resistors to interface inputs to voltages in
excess of VCC.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Complies with JEDEC standard JESD7A
Input levels:
For 74HC10-Q100: CMOS level
For 74HCT10-Q100: TTL level
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Multiple package options
3. Ordering information
Table 1.
Ordering information
Type number
74HC10D-Q100
Package
Temperature range
Name
Description
Version
40 C to +125 C
SO14
plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
40 C to +125 C
TSSOP14
plastic thin shrink small outline package;
14 leads; body width 4.4 mm
SOT402-1
74HCT10D-Q100
74HC10PW-Q100
74HCT10PW-Q100
74HC10-Q100; 74HCT10-Q100
Nexperia
Triple 3-input NAND gate
4. Functional diagram
1
1
2
1A
2
1B
13
1C
3
2A
4
2B
5
2C
9
3A
10
3B
11
3C
1Y
12
12
&
6
3
2Y
4
6
5
A
3Y
9
8
&
10
8
Y
B
11
C
mna759
mna757
Fig 1.
&
13
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
mna758
Logic diagram for one gate
5. Pinning information
5.1 Pinning
+&4
+&74
$
9&&
%
&
$
<
%
&
&
%
<
$
*1'
<
+&4
+&74
$
%
9&&
&
$
<
%
&
&
%
<
$
*1'
<
DDD
Fig 4.
DDD
Pin configuration SO14
Fig 5.
Pin configuration TSSOP14
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
1A, 2A, 3A
1, 3, 9
data input
1B, 2B, 3B
2, 4, 10
data input
GND
7
ground (0 V)
1C, 2C, 3C
13, 5, 11
data input
1Y, 2Y, 3Y
12, 6, 8
data output
VCC
14
supply voltage
74HC_HCT10_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 February 2013
©
Nexperia B.V. 2017. All rights reserved
2 of 13
74HC10-Q100; 74HCT10-Q100
Nexperia
Triple 3-input NAND gate
6. Functional description
Table 3.
Function selection[1]
Input
Output
nA
nB
nC
nY
L
X
X
H
X
L
X
H
X
X
L
H
H
H
H
L
[1]
H = HIGH voltage level; L = LOW voltage level; X = don’t care.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
IIK
input clamping current
VI < 0.5 V or VI > VCC + 0.5 V
[1]
IOK
output clamping current
VO < 0.5 V or VO > VCC + 0.5 V
[1]
IO
output current
0.5 V < VO < VCC + 0.5 V
ICC
IGND
Tstg
storage temperature
Max
Unit
0.5
+7
V
-
20
mA
-
20
mA
-
25
mA
supply current
-
50
mA
ground current
50
-
mA
65
+150
C
-
500
mW
total power dissipation
Ptot
Conditions
SO14 and TSSOP14 packages
Min
[2]
[1]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2]
For SO14 package: Ptot derates linearly with 8 mW/K above 70 C.
For TSSOP14 package Ptot derates linearly with 5.5 mW/K above 60 C.
74HC_HCT10_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 February 2013
©
Nexperia B.V. 2017. All rights reserved
3 of 13
74HC10-Q100; 74HCT10-Q100
Nexperia
Triple 3-input NAND gate
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
74HC10-Q100
Min
Typ
74HCT10-Q100
Max
Min
Typ
Unit
Max
VCC
supply voltage
2.0
5.0
6.0
4.5
5.0
5.5
V
VI
input voltage
0
-
VCC
0
-
VCC
V
VO
output voltage
0
-
VCC
0
-
VCC
V
Tamb
ambient temperature
40
-
+125
40
-
+125
C
t/V
input transition rise and fall rate
VCC = 2.0 V
-
-
625
-
-
-
ns/V
VCC = 4.5 V
-
1.67
139
-
1.67
139
ns/V
VCC = 6.0 V
-
-
83
-
-
-
ns/V
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
25 C
Conditions
40 C to +85 C 40 C to +125 C Unit
Min
Typ
Max
Min
Max
Min
Max
VCC = 2.0 V
1.5
1.2
-
1.5
-
1.5
-
V
VCC = 4.5 V
3.15
2.4
-
3.15
-
3.15
-
V
VCC = 6.0 V
4.2
3.2
-
4.2
-
4.2
-
V
VCC = 2.0 V
-
0.8
0.5
-
0.5
-
0.5
V
VCC = 4.5 V
-
2.1
1.35
-
1.35
-
1.35
V
VCC = 6.0 V
-
2.8
1.8
-
1.8
-
1.8
V
IO = 20 A; VCC = 2.0 V
1.9
2.0
-
1.9
-
1.9
-
V
IO = 20 A; VCC = 4.5 V
4.4
4.5
-
4.4
-
4.4
-
V
IO = 20 A; VCC = 6.0 V
5.9
6.0
-
5.9
-
5.9
-
V
IO = 4.0 mA; VCC = 4.5 V
3.98
4.32
-
3.84
-
3.7
-
V
IO = 5.2 mA; VCC = 6.0 V
5.48
5.81
-
5.34
-
5.2
-
V
IO = 20 A; VCC = 2.0 V
-
0
0.1
-
0.1
-
0.1
V
IO = 20 A; VCC = 4.5 V
-
0
0.1
-
0.1
-
0.1
V
IO = 20 A; VCC = 6.0 V
-
0
0.1
-
0.1
-
0.1
V
IO = 4.0 mA; VCC = 4.5 V
-
0.15
0.26
-
0.33
-
0.4
V
IO = 5.2 mA; VCC = 6.0 V
-
0.16
0.26
-
0.33
-
0.4
V
74HC10-Q100
VIH
VIL
VOH
VOL
HIGH-level
input voltage
LOW-level
input voltage
HIGH-level
output voltage
LOW-level
output voltage
VI = VIH or VIL
VI = VIH or VIL
II
input leakage
current
VI = VCC or GND;
VCC = 6.0 V
-
-
0.1
-
1
-
1
A
ICC
supply current
VI = VCC or GND; IO = 0 A;
VCC = 6.0 V
-
-
2.0
-
20
-
40
A
74HC_HCT10_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 February 2013
©
Nexperia B.V. 2017. All rights reserved
4 of 13
74HC10-Q100; 74HCT10-Q100
Nexperia
Triple 3-input NAND gate
Table 6.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
CI
25 C
Conditions
input
capacitance
40 C to +85 C 40 C to +125 C Unit
Min
Typ
Max
Min
Max
Min
Max
-
3.5
-
-
-
-
-
pF
74HCT10-Q100
VIH
HIGH-level
input voltage
VCC = 4.5 V to 5.5 V
2.0
1.6
-
2.0
-
2.0
-
V
VIL
LOW-level
input voltage
VCC = 4.5 V to 5.5 V
-
1.2
0.8
-
0.8
-
0.8
V
VOH
HIGH-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 A
4.4
4.5
-
4.4
-
4.4
-
V
IO = 4.0 mA
3.98
4.32
-
3.84
-
3.7
-
V
LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
-
0
0.1
-
0.1
-
0.1
V
II
input leakage
current
VI = VCC or GND;
VCC = 5.5 V
-
-
0.1
-
1
-
1
A
ICC
supply current
VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
2.0
-
20
-
40
A
ICC
additional
supply current
per input pin;
VI = VCC 2.1 V; IO = 0 A;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V
-
150
540
-
675
-
735
A
CI
input
capacitance
-
3.5
-
-
-
-
-
pF
VOL
IO = 20 A; VCC = 4.5 V
10. Dynamic characteristics
Table 7.
Dynamic characteristics
GND = 0 V; CL = 50 pF; for test circuit see Figure 7.
Symbol Parameter
25 C
Conditions
40 C to +125 C Unit
Min
Typ
Max
Max
(85 C)
Max
(125 C)
VCC = 2.0 V
-
30
95
120
145
ns
VCC = 4.5 V
-
11
19
24
29
ns
VCC = 5.0 V; CL = 15 pF
-
9
-
-
-
ns
VCC = 6.0 V
-
9
16
20
25
ns
VCC = 2.0 V
-
19
75
95
110
ns
VCC = 4.5 V
-
7
15
19
22
ns
VCC = 6.0 V
-
6
13
16
19
ns
-
12
-
-
-
pF
74HC10-Q100
tpd
tt
CPD
propagation delay nA, nB to nY; see Figure 6
transition time
power dissipation
capacitance
74HC_HCT10_Q100
Product data sheet
[1]
[2]
see Figure 6
per package; VI = GND to VCC
[3]
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 February 2013
©
Nexperia B.V. 2017. All rights reserved
5 of 13
74HC10-Q100; 74HCT10-Q100
Nexperia
Triple 3-input NAND gate
Table 7.
Dynamic characteristics
GND = 0 V; CL = 50 pF; for test circuit see Figure 7.
Symbol Parameter
25 C
Conditions
40 C to +125 C Unit
Min
Typ
Max
Max
(85 C)
Max
(125 C)
-
14
24
30
36
ns
-
11
-
-
-
ns
74HCT10-Q100
[1]
propagation delay nA, nB to nY; see Figure 6
tpd
VCC = 4.5 V
VCC = 5.0 V; CL = 15 pF
tt
transition time
VCC = 4.5 V; see Figure 6
[2]
CPD
power dissipation
capacitance
per package;
VI = GND to VCC 1.5 V
[3]
[1]
-
7
15
19
22
ns
-
14
-
-
-
pF
tpd is the same as tPHL and tPLH.
[2]
tt is the same as tTHL and tTLH.
[3]
CPD is used to determine the dynamic power dissipation (PD in W):
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of outputs.
11. Waveform and test circuit
9O
Q$Q%Q&LQSXW
90
*1'
W3+/
92+
W3/+
9<
90
9;
Q
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