74HC2G00DC-Q100H

74HC2G00-Q100; 74HCT2G00-Q100 Dual 2-input NAND gate Rev. 2 — 20 November 2018 Product data sheet 1. General description The 74HC2G00-Q100; 74HCT2G00-Q100 is a dual 2-input NAND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits • • • • • • • • Automotive product qualification in accordance with AEC-Q100 (Grade 1) • Specified from -40 °C to +85 °C and from -40 °C to +125 °C Wide supply voltage range from 2.0 V to 6.0 V Input levels: • For 74HC2G00-Q100: CMOS level • For 74HCT2G00-Q100: TTL level Symmetrical output impedance High noise immunity Low power dissipation Balanced propagation delays ESD protection: • MIL-STD-883, method 3015 exceeds 2000 V • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-A exceeds 200 V (C = 200 pF; R = 0 Ω) 3. Ordering information Table 1. Ordering information Type number Package 74HC2G00DP-Q100 Temperature range Name Description Version -40 °C to +125 °C TSSOP8 plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2 -40 °C to +125 °C VSSOP8 plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1 74HCT2G00DP-Q100 74HC2G00DC-Q100 74HCT2G00DC-Q100 Nexperia 74HC2G00-Q100; 74HCT2G00-Q100 Dual 2-input NAND gate 4. Marking Table 2. Marking code Type number Marking code[1] 74HC2G00DP-Q100 H00 74HCT2G00DP-Q100 T00 74HC2G00DC-Q100 H00 74HCT2G00DC-Q100 T00 [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 1 1 1A 2 1B 5 2A 6 2B 1Y 7 2Y 3 2 5 6 mna712 Fig. 1. Logic symbol & 7 B & 3 Y A mna713 Fig. 2. IEC logic symbol Fig. 3. mna099 Logic diagram (one driver) 6. Pinning information 6.1. Pinning 74HC2G00 74HCT2G00 1A 1 8 VCC 1B 2 7 1Y 2Y 3 6 2B GND 4 5 2A 001aai255 Fig. 4. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8) 6.2. Pin description Table 3. Pin description Symbol Pin Description 1A, 2A 1, 5 data input 1B, 2B 2, 6 data input GND 4 ground (0 V) 1Y, 2Y 7, 3 data output VCC 8 supply voltage 74HC_HCT2G00_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 20 November 2018 © Nexperia B.V. 2018. All rights reserved 2 / 11 Nexperia 74HC2G00-Q100; 74HCT2G00-Q100 Dual 2-input NAND gate 7. Functional description Table 4. Function table H = HIGH voltage level; L = LOW voltage level. Output Input nA nB nY L L H L H H H L H H H L 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current VI < -0.5 V or VI > VCC + 0.5 V IOK output clamping current IO output current ICC supply current IGND ground current Tstg storage temperature PD dynamic power dissipation [1] [2] Conditions Min Max Unit -0.5 +7.0 V [1] - ±20 mA VO < -0.5 V or VO > VCC + 0.5 V [1] - ±20 mA VO = -0.5 V to (VCC + 0.5 V) [1] - 25 mA [1] - 50 mA [1] -50 - mA -65 +150 °C - 300 mW Tamb = -40 °C to +125 °C [2] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For TSSOP8 package: above 55 °C the value of Ptot derates linearly with 2.5 mW/K. For VSSOP8 package: above 110 °C the value of Ptot derates linearly with 8 mW/K. 9. Recommended operating conditions Table 6. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 74HC2G00-Q100 74HCT2G00-Q100 Unit Min Typ Max Min Typ Max 2.0 5.0 6.0 4.5 5.0 5.5 V VCC supply voltage VI input voltage 0 - VCC 0 - VCC V VO output voltage 0 - VCC 0 - VCC V Tamb ambient temperature -40 +25 +125 -40 +25 +125 °C Δt/ΔV input transition rise and VCC = 2.0 V fall rate VCC = 4.5 V - - 625 - - - ns/V - 1.67 139 - 1.67 139 ns/V VCC = 6.0 V - - 83 - - - ns/V 74HC_HCT2G00_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 20 November 2018 © Nexperia B.V. 2018. All rights reserved 3 / 11 Nexperia 74HC2G00-Q100; 74HCT2G00-Q100 Dual 2-input NAND gate 10. Static characteristics Table 7. Static characteristics Voltages are referenced to GND (ground = 0 V). All typical values are measured at Tamb = 25 °C. Symbol Parameter Conditions -40 °C to +85 °C Min Typ Max VCC = 2.0 V 1.5 1.2 VCC = 4.5 V 3.15 2.4 VCC = 6.0 V 4.2 VCC = 2.0 V -40 °C to +125 °C Unit Min Max - 1.5 - V - 3.15 - V 3.2 - 4.2 - V - 0.8 0.5 - 0.5 V VCC = 4.5 V - 2.1 1.35 - 1.35 V VCC = 6.0 V - 2.8 1.8 - 1.8 V IO = -20 μA; VCC = 2.0 V 1.9 2.0 - 1.9 - V IO = -20 μA; VCC = 4.5 V 4.4 4.5 - 4.4 - V IO = -20 μA; VCC = 6.0 V 5.9 6.0 - 5.9 - V IO = -4.0 mA; VCC = 4.5 V 4.13 4.32 - 3.7 - V IO = -5.2 mA; VCC = 6.0 V 5.63 5.81 - 5.2 - V IO = 20 μA; VCC = 2.0 V - 0 0.1 - 0.1 V IO = 20 μA; VCC = 4.5 V - 0 0.1 - 0.1 V IO = 20 μA; VCC = 6.0 V - 0 0.1 - 0.1 V IO = 4.0 mA; VCC = 4.5 V - 0.15 0.33 - 0.4 V IO = 5.2 mA; VCC = 6.0 V - 0.16 0.33 - 0.4 V 74HC2G00-Q100 VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VI = VIH or VIL VI = VIH or VIL II input leakage current VI = VCC or GND; VCC = 6.0 V - - ±1.0 - ±1.0 μA ICC supply current per input pin; VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 10 - 20 μA CI input capacitance - 1.5 - - - pF 74HCT2G00-Q100 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 V VOH HIGH-level output voltage VI = VIH or VIL IO = -20 μA; VCC = 4.5 V 4.4 4.5 - 4.4 - V IO = -4.0 mA; VCC = 4.5 V 4.13 4.32 - 3.7 - V LOW-level output voltage VI = VIH or VIL IO = 20 μA; VCC = 4.5 V - 0 0.1 - 0.1 V IO = 4.0 mA; VCC = 4.5 V - 0.15 0.33 - 0.4 V VOL II input leakage current VI = VCC or GND; VCC = 5.5 V - - ±1.0 - ±1.0 μA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 10 - 20 μA ΔICC additional supply current per input; VCC = 4.5 V to 5.5 V; VI = VCC - 2.1 V; IO = 0 A - - 375 - 410 μA CI input capacitance - 1.5 - - - pF 74HC_HCT2G00_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 20 November 2018 © Nexperia B.V. 2018. All rights reserved 4 / 11 Nexperia 74HC2G00-Q100; 74HCT2G00-Q100 Dual 2-input NAND gate 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); all typical values are measured at Tamb = 25 °C; for test circuit see Fig. 6. Symbol Parameter Conditions -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max VCC = 2.0 V - 25 95 - 110 ns VCC = 4.5 V - 9 19 - 22 ns VCC = 6.0 V - 7 16 - 20 ns VCC = 2.0 V - 18 95 - 125 ns VCC = 4.5 V - 6 19 - 25 ns VCC = 6.0 V - 5 16 - 20 ns - 10 - - - pF - 12 24 - 29 ns [2] - 6 19 - 22 ns [3] - 10 - - - pF 74HC2G00-Q100 tpd tt CPD propagation delay nA and nB to nY; see Fig. 5 transition time see Fig. 5 [1] [2] power dissipation VI = GND to VCC capacitance [3] 74HCT2G00-Q100 tpd propagation delay nA and nB to nY; see Fig. 5 [1] VCC = 4.5 V tt transition time CPD power dissipation VI = GND to VCC - 1.5 V capacitance [1] [2] [3] VCC = 4.5 V; see Fig. 5 tpd is the same as tPLH and tPHL. tt is the same as tTLH and tTHL. CPD is used to determine the dynamic power dissipation (PD in μW). 2 2 PD = CPD x VCC x fi x N + Σ(CL x VCC x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; 2 Σ(CL x VCC x fo) = sum of outputs. 74HC_HCT2G00_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 20 November 2018 © Nexperia B.V. 2018. All rights reserved 5 / 11 Nexperia 74HC2G00-Q100; 74HCT2G00-Q100 Dual 2-input NAND gate 11.1. Waveforms and test circuit VI VM nA, nB input VM GND tPHL tPLH VOH 90% VM VM nY output 10% VOL tTHL tTLH 001aae759 Measurement points are given in Table 9. VOL and VOH are typical output voltage levels that occur with the output load. Fig. 5. Propagation delay data input (nA, nB) to data output (nY) and transition time output (nY) Table 9. Measurement points Type Input Output VM VM 74HC2G00-Q100 0.5 x VCC 0.5 x VCC 74HCT2G00-Q100 1.3 V 1.3 V VI negative pulse tW 90 % VM 0V VI positive pulse 0V VM 10 % tf tr tr tf 90 % VM VM 10 % tW VCC VI G DUT RT VCC VO RL S1 open CL 001aad983 Test data is given in Table 10. Definitions for test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator; CL = Load capacitance including jig and probe capacitance; RL = Load resistance; S1 = Test selection switch. Fig. 6. Test circuit for measuring switching times Table 10. Test data Type Input S1 position Load VI tr, tf CL RL tPHL, tPLH VCC ≤ 6 ns 50 pF 1 kΩ open 74HCT2G00-Q100 3 V ≤ 6 ns 50 pF 1 kΩ open 74HC2G00-Q100 74HC_HCT2G00_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 20 November 2018 © Nexperia B.V. 2018. All rights reserved 6 / 11 Nexperia 74HC2G00-Q100; 74HCT2G00-Q100 Dual 2-input NAND gate 12. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm D E A SOT505-2 X c HE y v M A Z 5 8 A A2 pin 1 index (A3) A1 θ Lp L 1 4 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(1) e HE L Lp v w y Z(1) θ mm 1.1 0.15 0.00 0.95 0.75 0.25 0.38 0.22 0.18 0.08 3.1 2.9 3.1 2.9 0.65 4.1 3.9 0.5 0.47 0.33 0.2 0.13 0.1 0.70 0.35 8° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT505-2 Fig. 7. REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 02-01-16 --- Package outline SOT505-2 (TSSOP8) 74HC_HCT2G00_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 20 November 2018 © Nexperia B.V. 2018. All rights reserved 7 / 11 Nexperia 74HC2G00-Q100; 74HCT2G00-Q100 Dual 2-input NAND gate VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm D SOT765-1 E A X c y HE v A Z 5 8 Q A A2 A1 pin 1 index (A3) θ Lp 1 detail X 4 e L w bp 0 5 mm scale Dimensions (mm are the original dimensions) Unit mm A max. max nom min 1 A1 A2 0.15 0.85 0.00 0.60 A3 0.12 D(1) E(2) 0.27 0.23 2.1 2.4 0.17 0.08 1.9 2.2 bp c e HE 0.5 3.2 3.0 L 0.4 Lp Q 0.40 0.21 0.15 0.19 v w y 0.2 0.08 0.1 Z(1) θ 0.4 8° 0.1 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. Outline version SOT765-1 Fig. 8. References IEC JEDEC JEITA sot765-1_po European projection Issue date 07-06-02 16-05-31 MO-187 Package outline SOT765-1 (VSSOP8) 74HC_HCT2G00_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 20 November 2018 © Nexperia B.V. 2018. All rights reserved 8 / 11 Nexperia 74HC2G00-Q100; 74HCT2G00-Q100 Dual 2-input NAND gate 13. Abbreviations Table 11. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor ESD ElectroStatic Discharge HBM Human Body Model MIL Military MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT2G00_Q100 v.2 20181120 Product data sheet - 74HC_HCT2G00_Q100 v.1 Modifications: • • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. 74HC_HCT2G00_Q100 v.1 20131107 74HC_HCT2G00_Q100 Product data sheet Product data sheet - All information provided in this document is subject to legal disclaimers. Rev. 2 — 20 November 2018 - © Nexperia B.V. 2018. All rights reserved 9 / 11 Nexperia 74HC2G00-Q100; 74HCT2G00-Q100 Dual 2-input NAND gate equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. 15. Legal information Data sheet status Document status [1][2] Product status [3] Definition Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Objective [short] data sheet Development This document contains data from the objective specification for product development. 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This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications — This Nexperia product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or 74HC_HCT2G00_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 20 November 2018 © Nexperia B.V. 2018. All rights reserved 10 / 11 Nexperia 74HC2G00-Q100; 74HCT2G00-Q100 Dual 2-input NAND gate Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................1 4. Marking.......................................................................... 2 5. Functional diagram.......................................................2 6. Pinning information......................................................2 6.1. Pinning.........................................................................2 6.2. Pin description............................................................. 2 7. Functional description................................................. 3 8. Limiting values............................................................. 3 9. Recommended operating conditions..........................3 10. Static characteristics..................................................4 11. Dynamic characteristics.............................................5 11.1. Waveforms and test circuit........................................ 6 12. Package outline.......................................................... 7 13. Abbreviations.............................................................. 9 14. Revision history..........................................................9 15. Legal information......................................................10 © Nexperia B.V. 2018. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 20 November 2018 74HC_HCT2G00_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 20 November 2018 © Nexperia B.V. 2018. All rights reserved 11 / 11