74HC4020D-Q100J

74HC4020-Q100; 74HCT4020-Q100 14-stage binary ripple counter Rev. 2 — 18 June 2020 Product data sheet 1. General description The 74HC4020-Q100; 74HCT4020-Q100 is a 14-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and 12 buffered parallel outputs (Q0, and Q3 to Q13). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP. Each counter stage is a static toggle flip-flop. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits • • • • • • • • • • Automotive product qualification in accordance with AEC-Q100 (Grade 1) • Specified from -40 °C to +85 °C and from -40 °C to +125 °C Wide supply voltage range from 2.0 V to 6.0 V CMOS low power dissipation High noise immunity Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Complies with JEDEC standards: • JESD8C (2.7 V to 3.6 V) • JESD7A (2.0 V to 6.0 V) Input levels: • For 74HC4020-Q100: CMOS level • For 74HCT4020-Q100: TTL level ESD protection: • MIL-STD-883, method 3015 exceeds 2000 V • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω) Multiple package options DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints 3. Applications • • • Frequency dividing circuits Time delay circuits Control counters Nexperia 74HC4020-Q100; 74HCT4020-Q100 14-stage binary ripple counter 4. Ordering information Table 1. Ordering information Type number Package 74HC4020D-Q100 Temperature range Name Description Version -40 °C to +125 °C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 -40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 -40 °C to +125 °C DHVQFN16 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 × 3.5 × 0.85 mm 74HCT4020D-Q100 74HC4020PW-Q100 74HCT4020PW-Q100 74HC4020BQ-Q100 74HCT4020BQ-Q100 SOT763-1 5. Functional diagram CP MR 10 11 T 14-STAGE COUNTER CD 9 7 5 4 6 13 12 14 15 1 2 3 Q0 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 001aal201 Fig. 1. Functional diagram 10 11 CP MR 9 10 + Q3 7 11 CT = 0 Q4 5 5 Q5 4 4 Q6 6 6 Q7 13 Q8 12 Q9 14 14 Q10 15 15 Q11 1 1 Q12 2 Q13 3 Logic symbol 74HC_HCT4020_Q100 Product data sheet 0 9 7 13 CT 12 2 13 3 001aal203 001aal202 Fig. 2. CTR14 Q0 Fig. 3. IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 June 2020 © Nexperia B.V. 2020. All rights reserved 2 / 16 Nexperia 74HC4020-Q100; 74HCT4020-Q100 14-stage binary ripple counter FF T 1 CP RD Q Q FF T 2 Q Q RD FF T 3 RD Q FF T 4 Q RD Q Q FF T 6 Q RD Q MR Q0 Q3 Q13 001aal204 Fig. 4. Logic diagram 6. Pinning information 6.1. Pinning 1 terminal 1 index area Q12 2 15 Q10 Q13 3 14 Q9 Q5 4 13 Q7 Q4 5 12 Q8 Q6 6 11 MR Q3 7 10 CP GND 8 9 3 14 Q9 Q5 4 13 Q7 Q4 5 12 Q8 Q6 6 Q3 7 VCC(1) 11 MR 10 CP 001aal206 Transparent top view (1) This is not a supply pin. There is no electrical or mechanical requirement to solder the pad. In case soldered, the solder land should remain floating or connected to VCC. Q0 001aal205 Fig. 5. Q13 9 16 VCC 15 Q10 Q0 1 2 8 Q11 Q12 GND 74HC4020 74HCT4020 16 VCC Q11 74HC4020 74HCT4020 Pin configuration SOT109-1 (SO16) and SOT403-1 (TSSOP16) Fig. 6. Pin configuration SOT763-1 (DHVQFN16) 6.2. Pin description Table 2. Pin description Symbol Pin Description Q0, Q3 to Q13 9, 7, 5, 4, 6, 13, 12, 14, 15, 1, 2, 3 output GND 8 ground (0 V) CP 10 clock input (HIGH-to-LOW, edge-triggered) MR 11 master reset input (active HIGH) VCC 16 positive supply voltage 74HC_HCT4020_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 June 2020 © Nexperia B.V. 2020. All rights reserved 3 / 16 Nexperia 74HC4020-Q100; 74HCT4020-Q100 14-stage binary ripple counter 7. Functional description Table 3. Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = LOW-to-HIGH clock transition; ↓ = HIGH-to-LOW clock transition. Output Input CP MR Q0, Q3 to Q13 ↑ L no change ↓ L count X H L 7.1. Timing diagram CP input 1 2 4 8 16 32 64 128 256 512 1024 2048 4096 8192 16384 MR input Q0 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 001aal207 Fig. 7. Timing diagram 74HC_HCT4020_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 June 2020 © Nexperia B.V. 2020. All rights reserved 4 / 16 Nexperia 74HC4020-Q100; 74HCT4020-Q100 14-stage binary ripple counter 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Min Max VCC supply voltage -0.5 +7 V IIK input clamping current VI < -0.5 V or VI > VCC + 0.5 V - ±20 mA IOK IO output clamping current VI < -0.5 V or VI > VCC + 0.5 V - ±20 mA output current -0.5 V < VO < VCC + 0.5 V - ±25 mA ICC supply current - ±50 mA IGND ground current - ±50 mA Tstg storage temperature -65 +150 °C Ptot total power dissipation - 500 mW [1] Conditions Tamb = -40 °C to +125 °C [1] Unit For SOT109-1 (SO16) package: Ptot derates linearly with 12.4 mW/K above 110 °C. For SOT403-1 (TSSOP16) package: Ptot derates linearly with 8.5 mW/K above 91 °C. For SOT763-1 (DHVQFN16) package: Ptot derates linearly with 11.2 mW/K above 106 °C. 9. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions 74HC4020-Q100 74HCT4020-Q100 Unit Min Typ Max Min Typ Max 2.0 5.0 6.0 4.5 5.0 5.5 V VCC supply voltage VI input voltage 0 - VCC 0 - VCC V VO output voltage 0 - VCC 0 - VCC V Δt/ΔV input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V - ns/V except for Schmitt trigger inputs VCC = 6.0 V Tamb ambient temperature 74HC_HCT4020_Q100 Product data sheet - - 83 - - -40 +25 +125 -40 +25 All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 June 2020 © +125 °C Nexperia B.V. 2020. All rights reserved 5 / 16 Nexperia 74HC4020-Q100; 74HCT4020-Q100 14-stage binary ripple counter 10. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max VCC = 2.0 V 1.5 1.2 VCC = 4.5 V 3.15 2.4 - 1.5 - 3.15 - 1.5 - V - 3.15 - V VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V 74HC4020-Q100 VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V VI = VIH or VIL HIGH-level output voltage IO = -20 μA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = -20 μA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = -20 μA; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V IO = -4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V IO = -5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V VI = VIH or VIL LOW-level output voltage IO = 20 μA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 20 μA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 20 μA; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V - - ±0.1 - ±1 - ±1 μA II input leakage current ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 8.0 - 80 - 160 μA CI input capacitance - 3.5 - - - - - pF 74HC_HCT4020_Q100 Product data sheet VI = VCC or GND; VCC = 6.0 V All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 June 2020 © Nexperia B.V. 2020. All rights reserved 6 / 16 Nexperia 74HC4020-Q100; 74HCT4020-Q100 14-stage binary ripple counter Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max 74HCT4020-Q100 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V VOH VI = VIH or VIL; VCC = 4.5 V HIGH-level output voltage IO = -20 μA 4.4 4.5 - 4.4 - 4.4 - V 3.98 4.32 - 3.84 - 3.7 - V - 0 0.1 - 0.1 - 0.1 V - 0.15 0.26 - 0.33 - 0.4 V - - ±0.1 - ±1 - ±1 μA - - 8.0 - 80 - 160 μA pin MR - 110 396 - 495 - 539 μA pin CP - 85 306 - 383 - 417 μA - 3.5 - - - - - pF IO = -4.0 mA VOL VI = VIH or VIL; VCC = 4.5 V LOW-level output voltage IO = 20 μA; VCC = 4.5 V IO = 4.0 mA; VCC = 4.5 V II input leakage current ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V ΔICC VI = VCC - 2.1 V; IO = 0 A; additional supply current other inputs at VCC or GND; VCC = 4.5 V to 5.5 V CI VI = VCC or GND; VCC = 5.5 V input capacitance 11. Dynamic characteristics Table 7. Dynamic characteristics GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Fig. 10 Symbol Parameter Conditions 25 °C Min -40 °C to +85 °C -40 °C to +125 °C Unit Typ Max Min Max Min Max 74HC4020-Q100 tpd propagation delay CP to Q0; see Fig. 8 [1] VCC = 2.0 V - 39 140 - 175 - 210 ns VCC = 4.5 V - 14 28 - 35 - 42 ns VCC = 5.0 V; CL = 15 pF - 11 - - - - - ns VCC = 6.0 V - 11 24 - 30 - 36 ns VCC = 2.0 V - 22 75 - 95 - 110 ns VCC = 4.5 V - 8 15 - 19 - 22 ns VCC = 5.0 V; CL = 15 pF - 6 - - - - - ns VCC = 6.0 V - 6 13 - 16 - 19 ns - 55 170 - 215 - 225 ns - 20 34 - 43 - 51 ns VCC = 5.0 V; CL = 15 pF - 17 - - - - - ns VCC = 6.0 V - 16 29 - 37 - 43 ns Qn to Qn+1; see Fig. 9 tPHL HIGH to LOW MR to Qn; see Fig. 8 propagation VCC = 2.0 V delay VCC = 4.5 V 74HC_HCT4020_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 June 2020 © Nexperia B.V. 2020. All rights reserved 7 / 16 Nexperia 74HC4020-Q100; 74HCT4020-Q100 14-stage binary ripple counter Symbol Parameter Conditions 25 °C Min tt tW transition time Qn; see Fig. 8 -40 °C to +85 °C -40 °C to +125 °C Unit Typ Max Min Max Min Max [2] VCC = 2.0 V - 19 75 - 95 - 110 ns VCC = 4.5 V - 7 15 - 19 - 22 ns VCC = 6.0 V - 6 13 - 16 - 19 ns VCC = 2.0 V 80 14 - 100 - 120 - ns VCC = 4.5 V 16 4 - 20 - 24 - ns VCC = 6.0 V 14 3 - 17 - 20 - ns VCC = 2.0 V 80 17 - 100 - 120 - ns VCC = 4.5 V 16 6 - 20 - 24 - ns VCC = 6.0 V 14 5 - 17 - 20 - ns VCC = 2.0 V 50 6 - 65 - 75 - ns VCC = 4.5 V 10 2 - 13 - 15 - ns VCC = 6.0 V 9 2 - 11 - 13 - ns VCC = 2.0 V 6.0 30 - 4.8 - 4.0 - MHz VCC = 4.5 V 30 92 - 24 - 20 - MHz - 101 - - - - - MHz 35 109 - 28 - 24 - MHz - 19 - - - - - pF VCC = 4.5 V - 18 36 - 45 - 54 ns VCC = 5.0 V; CL = 15 pF - 15 - - - - - ns VCC = 4.5 V - 8 15 - 19 - 22 ns VCC = 5.0 V; CL = 15 pF - 6 - - - - - ns HIGH to LOW MR to Qn; see Fig. 8 propagation VCC = 4.5 V delay VCC = 5.0 V; CL = 15 pF - 22 45 - 56 - 68 ns - 19 - - - - - ns - 7 15 - 19 - 22 ns 20 7 - 25 - 30 - ns 20 8 - 25 - 30 - ns 10 2 - 13 - 15 - ns pulse width CP HIGH or LOW; see Fig. 8 MR HIGH; see Fig. 8 trec fmax recovery time MR to CP; see Fig. 8 maximum frequency see Fig. 8 VCC = 5.0 V; CL = 15 pF VCC = 6.0 V CPD power dissipation capacitance [3] 74HCT4020-Q100 tpd propagation delay CP to Q0; see Fig. 8 [1] Qn to Qn+1; see Fig. 9 tPHL tt transition time Qn; see Fig. 8 tW pulse width [2] VCC = 4.5 V CP HIGH or LOW; see Fig. 8 VCC = 4.5 V MR HIGH; see Fig. 8 VCC = 4.5 V trec recovery time MR to CP; see Fig. 8 VCC = 4.5 V 74HC_HCT4020_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 June 2020 © Nexperia B.V. 2020. All rights reserved 8 / 16 Nexperia 74HC4020-Q100; 74HCT4020-Q100 14-stage binary ripple counter Symbol Parameter Conditions 25 °C Min fmax maximum frequency [1] [2] [3] Typ Max Min Max Min Max see Fig. 8 VCC = 4.5 V VCC = 5.0 V; CL = 15 pF CPD -40 °C to +85 °C -40 °C to +125 °C Unit power dissipation capacitance [3] 25 47 - 20 - 17 - MHz - 52 - - - - - MHz - 20 - - - - - pF tpd is the same as tPHL and tPLH. tt is the same as tTHL and tTLH. CPD is used to determine the dynamic power dissipation (PD in μW). 2 2 PD = CPD x VCC x fi + Σ (CL x VCC x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; 2 Σ (CL x VCC x fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in V. 11.1. Waveforms and test circuit VI VM MR input tW trec VI 1/fmax VM CP input tPHL Q0 or Qn output tPLH 90 % tW tPHL 90 % 10 % VM 10 % tTLH tTHL 001aad590 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 8. Clock timing, propagation delays and pulse widths 74HC_HCT4020_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 June 2020 © Nexperia B.V. 2020. All rights reserved 9 / 16 Nexperia 74HC4020-Q100; 74HCT4020-Q100 14-stage binary ripple counter VOH Qn output VM VOL tPLH VOH tPHL VM Qn+1 output VOL 001aai120 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 9. Waveforms showing the output Qn to output Qn+1 propagation delays Table 8. Measurement points Type Input Output VM VM 74HC4020-Q100 0.5 x VCC 0.5 x VCC 74HCT4020-Q100 1.3 V 1.3 V VI negative pulse VM VI GND VM 10 % GND positive pulse tW 90 % tf tr tr tf 90 % VM VM 10 % tW VCC G VI DUT VO RT CL 001aah768 Test data is given in Table 9. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. Fig. 10. Test circuit for measuring switching times Table 9. Test data Type Load Input VI tr, tf CL 74HC4020-Q100 VCC 6 ns 15 pF, 50 pF 74HCT4020-Q100 3V 6 ns 15 pF, 50 pF 74HC_HCT4020_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 June 2020 © Nexperia B.V. 2020. All rights reserved 10 / 16 Nexperia 74HC4020-Q100; 74HCT4020-Q100 14-stage binary ripple counter 12. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e w M bp 0 2.5 detail X 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 inches 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.16 0.15 0.05 0.039 0.016 0.028 0.020 0.01 0.01 0.004 0.028 0.012 0.244 0.041 0.228 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig. 11. Package outline SOT109-1 (SO16) 74HC_HCT4020_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 June 2020 © Nexperia B.V. 2020. All rights reserved 11 / 16 Nexperia 74HC4020-Q100; 74HCT4020-Q100 14-stage binary ripple counter TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm D SOT403-1 E A X c y HE v M A Z 9 16 Q A2 pin 1 index (A 3 ) A1 A θ Lp 1 L 8 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig. 12. Package outline SOT403-1 (TSSOP16) 74HC_HCT4020_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 June 2020 © Nexperia B.V. 2020. All rights reserved 12 / 16 Nexperia 74HC4020-Q100; 74HCT4020-Q100 14-stage binary ripple counter DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT763-1 16 terminals; body 2.5 x 3.5 x 0.85 mm B D A A E A1 c detail X terminal 1 index area terminal 1 index area C e1 e b 2 7 y y1 C v M C A B w M C L 1 8 Eh e 16 9 15 10 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b c D (1) Dh E (1) Eh e e1 L v w y y1 mm 1 0.05 0.00 0.30 0.18 0.2 3.6 3.4 2.15 1.85 2.6 2.4 1.15 0.85 0.5 2.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT763-1 --- MO-241 --- EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig. 13. Package outline SOT763-1 (DHVQFN16) 74HC_HCT4020_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 June 2020 © Nexperia B.V. 2020. All rights reserved 13 / 16 Nexperia 74HC4020-Q100; 74HCT4020-Q100 14-stage binary ripple counter 13. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MIL Military MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT4020_Q100 v.2 20200618 Product data sheet - 74HC_HCT4020_Q100 v.1 Modifications: • • • • 74HC_HCT4020_Q100 v.1 74HC_HCT4020_Q100 Product data sheet The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Section 1 and Section 2 updated. Table 4: Derating values for Ptot total power dissipation have been updated. 20130523 Product data sheet - All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 June 2020 - © Nexperia B.V. 2020. All rights reserved 14 / 16 Nexperia 74HC4020-Q100; 74HCT4020-Q100 14-stage binary ripple counter equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. 15. 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Notwithstanding any damages that customer might incur for any reason whatsoever, Nexperia’s aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of Nexperia. Right to make changes — Nexperia reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications — This Nexperia product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or 74HC_HCT4020_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 June 2020 © Nexperia B.V. 2020. All rights reserved 15 / 16 Nexperia 74HC4020-Q100; 74HCT4020-Q100 14-stage binary ripple counter Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Applications.................................................................. 1 4. Ordering information....................................................2 5. Functional diagram.......................................................2 6. Pinning information......................................................3 6.1. Pinning.........................................................................3 6.2. Pin description............................................................. 3 7. Functional description................................................. 4 7.1. Timing diagram............................................................ 4 8. Limiting values............................................................. 5 9. Recommended operating conditions..........................5 10. Static characteristics..................................................6 11. Dynamic characteristics.............................................7 11.1. Waveforms and test circuit........................................ 9 12. Package outline........................................................ 11 13. Abbreviations............................................................ 14 14. Revision history........................................................14 15. Legal information......................................................15 © Nexperia B.V. 2020. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 18 June 2020 74HC_HCT4020_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 18 June 2020 © Nexperia B.V. 2020. All rights reserved 16 / 16