74LVC245ADB,118

INTEGRATED CIRCUITS DATA SHEET 74LVC245A; 74LVCH245A Octal bus transceiver with direction pin with 5 V tolerant input/outputs (3-state) Product specification Supersedes data of 2002 Jun 20 2003 May 07 Philips Semiconductors Product specification Octal bus transceiver with direction pin with 5 V tolerant input/outputs (3-state) 74LVC245A; 74LVCH245A FEATURES DESCRIPTION • 5 V tolerant inputs/outputs for interfacing with 5 V logic The 74LVC245A/74LVCH245A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. • Wide supply voltage range from 1.2 to 3.6 V • CMOS low power consumption Inputs can be driven from either 3.3 or 5 V devices. In 3-state operation outputs can handle 5 V. These features allow the use of these devices as translators in a mixed 3.3 and 5 V environment. • Direct interface with TTL levels • Inputs accept voltages up to 5.5 V • High-impedance when VCC = 0 V • bus-hold on all data inputs (74LVCH245A only) The 74LVC245A/74LVCH245A is an octal transceiver with non-inverting 3-state bus compatible outputs in both send and receive directions. • Complies with JEDEC standard no. 8-1A • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V The 74LVC245A/74LVCH245A has an output enable (OE) input for easy cascading and a send/receive (DIR) input for direction control. OE controls the outputs so that the buses are effectively isolated. • Specified from −40 to +85 °C and −40 to +125 °C. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns. SYMBOL PARAMETER CONDITIONS TYPICAL UNIT tPHL/tPLH propagation delay An to Bn, Bn to An 2.9 ns CI input capacitance 4.0 pF CI/O input/output capacitance 10.0 pF CPD power dissipation capacitance per buffer 15 pF CL = 50 pF; VCC = 3.3 V VCC = 3.3 V; notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; Σ(CL × VCC2 × fo) = sum of the outputs. 2. The condition is VI = GND to VCC. 2003 May 07 2 Philips Semiconductors Product specification Octal bus transceiver with direction pin with 5 V tolerant input/outputs (3-state) 74LVC245A; 74LVCH245A ORDERING INFORMATION PACKAGE TYPE NUMBER TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE SO20 plastic SOT163-1 74LVC245AD −40 to +125 °C 20 74LVCH245AD −40 to +125 °C 20 SO20 plastic SOT163-1 74LVC245ADB −40 to +125 °C 20 SSOP20 plastic SOT339-1 74LVCH245ADB −40 to +125 °C 20 SSOP20 plastic SOT339-1 74LVC245APW −40 to +125 °C 20 TSSOP20 plastic SOT360-1 74LVCH245APW −40 to +125 °C 20 TSSOP20 plastic SOT360-1 74LVC245ABQ −40 to +125 °C 20 DHVQFN20 plastic SOT764-1 74LVCH245ABQ −40 to +125 °C 20 DHVQFN20 plastic SOT764-1 FUNCTION TABLE See note 1. INPUT INPUT/OUTPUT OE DIR An Bn L L A=B input L H input B=A H X Z Z Note 1. H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. PINNING PIN 1 PIN SYMBOL SYMBOL DESCRIPTION DESCRIPTION 11 B7 data input/output DIR direction control input 12 B6 data input/output 2 A0 data input/output 13 B5 data input/output 3 A1 data input/output 14 B4 data input/output 4 A2 data input/output 15 B3 data input/output 5 A3 data input/output 16 B2 data input/output 6 A4 data input/output 17 B1 data input/output 7 A5 data input/output 18 B0 data input/output 8 A6 data input/output 19 OE 9 A7 data input/output output enable input (active LOW) 10 GND ground (0 V) 20 VCC supply voltage 2003 May 07 3 Philips Semiconductors Product specification Octal bus transceiver with direction pin with 5 V tolerant input/outputs (3-state) handbook, halfpage handbook, halfpage 20 VCC DIR 1 A0 2 19 OE A1 3 18 B0 A2 4 17 B1 16 B2 A3 5 A4 6 245 14 B4 A6 8 13 B5 A7 9 12 B6 GND 10 11 B7 DIR VCC 1 20 A0 2 19 OE A1 3 18 B0 A2 4 17 B1 A3 5 16 B2 GND* 15 B3 A5 7 74LVC245A; 74LVCH245A MNA173 A4 6 15 B3 A5 7 14 B4 A6 8 13 B5 A7 9 12 B6 10 11 GND B7 MCE182 * The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig.1 Pin configuration SO20 and (T)SSOP20. 2003 May 07 Fig.2 Pin configuration DHVQFN20. 4 Philips Semiconductors Product specification Octal bus transceiver with direction pin with 5 V tolerant input/outputs (3-state) handbook, halfpage 1 74LVC245A; 74LVCH245A DIR OE 2 handbook, halfpage 19 1 B0 G3 3EN1 3EN2 3 2 2 4 18 3 17 4 16 5 15 6 14 7 13 8 12 9 11 18 A1 B1 1 19 A0 17 A2 B2 16 A3 5 B3 6 B4 7 13 A6 B6 MNA175 9 14 A5 B5 8 15 A4 12 A7 B7 11 MNA174 Fig.3 Logic symbol (IEEE/IEC). 2003 May 07 Fig.4 Logic symbol. 5 Philips Semiconductors Product specification Octal bus transceiver with direction pin with 5 V tolerant input/outputs (3-state) 74LVC245A; 74LVCH245A RECOMMENDED OPERATING CONDITIONS SYMBOL VCC PARAMETER supply voltage VI input voltage VO output voltage Tamb operating ambient temperature tr, tf input rise and fall times CONDITIONS MIN. MAX. UNIT for maximum speed performance 2.7 3.6 V for low-voltage applications 1.2 3.6 V 0 5.5 V output HIGH or LOW state 0 VCC V output 3-state 0 5.5 V −40 +125 °C VCC = 1.2 to 2.7 V 0 20 ns/V VCC = 2.7 to 3.6 V 0 10 ns/V LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCC supply voltage −0.5 +6.5 V IIK input diode current VI < 0 − −50 mA VI input voltage note 1 −0.5 +6.5 V IOK output diode current VO > VCC or VO < 0 − ±50 mA VO output voltage output HIGH or LOW state; note 1 −0.5 VCC + 0.5 V output 3-state; note 1 −0.5 +6.5 V VO = 0 to VCC IO output source or sink current − ±50 mA ICC, IGND VCC or GND current − ±100 mA Tstg storage temperature −65 +150 °C Ptot power dissipation − 500 mW Tamb = −40 to +125 °C; note 2 Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. For SO20 packages: above 70 °C derate linearly with 8 mW/K. For SSOP20 and TSSOP20 packages: above 60 °C derate linearly with 5.5 mW/K. For DHVQFN20 packages: above 60 °C derate linearly with 4.5 mW/K. 2003 May 07 6 Philips Semiconductors Product specification Octal bus transceiver with direction pin with 5 V tolerant input/outputs (3-state) 74LVC245A; 74LVCH245A DC CHARACTERISTICS At recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER MIN. OTHER TYP.(1) MAX. UNIT VCC (V) Tamb = −40 to +85 °C HIGH-level input voltage 1.2 VCC − − V 2.7 to 3.6 2.0 − − V VIL LOW-level input voltage 1.2 − − 0 V 2.7 to 3.6 − − 0.8 V VOH HIGH-level output voltage IO = −100 µA 2.7 to 3.6 VCC − 0.2 VCC − V IO = −12 mA 2.7 VCC − 0.5 − − V IO = −18 mA 3.0 VCC − 0.6 − − V IO = −24 mA 3.0 VCC − 0.8 − − V IO = 100 µA 2.7 to 3.6 − 0 0.2 V IO = 12 mA 2.7 − − 0.4 V IO = 24 mA 3.0 − − 0.55 V VIH VOL LOW-level output voltage VI = VIH or VIL VI = VIH or VIL ILI input leakage current VI = 5.5 V or GND; note 2 3.6 − ±0.1 ±5 µA IOZ 3-state output OFF-state current VI = VIH or VIL; VO = 5.5 V or GND; notes 2 and 3 3.6 − ±0.1 ±5 µA Ioff power off leakage supply VI or VO = 5.5 V 0.0 − ±0.1 ±10 µA ICC quiescent supply current VI = VCC or GND; IO = 0 3.6 − 0.1 10 µA ∆ICC additional quiescent supply current per pin VI = VCC − 0.6 V; IO = 0 2.7 to 3.6 − 5 500 µA IBH(L) bus-hold LOW sustaining current VI = 0.8 V; notes 4, 5 and 6 3.0 75 − − µA IBH(H) bus-hold HIGH sustaining current VI = 2.0 V; notes 4, 5 and 6 3.0 −75 − − µA IBH(LO) bus-hold LOW overdrive notes 4, 5 and 7 current 3.6 500 − − µA IBH(HO) bus-hold HIGH overdrive current 3.6 −500 − − µA 2003 May 07 notes 4, 5 and 7 7 Philips Semiconductors Product specification Octal bus transceiver with direction pin with 5 V tolerant input/outputs (3-state) TEST CONDITIONS SYMBOL PARAMETER MIN. OTHER 74LVC245A; 74LVCH245A TYP.(1) MAX. UNIT VCC (V) Tamb = −40 to +125 °C VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage 1.2 VCC − − V 2.7 to 3.6 2.0 − − V 1.2 − − 0 V 2.7 to 3.6 − − 0.8 V VI = VIH or VIL IO = −100 µA 2.7 to 3.6 VCC − 0.3 − − V IO = −12 mA 2.7 VCC − 0.65 − − V IO = −18 mA 3.0 VCC − 0.75 − − V IO = −24 mA 3.0 VCC − 1 − − V IO = 100 µA 2.7 to 3.6 − − 0.3 V IO = 12 mA 2.7 − − 0.6 V IO = 24 mA 3.0 − − 0.8 V VI = VIH or VIL ILI input leakage current VI = 5.5 V or GND; note 2 3.6 − − ±20 µA IOZ 3-state output OFF-state current VI = VIH or VIL; VO = 5.5 V or GND; notes 2 and 3 3.6 − − ±20 µA Ioff power off leakage supply VI or VO = 5.5 V 0.0 − − ±20 µA ICC quiescent supply current VI = VCC or GND; IO = 0 3.6 − − 40 µA ∆ICC additional quiescent supply current per in. pin VI = VCC − 0.6 V; IO = 0 2.7 to 3.6 − − 5000 µA IBH(L) bus-hold LOW sustaining current VI = 0.8 V; notes 4, 5 and 6 3.0 60 − − µA IBH(H) bus-hold HIGH sustaining current VI = 2.0 V; notes 4, 5 and 6 3.0 −60 − − µA IBH(LO) bus-hold LOW overdrive notes 4, 5 and 7 current 3.6 500 − − µA IBH(HO) bus-hold HIGH overdrive current 3.6 −500 − − µA notes 4, 5 and 7 Notes 1. All typical values are measured at VCC = 3.3 V and Tamb = 25 °C. 2. For bus-hold parts, the bus-hold circuit is switched off when VI > VCC allowing 5.5 V on the input terminal. 3. For I/O ports the parameter IOZ includes the input leakage current. 4. Valid for data inputs of bus-hold parts (74LVCH245A) only. 5. For data inputs only, control inputs do not have a bus-hold circuit. 6. The specified sustaining current at the data input holds the input below the specified VI level. 7. The specified overdrive current at the data input forces the data input to the opposite logic input state. 2003 May 07 8 Philips Semiconductors Product specification Octal bus transceiver with direction pin with 5 V tolerant input/outputs (3-state) 74LVC245A; 74LVCH245A AC CHARACTERISTICS GND = 0 V; tr = tf ≤ 2.5 ns. TEST CONDITIONS SYMBOL PARAMETER MIN. WAVEFORMS TYP. MAX. UNIT VCC (V) Tamb = −40 to +85 °C tPHL/tPLH tPZH/tPZL tPHZ/tPLZ tsk(0) propagation delay An to Bn, Bn to An 3-state output enable time OE to An, OE to Bn 3-state output disable time OE to An, OE to Bn skew − 17 − ns 2.7 1.5 3.4 7.3 ns 3.0 to 3.6 1.5 2.9(1) 6.3 ns − 22 − ns 2.7 1.5 5.0 9.5 ns 3.0 to 3.6 1.5 4.0(1) 8.5 ns − 12 − ns 2.7 1.5 3.6 8.0 ns 3.0 to 3.6 1.7 3.4(1) 7.0 ns note 2 − − 1.0 ns see Figs 5 and 7 1.2 − − − ns 1.5 − 9.5 ns see Figs 5 and 7 1.2 see Figs 6 and 7 1.2 see Figs 6 and 7 1.2 Tamb = −40 to +125 °C tPHL/tPLH propagation delay An to Bn, Bn to An 2.7 1.5 − 8.0 ns − − − ns 2.7 1.5 − 12.0 ns 3.0 to 3.6 1.5 − 11.0 ns 3.0 to 3.6 tPZH/tPZL tPHZ/tPLZ tsk(0) 3-state output enable time OE to An, OE to Bn 3-state output disable time OE to An, OE to Bn skew see Figs 6 and 7 1.2 − − − ns 2.7 1.5 − 10.0 ns 3.0 to 3.6 1.7 − 9.0 ns − − 1.5 ns see Figs 6 and 7 1.2 note 2 Notes 1. Typical values are measured at VCC = 3.3 V. 2. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. 2003 May 07 9 Philips Semiconductors Product specification Octal bus transceiver with direction pin with 5 V tolerant input/outputs (3-state) 74LVC245A; 74LVCH245A AC WAVEFORMS handbook, halfpage VI An, Bn input VM VM GND tPLH tPHL VOH VM VM Bn, An output VOL MNA176 VM = 1.5 V at VCC ≥ 2.7 V. VM = 0.5VCC at VCC < 2.7 V. VOL and VOH are typical output voltage drop that occur with the output load. Fig.5 The inputs An, Bn to outputs Bn, An propagation delays. VI handbook, full pagewidth nOE input VM GND tPLZ tPZL VCC output LOW-to-OFF OFF-to-LOW VM VX VOL tPHZ VOH tPZH VY output HIGH-to-OFF OFF-to-HIGH GND VM outputs enabled outputs disabled outputs enabled MNA362 VM = 1.5 V at VCC ≥ 2.7 V; VM = 0.5VCC at VCC < 2.7 V; VX = VOL + 0.3 V at VCC ≥ 2.7 V; VX = VOL + 0.1 V at VCC < 2.7 V; VY = VOH − 0.3 V at VCC ≥ 2.7 V; VY = VOH − 0.1 V at VCC < 2.7 V. VOL and VOH are typical output voltage drop that occur with the output load. Fig.6 3-state enable and disable times. 2003 May 07 10 Philips Semiconductors Product specification Octal bus transceiver with direction pin with 5 V tolerant input/outputs (3-state) S1 handbook, full pagewidth VCC PULSE GENERATOR VI RL 500 Ω VO 74LVC245A; 74LVCH245A 2 × VCC open GND D.U.T. CL 50 pF RT RL 500 Ω MNA368 SWITCH POSITION TEST SWITCH tPLH/tPHL open tPLZ/tPZL 2 x VCC tPHZ/tPZH GND VCC VI < 2.7 V VCC 2.7 - 3.6 V 2.7 V Definitions for test circuit: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. Fig.7 Load circuitry for switching times. 2003 May 07 11 Philips Semiconductors Product specification Octal bus transceiver with direction pin with 5 V tolerant input/outputs (3-state) 74LVC245A; 74LVCH245A PACKAGE OUTLINES SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c HE y v M A Z 11 20 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 10 e bp detail X w M 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.9 0.4 inches 0.1 0.012 0.096 0.004 0.089 0.01 0.019 0.013 0.014 0.009 0.51 0.49 0.30 0.29 0.05 0.419 0.043 0.055 0.394 0.016 0.043 0.039 0.01 0.01 0.004 0.035 0.016 Z (1) θ 8o 0o Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT163-1 075E04 MS-013 2003 May 07 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 12 Philips Semiconductors Product specification Octal bus transceiver with direction pin with 5 V tolerant input/outputs (3-state) 74LVC245A; 74LVCH245A SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm D SOT339-1 E A X c HE y v M A Z 20 11 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 10 bp e detail X w M 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 7.4 7.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 0.9 0.5 8 0o Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION SOT339-1 2003 May 07 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 13 o Philips Semiconductors Product specification Octal bus transceiver with direction pin with 5 V tolerant input/outputs (3-state) 74LVC245A; 74LVCH245A TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 E D A X c HE y v M A Z 11 20 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 10 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.5 0.2 8 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 2003 May 07 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 14 o Philips Semiconductors Product specification Octal bus transceiver with direction pin with 5 V tolerant input/outputs (3-state) 74LVC245A; 74LVCH245A DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT764-1 20 terminals; body 2.5 x 4.5 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 9 y y1 C v M C A B w M C b L 1 10 Eh e 20 11 19 12 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b c D (1) Dh E (1) Eh e e1 L v w y y1 mm 1 0.05 0.00 0.30 0.18 0.2 4.6 4.4 3.15 2.85 2.6 2.4 1.15 0.85 0.5 3.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT764-1 --- MO-241 --- 2003 May 07 15 EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Philips Semiconductors Product specification Octal bus transceiver with direction pin with 5 V tolerant input/outputs (3-state) If wave soldering is used the following conditions must be observed for optimal results: SOLDERING Introduction to soldering surface mount packages • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferably be kept: Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. • below 220 °C for all the BGA packages and packages with a thickness ≥ 2.5mm and packages with a thickness