74LVT08D,118

74LVT08 3.3 V Quad 2-input AND gate Rev. 3 — 22 March 2017 1 Product data sheet General description The 74LVT08 is a high-performance BiCMOS product designed for VCC operation at 3.3 V. The 74LVT08 is a quad 2-input AND gate. 2 Features and benefits • • • • Wide supply voltage range from 2.7 V to 3.6 V Output capability: +64 mA and -32 mA TTL input and output switching levels Latch-up protection – JESD78 Class II exceeds 500 mA • Complies with JEDEC standards: – JESD8C (2.7 V to 3.6 V) • ESD protection: – HBM JESD22-A114E exceeds 2000 V – MM JESD22-A115-A exceeds 200 V • Specified from -40 °C to 85 °C 3 Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVT08D -40 °C to +85 °C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 74LVT08DB -40 °C to +85 °C SSOP14 plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 74LVT08PW -40 °C to +85 °C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 74LVT08 Nexperia 3.3 V Quad 2-input AND gate 4 Functional diagram 1 & 3 & 6 & 8 2 1 1A 2 1B 4 2A 5 2B 9 3A 10 3B 12 4A 13 4B 4 1Y 3 5 2Y 6 9 3Y 10 8 12 11 4Y 11 13 Y B mna223 mna222 Figure 1. Logic symbol 5 A & Figure 2. IEC logic symbol mna221 Figure 3. Logic diagram (one gate) Pinning information 5.1 Pinning 74LVT08 1A 1 14 VCC 1B 2 13 4B 1Y 3 12 4A 2A 4 11 4Y 2B 5 10 3B 2Y 6 9 3A GND 7 8 3Y 74LVT08 1A 1 1B 2 14 VCC 13 4B 1Y 3 12 4A 2A 4 11 4Y 2B 5 10 3B 2Y 6 9 3A GND 7 8 3Y aaa-026560 aaa-026559 Figure 4. Pin configuration for SOT108-1 (SO14) Figure 5. Pin configuration for SOT337-1 and SOT402-1 (SSOP14 and TSSOP14) 5.2 Pin description Table 2. Pin description Symbol Pin Description 1Y to 4Y 3, 6, 8, 11 data output 1A to 4A 1, 4, 9, 12 data input 1B to 4B 2, 5, 10, 13 data input GND 7 ground (0 V) VCC 14 supply voltage 74LVT08 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 22 March 2017 © Nexperia B.V. 2017. All rights reserved. 2 / 13 74LVT08 Nexperia 3.3 V Quad 2-input AND gate 6 Functional description Table 3. Function table [1] Output Input nA nB nY H H H H L L L H L L L L [1] H = HIGH voltage level; L = LOW voltage level 7 Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC Conditions supply voltage Min Max Unit -0.5 +4.6 V [1] -0.5 +7.0 V [1] -0.5 +7.0 V VI input voltage VO output voltage output in OFF-state or HIGH-state IIK input clamping current VI < 0 V -50 - mA IOK output clamping current VO < 0 V -50 - mA IO output current output in LOW-state - 64 mA output in HIGH-state -32 - mA -65 +150 °C Tstg storage temperature Tj junction temperature [2] - 150 °C total power dissipation [3] - 500 mW Ptot [1] [2] [3] Tamb = -40 to +85 °C The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. For SO14 packages: above 70 °C derate linearly with 8 mW/K. For SSOP14 and TSSOP14 packages: above 60 °C derate linearly with 5.5 mW/K. 8 Recommended operating conditions Table 5. Operating conditions Symbol Parameter Conditions Min Typ Max Unit 2.7 - 3.6 V 0 - 5.5 V VCC supply voltage VI input voltage IOH HIGH-level output current -20 - - mA IOL LOW-level output current - - 32 mA 74LVT08 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 22 March 2017 © Nexperia B.V. 2017. All rights reserved. 3 / 13 74LVT08 Nexperia 3.3 V Quad 2-input AND gate Symbol Parameter Conditions Min Typ Max Unit Tamb ambient temperature in free-air -40 - +85 °C Δt/ΔV input transition rise and fall rate outputs enabled - - 10 ns/V Max Unit 9 Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min VCC = 2.7 V; IIK = -18 mA -1.2 [1] Typ Tamb = -40 °C to +85 °C VIK input clamping voltage VIH HIGH-level input voltage 2.0 VIL LOW-level input voltage - VOH HIGH-level output voltage VOL II VCC = 2.7 V to 3.6 V; IOH = -100 μA - V - - V - 0.8 V - V VCC - 0.2 VCC = 2.7 V; IOH = -6 mA 2.4 - - V VCC = 3.0 V; IOH = -20 mA 2.0 - - V LOW-level output voltage VCC = 2.7 V; IOL = 100 μA - 0.2 V VCC = 2.7 V; IOL = 24 mA - 0.5 V VCC = 3.0 V; IOL = 32 mA - 0.5 V VCC = 0 V or 3.6 V; VI = 5.5 V - - 10 μA - ±1 μA ±100 μA input leakage current VCC = 3.6 V; VI = VCC or GND IOFF power-off leakage current VCC = 0 V; VI or VO = 0 V to 4.5 V ICC supply current VCC = 3.6 V; VI = GND or VCC; IO = 0 A output HIGH output LOW [2] - - 0.02 mA - 1 2 mA 0.2 μA ΔICC additional supply current per input pin; VCC = 3.0 V to 3.6 V; one input at VCC - 0.6 V and other inputs at VCC or GND CI input capacitance VI = 0 V or 3.0 V - 4 - pF CO output capacitance VO = 0 V or 3.0 V - 10 - pF [1] [2] - Typical values are measured at Tamb = 25 °C and VCC = 3.3 V. This is the increase in supply current for each input at the specified voltage level other than VCC or GND. 74LVT08 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 22 March 2017 © Nexperia B.V. 2017. All rights reserved. 4 / 13 74LVT08 Nexperia 3.3 V Quad 2-input AND gate 10 Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7. Symbol Parameter Conditions Min [1] Typ Max Unit Tamb = -40 °C to +85 °C tPLH LOW to HIGH nA or nB to nY; see Figure 6 propagation delay tPHL HIGH to LOW - - 4.7 ns VCC = 3.0 V to 3.6 V 1 3.0 3.9 ns VCC = 2.7 V - - 4.8 ns VCC = 3.0 V to 3.6 V 1 3.4 4.6 ns nA or nB to nY; see Figure 6 propagation delay [1] VCC = 2.7 V Typical values are measured at VCC = 3.3 V and Tamb = 25 °C. 10.1 Waveforms and test circuit VI VM nA, nB input GND t PHL t PLH VOH nY output VM VOL mna224 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Figure 6. Propagation delay input (nA, nB) to output (nY) Table 8. Measurement points Output Input VM VI VM 1.5 V 2.7 V 1.5 V 74LVT08 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 22 March 2017 © Nexperia B.V. 2017. All rights reserved. 5 / 13 74LVT08 Nexperia 3.3 V Quad 2-input AND gate tW VI 90 % negative pulse VM VM 10 % 0V VI tf tr tr tf 90 % positive pulse VM VM 10 % 0V tW VCC PULSE GENERATOR VI VO DUT RT CL RL 001aaf615 Test data is given in Table 9. Definitions test circuit: RT = termination resistance should be equal to output impedance Zo of the pulse generator. CL = load capacitance including jig and probe capacitance. RL = load resistance. Figure 7. Test circuit for measuring switching times Table 9. Test data Input Load Test VI fi tW tr, tf CL RL 2.7 V ≤ 10 MHz 500 ns ≤ 2.5 ns 50 pF 500 Ω 74LVT08 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 22 March 2017 tPLH, tPHL © Nexperia B.V. 2017. All rights reserved. 6 / 13 74LVT08 Nexperia 3.3 V Quad 2-input AND gate 11 Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 A2 Q A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 inches 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.05 0.01 0.01 0.004 0.028 0.012 0.244 0.039 0.028 0.041 0.228 0.016 0.024 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Figure 8. Package outline SOT108-1 (SO14) 74LVT08 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 22 March 2017 © Nexperia B.V. 2017. All rights reserved. 7 / 13 74LVT08 Nexperia 3.3 V Quad 2-input AND gate SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm D SOT337-1 E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp L 7 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.4 0.9 8o 0o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT337-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 Figure 9. Package outline SOT337-1 (SSOP14) 74LVT08 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 22 March 2017 © Nexperia B.V. 2017. All rights reserved. 8 / 13 74LVT08 Nexperia 3.3 V Quad 2-input AND gate TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm D SOT402-1 E A X c y HE v M A Z 8 14 Q A2 pin 1 index (A 3 ) A1 A θ Lp 1 L 7 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Figure 10. .Package outline SOT402-1 (TSSOP14) 74LVT08 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 22 March 2017 © Nexperia B.V. 2017. All rights reserved. 9 / 13 74LVT08 Nexperia 3.3 V Quad 2-input AND gate 12 Abbreviations Table 10. Abbreviations Acronym Description BiCMOS Bipolar Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 13 Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVT08 v.3 20170322 Product data sheet - 74LVT08 v.2 Modifications: • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. • Legal texts have been adapted to the new company name where appropriate. 74LVT08 v.2 19960529 74LVT08 Product data sheet Product specification - All information provided in this document is subject to legal disclaimers. Rev. 3 — 22 March 2017 74LVT08 v.1 © Nexperia B.V. 2017. All rights reserved. 10 / 13 74LVT08 Nexperia 3.3 V Quad 2-input AND gate 14 Legal information 14.1 Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nexperia.com. 14.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Nexperia does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 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Suitability for use — Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical 74LVT08 Product data sheet systems or equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. 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All information provided in this document is subject to legal disclaimers. Rev. 3 — 22 March 2017 © Nexperia B.V. 2017. All rights reserved. 11 / 13 74LVT08 Nexperia 3.3 V Quad 2-input AND gate Non-automotive qualified products — Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia's warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia's specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer 74LVT08 Product data sheet design and use of the product for automotive applications beyond Nexperia's standard warranty and Nexperia's product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 14.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 3 — 22 March 2017 © Nexperia B.V. 2017. All rights reserved. 12 / 13 74LVT08 Nexperia 3.3 V Quad 2-input AND gate Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 10.1 11 12 13 14 General description ............................................ 1 Features and benefits .........................................1 Ordering information .......................................... 1 Functional diagram ............................................. 2 Pinning information ............................................ 2 Pinning ............................................................... 2 Pin description ................................................... 2 Functional description ........................................3 Limiting values .................................................... 3 Recommended operating conditions ................ 3 Static characteristics .......................................... 4 Dynamic characteristics .....................................5 Waveforms and test circuit ................................ 5 Package outline ...................................................7 Abbreviations .................................................... 10 Revision history ................................................ 10 Legal information .............................................. 11 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © Nexperia B.V. 2017. All rights reserved. For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 22 March 2017 Document identifier: 74LVT08