74LVT16543ADL,518

74LVT16543A 3.3 V 16-bit registered transceiver; 3-state Rev. 3 — 1 October 2018 Product data sheet 1. General description The 74LVT16543A is a high-performance BiCMOS product designed for VCC operation at 3.3 V. The device can be used as two 8-bit transceivers or one 16-bit transceiver. The 74LVT16543A contains two sets of eight D-type latches, with separate control pins for each set. Using data flow from A to B as an example, when the A-to-B enable (nEAB) input and the A-to-B latch enable (nLEAB) input are LOW, the A-to-B path is transparent. A subsequent LOW-to-HIGH transition of the nLEAB signal puts the A data into the latches where it is stored and the B outputs no longer change with the A inputs. With nEAB and nOEAB both LOW, the 3-State B output buffers are active and display the data present at the outputs of the A latches. Control of data flow from B to A is similar, but using the nEBA, nLEBA, and nOEBA inputs. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. 2. Features and benefits • • • • • • • • • • • • 16-bit universal bus interface 3-state buffers Input and output interface capability to systems at 5 V supply TTL input and output switching levels Output capability: +64 mA/-32 mA Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs Live insertion/extraction permitted Power-up 3-state Power-up reset No bus current loading when output is tied to 5 V bus Latch-up protection: • JESD78B Class II exceeds 500 mA ESD protection: • HBM: JESD22-A114F exceeds 2000 V • MM: JESD22-A115-A exceeds 200 V 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVT16543ADL -40 °C to +85 °C SSOP56 plastic shrink small outline package; 56 leads; body width 7.5 mm SOT371-1 74LVT16543ADGG -40 °C to +85 °C TSSOP56 plastic thin shrink small outline package; 56 leads; SOT364-1 body width 6.1 mm 74LVT16543A Nexperia 3.3 V 16-bit registered transceiver; 3-state 4. Functional diagram 5 6 8 9 10 12 13 14 1 56 3 54 2 55 1A0 1B0 1A1 1B1 1A2 1B2 1A3 1B3 1A4 1B4 1A5 1B5 1A6 1B6 1A7 1B7 52 15 51 16 49 17 48 19 47 20 45 21 44 23 43 24 2A0 2B0 2A1 2B1 2A2 2B2 2A3 2B3 2A4 2B4 2A5 2B5 2A6 2B6 2A7 2B7 1OEAB 2OEAB 1OEBA 2OEBA 1EAB 2EAB 1EBA 2EBA 1LEAB 2LEAB 1LEBA 2LEBA 42 41 40 38 37 36 34 33 28 29 26 31 27 30 aaa-027924 Fig. 1. Logic symbol 56 1EN3 (BA) 29 7EN9 (BA) 54 G1 31 G7 55 1C5 30 7C11 1 2EN4 (AB) 28 8EN10 (AB) 3 G2 26 G8 2 2C6 27 8C12 5 3 52 15 9 6 51 16 41 8 49 17 40 9 48 19 38 10 47 20 37 12 45 21 36 13 44 23 34 14 43 24 6D 5D 4 12D 11D 42 10 33 aaa-027925 Fig. 2. IEC logic symbol 74LVT16543A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 1 October 2018 © Nexperia B.V. 2018. All rights reserved 2 / 16 74LVT16543A Nexperia 3.3 V 16-bit registered transceiver; 3-state nOEBA nEBA nLEBA nOEAB nEAB nLEAB LE Q nA1 D nB1 LE Q 8 IDENTICAL CHANNELS D to 7 other channels Fig. 3. aaa-027926 Logic diagram 74LVT16543A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 1 October 2018 © Nexperia B.V. 2018. All rights reserved 3 / 16 74LVT16543A Nexperia 3.3 V 16-bit registered transceiver; 3-state 5. Pinning information 5.1. Pinning 74LVT16543A 1OEAB 1 56 1OEBA 1LEAB 2 55 1LEBA 1EAB 3 54 1EBA GND 4 53 GND 1A0 5 52 1B0 1A1 6 51 1B1 VCC 7 50 VCC 1A2 8 49 1B2 1A3 9 48 1B3 1A4 10 47 1B4 GND 11 46 GND 1A5 12 45 1B5 1A6 13 44 1B6 1A7 14 43 1B7 2A0 15 42 2B0 2A1 16 41 2B1 2A2 17 40 2B2 GND 18 39 GND 2A3 19 38 2B3 2A4 20 37 2B4 2A5 21 36 2B5 VCC 22 35 VCC 2A6 23 34 2B6 2A7 24 33 2B7 GND 25 32 GND 2EAB 26 31 2EBA 2LEAB 27 30 2LEBA 2OEAB 28 29 2OEBA aaa-029134 Fig. 4. Pin configuration for SOT371-1 (SSOP56) and SOT364-1 (TSSOP56) 74LVT16543A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 1 October 2018 © Nexperia B.V. 2018. All rights reserved 4 / 16 74LVT16543A Nexperia 3.3 V 16-bit registered transceiver; 3-state 5.2. Pin description Table 2. Pin description Symbol Pin Description 1A0, 1A1, 1A2, 1A3, 1A4, 1A5, 1A6, 1A7 5, 6, 8, 9, 10, 12, 13, 14 data inputs/outputs 2A0, 2A1, 2A2, 2A3, 2A4, 2A5, 2A6, 2A7 15, 16, 17, 19, 20, 21, 23, 24 data inputs/outputs 1B0, 1B1, 1B2, 1B3, 1B4, 1B5, 1B6, 1B7 52, 51, 49, 48, 47, 45, 44, 43 data inputs/outputs 2B0, 2B1, 2B2, 2B3, 2B4, 2B5, 2B6, 2B7 42, 41, 40, 38, 37, 36, 34, 33 data inputs/outputs 1OEAB, 1OEBA, 2OEAB, 2OEBA 1, 56, 28, 29 A to B / B to A output enable inputs (active LOW) 1EAB, 1EBA, 2EAB, 2EBA 3, 54, 26, 31 A to B / B to A enable inputs (active LOW) 1LEAB, 1LEBA, 2LEAB, 2LEBA 2, 55, 27, 30 A to B / B to A latch enable inputs (active LOW) GND 4, 11, 18, 25, 32, 39, 46, 53 ground (0 V) VCC 7, 22, 35, 50 supply voltage 6. Functional description Table 3. Function selection [1] Inputs Outputs Status nOEAB or nOEBA nEAB or nEBA nLEAB or nLEBA nAn or nBn nBn or nAn H X X X Z Disabled X H X X Z Disabled L ↑ L h Z Disabled + Latch L ↑ L l Z Disabled + Latch L L ↑ h H Latch + Display L L ↑ l L Latch + Display L L L H H Transparent L L L L L Transparent L L H X NC Hold [1] H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH transition of nLEAB, nLEBA, nEAB and nEBA; L = LOW voltage level; l = LOW voltage level one set-up time prior to the LOW-to-HIGH transition of nLEAB, nLEBA, nEAB and nEBA; X = don’t care; ↑ = LOW-to-HIGH transition of nLEAB, nLEBA, nEAB or nEBA; NC = no change; Z = high-impedance OFF-state. 74LVT16543A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 1 October 2018 © Nexperia B.V. 2018. All rights reserved 5 / 16 74LVT16543A Nexperia 3.3 V 16-bit registered transceiver; 3-state 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage VI input voltage VO output voltage output in OFF or HIGH state IIK input clamping current VI < 0 IOK output clamping current VO < 0 IO output current Tstg storage temperature Tj junction temperature [1] [2] Conditions Min Max Unit -0.5 +4.6 V [1] -0.5 +7.0 V [1] -0.5 +7.0 V -50 - mA -50 - mA output in LOW state - 128 mA output in HIGH state -64 - mA -65 +150 °C - +150 °C [2] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions Min Max Unit VCC supply voltage 2.7 3.6 V VI input voltage 0 5.5 V Tamb ambient temperature in free air -40 +85 °C Δt/ΔV input transition rise and fall rate outputs enabled - 10 ns/V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions VIK input clamping voltage VCC = 2.7 V; IIK = -18 mA VIH HIGH-level input voltage VIL LOW-level input voltage VOH HIGH-level output voltage VOL IOH LOW-level output voltage Min Typ [1] Max Unit - -0.85 -1.2 V 2.0 - - V - - 0.8 V VCC - 0.2 VCC - V VCC = 2.7 V; IOH = -8 mA 2.4 2.54 - V VCC = 3.0 V; IOH = -32 mA 2.0 2.36 - V VCC = 2.7 V; IOL = 100 μA - 0.07 0.2 V VCC = 2.7 V; IOL = 24 mA - 0.3 0.5 V VCC = 3.0 V; IOL = 16 mA - 0.2 0.4 V VCC = 3.0 V; IOL = 32 mA - 0.3 0.5 V VCC = 3.0 V; IOL = 64 mA - 0.35 0.55 V - - -32 mA VCC = 2.7 V to 3.6 V; IOH = -100 μA HIGH-level output current 74LVT16543A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 1 October 2018 © Nexperia B.V. 2018. All rights reserved 6 / 16 74LVT16543A Nexperia 3.3 V 16-bit registered transceiver; 3-state Symbol Parameter IOL LOW-level output current Conditions Min Typ [1] Max Unit - - 32 mA current duty cycle ≤ 50 %; fi ≥ 1 kHz - - 64 mA - 0.13 0.55 V VCC = 0 V or 3.6 V; VI = 5.5 V - 0.1 10 μA VCC = 3.6 V; VI = VCC or GND - 0.1 ±1 μA VCC = 3.6 V; VI = 5.5 V - 0.5 20 μA VCC = 3.6 V; VI = VCC - 0.5 10 μA VCC = 3.6 V; VI = 0 V - 1 -5 μA - 1 ±100 μA VOL(pu) power-up LOW-level output voltage VCC = 3.6 V; IO = 1 mA; VI = VCC or GND [2] II input leakage current control pins I/O data pins [3] IOFF power-off leakage current VCC = 0 V; VI or VO = 0 V to 4.5 V IBHL bus hold LOW current VCC = 3.0 V; VI = 0.8 V 75 130 - μA IBHH bus hold HIGH current VCC = 3.0 V; VI = 2.0 V -75 -140 - μA IBHLO bus hold LOW overdrive current VCC = 3.6 V; VI = 0 V to 3.6 V [4] 500 - - μA IBHHO bus hold HIGH overdrive current VCC = 3.6 V; VI = 0 V to 3.6 V [4] - - -500 μA ICEX output high leakage current output in HIGH-state when VO > VCC; VO = 5.5 V; VCC = 3.0 V - 45 125 μA IO(pu/pd) power-up/power-down output current VCC ≤ 1.2 V; VO = 0.5 V to VCC; VI = GND or VCC; nOE = don’t care - 35 ±100 μA ICC supply current VCC = 3.6 V; VI = VCC or GND; IO = 0 A outputs HIGH - 0.07 0.12 mA outputs LOW - 4.5 6 mA [6] - 0.07 0.12 mA [7] - 0.1 0.2 mA outputs disabled [5] ΔICC additional supply current per input pin; VCC = 3.0 V to 3.6 V; one input = VCC - 0.6 V; other inputs at VCC or GND CI input capacitance at control pins; VI = 0 V or 3.0 V - 3 - pF CI/O input/output capacitance at input/output data pins, outputs disabled; VI/O = 0 V or 3.0 V - 9 - pF [1] [2] [3] [4] [5] [6] [7] All typical values are measured at VCC = 3.3 V and Tamb = 25 °C. For valid test results, data must not be loaded into the latches after applying power. Unused pins at VCC or GND. This is the bus hold overdrive current required to force the input to the opposite logic state. This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to VCC = 3.0 V to 3.6 V a transition time of 100 µs is permitted. This parameter is valid for Tamb = +25 °C only. ICC with the outputs disabled is measured with outputs pulled to VCC or GND. This is the increase in supply current for each input at the specified voltage level other than VCC or GND. 74LVT16543A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 1 October 2018 © Nexperia B.V. 2018. All rights reserved 7 / 16 74LVT16543A Nexperia 3.3 V 16-bit registered transceiver; 3-state 10. Dynamic characteristics Table 7. Dynamic characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). For test circuit see Fig. 9. Symbol Parameter Conditions tpd propagation delay nAn to nBn or nBn to nAn; see Fig. 5 VCC = 3.3 V ± 0.3 V propagation delay nLEBA to nAn, nLEAB to nBn; see Fig. 6 VCC = 3.3 V ± 0.3 V OFF-state to HIGH propagation delay OFF-state to LOW propagation delay VCC = 2.7 V HIGH to OFF-state propagation delay VCC = 2.7 V VCC = 2.7 V LOW to OFF-state propagation delay nOEBA to nAn, nOEAB to nBn; see Fig. 7 OFF-state to HIGH propagation delay nEBA to nAn, nEAB to nBn; see Fig. 7 VCC = 2.7 V VCC = 3.3 V ± 0.3 V tPZH VCC = 2.7 V VCC = 3.3 V ± 0.3 V tPZL OFF-state to LOW propagation delay HIGH to OFF-state propagation delay VCC = 2.7 V LOW to OFF-state propagation delay tsu(L) th(H) set-up time HIGH set-up time LOW hold time HIGH 74LVT16543A Product data sheet 1.0 2.2 3.7 ns - - 6.2 ns 1.5 2.7 4.8 ns - - 6.1 ns 1.5 2.8 4.6 ns - - 6.6 ns 1.5 2.6 5.0 ns - - 5.7 ns 2.0 3.1 5.2 ns - - 4.7 ns 2.0 3.2 4.6 ns - - 6.1 ns 1.5 2.9 4.8 ns - - 6.6 ns 2.6 5.1 ns - - 5.7 ns 2.0 3.1 5.1 ns - - 4.5 ns 2.0 3.2 4.3 ns VCC = 2.7 V 0.5 - - ns VCC = 3.3 V ± 0.3 V 0.8 0.4 - ns VCC = 2.7 V 1.5 - - ns VCC = 3.3 V ± 0.3 V 1.0 0.1 - ns nEBA to nAn, nEAB to nBn; see Fig. 7 VCC = 2.7 V nEBA to nAn, nEAB to nBn; see Fig. 7 VCC = 2.7 V VCC = 3.3 V ± 0.3 V tsu(H) ns 1.5 VCC = 3.3 V ± 0.3 V tPLZ 4.4 nEBA to nAn, nEAB to nBn; see Fig. 7 VCC = 3.3 V ± 0.3 V tPHZ - nOEBA to nAn, nOEAB to nBn; see Fig. 7 VCC = 3.3 V ± 0.3 V tPLZ - nOEBA to nAn, nOEAB to nBn; see Fig. 7 VCC = 3.3 V ± 0.3 V tPHZ Unit nOEBA to nAn, nOEAB to nBn; see Fig. 7 VCC = 3.3 V ± 0.3 V tPZL Max [2] VCC = 2.7 V tPZH Typ [1] [2] VCC = 2.7 V tpd Min nAn to nLEAB, nBn to nLEBA; see Fig. 8 nAn to nLEAB, nBn to nLEBA; see Fig. 8 nAn to nLEAB, nBn to nLEBA; see Fig. 8 VCC = 2.7 V 0.5 - - ns VCC = 3.3 V ± 0.3 V 1.0 0.2 - ns All information provided in this document is subject to legal disclaimers. Rev. 3 — 1 October 2018 © Nexperia B.V. 2018. All rights reserved 8 / 16 74LVT16543A Nexperia 3.3 V 16-bit registered transceiver; 3-state Symbol Parameter Conditions th(L) hold time LOW nAn to nLEAB, nBn to nLEBA; see Fig. 8 tsu(H) tsu(L) th(H) set-up time LOW hold time HIGH th(L) hold time LOW tWL [1] [2] set-up time HIGH pulse width LOW Min Typ [1] Max Unit VCC = 2.7 V 1.3 - - ns VCC = 3.3 V ± 0.3 V 1.2 0.4 - ns VCC = 2.7 V 0.4 - - ns VCC = 3.3 V ± 0.3 V 0.7 0.1 - ns nAn to nEAB, nBn to nEBA; see Fig. 8 nAn to nEAB, nBn to nEBA; see Fig. 8 VCC = 2.7 V 1.5 - - ns VCC = 3.3 V ± 0.3 V 1.3 0.1 - ns VCC = 2.7 V 0.8 - - ns VCC = 3.3 V ± 0.3 V 1.2 0.2 - ns VCC = 2.7 V 1.4 - - ns VCC = 3.3 V ± 0.3 V 1.3 0.4 - ns VCC = 2.7 V 1.8 - - ns VCC = 3.3 V ± 0.3 V 1.8 1.0 - ns nAn to nEAB, nBn to nEBA; see Fig. 8 nAn to nEAB, nBn to nEBA; see Fig. 8 nLEAB and nLEBA; see Fig. 6 Typical values are measured at Tamb = 25 °C and VCC = 3.3 V tpd is the same as tPLH and tPHL 10.1. Waveforms and test circuit VI nAn, nBn input VM VM tPHL tPLH GND VOH nBn, nAn output VM VOL VM aaa-027928 See Table 8 for measurement points. VOL and VOH are typical output voltage levels that occur with the output load. Fig. 5. Input (nAn, nBn) to output (nBn, nAn) propagation delays 74LVT16543A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 1 October 2018 © Nexperia B.V. 2018. All rights reserved 9 / 16 74LVT16543A Nexperia 3.3 V 16-bit registered transceiver; 3-state VI nLEAB, nLEBA input VM VM VM GND tW tPHL tPLH VOH nAn, nBn output VM VM VOL aaa-027929 See Table 8 for measurement points. VOL and VOH are typical output voltage levels that occur with the output load. Fig. 6. Input (nLEAB, nLEBA) to output (nBn, nAn) propagation delays and pulse width LOW VI nOEAB, nOEBA nEAB, nEBA input VM VM GND tPLZ output LOW-to-OFF OFF-to-LOW tPZL 3.0 V VM VX VOL tPHZ output HIGH-to-OFF OFF-to-HIGH VOH tPZH VY VM GND outputs enabled outputs disabled outputs enabled aaa-029135 See Table 8 for measurement points. VOL and VOH are typical output voltage levels that occur with the output load. Fig. 7. 3-state output enable and disable times VI nAn, nBn input VM VM VM VM GND th th tsu VI nLEBA, nLEAB nEBA, nEAB input tsu VM VM GND aaa-027931 See Table 8 for measurement points. The shaded areas indicate when the input is permitted to change for predictable output performance. Fig. 8. Data set-up and hold times for the inputs nAn and nBn to nLEBA, nLEAB, nEBA and nEAB inputs Table 8. Measurement points Input Output VI VM VM Vx Vy 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH - 0.3 V 74LVT16543A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 1 October 2018 © Nexperia B.V. 2018. All rights reserved 10 / 16 74LVT16543A Nexperia 3.3 V 16-bit registered transceiver; 3-state VI negative pulse tW 90 % VM 0V VI positive pulse 0V VM 10 % tf tr tr tf 90 % VM VM 10 % tW VEXT VCC G VI RL VO DUT RT CL RL 001aae331 Test data is given in Table 9. Definitions test circuit: RL = Load resistance; CL = Load capacitance including jig and probe capacitance; RT = Termination resistance should be equal to output impedance Zo of the pulse generator; VEXT = External voltage for measuring switching times. Fig. 9. Test circuit for measuring switching times Table 9. Test data Input Load VEXT VI fi tW tr, tf RL CL tPHZ, tPZH tPLZ, tPZL tPLH, tPHL 2.7 V ≤ 10 MHz 500 ns ≤ 2.5 ns 500 Ω 50 pF GND 6V open 74LVT16543A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 1 October 2018 © Nexperia B.V. 2018. All rights reserved 11 / 16 74LVT16543A Nexperia 3.3 V 16-bit registered transceiver; 3-state 11. Package outline SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm SOT371-1 D E A X c y HE v M A Z 29 56 Q A2 A1 A (A 3 ) θ pin 1 index Lp L 28 1 bp e 0 detail X w M 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2.8 0.4 0.2 2.35 2.20 0.25 0.3 0.2 0.22 0.13 18.55 18.30 7.6 7.4 0.635 10.4 10.1 1.4 1.0 0.6 1.2 1.0 0.25 0.18 0.1 0.85 0.40 8o 0o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT371-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-118 Fig. 10. Package outline SOT371-1 (SSOP56) 74LVT16543A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 1 October 2018 © Nexperia B.V. 2018. All rights reserved 12 / 16 74LVT16543A Nexperia 3.3 V 16-bit registered transceiver; 3-state TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm SOT364-1 E D A X c HE y v M A Z 56 29 Q A2 (A 3 ) A1 pin 1 index A θ Lp L 1 28 w M bp e detail X 2.5 0 5 mm scale DIMENSIONS (mm are the original dimensions). UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z θ mm 1.2 0.15 0.05 1.05 0.85 0.25 0.28 0.17 0.2 0.1 14.1 13.9 6.2 6.0 0.5 8.3 7.9 1 0.8 0.4 0.50 0.35 0.25 0.08 0.1 0.5 0.1 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT364-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 Fig. 11. Package outline SOT364-1 (TSSOP56) 74LVT16543A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 1 October 2018 © Nexperia B.V. 2018. All rights reserved 13 / 16 74LVT16543A Nexperia 3.3 V 16-bit registered transceiver; 3-state 12. Abbreviations Table 10. Abbreviations Acronym Description BiCMOS Bipolar Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge MIL Military MM Machine Model TTL Transistor-Transistor Logic 13. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVT16543A v.3 20181001 Product data sheet - 74LVT16543A v.2 Modifications: • • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. 74LVT16543A v.2 19980219 Product specification 74LVT16543A v.1 - Product specification 74LVT16543A Product data sheet - All information provided in this document is subject to legal disclaimers. Rev. 3 — 1 October 2018 74LVT16543A v.1 - © Nexperia B.V. 2018. All rights reserved 14 / 16 74LVT16543A Nexperia 3.3 V 16-bit registered transceiver; 3-state 14. Legal information injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Data sheet status Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. 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It is customer’s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 3 — 1 October 2018 © Nexperia B.V. 2018. All rights reserved 15 / 16 74LVT16543A Nexperia 3.3 V 16-bit registered transceiver; 3-state Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................1 4. Functional diagram.......................................................2 5. Pinning information......................................................4 5.1. Pinning.........................................................................4 5.2. Pin description............................................................. 5 6. Functional description................................................. 5 7. Limiting values............................................................. 6 8. Recommended operating conditions..........................6 9. Static characteristics....................................................6 10. Dynamic characteristics............................................ 8 10.1. Waveforms and test circuit........................................ 9 11. Package outline........................................................ 12 12. Abbreviations............................................................ 14 13. Revision history........................................................14 14. Legal information......................................................15 © Nexperia B.V. 2018. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 1 October 2018 74LVT16543A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 1 October 2018 © Nexperia B.V. 2018. All rights reserved 16 / 16