74LVT240D,118

74LVT240 3.3 V Octal inverting buffer/line driver; 3-state Rev. 3 — 10 April 2017 1 Product data sheet General description The 74LVT240 is a high-performance BiCMOS product designed for VCC operation at 3.3 V. This device is an octal inverting buffer that is ideal for driving bus lines. The device features two output enable pins (1OE, 2OE), each controlling four of the 3-State outputs. 2 Features and benefits • • • • • • • • • • Octal bus interface 3-state buffers Output capability: +64 mA and -32 mA TTL input and output switching levels Input and output interface capability to systems at 5 V supply Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs Live insertion and extraction permitted Power-up 3-state No bus current loading when output is tied to 5 V bus Latch-up protection – JESD78 Class II exceeds 500 mA • ESD protection: – MIL STD 883 method 3015: exceeds 2000 V – MM JESD22-A115-A exceeds 200 V 3 Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVT240D -40 °C to +85 °C SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 74LVT240DB -40 °C to +85 °C SSOP20 plastic shrink small outline package; 20 leads; SOT339-1 body width 5.3 mm 74LVT240PW -40 °C to +85 °C TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 74LVT240 Nexperia 3.3 V Octal inverting buffer/line driver; 3-state 4 Functional diagram 1 2 11 1A0 2A0 1Y0 2Y0 18 9 18 4 16 6 14 12 1A1 2A1 1Y1 2Y1 16 7 8 6 15 1A2 2A2 1Y2 2Y2 14 5 19 8 17 1A3 2A3 1Y3 2Y3 12 3 1OE 2OE EN 11 9 13 7 15 5 17 3 aaa-026569 Figure 1. Logic symbol 5 2 4 13 1 19 EN aaa-026570 Figure 2. IEC logic symbol Pinning information 5.1 Pinning 74LVT240 74LVT240 1OE 1 1 2 20 VCC 19 2OE 1OE 1A0 1A0 2 20 VCC 19 2OE 2Y3 3 18 1Y0 2Y3 3 18 1Y0 1A1 4 17 2A3 1A1 4 17 2A3 2Y2 5 16 1Y1 2Y2 5 16 1Y1 1A2 6 15 2A2 1A2 6 15 2A2 2Y1 7 14 1Y2 2Y1 7 14 1Y2 1A3 8 13 2A1 1A3 8 13 2A1 2Y0 9 12 1Y3 2Y0 9 12 1Y3 GND 10 11 2A0 GND 10 11 2A0 aaa-026571 Figure 3. Pin configuration for SO20 74LVT240 Product data sheet aaa-026572 Figure 4. Pin configuration for (T)SSOP20 All information provided in this document is subject to legal disclaimers. Rev. 3 — 10 April 2017 © Nexperia B.V. 2017. All rights reserved. 2 / 15 74LVT240 Nexperia 3.3 V Octal inverting buffer/line driver; 3-state 5.2 Pin description Table 2. Pin description Symbol Pin Description 1OE, 2OE 1, 19 output enable input (active LOW) 1A0, 1A1, 1A2, 1A3 2, 4, 6, 8 data input 2Y0, 2Y1, 2Y2, 2Y3 9, 7, 5, 3 bus output GND 10 ground (0 V) 2A0, 2A1, 2A2, 2A3 11, 13, 15, 17 data input 1Y0, 1Y1, 1Y2, 1Y3 18, 16, 14, 12 bus output VCC 20 supply voltage 6 Functional description Table 3. Function table [1] Outputs Inputs nOE nAn nYn L L H L H L H X Z [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. 74LVT240 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 10 April 2017 © Nexperia B.V. 2017. All rights reserved. 3 / 15 74LVT240 Nexperia 3.3 V Octal inverting buffer/line driver; 3-state 7 Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC Conditions supply voltage Min Max Unit -0.5 +4.6 V input voltage [1] -0.5 +7.0 V VO output voltage output in OFF or HIGH state [1] -0.5 +7.0 V IIK input clamping current VI < 0 V -50 - mA IOK output clamping current VO < 0 V -50 - mA IO output current output in LOW state - 128 mA output in HIGH state -64 - mA VI Tstg storage temperature Tj Ptot [1] [2] [3] -65 +150 °C junction temperature [2] - +150 °C total power dissipation [3] - 500 mW Tamb = -40 °C to +85 °C The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. For SO20 packages: above 70 °C derate linearly with 8 mW/K. For SSOP20 and TSSOP20 packages: above 60 °C derate linearly with 5.5 mW/K. 8 Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions Min Max Unit 2.7 3.6 V 0 5.5 V VCC supply voltage VI input voltage IOH HIGH-level output current -32 - mA IOL LOW-level output current - 32 mA - 64 mA -40 +85 °C - 10 ns/V current duty cycle ≤ 50 %; fi ≥ 1 kHz Tamb ambient temperature in free air Δt/ΔV input transition rise and fall rate outputs enabled 74LVT240 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 10 April 2017 © Nexperia B.V. 2017. All rights reserved. 4 / 15 74LVT240 Nexperia 3.3 V Octal inverting buffer/line driver; 3-state 9 Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter [1] Conditions Min Typ Max Unit VCC = 2.7 V; IIK = –18 mA -1.2 -0.9 - V Tamb = -40 °C to +85 °C VIK input clamping voltage VIH HIGH-level input voltage 2.0 - - V VIL LOW-level input voltage - - 0.8 V VOH HIGH-level output voltage - V VOL II LOW-level output voltage input leakage current VCC = 2.7 V to 3.6 V; IOH = -100 μA VCC - 0.2 VCC - 0.1 VCC = 2.7 V; IOH = -8 mA 2.4 2.5 - V VCC = 3.0 V; IOH = -32 mA 2.0 2.2 - V 0.1 0.2 V VCC = 2.7 V; IOL = 100 μA VCC = 2.7 V; IOL = 24 mA - 0.3 0.5 V VCC = 3.0 V; IOL = 16 mA - 0.25 0.4 V VCC = 3.0 V; IOL = 32 mA - 0.3 0.5 V VCC = 3.0 V; IOL = 64 mA - 0.4 0.55 V - 1 10 μA - ±0.1 ±1 μA VCC = 3.6 V; VI = VCC - 0.1 1 μA VCC = 3.6 V; VI = 0 V -5 -1 - μA - 1 ±100 μA 75 150 - μA all input pins VCC = 0 V or 3.6 V; VI = 5.5 V control pins VCC = 3.6 V; VI = VCC or GND [2] data pins IOFF power-off leakage current VCC = 0 V; VI or VO = 0 V to 4.5 V IBHL bus hold LOW current VCC = 3.0 V; VI = 0.8 V IBHH bus hold HIGH current VCC = 3.0 V; VI = 2.0 V - -150 -75 μA 500 - - μA - - -500 μA - 60 125 μA - ±1 ±100 μA IBHLO bus hold LOW overdrive current VCC = 3.6 V; VI = 0 V to 3.6 V [3] IBHHO bus hold HIGH overdrive current VCC = 3.6 V; VI = 0 V to 3.6 V [3] ICEX output high leakage current nYn output in HIGH-state when VO > VCC; VO = 5.5 V; VCC = 3.0 V IO(pu/pd) power-up/power-down output current VCC ≤ 1.2 V; VO = 0.5 V to VCC; VI = GND or VCC; nOE = don’t care IOZ OFF-state output current VCC = 3.6 V; VO = 3.0 V - 1 5 μA VCC = 3.6 V; VO = 0.5 V -5 -1 - μA outputs HIGH - 0.12 0.19 mA outputs LOW - 3 12 mA ICC supply current 74LVT240 Product data sheet [4] VCC = 3.6 V; VI = VCC or GND; IO = 0 A All information provided in this document is subject to legal disclaimers. Rev. 3 — 10 April 2017 © Nexperia B.V. 2017. All rights reserved. 5 / 15 74LVT240 Nexperia 3.3 V Octal inverting buffer/line driver; 3-state Symbol Parameter Conditions outputs disabled Min [1] Typ Max Unit [5] - 0.12 0.19 mA [6] - 0.1 0.2 mA ΔICC additional supply current per input pin; VCC = 3.0 V to 3.6 V; one input = VCC - 0.6 V; other inputs at VCC or GND CI input capacitance VI = 0 V or 3.0 V - 4 - pF CO output capacitance outputs disabled; VO = 0 V or 3.0 V - 8 - pF [1] [2] [3] [4] [5] [6] All typical values are measured at Tamb = 25 °C. Unused pins at VCC or GND. This is the bus hold overdrive current required to force the input to the opposite logic state. This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to VCC = 3.3 V ± 0.3 V a transition time of 100 ms is permitted. This parameter is valid for Tamb = +25 °C only. ICC with the outputs disabled is measured with outputs pulled to VCC or GND. This is the increase in supply current for each input at the specified voltage level other than VCC or GND. 10 Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 7. Symbol Parameter Conditions Min [1] Typ Max Unit Tamb = -40 °C to +85 °C tPLH LOW to HIGH propagation delay nAn to nYn; see Figure 5 VCC = 2.7 V VCC = 3.3 V ± 0.3 V tPHL HIGH to LOW propagation delay VCC = 3.3 V ± 0.3 V OFF-state to HIGH propagation delay VCC = 2.7 V VCC = 2.7 V VCC = 3.3 V ± 0.3 V HIGH to OFF-state propagation delay LOW to OFF-state propagation delay VCC = 2.7 V 2.5 4.3 ns - - 5.0 ns 1.0 2.5 4.3 ns - - 6.3 ns 1.0 3.7 5.2 ns - - 6.7 ns 1.0 3.1 5.2 ns - - 6.3 ns 2.0 3.4 5.6 ns - - 5.6 ns 1.6 3.2 5.1 ns nOE to nYn; see Figure 6 VCC = 2.7 V VCC = 3.3 V ± 0.3 V [1] 1.0 nOE to nYn; see Figure 6 VCC = 3.3 V ± 0.3 V tPLZ ns nOE to nYn; see Figure 6 OFF-state to LOW propagation delay tPHZ 5.2 nOE to nYn; see Figure 6 VCC = 3.3 V ± 0.3 V tPZL - nAn to nYn; see Figure 5 VCC = 2.7 V tPZH - Typical values are measured at Tamb = 25 °C and VCC = 3.3 V. 74LVT240 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 10 April 2017 © Nexperia B.V. 2017. All rights reserved. 6 / 15 74LVT240 Nexperia 3.3 V Octal inverting buffer/line driver; 3-state 10.1 Waveforms and test circuit VI input nAn VM VM 0V tPHL tPLH VOH output nYn VM VM VOL 001aaj028 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Figure 5. Input (nAn) to output (nYn) propagation delays VI nOE input VM GND tPZL tPLZ 3.0 V VM nYn output VOL VX t PZH t PHZ VOH nYn output VY VM 0V 001aae464 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Figure 6. 3-state enable and disable times Table 8. Measurement points Input Output VM VM VX VY 1.5 V 1.5 V VOL + 0.3 V VOH - 0.3 V 74LVT240 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 10 April 2017 © Nexperia B.V. 2017. All rights reserved. 7 / 15 74LVT240 Nexperia 3.3 V Octal inverting buffer/line driver; 3-state VI negative pulse tW 90 % 90 % VM 10 % 0V VI positive pulse 0V VM 10 % tf tr tr tf 90 % 90 % VM VM 10 % 10 % tW 001aai298 VEXT VCC PULSE GENERATOR VI DUT RL VO CL RT RL 001aac764 Test data is given in Table 9. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. Figure 7. Test circuit for measuring switching times Table 9. Test data Input Load VEXT VI fi tW tr, tf RL CL tPHZ, tPZH tPLZ, tPZL tPLH, tPHL 2.7 V ≤ 10 MHz 500 ns ≤ 2.5 ns 500 Ω 50 pF GND 6V open 74LVT240 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 10 April 2017 © Nexperia B.V. 2017. All rights reserved. 8 / 15 74LVT240 Nexperia 3.3 V Octal inverting buffer/line driver; 3-state 11 Package outline SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c y HE v M A Z 20 11 Q A2 A (A 3 ) A1 pin 1 index θ Lp L 1 10 e detail X w M bp 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.9 0.4 inches 0.1 0.012 0.096 0.004 0.089 0.01 0.019 0.013 0.014 0.009 0.51 0.49 0.30 0.29 0.05 0.419 0.043 0.055 0.394 0.016 0.043 0.039 0.01 0.01 0.004 0.035 0.016 Z (1) θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT163-1 075E04 MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Figure 8. Package outline SOT163-1 (SO20) 74LVT240 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 10 April 2017 © Nexperia B.V. 2017. All rights reserved. 9 / 15 74LVT240 Nexperia 3.3 V Octal inverting buffer/line driver; 3-state SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm D SOT339-1 E A X c HE y v M A Z 20 11 Q A2 pin 1 index A (A 3) A1 θ Lp L 1 10 bp e detail X w M 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 7.4 7.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 0.9 0.5 8o 0o Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION SOT339-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 Figure 9. Package outline SOT339-1 (SSOP20) 74LVT240 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 10 April 2017 © Nexperia B.V. 2017. All rights reserved. 10 / 15 74LVT240 Nexperia 3.3 V Octal inverting buffer/line driver; 3-state TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm D SOT360-1 E A X c HE y v M A Z 11 20 Q A2 pin 1 index (A 3 ) A1 A θ Lp 1 L 10 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.5 0.2 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 Figure 10. Package outline SOT360-1 (TSSOP20) 74LVT240 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 10 April 2017 © Nexperia B.V. 2017. All rights reserved. 11 / 15 74LVT240 Nexperia 3.3 V Octal inverting buffer/line driver; 3-state 12 Abbreviations Table 10. Abbreviations Acronym Description BiCMOS Bipolar Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 13 Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVT240 v.3 20170410 Product data sheet Modifications: • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. • Legal texts have been adapted to the new company name where appropriate. 74LVT240 v.2 19980219 Product specification - 74LVT240 v.1 74LVT240 v.1 19940516 Product specification - - 74LVT240 Product data sheet - All information provided in this document is subject to legal disclaimers. Rev. 3 — 10 April 2017 74LVT240 v.2 © Nexperia B.V. 2017. All rights reserved. 12 / 15 74LVT240 Nexperia 3.3 V Octal inverting buffer/line driver; 3-state 14 Legal information 14.1 Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nexperia.com. 14.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Nexperia does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Nexperia sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between Nexperia and its customer, unless Nexperia and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the Nexperia product is deemed to offer functions and qualities beyond those described in the Product data sheet. 14.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, Nexperia does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Nexperia takes no responsibility for the content in this document if provided by an information source outside of Nexperia. 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Suitability for use — Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical 74LVT240 Product data sheet systems or equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. All information provided in this document is subject to legal disclaimers. Rev. 3 — 10 April 2017 © Nexperia B.V. 2017. All rights reserved. 13 / 15 74LVT240 Nexperia 3.3 V Octal inverting buffer/line driver; 3-state Non-automotive qualified products — Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia's warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia's specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer 74LVT240 Product data sheet design and use of the product for automotive applications beyond Nexperia's standard warranty and Nexperia's product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 14.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 3 — 10 April 2017 © Nexperia B.V. 2017. All rights reserved. 14 / 15 74LVT240 Nexperia 3.3 V Octal inverting buffer/line driver; 3-state Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 10.1 11 12 13 14 General description ............................................ 1 Features and benefits .........................................1 Ordering information .......................................... 1 Functional diagram ............................................. 2 Pinning information ............................................ 2 Pinning ............................................................... 2 Pin description ................................................... 3 Functional description ........................................3 Limiting values .................................................... 4 Recommended operating conditions ................ 4 Static characteristics .......................................... 5 Dynamic characteristics .....................................6 Waveforms and test circuit ................................ 7 Package outline ...................................................9 Abbreviations .................................................... 12 Revision history ................................................ 12 Legal information .............................................. 13 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © Nexperia B.V. 2017. All rights reserved. For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 10 April 2017 Document identifier: 74LVT240