HEF4081BT,652

HEF4081B Quad 2-input AND gate Rev. 8 — 15 December 2015 Product data sheet 1. General description The HEF4081B is a quad 2-input AND gate. The outputs are fully buffered for highest noise immunity and pattern insensitivity to output impedance variations. It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input. 2. Features and benefits       Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Inputs and outputs are protected against electrostatic effects Specified from40 C to +85 C and 40 C to +125 C Complies with JEDEC standard JESD 13-B 3. Ordering information Table 1. Ordering information All types operate from 40 C to +125 C. Type number Package HEF4081BT Name Description Version SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 4. Functional diagram   $ %  $  %  $  %  $  % <  <  <  <  Q$ Q% DDJ DDL Fig 1. Functional diagram Q< Fig 2. Logic diagram (one gate) HEF4081B Nexperia Quad 2-input AND gate 5. Pinning information 5.1 Pinning $   9'' %   % <   $ <  $  %  966  +()%  <  <  %  $ DDJ Fig 3. Pin configuration 5.2 Pin description Table 2. Pin description Symbol Pin Description 1A to 4A 1, 5, 8, 12 input 1B to 4B 2, 6, 9, 13 input 1Y to 4Y 3, 4, 10, 11 output VSS 7 ground (0 V) VDD 14 supply voltage 6. Functional description Table 3. Function table[1] Input Output nA nB nY L L L L H L H L L H H H [1] H = HIGH voltage level; L = LOW voltage level. HEF4081B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 15 December 2015 © Nexperia B.V. 2017. All rights reserved 2 of 11 HEF4081B Nexperia Quad 2-input AND gate 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground). Symbol Parameter Conditions VDD supply voltage IIK input clamping current VI input voltage IOK output clamping current II/O input/output current IDD supply current - 50 mA Tstg storage temperature 65 +150 C Tamb ambient temperature 40 +125 C Ptot total power dissipation - 500 mW - 100 mW VI < 0.5 V or VI > VDD + 0.5 V [1] Max Unit 0.5 +18 V 10 mA 0.5 VO < 0.5 V or VO > VDD + 0.5 V VDD + 0.5 V - 10 mA - 10 mA Tamb = 40 C to + 125 C SO14 P Min power dissipation per output [1] For SO14 packages: above Tamb = 70 C, Ptot derates linearly with 8 mW/K. 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter VDD VI Conditions Min Max Unit supply voltage 3 15 V input voltage 0 VDD V Tamb ambient temperature in free air 40 +125 C t/V input transition rise and fall rate VDD = 5 V - 3.75 s/V VDD = 10 V - 0.5 s/V VDD = 15 V - 0.08 s/V HEF4081B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 15 December 2015 © Nexperia B.V. 2017. All rights reserved 3 of 11 HEF4081B Nexperia Quad 2-input AND gate 9. Static characteristics Table 6. Static characteristics VSS = 0 V; VI = VSS or VDD; unless otherwise specified. Symbol Parameter VIH VIL VOH VOL IOH IOL HIGH-level input voltage LOW-level input voltage IO < 1 A IO < 1 A HIGH-level output voltage IO < 1 A LOW-level output voltage IO < 1 A HIGH-level output current LOW-level output current II input leakage current IDD supply current CI Conditions input capacitance HEF4081B Product data sheet VDD Tamb = 40 C Tamb = +25 C Tamb = +85 C Tamb = +125 C Unit Min Max Min Max Min Max Min Max 5V 3.5 - 3.5 - 3.5 - 3.5 - V 10 V 7.0 - 7.0 - 7.0 - 7.0 - V 15 V 11.0 - 11.0 - 11.0 - 11.0 - V 5V - 1.5 - 1.5 - 1.5 - 1.5 V 10 V - 3.0 - 3.0 - 3.0 - 3.0 V 15 V - 4.0 - 4.0 - 4.0 - 4.0 V 5V 4.95 - 4.95 - 4.95 - 4.95 - V 10 V 9.95 - 9.95 - 9.95 - 9.95 - V 15 V 14.95 - 14.95 - 14.95 - 14.95 - V 5V - 0.05 - 0.05 - 0.05 - 0.05 V 10 V - 0.05 - 0.05 - 0.05 - 0.05 V 15 V - 0.05 - 0.05 - 0.05 - 0.05 V VO = 2.5 V 5V - 1.7 - 1.4 - 1.1 - 1.1 mA VO = 4.6 V 5V - 0.64 - 0.5 - 0.36 - 0.36 mA VO = 9.5 V 10 V - 1.6 - 1.3 - 0.9 - 0.9 mA VO = 13.5 V 15 V - 4.2 - 3.4 - 2.4 - 2.4 mA VO = 0.4 V 5V 0.64 - 0.5 - 0.36 - 0.36 - mA VO = 0.5 V 10 V 1.6 - 1.3 - 0.9 - 0.9 - mA VO = 1.5 V 15 V 4.2 - 3.4 - 2.4 - 2.4 - mA 15 V - 0.1 - 0.1 - 1.0 - 1.0 A all valid input 5 V combinations; 10 V IO = 0 A 15 V - 0.25 - 0.25 - 7.5 - 7.5 A - 0.5 - 0.5 - 15.0 - 15.0 A - 1.0 - 1.0 - 30.0 - 30.0 A - - - 7.5 - - - - pF All information provided in this document is subject to legal disclaimers. Rev. 8 — 15 December 2015 © Nexperia B.V. 2017. All rights reserved 4 of 11 HEF4081B Nexperia Quad 2-input AND gate 10. Dynamic characteristics Table 7. Dynamic characteristics Tamb = 25 C; for waveforms see Figure 4; for test circuit see Figure 5; unless otherwise specified. [1] Symbol Parameter HIGH to LOW propagation delay tPHL LOW to HIGH propagation delay tPLH VDD Extrapolation formula Min Typ Max Unit nA or nB to nY 5 V 28 ns + (0.55 ns/pF)CL - 55 110 ns 10 V 14 ns + (0.23 ns/pF)CL - 25 50 ns 15 V 12 ns + (0.16 ns/pF)CL - 20 40 ns 18 ns + (0.55 ns/pF)CL - 45 90 ns 9 ns + (0.23 ns/pF)CL - 20 40 ns nA or nB to nY 5 V 10 V HIGH to LOW output transition time tTHL LOW to HIGH output transition time tTLH [1] Conditions 15 V 7 ns + (0.16 ns/pF)CL - 15 30 ns 5V 10 ns + (1.0 ns/pF)CL - 60 120 ns 10 V 9 ns + (0.42 ns/pF)CL - 30 60 ns 15 V 6 ns + (0.28 ns/pF)CL - 20 40 ns 5V 10 ns + (1.00 ns/pF)CL - 60 120 ns 10 V 9 ns + (0.42 ns/pF)CL - 30 60 ns 15 V 6 ns + (0.28 ns/pF)CL - 20 40 ns The typical value of the propagation delay and output transition time can be calculated with the extrapolation formula (CL in pF). Table 8. Dynamic power dissipation VSS = 0 V; tr = tf  20 ns; Tamb = 25 C. Symbol Parameter PD dynamic power dissipation VDD Typical formula where: 5V PD = 450  fi + (fo  CL)  VDD (W) 2 fi = input frequency in MHz; 10 V PD = 2900  fi + (fo  CL)  VDD2 (W) fo = output frequency in MHz; 15 V PD = 11700  fi + (fo  CL)  VDD2 (W) CL = output load capacitance in pF; (fo  CL) = sum of the outputs; VDD = supply voltage in V. HEF4081B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 15 December 2015 © Nexperia B.V. 2017. All rights reserved 5 of 11 HEF4081B Nexperia Quad 2-input AND gate 11. Waveforms WU 9, WI  Q$Q%LQSXW 90 9  W3/+ 92+ W3+/  90 Q