Rev. 0.9, Sep. 2018
K4A4G165WF
Preliminary
4Gb F-die DDR4 SDRAM x16 only
96FBGA with Lead-Free & Halogen-Free
(RoHS compliant)
datasheet
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-1-
1.2V
datasheet
K4A4G165WF
Preliminary Rev. 0.9
DDR4 SDRAM
Revision History
Revision No.
0.0
History
- First SPEC release
Draft Date
Remark
Editor
12th Jul, 2018
Target
H.G.Lee
J.Y.Bae
0.9
- Preliminary datasheet.
19th Sep, 2018
- Update note for Output Driver DC Electrical Characteristics, assuming
RZQ=240ohm; entire operating temperature range; after proper ZQ calibration table.
- Add Output Driver Temperature and Voltage Sensitivity section.
- Update note for Input/Output capacitance.
- Update AC Timing table.
1. tDVWp : TBD -> 0.72 [UI] @ DDR-2933
2. tGEAR_setup/tGEAR_hold : TBD -> 2 [nCK] @ DDR-2933
3. Update notes.
-2-
Preliminary
H.G.Lee
J.Y.Bae
K4A4G165WF
datasheet
Preliminary Rev. 0.9
DDR4 SDRAM
Table Of Contents
4Gb F-die DDR4 SDRAM x16 only
1. ORDERING INFORMATION ............................................................................................................................................................... 4
2. KEY FEATURES ................................................................................................................................................................................. 4
3. PACKAGE PINOUT/MECHANICAL DIMENSION & ADDRESSING .................................................................................................. 5
3.1 x16 Package Pinout (Top view): 96ball FBGA Package.................................................................................................................5
3.2 FBGA Package Dimension (x16)....................................................................................................................................................6
4. INPUT/OUTPUT FUNCTIONAL DESCRIPTION ................................................................................................................................ 7
5. DDR4 SDRAM ADDRESSING ............................................................................................................................................................ 9
6. ABSOLUTE MAXIMUM RATINGS ...................................................................................................................................................... 10
6.1 DRAM Component Operating Temperature Range........................................................................................................................10
7. AC & DC OPERATING CONDITIONS ................................................................................................................................................ 10
8. AC AND DC INPUT MEASUREMENT LEVELS ................................................................................................................................. 11
8.1 AC And DC Logic Input Levels for Single-Ended Signals...............................................................................................................11
8.2 AC and DC Input Measurement Levels: VREF Tolerances............................................................................................................11
8.3 AC and DC Logic Input Levels for Differential Signals ...................................................................................................................12
8.3.1. Differential Signals Definition ..................................................................................................................................................12
8.3.2. Differential Swing Requirements for Clock (CK_t - CK_c) ......................................................................................................12
8.3.3. Single-ended Requirements for Differential Signals ...............................................................................................................13
8.3.4. Address, Command and Control Overshoot and Undershoot specifications..........................................................................14
8.3.5. Clock Overshoot and Undershoot Specifications....................................................................................................................15
8.3.6. Data, Strobe and Mask Overshoot and Undershoot Specifications........................................................................................16
8.4 Slew Rate Definitions......................................................................................................................................................................17
8.4.1. Slew Rate Definitions for Differential Input Signals (CK) ........................................................................................................17
8.4.2. Slew Rate Definition for Single-ended Input Signals (CMD/ADD) ..........................................................................................18
8.5 Differential Input Cross Point Voltage.............................................................................................................................................19
8.6 CMOS rail to rail Input Levels .........................................................................................................................................................20
8.6.1. CMOS rail to rail Input Levels for RESET_n ...........................................................................................................................20
8.7 AC and DC Logic Input Levels for DQS Signals.............................................................................................................................21
8.7.1. Differential signal definition .....................................................................................................................................................21
8.7.2. Differential swing requirements for DQS (DQS_t - DQS_c)....................................................................................................21
8.7.3. Peak voltage calculation method ............................................................................................................................................22
8.7.4. Differential Input Cross Point Voltage .....................................................................................................................................23
8.7.5. Differential Input Slew Rate Definition ....................................................................................................................................24
9. AC AND DC OUTPUT MEASUREMENT LEVELS ............................................................................................................................. 25
9.1 Output Driver DC Electrical Characteristics....................................................................................................................................25
9.1.1. Output Driver Temperature and Voltage Sensitivity................................................................................................................27
9.1.2. Alert_n output Drive Characteristic .........................................................................................................................................27
9.1.3. Output Driver Characteristic of Connectivity Test (CT) Mode.................................................................................................28
9.2 Single-ended AC & DC Output Levels............................................................................................................................................29
9.3 Differential AC & DC Output Levels................................................................................................................................................29
9.4 Single-ended Output Slew Rate .....................................................................................................................................................30
9.5 Differential Output Slew Rate .........................................................................................................................................................31
9.6 Single-ended AC & DC Output Levels of Connectivity Test Mode .................................................................................................32
9.7 Test Load for Connectivity Test Mode Timing ................................................................................................................................33
10. SPEED BIN ....................................................................................................................................................................................... 34
10.1 Speed Bin Table Note...................................................................................................................................................................41
11. IDD AND IDDQ SPECIFICATION PARAMETERS AND TEST CONDITIONS ................................................................................. 42
11.1 IDD, IPP and IDDQ Measurement Conditions..............................................................................................................................42
11.2 4Gb DDR4 SDRAM F-die IDD SPECIFICATION TABLE.............................................................................................................57
12. INPUT/OUTPUT CAPACITANCE ..................................................................................................................................................... 59
13. ELECTRICAL CHARACTERISTICS & AC TIMING .......................................................................................................................... 61
13.1 Reference Load for AC Timing and Output Slew Rate .................................................................................................................61
13.2 tREFI.............................................................................................................................................................................................61
13.3 Clock Specification .......................................................................................................................................................................62
13.3.1. Definition for tCK(abs)...........................................................................................................................................................62
13.3.2. Definition for tCK(avg)...........................................................................................................................................................62
13.3.3. Definition for tCH(avg) and tCL(avg)....................................................................................................................................62
13.3.4. Definition for tERR(nper).......................................................................................................................................................62
14. TIMING PARAMETERS BY SPEED GRADE ................................................................................................................................... 63
14.1 Rounding Algorithms ...................................................................................................................................................................69
14.2 The DQ input receiver compliance mask for voltage and timing ..................................................................................................70
14.3 Command, Control, and Address Setup, Hold, and Derating .......................................................................................................74
14.4 DDR4 Function Matrix ..................................................................................................................................................................76
-3-
Preliminary Rev. 0.9
datasheet
K4A4G165WF
DDR4 SDRAM
1. ORDERING INFORMATION
[Table 1] Samsung 4Gb DDR4 F-die ordering information table
Organization
DDR4-2666 (19-19-19) 2)
DDR4-3200 (22-22-22) 2)
Package
256Mx16
K4A4G165WF-BCTD
K4A4G165WF-BCWE
96FBGA
NOTE :
1) Speed bin is in order of CL-tRCD-tRP.
2) Backward compatible to lower frequency
3) 13th digit stands for below.
"C" : Commercial temp/Normal power
2. KEY FEATURES
[Table 2] 4Gb DDR4 F-die Speed bins
Speed
tCK(min)
DDR4-1600
DDR4-1866
DDR4-2133
DDR4-2400
DDR4-2666
DDR4-3200
11-11-11
13-13-13
15-15-15
17-17-17
19-19-19
22-22-22
1.25
1.071
0.937
0.833
0.75
0.625
ns
Unit
CAS Latency
11
13
15
17
19
22
nCK
tRCD(min)
13.75
13.92
14.06
14.16
14.25
13.75
ns
tRP(min)
13.75
13.92
14.06
14.16
14.25
13.75
ns
tRAS(min)
35
34
33
32
32
32
ns
tRC(min)
48.75
47.92
47.06
46.16
46.25
45.75
ns
• JEDEC standard 1.2V (1.14V~1.26V)
• VDDQ = 1.2V (1.14V~1.26V)
• VPP = 2.5V (2.375V~2.75V)
• 800 MHz fCK for 1600Mb/sec/pin,933 MHz fCK for 1866Mb/sec/pin,
1067MHz fCK for 2133Mb/sec/pin, 1200MHz fCK for 2400Mb/sec/pin,
1333MHz fCK for 2666Mb/sec/pin, 1600MHz fCK for 3200Mb/sec/pin
• 8 Banks (2 Bank Groups)
• Programmable CAS Latency (posted CAS):
10,11,12,13,14,15,16,17,18,19,20,22,24
• Programmable CAS Write Latency (CWL) = 9,11 (DDR4-1600), 10,12
(DDR4-1866),11,14 (DDR4-2133),12,16 (DDR4-2400), 14,18 (DDR42666) and 16,20 (DDR4-3200)
• 8-bit pre-fetch
• Burst Length: 8, 4 with tCCD = 4 which does not allow seamless read
or write [either On the fly using A12 or MRS]
• Bi-directional Differential Data-Strobe
• Internal (self) calibration: Internal self calibration through ZQ pin
(RZQ: 240 ohm ± 1%)
• On Die Termination using ODT pin
• Average Refresh Period 7.8us at lower than TCASE 85C, 3.9us at
85C < TCASE < 95 C
The 4Gb DDR4 SDRAM F-die is organized as a 32Mbit x 16 I/Os x 8banks
device. This synchronous device achieves high speed double-data-rate
transfer rates of up to 3200Mb/sec/pin (DDR4-3200) for general applications.
The chip is designed to comply with the following key DDR4 SDRAM features such as posted CAS, Programmable CWL, Internal (Self) Calibration,
On Die Termination using ODT pin and Asynchronous Reset.
All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the crosspoint of differential clocks (CK rising and CK falling). All I/Os are synchronized with a
pair of bidirectional strobes (DQS and DQS) in a source synchronous fashion. The address bus is used to convey row, column, and bank address
information in a RAS/CAS multiplexing style. The DDR4 device operates
with a single 1.2V (1.14V~1.26V) power supply, 1.2V(1.14V~1.26V) VDDQ
and 2.5V (2.375V~2.75V) VPP.
The 4Gb DDR4 F-die device is available in 96ball FBGAs(x16).
•
•
•
•
•
•
•
•
•
•
•
•
•
Asynchronous Reset
Package: 96 balls FBGA - x16
All of Lead-Free products are compliant for RoHS
All of products are Halogen-free
CRC (Cyclic Redundancy Check) for Read/Write data security
Command address parity check
DBI (Data Bus Inversion)
Gear down mode
POD (Pseudo Open Drain) interface for data input/output
Internal VREF for data inputs
External VPP for DRAM Activating Power
hPPR is supported
NOTE :
1) This data sheet is an abstract of full DDR4 specification and does not cover the common features which are described in “DDR4 SDRAM Device Operation & Timing
gram”.
2) The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation.
-4-
Dia-
Preliminary Rev. 0.9
datasheet
K4A4G165WF
DDR4 SDRAM
3. PACKAGE PINOUT/MECHANICAL DIMENSION & ADDRESSING
3.1 x16 Package Pinout (Top view): 96ball FBGA Package
1
2
3
A
VDDQ
VSSQ
B
VPP
C
VDDQ
D
4
5
6
7
8
9
DQU0
DQSU_c
VSSQ
VDDQ
A
VSS
VDD
DQSU_t
DQU1
VDD
B
DQU4
DQU2
DQU3
DQU5
VSSQ
C
VDD
VSSQ
DQU6
DQU7
VSSQ
VDDQ
D
E
VSS
DMU_n/
DBIU_n
VSSQ
DML_n
DBIL_n
VSSQ
VSS
E
F
VSSQ
VDDQ
DQSL_c
DQL1
VDDQ
ZQ
F
G
VDDQ
DQL0
DQSL_t
VDD
VSS
VDDQ
G
H
VSSQ
DQL4
DQL2
DQL3
DQL5
VSSQ
H
J
VDD
VDDQ
DQL6
DQL7
VDDQ
VDD
J
K
VSS
CKE
ODT
CK_t
CK_c
VSS
K
L
VDD
WE_n/
A14
ACT_n
CS_n
RAS_n
VDD
L
M
VREFCA
BG0
A10/AP
A12/BC_n
CAS_n
VSS
M
N
VSS
BA0
A4
A3
BA1
TEN
N
P
RESET_n
A6
A0
A1
A5
ALERT_n
P
R
VDD
A8
A2
A9
A7
VPP
R
T
VSS
A11
PAR
NC
A13
VDD
T
1
Ball Locations (x16)
A
B
C
Populated ball
Ball not populated
D
E
F
G
H
Top view
(See the balls through the package)
J
K
L
M
N
P
R
T
-5-
2
3
4
5
6
7
8
9
Preliminary Rev. 0.9
datasheet
K4A4G165WF
DDR4 SDRAM
3.2 FBGA Package Dimension (x16)
Units : Millimeters
7.50 0.10
0.80 x 8 = 6.40
0.80
1.60
#A1 INDEX MARK
3.20
B
0.40
0.80
(Datum B)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
0.80 x15 = 12.00
9 8 7 6 5 4 3 2 1
13.30 0.10
(Datum A)
A
96 - 0.48 Solder ball
(Post reflow 0.50 ± 0.05)
0.2 M A B
7.50 0.10
13.30 0.10
#A1
0.10MAX
BOTTOM VIEW
0.37 0.05
TOP VIEW
1.10 0.10
-6-
datasheet
K4A4G165WF
Preliminary Rev. 0.9
DDR4 SDRAM
4. INPUT/OUTPUT FUNCTIONAL DESCRIPTION
[Table 3] Input/Output function description
Symbol
Type
CK_t, CK_c
Input
Clock: CK_t and CK_c are differential clock inputs. All address and control input signals are sampled on
the crossing of the positive edge of CK_t and negative edge of CK_c.
CKE, (CKE1)
Input
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input
buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self-Refresh operation
(all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for Self-Refresh exit.
After VREFCA and Internal DQ Vref have become stable during the power on and initialization sequence,
they must be maintained during all operations (including Self-Refresh). CKE must be maintained high
throughout read and write accesses. Input buffers, excluding CK_t, CK_cSGODT and CKE are disabled
during power-down. Input buffers, excluding CKE, are disabled during Self-Refresh.
CS_n, (CS1_n)
Input
Chip Select: All commands are masked when CS_n is registered HIGH. CS_n provides for external Rank
selection on systems with multiple Ranks. CS_n is considered part of the command code.
C0,C1,C2
Input
Chip ID : Chip ID is only used for 3DS for 2,4,8high stack via TSV to select each slice of stacked
component. Chip ID is considered part of the command code
ODT, (ODT1)
Input
On Die Termination: ODT (registered HIGH) enables RTT_NOM termination resistance internal to the
DDR4 SDRAM. When enabled, ODT is only applied to each DQ, DQS_t, DQS_c and DM_n/DBI_n/
TDQS_t, NU/TDQS_c (When TDQS is enabled via Mode Register A11=1 in MR1) signal for x8
configurations. For x16 configuration ODT is applied to each DQ, DQSU_t, DQSU_c, DQSL_t, DQSL_c,
DMU_n, and DML_n signal. The ODT pin will be ignored if MR1 is programmed to disable RTT_NOM.
ACT_n
Input
Activation Command Input : ACT_n defines the Activation command being entered along with CS_n. The
input into RAS_n/A16, CAS_n/A15 and WE_n/A14 will be considered as Row Address A16, A15 and A14
Input
Command Inputs: RAS_n/A16, CAS_n/A15 and WE_n/A14 (along with CS_n) define the command being
entered. Those pins have multi function. ForG example, for activation with ACT_n Low, those are
Addressing like A16,A15 and A14 but for non-activation command with ACT_n High, those are Command
pins for Read, Write and other command defined in command truth table
DM_n/DBI_n/TDQS_t,
(DMU_n/DBIU_n),
(DML_n/DBIL_n)
Input/Output
Input Data Mask and Data Bus Inversion: DM_n is an input mask signal for write data. Input data is masked
when DM_n is sampled LOW coincident with that input data during a Write access. DM_n is sampled on
both edges of DQS. DM is muxed with DBI function by Mode Register A10,A11,A12 setting in MR5. For x8
device, the function of DM or TDQS is enabled by Mode Register A11 setting in MR1. DBI_n is an input/
output identifing whether to store/output the true or inverted data. If DBI_n is LOW, the data will be stored/
output after inversion inside the DDR4 SDRAM and not inverted if DBI_n is HIGH. TDQS is only supported
in X8
BG0 - BG1
Input
Bank Group Inputs : BG0 - BG1 define to which bank group an Active, Read, Write or Precharge command
is being applied. BG0 also determines which mode register is to be accessed during a MRS cycle. X4/8
have BG0 and BG1 but X16 has only BG0
BA0 - BA1
Input
Bank Address Inputs: BA0 - BA1 define to which bank an Active, Read, Write or Precharge command is
being applied. Bank address also determines which mode register is to be accessed during a MRS cycle.
Input
Address Inputs: Provide the row address for ACTIVATE Commands and the column address for Read/
Write commands to select one location out of the memory array in the respective bank. (A10/AP, A12/
BC_n, RAS_n/A16, CAS_n/A15 and WE_n/A14 have additional functions, see other rows.The address
inputs also provide the op-code during Mode Register Set commands.A17 is only defined for the x4
configurations.
A10 / AP
Input
Auto-precharge: A10 is sampled during Read/Write commands to determine whether Autoprecharge
should be performed to the accessed bank after the Read/Write operation. (HIGH: Autoprecharge; LOW:
no Autoprecharge).A10 is sampled during a Precharge command to determine whether the Precharge
applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is
selected by bank addresses.
A12 / BC_n
Input
Burst Chop: A12 / BC_n is sampled during Read and Write commands to determine if burst chop (on-thefly) will be performed. (HIGH, no burst chop; LOW: burst chopped). See command truth table for details.
RESET_n
Input
Active Low Asynchronous Reset: Reset is active when RESET_n is LOW, and inactive when RESET_n is
HIGH. RESET_n must be HIGH during normal operation. RESET_n is a CMOS rail to rail signal with DC
high and low at 80% and 20% of VDD.
Input / Output
Data Input/ Output: Bi-directional data bus. If CRC is enabled via Mode register then CRC code is added at
the end of Data Burst. Any DQ from DQ0~DQ3 may indicate the internal Vref level during test via Mode
Register Setting MR4 A4=High. During this mode, RTT value should be set to Hi-Z. Refer to vendor
specific datasheets to determine which DQ is used.
RAS_n/A16. CAS_n/
A15. WE_n/A14
A0 - A17
DQ
Function
-7-
datasheet
K4A4G165WF
Preliminary Rev. 0.9
DDR4 SDRAM
[Table 3] Input/Output function description
Symbol
DQS_t, DQS_c,
DQSU_t, DQSU_c,
DQSL_t, DQSL_c
TDQS_t, TDQS_c
PAR
ALERT_n
TEN
Type
Function
Input / Output
Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered in write
data. For the x16, DQSL corresponds to the data on DQL0-DQL7; DQSU corresponds to the data on
DQU0-DQU7. The data strobe DQS_t, DQSL_t and DQSU_t are paired with differential signals DQS_c,
DQSL_c, and DQSU_c, respectively, to provide differential pair signaling to the system during reads and
writes. DDR4 SDRAM supports differential data strobe only and does not support single-ended.
Output
Termination Data Strobe: TDQS_t/TDQS_c is applicable for x8 DRAMs only. When enabled via Mode
Register A11 = 1 in MR1, the DRAM will enable the same termination resistance function on TDQS_t/
TDQS_c that is applied to DQS_t/DQS_c. When disabled via mode register A11 = 0 in MR1, DM/DBI/
TDQS will provide the data mask function or Data Bus Inversion depending on MR5; A11,12,10and
TDQS_c is not used. x4/x16 DRAMs must disable the TDQS function via mode register A11 = 0 in MR1.
Input
Command and Address Parity Input: DDR4 Supports Even Parity check in DRAM with MR setting. Once
it’s enabled via Register in MR5, then DRAM calculates Parity with ACT_n,RAS_n/A16,CAS_n/A15,WE_n/
A14,BG0-BG1,BA0-BA1,A17-A0, and C0-C2 (3DS devices). Command and address inputs shall have
parity check performed when commands are latched via the rising edge of CK_t and when CS_n is low.
Input/Output
Alert : It has multi functions such as CRC error flag, Command and Address Parity error flag as Output
signal. If there is error in CRC, then Alert_n goes LOW for the period time interval and goes back HIGH. If
there is error in Command Address Parity Check, then Alert_n goes LOW for relatively long period until on
going DRAM internal recovery transaction to complete. During Connectivity Test mode, this pin works as
input. Using this signal or not is dependent on system. In case of not connected as Signal, ALERT_n Pin
must be bounded to VDD on board.
Input
Connectivity Test Mode Enable: Required on X16 devices and optional input on x4/x8 with densities equal
to or greater than 8Gb.HIGH in this pin will enable Connectivity Test Mode operation along with other pins.
It is a CMOS rail to rail signal with AC high and low at 80% and 20% of VDD. Using this signal or not is
dependent on System. This pin may be DRAM internally pulled low through a weak pull-down resistor to
VSS.
No Connect: No internal electrical connection is present.
NC
VDDQ
Supply
DQ Power Supply: 1.2 V +/- 0.06 V
VSSQ
Supply
DQ Ground
VDD
Supply
Power Supply: 1.2 V +/- 0.06 V
VSS
Supply
Ground
VPP
Supply
DRAM Activating Power Supply: 2.5V (2.375V min, 2.75V max)
VREFCA
Supply
Reference voltage for CA
ZQ
Supply
Reference Pin for ZQ calibration
NOTE :
1) Input only pins (BG0-BG1,BA0-BA1, A0-A17, ACT_n, RAS_n/A16, CAS_n/A15, WE_n/A14, CS_n, CKE, ODT, and RESET_n) do not supply termination.
-8-
datasheet
K4A4G165WF
Preliminary Rev. 0.9
DDR4 SDRAM
5.0 DDR4 SDRAM ADDRESSING
2Gb Addressing Table
Configuration
128Mb x16
# of Bank Groups
2
BG Address
BG0
Bank Address in a BG
BA0~BA1
Bank Address
Row Address
A0~A13
Column Address
A0~A9
Page size
2KB
4Gb Addressing Table
Configuration
256Mb x16
# of Bank Groups
Bank Address
2
BG Address
BG0
Bank Address in a BG
BA0~BA1
Row Address
A0~A14
Column Address
A0~A9
Page size
2KB
8Gb Addressing Table
Configuration
512Mb x16
# of Bank Groups
Bank Address
2
BG Address
BG0
Bank Address in a BG
BA0~BA1
Row Address
A0~A15
Column Address
A0~A9
Page size
2KB
NOTE :
1) Page size is the number of bytes of data delivered from the array to the internal sense amplifiers when an ACTIVE command is registered.
Page size is per bank, calculated as follows:
page size = 2 COLBITS * ORG8
where, COLBITS = the number of column address bits,
ORG = the number of I/O (DQ) bits
-9-
Preliminary Rev. 0.9
datasheet
K4A4G165WF
DDR4 SDRAM
6.0 ABSOLUTE MAXIMUM RATINGS
[Table 4] Absolute Maximum DC Ratings
Symbol
VDD
VDDQ
VPP
VIN, VOUT
TSTG
Parameter
Rating
Units
NOTE
Voltage on VDD pin relative to Vss
-0.3 ~ 1.5
V
1,3
Voltage on VDDQ pin relative to Vss
-0.3 ~ 1.5
V
1,3
Voltage on VPP pin relative to Vss
-0.3 ~ 3.0
V
4
Voltage on any pin except VREFCA relative to Vss
-0.3 ~ 1.5
V
1,3,5
-55 to +100
°C
1,2
Storage Temperature
NOTE :
1) Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability
2) Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.
3) VDD and VDDQ must be within 300mV of each other at all times; and VREFCA must be not greater than 0.6 x VDDQ, When VDD and VDDQ are less than 500mV; VREFCA
may be equal to or less than 300mV
4) VPP must be equal or greater than VDD/VDDQ at all times.
5) Overshoot area above 1.5 V is specified in 8.3.4 Address, Command and Control Overshoot and Undershoot specifications, 8.3.5 Clock Overshoot and Undershoot
Specifications and 8.3.6 Data, Strobe and Mask Overshoot and Undershoot Specifications.
6.1 DRAM Component Operating Temperature Range
[Table 5] Temperature Range
Symbol
Parameter
rating
Unit
NOTE
TOPER
Operating Temperature Range
0 to 95
C
1, 2, 3
NOTE :
1) Operating Temperature TOPER is the case surface temperature on the center/top side of the DRAM.
2) The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0-85°C under all operating conditions.
3) Some applications require operation of the Extended Temperature Range between 85°C and 95°C case temperature. Full specifications are guaranteed in this range, but the
following additional conditions apply:
a) Refresh commands must be doubled in frequency, therefore reducing the refresh interval tREFI to 3.9us.
b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature
Range capability (MR2 A6 = 0b and MR2 A7 = 1b), in this case IDD6 current can be increased around 10~20% than normal Temperature range.
7.0 AC & DC OPERATING CONDITIONS
[Table 6] Recommended DC Operating Conditions
Symbol
Parameter
Rating
Min.
Typ.
Max.
Unit
NOTE
VDD
Supply Voltage
1.14
1.2
1.26
V
1,2,3
VDDQ
Supply Voltage for Output
1.14
1.2
1.26
V
1,2,3
VPP
Peak-to-Peak Voltage
2.375
2.5
2.75
V
3
NOTE :
1) Under all conditions VDDQ must be less than or equal to VDD.
2) VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
3) DC bandwidth is limited to 20MHz.
- 10 -
Preliminary Rev. 0.9
datasheet
K4A4G165WF
DDR4 SDRAM
8.0 AC AND DC INPUT MEASUREMENT LEVELS
8.1 AC And DC Logic Input Levels for Single-Ended Signals
[Table 7] Single-ended AC and DC Input Levels for Command and Address
Symbol
VIH.CA(DC75)
VIH.CA(DC65)
VIL.CA(DC75)
VIL.CA(DC65)
VIH.CA(AC100)
VIH.CA(AC90)
VIL.CA(AC100)
VIL.CA(AC90)
VREFCA(DC)
Parameter
DC input logic high
DC input logic low
AC input logic high
AC input logic low
Reference Voltage for ADD, CMD inputs
DDR4-1600/1866/2133/2400
DDR4-2666/2933/3200
Min.
Max.
Min.
Max.
VREFCA+ 0.075
VDD
-
-
-
-
VREFCA+ 0.065
VDD
VSS
VREFCA-0.075
-
-
-
-
VSS
VREFCA-0.065
VREF + 0.1
Note 2
-
-
-
-
VREF + 0.09
Note 2
Note 2
VREF - 0.1
-
-
-
-
Note 2
VREF - 0.09
0.49*VDD
0.51*VDD
0.49*VDD
0.51*VDD
Unit
NOTE
V
V
V
V
V
1
1
2,3
NOTE :
1) See “Overshoot and Undershoot Specifications” on section 8.3 AC and DC Logic Input Levels for Differential Signals.
2) The AC peak noise on VREFCA may not allow VREFCA to deviate from VREFCA(DC) by more than ± 1% VDD (for reference : approx. ± 12mV)
3) For reference : approx. VDD/2 ± 12mV.
8.2 AC and DC Input Measurement Levels: VREF Tolerances.
The DC-tolerance limits and ac-noise limits for the reference voltages VREFCA is illustrated in Figure 1. It shows a valid reference voltage VREF(t) as a
function of time. (VREF stands for VREFCA).
VREF(DC) is the linear average of VREF(t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirement in Table 7.
Furthermore VREF(t) may temporarily deviate from VREF(DC) by no more than ± 1% VDD.
voltage
VDD
VSS
time
Figure 1. Illustration of VREF(DC) tolerance and VREF AC-noise limits
The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on VREF.
"VREF" shall be understood as VREF(DC), as defined in Figure 1.
This clarifies, that DC-variations of VREF affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to
which setup and hold is measured. System timing and voltage budgets need to account for VREF(DC) deviations from the optimum position within the
data-eye of the input signals.
This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with VREF AC-noise. Timing
and voltage effects due to AC-noise on VREF up to the specified limit (+/-1% of VDD) are included in DRAM timings and their associated deratings.
- 11 -
Preliminary Rev. 0.9
datasheet
K4A4G165WF
DDR4 SDRAM
8.3 AC and DC Logic Input Levels for Differential Signals
8.3.1 Differential Signals Definition
tDVAC
VIH.DIFF.AC.MIN
Differential Input Voltage (CK-CK)
(CK_t - CK_c)
VIH.DIFF.MIN
0.0
half cycle
VIL.DIFF.MAX
VIL.DIFF.AC.MAX
tDVAC
time
Figure 2. Definition of differential ac-swing and “time above ac-level” tDVAC
NOTE:
1) Differential signal rising edge from VIL.DIFF.MAX to VIH.DIFF.MIN must be monotonic slope.
2) Differential signal falling edge from VIH.DIFF.MIN to VIL.DIFF.MAX must be monotonic slope.
8.3.2 Differential Swing Requirements for Clock (CK_t - CK_c)
[Table 8] Differential AC and DC Input Levels
Symbol
Parameter
DDR4 -1600/1866/2133
Min
Max
DDR4 -2400
DDR4-2666
Min
Max
Min
Max
DDR4-2933
Min
Max
DDR4-3200
Min
Max
uni NOT
t
E
VIHdiff
differential input high
+0.150
NOTE 3
+0.135
NOTE 3
+0.135
NOTE 3
+0.125
NOTE 3
TBD
NOTE 3
V
1
VILdiff
differential input low
NOTE 3
-0.150
NOTE 3
-0.135
NOTE 3
-0.135
NOTE 3
-0.125
NOTE 3
TBD
V
1
NOTE 3
2 x (VIH(AC) VREF)
NOTE 3
2 x (VIH(AC) VREF)
NOTE 3
2 x (VIH(AC) VREF)
NOTE 3
2 x (VIH(AC) VREF)
NOTE 3
V
2
2 x (VIL(AC) VREF)
NOTE 3
2 x (VIL(AC) VREF)
NOTE 3
2 x (VIL(AC) VREF)
NOTE 3
2 x (VIL(AC) VREF)
NOTE 3
2 x (VIL(AC) VREF)
V
2
VIHdiff(AC)
2 x (VIH(AC) differential input high ac
VREF)
VILdiff(AC)
differential input low ac
NOTE 3
NOTE :
1) Used to define a differential signal slew-rate.
2) for CK_t - CK_c use VIH.CA/VIL.CA(AC) of ADD/CMD and VREFCA;
3) These values are not defined; however, the differential signals CK_t - CK_c, need to be within the respective limits (VIH.CA(DC) max, VIL.CA(DC)min) for single-ended signals
as well as the limitations for overshoot and undershoot.
[Table 9] Allowed Time Before Ringback (tDVAC) for CK_t - CK_c
Slew Rate [V/ns]
tDVAC [ps] @ |VIH/Ldiff(AC)| = 200mV
min
max
> 4.0
120
-
4.0
115
-
3.0
110
-
2.0
105
-
1.8
100
-
1.6
95
-
1.4
90
-
1.2
85
-
1.0
80
-
< 1.0
80
-
- 12 -
Preliminary Rev. 0.9
datasheet
K4A4G165WF
DDR4 SDRAM
8.3.3 Single-ended Requirements for Differential Signals
Each individual component of a differential signal (CK_t, CK_c) has also to comply with certain requirements for single-ended signals.
CK_t and CK_c have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels (VIH.CA(AC) / VIL.CA(AC)) for ADD/CMD
signals) in every half-cycle.
Note that the applicable ac-levels for ADD/CMD might be different per speed-bin etc. E.g., if Different value than VIH.CA(AC100)/VIL.CA(AC100) is used
for ADD/CMD signals, then these ac-levels apply also for the single-ended signals CK_t and CK_c.
VDD or VDDQ
VSEH min
VSEH
VDD/2 or VDDQ/2
CK
VSEL max
VSEL
VSS or VSSQ
time
Figure 3. Single-ended requirement for differential signals.
Note that, while ADD/CMD signal requirements are with respect to VrefCA, the single-ended components of differential signals have a requirement with
respect to VDD / 2; this is nominally the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For singleended components of differential signals the requirement to reach VSELmax, VSEHmin has no bearing on timing, but adds a restriction on the common
mode characteristics of these signals.
[Table 10] Single-ended Levels for CK_t, CK_c
Symbol
Parameter
VSEH
VSEL
DDR4-1600/1866/2133
DDR4-2400/2666
DDR4-2933
DDR4-3200
Un NOT
it
E
Min
Max
Min
Max
Min
Max
Min
Max
Single-ended high-level
for CK_t, CK_c
(VDD/
2)+0.100
NOTE3
(VDD/
2)+0.95
NOTE3
(VDD/
2)+0.85
NOTE3
TBD
NOTE3
V
1, 2
Single-ended low-level
for CK_t, CK_c
NOTE3
(VDD/2)0.100
NOTE3
(VDD/2)0.95
NOTE3
(VDD/2)0.85
NOTE3
TBD
V
1, 2
NOTE :
1) For CK_t - CK_c use VIH.CA/VIL.CA(AC) of ADD/CMD;
2) VIH(AC)/VIL(AC) for ADD/CMD is based on VREFCA;
3) These values are not defined, however the single-ended signals CK_t - CK_c need to be within the respective limits (VIH.CA(DC) max, VIL.CA(DC)min) for single-ended
signals as well as the limitations for overshoot and undershoot.
- 13 -
Preliminary Rev. 0.9
datasheet
K4A4G165WF
DDR4 SDRAM
8.3.4 Address, Command and Control Overshoot and Undershoot specifications
[Table 11] AC overshoot/undershoot specification for Address, Command and Control pins
Symbol
Parameter
Specification
DDR41600
DDR41866
DDR42133
DDR42400
DDR42666
DDR42933
DDR43200
Unit
Maximum peak amplitude above VAOS
VAOSP
0.06
V
Upper boundary of overshoot area AAOS1
VAOS
VDD +0.24
V
Maximum peak amplitude allowed for undershoot
VAUS
0.30
V
Maximum overshoot area per 1 tCK above VAOS
AAOS2
0.0083
0.0071
0.0062
0.0055
0.0055
0.0055
0.0055
V-ns
Maximum overshoot area per 1 tCK between VDD
AAOS1
and VAOS
0.2550
0.2185
0.1914
0.1699
0.1699
0.1699
0.1699
V-ns
AAUS
0.2644
0.2265
0.1984
0.1762
0.1762
0.1762
0.1762
V-ns
Maximum undershoot area per 1 tCK below VSS
NOT
E
1
(A0-A13,A17,BG0-BG1,BA0-BA1,ACT_n,RAS_n/A16,CAS_n/A15,WE_n/A14,CS_n,CKE,ODT,C2-C0)
NOTE :
1) The value of VAOS matches VDD absolute max as defined in Table 4 Absolute Maximum DC Ratings if VDD equals VDD max as defined in Table 6 Recommended DC
Operating Conditions. If VDD is above the recommended operating conditions, VAOS remains at VDD absolute max as defined in Table 4.
VAOSP
VAOS
Volts
(V)
VDD
AAOS2
AAOS1
1 tCK
VSS
AAUS
VAUS
Figure 4. Address, Command and Control Overshoot and Undershoot Definition
- 14 -
Preliminary Rev. 0.9
datasheet
K4A4G165WF
DDR4 SDRAM
8.3.5 Clock Overshoot and Undershoot Specifications
[Table 12] AC overshoot/undershoot specification for Clock
Symbol
Parameter
Specification
DDR41600
DDR41866
DDR42133
DDR42400
DDR42666
DDR42933
DDR43200
Unit
Maximum peak amplitude above VCOS
VCOSP
0.06
V
Upper boundary of overshoot area ADOS1
VCOS
VDD +0.24
V
Maximum peak amplitude allowed for undershoot
VCUS
0.30
V
Maximum overshoot area per 1 UI above VCOS
ACOS2
0.0038
0.0032
0.0028
0.0025
0.0025
0.0025
0.0025
V-ns
Maximum overshoot area per 1 UI between VDD
ACOS1
and VDOS
0.1125
0.0964
0.0844
0.0750
0.0750
0.0750
0.0750
V-ns
ACUS
0.1144
0.0980
0.0858
0.0762
0.0762
0.0762
0.0762
V-ns
Maximum undershoot area per 1 UI below VSS
NOT
E
1
(CK_t, CK_c)
NOTE :
1) The value of VCOS matches VDD absolute max as defined in Table 4 Absolute Maximum DC Ratings if VDD equals VDD max as defined in Table 6 Recommended DC
Operating Conditions. If VDD is above the recommended operating conditions, VCOS remains at VDD absolute max as defined in Table 4.
VCOSP
VCOS
Volts
(V)
VDD
ACOS2
ACOS1
1 UI
VSS
ACUS
VCUS
Figure 5. Clock Overshoot and Undershoot Definition
- 15 -
Preliminary Rev. 0.9
datasheet
K4A4G165WF
DDR4 SDRAM
8.3.6 Data, Strobe and Mask Overshoot and Undershoot Specifications
[Table 13] AC overshoot/undershoot specification for Data, Strobe and Mask
Specification
Parameter
Symbol
DDR41600
DDR41866
DDR42133
DDR42400
DDR42666
DDR42933
DDR43200
Unit
NOT
E
Maximum peak amplitude above VDOS
VDOSP
0.16
V
Upper boundary of overshoot area ADOS1
VDOS
VDDQ + 0.24
V
1
Lower boundary of undershoot area ADUS1
VDUS
0.30
V
2
Maximum peak amplitude below VDUS
VDUSP
0.10
0.10
0.10
0.10
0.10
0.10
0.10
V
Maximum overshoot area per 1 UI above VDOS
ADOS2
0.0150
0.0129
0.0113
0.0100
0.0100
0.0100
0.0100
V-ns
Maximum overshoot area per 1 UI between
VDDQ and VDOS
ADOS1
0.1050
0.0900
0.0788
0.0700
0.0700
0.0700
0.0700
V-ns
Maximum undershoot area per 1 UI between
VSSQ and VDUS1
ADUS1
0.1050
0.0900
0.0788
0.0700
0.0700
0.0700
0.0700
V-ns
Maximum undershoot area per 1 UI below VDUS
ADUS2
0.0150
0.0129
0.0113
0.0100
0.0100
0.0100
0.0100
V-ns
NOTE :
1) The value of VDOS matches (VIN, VOUT) max as defined in Table 4 Absolute Maximum DC Ratings if VDDQ equals VDDQ max as defined in Table 6 Recommended DC
Operating Conditions. If VDDQ is above the recommended operating conditions, VDOS remains at (VIN, VOUT) max as defined in Table 4.
2) The value of VDUS matches (VIN, VOUT) min as defined in Table 4 Absolute Maximum DC Ratings
VDOSP
VDOS
Volts
(V)
VDDQ
ADOS2
ADOS1
1 UI
VSSQ
ADUS1
VDUSP
ADUS2
Figure 6. Data, Strobe and Mask Overshoot and Undershoot Definition
- 16 -
Preliminary Rev. 0.9
datasheet
K4A4G165WF
DDR4 SDRAM
8.4 Slew Rate Definitions
8.4.1 Slew Rate Definitions for Differential Input Signals (CK)
Input slew rate for differential signals (CK_t, CK_c) are defined and measured as shown in Table 14 and Figure 7.
[Table 14] Differential Input Slew Rate Definition
Measured
Description
Defined by
from
to
Differential input slew rate for rising edge (CK_t - CK_c)
VILdiffmax
VIHdiffmin
[VIHdiffmin - VILdiffmax] / DeltaTRdiff
Differential input slew rate for falling edge (CK_t - CK_c)
VIHdiffmin
VILdiffmax
[VIHdiffmin - VILdiffmax] / DeltaTFdiff
NOTE :
1) The differential signal (i,e.,CK_t - CK_c) must be linear between these thresholds.
Differential Input Voltage(i,e, CK_t - CK_c)
Delta TRdiff
VIHdiffmin
0
VILdiffmax
Delta TFdiff
Figure 7. Differential Input Slew Rate Definition for CK_t, CK_c
- 17 -
Preliminary Rev. 0.9
datasheet
K4A4G165WF
DDR4 SDRAM
8.4.2 Slew Rate Definition for Single-ended Input Signals (CMD/ADD)
Delta TRsingle
V
IHCA(AC) Min
V
IHCA(DC) Min
VREFCA(DC)
V
ILCA(DC) Max
V
ILCA(AC) Max
Delta TFsingle
Figure 8. Single-ended Input Slew Rate definition for CMD and ADD
NOTE :
1) Single-ended input slew rate for rising edge = {VIHCA(AC)Min - VILCA(DC)Max} / Delta TR single.
2) Single-ended input slew rate for falling edge = {VIHCA(DC)Min - VILCA(AC)Max} / Delta TF single.
3) Single-ended signal rising edge from VILCA(DC)Max to VIHCA(DC)Min must be monotonic slope.
4) Single-ended signal falling edge from VIHCA(DC)Min to VILCA(DC)Max must be monotonic slope.
- 18 -
Preliminary Rev. 0.9
datasheet
K4A4G165WF
DDR4 SDRAM
8.5 Differential Input Cross Point Voltage
To guarantee tight setup and hold times as well as output skew parameters with respect to clock, each cross point voltage of differential input signals
(CK_t, CK_c) must meet the requirements in Table 15. The differential input cross point voltage VIX is measured from the actual cross point of true and
complement signals to the midlevel between of VDD and VSS.
VDD
CK_t
Vix
VDD/2
Vix
CK_c
VSEL
VSEH
VSS
Figure 9. Vix Definition (CK)
[Table 15] Cross Point Voltage for Differential Input Signals (CK)
Symbol
-
VlX(CK)
Symbol
-
VlX(CK)
Symbol
-
VlX(CK)
DDR4-1600/1866/2133
Parameter
Area of VSEH, VSEL
Differential Input Cross Point Voltage relative to
VDD/2 for CK_t, CK_c
min
VSEL < VDD/2 145mV
VDD/2 + 100mV
VDD/2 + 145mV <
=< VSEH =< VDD/
VSEH
2 + 145mV
-120mV
-(VDD/2 - VSEL) +
25mV
(VSEH - VDD/2) 25mV
Differential Input Cross Point Voltage relative to
VDD/2 for CK_t, CK_c
min
Differential Input Cross Point Voltage relative to
VDD/2 for CK_t, CK_c
max
VSEL <
VDD/2 - 145 mV
VDD/2 - 145 mV
=< VSEL =<
VDD/2 - 100 mV
VDD/2 + 100 mV
=< VSEH =<
VDD/2 + 145 mV
VDD/2 + 145 mV <
VSEH
-120mV
- (VDD/2 - VSEL) +
25 mV
(VSEH - VDD/2) 25 mV
120mV
DDR4-2666/2933/3200
Parameter
Area of VSEH, VSEL
120mV
DDR4-2400
Parameter
Area of VSEH, VSEL
max
VDD/2 - 145mV =<
VSEL =< VDD/2 100mV
min
max
VSEL <
VDD/2 - 145 mV
VDD/2 - 145 mV
=< VSEL =<
VDD/2 - 100 mV
VDD/2 + 100 mV
=< VSEH =<
VDD/2 + 145 mV
VDD/2 + 145 mV
< VSEH
-110 mV
- (VDD/2 - VSEL)
+ 30 mV
(VSEH - VDD/2)
- 30 mV
110mV
- 19 -
Preliminary Rev. 0.9
datasheet
K4A4G165WF
DDR4 SDRAM
8.6 CMOS rail to rail Input Levels
8.6.1 CMOS rail to rail Input Levels for RESET_n
[Table 16] CMOS rail to rail Input Levels for RESET_n
Parameter
Symbol
Min
Max
Unit
NOTE
AC Input High Voltage
VIH(AC)_RESET
0.8*VDD
VDD
V
6
DC Input High Voltage
VIH(DC)_RESET
0.7*VDD
VDD
V
2
DC Input Low Voltage
VIL(DC)_RESET
VSS
0.3*VDD
V
1
AC Input Low Voltage
VIL(AC)_RESET
VSS
0.2*VDD
V
7
Rising time
TR_RESET
-
1.0
us
4
RESET pulse width
tPW_RESET
1.0
-
us
3,5
NOTE :
1) After RESET_n is registered LOW, RESET_n level shall be maintained below VIL(DC)_RESET during tPW_RESET, otherwise, SDRAM may not be reset.
2) Once RESET_n is registered HIGH, RESET_n level must be maintained above VIH(DC)_RESET, otherwise, SDRAM operation will not be guaranteed until it is reset
asserting RESET_n signal LOW.
3) RESET is destructive to data contents.
4) No slope reversal (ringback) requirement during its level transition from Low to High.
5) This definition is applied only “Reset Procedure at Power Stable”.
6) Overshoot might occur. It should be limited by the Absolute Maximum DC Ratings.
7) Undershoot might occur. It should be limited by Absolute Maximum DC Ratings.
tPW_RESET
0.8*VDD
0.7*VDD
0.3*VDD
0.2*VDD
TR_RESET
Figure 10. RESET_n Input Slew Rate Definition
- 20 -
Preliminary Rev. 0.9
datasheet
K4A4G165WF
DDR4 SDRAM
8.7 AC and DC Logic Input Levels for DQS Signals
8.7.1 Differential signal definition
Figure 11. Definition of differential DQS Signal AC-swing Level
8.7.2 Differential swing requirements for DQS (DQS_t - DQS_c)
[Table 17] Differential AC and DC Input Levels for DQS
Symbol
Parameter
DDR4-1600/1866/
2133
DDR4-2400
DDR4-2666
DDR4-2933
DDR4-3200
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Unit Note
VIHDiffPeak
VIH.DIFF.Peak Voltage
186
Note2
160
Note2
150
Note2
145
Note2
140
Note2
mV
1
VILDiffPeak
VIL.DIFF.Peak Voltage
Note2
-186
Note2
-160
Note2
-150
-145
Note2
-140
Note2
mV
1
NOTE :
1) Used to define a differential signal slew-rate.
2) These values are not defined; however, the differential signals DQS_t - DQS_c, need to be within the respective limits Overshoot, Undershoot Specification for single-ended
signals.
- 21 -
Preliminary Rev. 0.9
datasheet
K4A4G165WF
DDR4 SDRAM
8.7.3 Peak voltage calculation method
The peak voltage of Differential DQS signals are calculated in a following equation.
VIH.DIFF.Peak Voltage = Max(f(t))
VIL.DIFF.Peak Voltage = Min(f(t))
f(t) = VDQS_t - VDQS_c
Single Ended Input Voltage : DQS_t and DQS_c
The Max(f(t)) or Min(f(t)) used to determine the midpoint which to reference the +/-35% window of the exempt non-monotonic signaling shall be the smallest peak voltage observed in all ui’s.
DQS_t
Max(f(t))
Min(f(t))
+35%
+35%
DQS_c
Time
Figure 12. Definition of differential DQS Peak Voltage and rage of exempt non-monotonic signaling
- 22 -
+50%
+50%
Preliminary Rev. 0.9
datasheet
K4A4G165WF
DDR4 SDRAM
8.7.4 Differential Input Cross Point Voltage
To achieve tight RxMask input requirements as well as output skew parameters with respect to strobe, the cross point voltage of differential input signals
(DQS_t, DQS_c) must meet the requirements in Table 18. The differential input cross point voltage VIX_DQS (VIX_DQS_FR and VIX_DQS_RF) is
measured from the actual cross point of DQS_t, DQS_c relative to the VDQSmid of the DQS_t and DQS_c signals.
VDQSmid is the midpoint of the minimum levels achieved by the transitioning DQS_t and DQS_c signals, and noted by VDQS_trans. VDQS_trans is the
difference between the lowest horizontal tangent above VDQSmid of the transitioning DQS signals and the highest horizontal tangent below VDQSmid of
the transitioning DQS signals.
A non-monotonic transitioning signal’s ledge is exempt or not used in determination of a horizontal tangent provided the said ledge occurs within +/- 35%
of the midpoint of either VIH.DIFF.Peak Voltage (DQS_t rising) or VIL.DIFF.Peak Voltage (DQS_c rising), refer to Figure 12. A secondary horizontal tangent resulting from a ring-back transition is also exempt in determination of a horizontal tangent. That is, a falling transition’s horizontal tangent is derived
from its negative slope to zero slope transition (point A in Figure 13) and a ring-back’s horizontal tangent derived from its positive slope to zero slope transition (point B in Figure 13) is not a valid horizontal tangent; and a rising transition’s horizontal tangent is derived from its positive slope to zero slope transition (point C in Figure 13) and a ring-back’s horizontal tangent derived from its negative slope to zero slope transition (point D in Figure 13) is not a valid
horizontal tangent
C
DQS_t
VIX_DQS,RF
VIX_DQS,FR
VDQSmid
VIX_DQS,RF
VIX_DQS,FR
B
DQS_c
VDQS_trans
D
VDQS_trans/2
DQS_t,DQS_c : Single-ended Input Voltages
Lowest horizontal tangent above VDQSmid of the transitioning signals
A
Highest horizontal tanget below VDQSmid of the transitioning signals
VSSQ
Figure 13. Vix Definition (DQS)
[Table 18] Cross point voltage for DQS differential input signals
Symbol
Vix_DQS_ratio
DDR4-1600/1866/2133/
2400
Parameter
DQS_t and DQS_c crossing relative to the midpoint of
the DQS_t and DQS_c signal swings
VDQSmid_to_Vcent VDQSmid offset relative to Vcent_DQ(midpoint)
DDR4-2666/2933/3200
Unit
Note
25
%
1, 2
min
(VIHdiff,50)
mV
3, 4, 5
Min
Max
Min
Max
-
25
-
-
min
(VIHdiff,50)
-
NOTE :
1) Vix_DQS_Ratio is DQS VIX crossing (Vix_DQS_FR or Vix_DQS_RF) divided by VDQS_trans. VDQS_trans is the difference between the lowest horizontal tangent above
VDQSmid of the transitioning DQS signals and the highest horizontal tangent below VDQSmid of the transitioning DQS signals.
2) VDQSmid will be similar to the VREFDQ internal setting value obtained during Vref Training if the DQS and DQs drivers and paths are matched.
3) The maximum limit shall not exceed the smaller of VIHdiff minimum limit or 50mV.
4) VIX measurements are only applicable for transitioning DQS_t and DQS_c signals when toggling data, preamble and high-z states are not applicable conditions.
5) The parameter VDQSmid is defined for simulation and ATE testing purposes, it is not expected to be tested in a system.
- 23 -
Preliminary Rev. 0.9
datasheet
K4A4G165WF
DDR4 SDRAM
8.7.5 Differential Input Slew Rate Definition
Input slew rate for differential signals (DQS_t, DQS_c) are defined and measured as shown in Figure 13 and Figure 14.
Figure 14. Differential Input Slew Rate Definition for DQS_t, DQS_c
NOTE :
1) Differential signal rising edge from VILDiff_DQS to VIHDiff_DQS must be monotonic slope.
2) Differential signal falling edge from VIHDiff_DQS to VILDiff_DQS must be monotonic slope.
[Table 19] Differential Input Slew Rate Definition for DQS_t, DQS_c
Measured
Description
Defined by
From
To
Differential input slew rate for rising edge (DQS_t - DQS_c)
VILDiff_DQS
VIHDiff_DQS
|VILDiff_DQS - VIHDiff_DQS|/DeltaTRdiff
Differential input slew rate for falling edge (DQS_t - DQS_c)
VIHDiff_DQS
VILDiff_DQS
|VILDiff_DQS - VIHDiff_DQS|/DeltaTFdiff
[Table 20] Differential Input Level for DQS_t, DQS_c
Symbol
Parameter
VIHDiff_DQS
Differential Input High
VILDiff_DQS
Differential Input Low
DDR4-1600/1866/2133
Min
DDR4-2400/2666
Max
Min
136
-
-
-136
DDR4-2933
Max
Min
130
-
-
-130
DDR4-3200
Max
Unit NOTE
Max
Min
115
-
110
-
mV
-
-115
-
-110
mV
[Table 21] Differential Input Slew Rate for DQS_t, DQS_c
Symbol
Parameter
SRIdiff
Differential Input Slew Rate
DDR4-1600/1866/2133/2400
DDR4-2666/2933/3200
Min
Max
Min
Max
3
18
2.5
18
- 24 -
Unit
V/ns
NOTE
datasheet
K4A4G165WF
Preliminary Rev. 0.9
DDR4 SDRAM
9.0 AC AND DC OUTPUT MEASUREMENT LEVELS
9.1 Output Driver DC Electrical Characteristics
The DDR4 driver supports two different Ron values. These Ron values are referred as strong(low Ron) and weak mode(high Ron). A functional
representation of the output buffer is shown in the figure below. Output driver impedance RON is defined as follows:
The individual pull-up and pull-down resistors (RONPu and RONPd) are defined as follows:
RONPu =
VDDQ -Vout
I out
under the condition that RONPd is off
RONPd =
Vout
I out
under the condition that RONPu is off
Chip In Drive Mode
Output Drive
To
other
circuity
like
RCV, ...
VDDQ
IPu
RONPu
DQ
RONPd
Iout
IPd
Vout
VSSQ
Figure 15. Output driver
- 25 -
Preliminary Rev. 0.9
datasheet
K4A4G165WF
DDR4 SDRAM
[Table 22] Output Driver DC Electrical Characteristics, assuming RZQ=240ohm; entire operating temperature range; after proper ZQ calibration
RONNOM
Resistor
Vout
Min
Nom
Max
Unit
NOTE
RON34Pd
34
RON34Pu
RON48Pd
48
VOLdc= 0.5*VDDQ
0.73
1
1.1
RZQ/7
1,2
VOMdc= 0.8* VDDQ
0.83
1
1.1
RZQ/7
1,2
VOHdc= 1.1* VDDQ
0.83
1
1.25
RZQ/7
1,2
VOLdc= 0.5* VDDQ
0.9
1
1.25
RZQ/7
1,2
VOMdc= 0.8* VDDQ
0.9
1
1.1
RZQ/7
1,2
VOHdc= 1.1* VDDQ
0.8
1
1.1
RZQ/7
1,2
VOLdc= 0.5*VDDQ
0.73
1
1.1
RZQ/5
1,2
VOMdc= 0.8* VDDQ
0.83
1
1.1
RZQ/5
1,2
VOHdc= 1.1* VDDQ
0.83
1
1.25
RZQ/5
1,2
1,2
VOLdc= 0.5* VDDQ
0.9
1
1.25
RZQ/5
VOMdc= 0.8* VDDQ
0.9
1
1.1
RZQ/5
1,2
VOHdc= 1.1* VDDQ
0.8
1
1.1
RZQ/5
1,2
Mismatch between pull-up and
pull-down, MMPuPd
VOMdc= 0.8* VDDQ
-10
-
17
%
1,2,3,4
Mismatch DQ-DQ within byte variation pull-up, MMPudd
VOMdc= 0.8* VDDQ
-
-
10
%
1,2,4
Mismatch DQ-DQ within byte variation pull-dn, MMPddd
VOMdc= 0.8* VDDQ
-
-
10
%
1,2,4
RON48Pu
NOTE :
1) The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity. 9.1.1 Output Driver Temperature and Voltage Sensitivity
2) Pull-up and pull-dn output driver impedances are recommended to be calibrated at 0.8 * VDDQ. Other calibration schemes may be used to achieve the linearity spec shown
above, e.g. calibration at 0.5 * VDDQ and 1.1 * VDDQ.
3) Measurement definition for mismatch between pull-up and pull-down, MMPuPd : Measure RONPu and RONPD both at 0.8*VDD separately; Ronnom is the nominal Ron
value
MMPuPd =
RONPu -RONPd
RONNOM
*100
4) RON variance range ratio to RON Nominal value in a given component, including DQS_t and DQS_c.
MMPudd =
MMPddd =
RONPuMax -RONPuMin
RONNOM
RONPdMax -RONPdMin
RONNOM
*100
*100
5) This parameter of x16 device is specified for Upper byte and Lower byte.
- 26 -
Preliminary Rev. 0.9
datasheet
K4A4G165WF
DDR4 SDRAM
9.1.1 Output Driver Temperature and Voltage Sensitivity
If temperature and/or voltage change after calibration, the tolerance limits widen according to the equations and tables below.
ΔT = T - T(@calibration); ΔV = VDDQ - VDDQ(@ calibration); VDD = VDDQ
[Table 23] Output Driver Sensitivity Definitions
Symbol
Min
Max
Unit
RONPU@ VOH(DC)
0.6 - dRONdTH × |ΔT| - dRONdVH × |ΔV|
1.1 - dRONdTH × |ΔT| + dRONdVH × |ΔV|
RZQ/6
RON@ VOM(DC)
0.9 - dRONdTM × |ΔT| - dRONdVM × |ΔV|
1.1 + dRONdTM × |ΔT| + dRONdVM × |ΔV|
RZQ/6
RONPD@ VOL(DC)
0.6 - dRONdTL × |ΔT| - dRONdVL × |ΔV|
1.1 + dRONdTL × |ΔT| + dRONdVL × |ΔV|
RZQ/6
[Table 24] Output Driver Temperature and Voltage Sensitivity
Voltage and Temperature Range
Symbol
Unit
Min
Max
dRONdTM
0
1.5
%/°C
dRONdVM
0
0.15
%/mV
dRONdTL
0
1.5
%/°C
dRONdVL
0
0.15
%/mV
dRONdTH
0
1.5
%/°C
dRONdVM
0
0.15
%/mV
9.1.2 Alert_n output Drive Characteristic
A functional representation of the output buffer is shown in the figure below. Output driver impedance RON is defined as follows:
RONPd =
Vout
l Iout l
under the condition that RONPu is off
Alert Driver
DRAM
Alert
RONPd
Iout
IPd
Vout
VSSQ
Resistor
RONPd
Vout
Min
Max
Unit
NOTE
VOLdc= 0.1* VDDQ
0.3
1.2
34Ω
1
VOMdc = 0.8* VDDQ
0.4
1.2
34Ω
1
VOHdc = 1.1* VDDQ
0.4
1.4
34Ω
1
NOTE:
1) VDDQ voltage is at VDDQ DC.
- 27 -
Preliminary Rev. 0.9
datasheet
K4A4G165WF
DDR4 SDRAM
9.1.3 Output Driver Characteristic of Connectivity Test (CT) Mode
Following Output driver impedance RON will be applied Test Output Pin during Connectivity Test (CT) Mode.
The individual pull-up and pull-down resistors (RONPu_CT and RONPd_CT) are defined as follows:
RONPu_CT =
RONPd_CT =
VDDQ-VOUT
l Iout l
VOUT
l Iout l
Chip In Driver Mode
Output Driver
VDDQ
IPu_CT
To
other
circuity
like
RCV,...
RON
Pu_CT
DQ
Iout
RON
Pd_CT
Vout
IPd_CT
VSSQ
Figure 16. Output Driver
RONNOM_CT
Resistor
RONPd_CT
34
RONPu_CT
Vout
Max
Units
NOTE
VOBdc = 0.2 x VDDQ
1.9
34
1
VOLdc = 0.5 x VDDQ
2.0
34
1
VOMdc = 0.8 x VDDQ
2.2
34
1
VOHdc = 1.1 x VDDQ
2.5
34
1
VOBdc = 0.2 x VDDQ
2.5
34
1
VOLdc = 0.5 x VDDQ
2.2
34
1
VOMdc = 0.8 x VDDQ
2.0
34
1
VOHdc = 1.1 x VDDQ
1.9
34
1
NOTE :
1) Connectivity test mode uses un-calibrated drivers, showing the full range over PVT. No mismatch between pull up and pull down is defined.
- 28 -
Preliminary Rev. 0.9
datasheet
K4A4G165WF
DDR4 SDRAM
9.2 Single-ended AC & DC Output Levels
[Table 25] Single-ended AC & DC Output Levels
Symbol
Parameter
VOH(DC)
DC output high measurement level (for IV curve linearity)
VOM(DC)
DDR4-1600/1866/2133/2400/2666/2933/3200
Units
1.1 x VDDQ
V
NOTE
DC output mid measurement level (for IV curve linearity)
0.8 x VDDQ
V
VOL(DC)
DC output low measurement level (for IV curve linearity)
0.5 x VDDQ
V
VOH(AC)
AC output high measurement level (for output SR)
(0.7 + 0.15) x VDDQ
V
1
VOL(AC)
AC output low measurement level (for output SR)
(0.7 - 0.15) x VDDQ
V
1
NOTE :
1) The swing of ± 0.15 × VDDQ is based on approximately 50% of the static single-ended output peak-to-peak swing with a driver impedance of RZQ/7Ω and an effective test
load of 50Ω to VTT = VDDQ.
9.3 Differential AC & DC Output Levels
[Table 26] Differential AC & DC Output Levels
Symbol
Parameter
DDR4-1600/1866/2133/2400/2666/2933/3200
Units
NOTE
VOHdiff(AC)
AC differential output high measurement level (for output SR)
+0.3 x VDDQ
V
1
VOLdiff(AC)
AC differential output low measurement level (for output SR)
-0.3 x VDDQ
V
1
NOTE :
1) The swing of ± 0.3 × VDDQ is based on approximately 50% of the static differential output peak-to-peak swing with a driver impedance of RZQ/7Ω and an effective test load
of 50Ω to VTT = VDDQ at each of the differential outputs.
- 29 -
Preliminary Rev. 0.9
datasheet
K4A4G165WF
DDR4 SDRAM
9.4 Single-ended Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC) for
single ended signals as shown in Table 27 and Figure 17.
[Table 27] Single-ended Output Slew Rate Definition
Measured
Description
Defined by
From
To
Single ended output slew rate for rising edge
VOL(AC)
VOH(AC)
[VOH(AC)-VOL(AC)] / Delta TRse
Single ended output slew rate for falling edge
VOH(AC)
VOL(AC)
[VOH(AC)-VOL(AC)] / Delta TFse
NOTE :
1) Output slew rate is verified by design and characterization, and may not be subject to production test.
VOH(AC)
VTT
VOL(AC)
delta TFse
delta TRse
Figure 17. Single-ended Output Slew Rate Definition
[Table 28] Single-ended Output Slew Rate
Parameter
Single ended output slew rate
Symbol
SRQse
DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 DDR4-2666 DDR4-2933 DDR4-3200
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
4
9
4
9
4
9
4
9
4
9
4
9
4
9
Units
V/ns
Description: SR: Slew Rate
Q: Query Output (like in DQ, which stands for Data-in, Query-Output)
se: Single-ended Signals
For Ron = RZQ/7 setting
NOTE :
1) In two cases, a maximum slew rate of 12 V/ns applies for a single DQ signal within a byte lane.
-Case 1 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low or low to high) while all remaining DQ signals in the
same byte lane are static (i.e. they stay at either high or low).
-Case 2 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low or low to high) while all remaining DQ signals in the
same byte lane are switching into the opposite direction (i.e. from low to high or high to low respectively). For the remaining DQ signal switching into the opposite direction, the
regular maximum limit of 9 V/ns applies
- 30 -
Preliminary Rev. 0.9
datasheet
K4A4G165WF
DDR4 SDRAM
9.5 Differential Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOLdiff(AC) and
VOHdiff(AC) for differential signals as shown in Table 29 and Figure 18.
[Table 29] Differential Output Slew Rate Definition
Measured
Description
Defined by
From
To
Differential output slew rate for rising edge
VOLdiff(AC)
VOHdiff(AC)
[VOHdiff(AC)-VOLdiff(AC)] / Delta TRdiff
Differential output slew rate for falling edge
VOHdiff(AC)
VOLdiff(AC)
[VOHdiff(AC)-VOLdiff(AC)] / Delta TFdiff
NOTE:
1) Output slew rate is verified by design and characterization, and may not be subject to production test.
VOHdiff(AC)
VTT
VOLdiff(AC)
delta TFdiff
delta TRdiff
Figure 18. Differential Output Slew Rate Definition
[Table 30] Differential Output Slew Rate
Parameter
Differential output slew rate
Symbol
SRQdiff
DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 DDR4-2666 DDR4-2933 DDR4-3200
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
8
18
8
18
8
18
8
18
8
18
8
18
8
18
Description:
SR: Slew Rate
Q: Query Output (like in DQ, which stands for Data-in, Query-Output)
diff: Differential Signals
For Ron = RZQ/7 setting
- 31 -
Units
V/ns
Preliminary Rev. 0.9
datasheet
K4A4G165WF
DDR4 SDRAM
9.6 Single-ended AC & DC Output Levels of Connectivity Test Mode
Following output parameters will be applied for DDR4 SDRAM Output Signal during Connectivity Test Mode.
[Table 31] Single-ended AC & DC Output Levels of Connectivity Test Mode
Symbol
DDR4-1600/1866/2133/2400/2666/2933/
Unit
3200
Parameter
Notes
VOH(DC)
DC output high measurement level (for IV curve linearity)
1.1 x VDDQ
V
VOM(DC)
DC output mid measurement level (for IV curve linearity)
0.8 x VDDQ
V
VOL(DC)
DC output low measurement level (for IV curve linearity)
0.5 x VDDQ
V
VOB(DC)
DC output below measurement level (for IV curve linearity)
0.2 x VDDQ
V
VOH(AC)
AC output high measurement level (for output SR)
VTT + (0.1 x VDDQ)
V
1
VOL(AC)
AC output below measurement level (for output SR)
VTT - (0.1 x VDDQ)
V
1
Unit
Notes
NOTE :
1) The effective test load is 50Ω terminated by VTT = 0.5 * VDDQ.
VOH(AC)
VTT
0.5 * VDDQ
VOL(AC)
TF_output_CT
TR_output_CT
Figure 19. Output Slew Rate Definition of Connectivity Test Mode
[Table 32] Single-ended Output Slew Rate of Connectivity Test Mode
Parameter
DDR4-1600/1866/2133/2400/2666/2933/3200
Symbol
Min
Max
Output signal Falling time
TF_output_CT
-
10
ns/V
Output signal Rising time
TR_output_CT
-
10
ns/V
- 32 -
Preliminary Rev. 0.9
datasheet
K4A4G165WF
DDR4 SDRAM
9.7 Test Load for Connectivity Test Mode Timing
The reference load for ODT timings is defined in Figure 20.
VDDQ
CT_INPUTS
DQ, DM
DQSL_t, DQSL_c
DQSU_t, DQSU_c
DQS_t, DQS_c
DUT
Rterm = 50 ohm
VSSQ
Timing Reference Points
Figure 20. Connectivity Test Mode Timing Reference Load
- 33 -
0.5*VDDQ
Preliminary Rev. 0.9
datasheet
K4A4G165WF
DDR4 SDRAM
10.0 SPEED BIN
[Table 33] DDR4-1600 Speed Bins and Operations
Speed Bin
DDR4-1600
CL-nRCD-nRP
11-11-11
Parameter
Symbol
Internal read command to first data
Internal read command to first data with read DBI enabled
ACT to internal read or write delay time
Normal
CWL = 9,11
CL = 9
ns
13
tAA(min) + 2nCK
tAA(max) +2nCK
ns
13
-
ns
13
-
ns
13
9 x tREFI
ns
13
-
ns
13
1.6
ns
1,2,3,4,12,15
13.75
(13.50)5),13)
13.75
(13.50)5),13)
tRAS
ACT to ACT or REF command period
CWL = 9
tAA_DBI
tRP
ACT to PRE command period
18.00
max
15)
(13.50)5),13)
tRCD
PRE command period
NOTE
min
13.75
tAA
Unit
35
48.75
tRC
(48.50)5),13)
Read DBI
CL = 11
(Optional)
5)
tCK(AVG)
1.5
(Optional)5),13)
CL = 10
CL = 12
tCK(AVG)
Reserved
ns
1,2,3,4,12
CL = 10
CL = 12
tCK(AVG)
Reserved
ns
1,2,3,4
CL = 11
CL = 13
tCK(AVG)
1.25
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