Rev. 1.4, Mar. 2016
K4A8G165WB
8Gb B-die DDR4 SDRAM x16
96FBGA with Lead-Free & Halogen-Free
(RoHS compliant)
datasheet
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-1-
1.2V
Rev. 1.4
datasheet
K4A8G165WB
DDR4 SDRAM
Revision History
Revision No.
History
Draft Date
Remark
Editor
1.0
- First SPEC Release
Mar. 2015
-
J.Y.Lee
1.01
- Correction of typo
Apr. 2015
-
J.Y.Lee
1.02
- IDD current table Typo
11th Aug. 2015
-
J.Y.Lee
1.1
- Added values on page 10 [Table 5]
27th Oct. 2015
-
J.Y.Lee
1.2
- Added information about I-temp
3th Dec. 2015
-
J.Y.Lee
1.3
- Modified pinout typo
16th Dec. 2015
-
J.Y.Lee
1.4
- Addition of DDR4-2666
23th Mar. 2016
-
J.Y.Lee
-2-
K4A8G165WB
datasheet
Rev. 1.4
DDR4 SDRAM
Table Of Contents
8Gb B-die DDR4 SDRAM x16
1. Ordering Information .....................................................................................................................................................4
2. Key Features.................................................................................................................................................................4
3. Package pinout/Mechanical Dimension & Addressing..................................................................................................5
3.1 x16 Package Pinout (Top view) : 96ball FBGA Package ........................................................................................ 5
3.2 FBGA Package Dimension (x16)............................................................................................................................. 6
4. Input/Output Functional Description..............................................................................................................................7
5. DDR4 SDRAM Addressing ...........................................................................................................................................9
6. Absolute Maximum Ratings ..........................................................................................................................................10
6.1 Absolute Maximum DC Ratings............................................................................................................................... 10
6.2 DRAM Component Operating Temperature Range ................................................................................................ 10
7. AC & DC Operating Conditions.....................................................................................................................................10
8. AC & DC Input Measurement Levels ...........................................................................................................................11
8.1 AC & DC Logic input levels for single-ended signals .............................................................................................. 11
8.2 VREF Tolerances .................................................................................................................................................... 11
8.3 AC & DC Logic Input Levels for Differential Signals ............................................................................................... 12
8.3.1. Differential signals definition ............................................................................................................................ 12
8.3.2. Differential swing requirement for clock (CK_t - CK_c) .................................................................................... 12
8.3.3. Single-ended requirements for differential signals ........................................................................................... 13
8.3.4. Address, Command and Control Overshoot and Undershoot specifications ................................................... 14
8.3.5. Clock Overshoot and Undershoot Specifications ............................................................................................. 15
8.3.6. Data, Strobe and Mask Overshoot and Undershoot Specifications ................................................................. 15
8.4 Slew Rate Definitions .............................................................................................................................................. 16
8.4.1. Slew Rate Definitions for Differential Input Signals (CK) ................................................................................. 16
8.4.2. Slew Rate Definition for Single-ended Input Signals ( CMD/ADD ).................................................................. 17
8.5 Differential Input Cross Point Voltage...................................................................................................................... 18
8.6 CMOS rail to rail Input Levels .................................................................................................................................. 19
8.6.1. CMOS rail to rail Input Levels for RESET_n .................................................................................................... 19
8.7 AC and DC Logic Input Levels for DQS Signals...................................................................................................... 20
8.7.1. Differential signal definition .............................................................................................................................. 20
8.7.2. Differential swing requirements for DQS (DQS_t - DQS_c) ............................................................................. 20
8.7.3. Peak voltage calculation method ..................................................................................................................... 20
8.7.4. Differential Input Cross Point Voltage .............................................................................................................. 21
8.7.5. Differential Input Slew Rate Definition.............................................................................................................. 22
9. AC and DC output Measurement levels........................................................................................................................23
9.1 Output Driver DC Electrical Characteristics............................................................................................................. 23
9.1.1. Alert_n output Drive Characteristic .................................................................................................................. 25
9.1.2. Output Driver Characteristic of Connectivity Test ( CT ) Mode ........................................................................ 25
9.2 Single-ended AC & DC Output Levels..................................................................................................................... 26
9.3 Differential AC & DC Output Levels......................................................................................................................... 26
9.4 Single-ended Output Slew Rate .............................................................................................................................. 27
9.5 Differential Output Slew Rate .................................................................................................................................. 28
9.6 Single-ended AC & DC Output Levels of Connectivity Test Mode .......................................................................... 29
9.7 Test Load for Connectivity Test Mode Timing ......................................................................................................... 29
10. Speed Bin ...................................................................................................................................................................30
10.1 Speed Bin Table Note ........................................................................................................................................... 35
11. IDD and IDDQ Specification Parameters and Test conditions....................................................................................36
11.1 IDD, IPP and IDDQ Measurement Conditions....................................................................................................... 36
12. 8Gb DDR4 SDRAM B-die IDD Specification Table ....................................................................................................51
13. Input/Output Capacitance ...........................................................................................................................................53
14. Electrical Characteristics & AC Timing .......................................................................................................................55
14.1 Reference Load for AC Timing and Output Slew Rate .......................................................................................... 55
14.2 tREFI ..................................................................................................................................................................... 55
14.3 Timing Parameters by Speed Grade ..................................................................................................................... 56
-3-
K4A8G165WB
datasheet
Rev. 1.4
DDR4 SDRAM
14.4 The DQ input receiver compliance mask for voltage and timing ........................................................................... 63
14.5 DDR4 Function Matrix ........................................................................................................................................... 67
-4-
Rev. 1.4
datasheet
K4A8G165WB
DDR4 SDRAM
1. Ordering Information
[ Table 1 ] Samsung 8Gb DDR4 B-die ordering information table
Organization
DDR4-2133 (15-15-15)
DDR4-2400 (17-17-17)2
DDR4-2666 (19-19-19)2
Package
512Mx16
K4A8G165WB-BCPB
K4A8G165WB-BCRC
K4A8G165WB-BCTD
96FBGA
512Mx16
K4A8G165WB-BIPB
K4A8G165WB-BIRC
-
96FBGA
NOTE :
1. Speed bin is in order of CL-tRCD-tRP.
2. Backward compatible to lower frequency
3. 13th digit stands for below.
"C" : Commercial temp/Normal power
"I" : Industrial temp/Normal power
2. Key Features
[ Table 2 ] 8Gb DDR4 B-die Speed bins
Speed
DDR4-1600
DDR4-1866
DDR4-2133
DDR4-2400
DDR4-2666
11-11-11
13-13-13
15-15-15
17-17-17
19-19-19
Unit
tCK(min)
1.25
1.071
0.938
0.833
0.75
ns
CAS Latency
11
13
15
17
19
nCK
tRCD(min)
13.75
13.92
14.06
14.16
14.25
ns
tRP(min)
13.75
13.92
14.06
14.16
14.25
ns
tRAS(min)
35
34
33
32
32
ns
tRC(min)
48.75
47.92
47.06
46.16
46.25
ns
•
JEDEC standard 1.2V (1.14V~1.26V)
•
VDDQ = 1.2V (1.14V~1.26V)
•
VPP = 2.5V (2.375V~2.75V)
•
800 MHz fCK for 1600Mb/sec/pin,933 MHz fCK for 1866Mb/sec/pin,
1067MHz fCK for 2133Mb/sec/pin, 1200MHz fCK for2400Mb/sec/pin,
1333MHz fCK for2666Mb/sec/pin1
•
8 Banks (2 Bank Groups)
•
Programmable CAS Latency(posted CAS):
10,11,12,13,14,15,16,17,18,19,20
•
Programmable CAS Write Latency (CWL) = 9,11 (DDR4-1600) , 10,12
(DDR4-1866) ,11,14 (DDR4-2133) ,12,16 (DDR4-2400) and 14,18 (DDR42666)
•
•
8-bit pre-fetch
Burst Length: 8, 4 with tCCD = 4 which does not allow seamless read or
write [either On the fly using A12 or MRS]
•
Bi-directional Differential Data-Strobe
•
Internal(self) calibration : Internal self calibration through ZQ pin
(RZQ : 240 ohm ± 1%)
The 8Gb DDR4 SDRAM B-die is organized as a 64Mbit x 16 I/Os x 8banks
device. This synchronous device achieves high speed double-data-rate
transfer rates of up to 2666Mb/sec/pin (DDR4-2666) for general applications.
The chip is designed to comply with the following key DDR4 SDRAM features such as posted CAS, Programmable CWL, Internal (Self) Calibration,
On Die Termination using ODT pin and Asynchronous Reset .
All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the crosspoint of differential clocks (CK rising and CK falling). All I/Os are synchronized with a
pair of bidirectional strobes (DQS and DQS) in a source synchronous fashion. The address bus is used to convey row, column, and bank address
information in a RAS/CAS multiplexing style. The DDR4 device operates
with a single 1.2V (1.14V~1.26V) power supply, 1.2V(1.14V~1.26V) VDDQ
and 2.5V (2.375V~2.75V) VPP.
The 8Gb DDR4 B-die device is available in 96ball FBGAs(x16).
• On Die Termination using ODT pin
• Average Refresh Period 7.8us at lower than TCASE 85C, 3.9us at 85C <
TCASE < 95 C
•
Support Industrial Temp ( -4095C )
- tREFI 7.8us at -40 °C ≤ TCASE ≤ 85°C
- tREFI 3.9us at 85 °C < TCASE ≤ 95°C
• Asynchronous Reset
• Package : 96 balls FBGA - x16
• All of Lead-Free products are compliant for RoHS
• All of products are Halogen-free
• CRC(Cyclic Redundancy Check) for Read/Write data security
• Command address parity check
• DBI(Data Bus Inversion)
• Gear down mode
• POD (Pseudo Open Drain) interface for data input/output
• Internal VREF for data inputs
• External VPP for DRAM Activating Power
• PPR and sPPR is supported
NOTE : 1. This data sheet is an abstract of full DDR4 specification and does not
cover the common features which are described in “DDR4 SDRAM Device Operation
& Timing Diagram”.
2. The functionality described and the timing specifications included in this data sheet
are for the DLL Enabled mode of operation.
-4-
Rev. 1.4
datasheet
K4A8G165WB
DDR4 SDRAM
3. Package pinout/Mechanical Dimension & Addressing
3.1 x16 Package Pinout (Top view) : 96ball FBGA Package
1
2
3
A
VDDQ
VSSQ
B
VPP
C
VDDQ
D
4
5
6
7
8
9
DQU0
DQSU_c
VSSQ
VDDQ
A
VSS
VDD
DQSU_t
DQU1
VDD
B
DQU4
DQU2
DQU3
DQU5
VSSQ
C
VDD
VSSQ
DQU6
DQU7
VSSQ
VDDQ
D
E
VSS
DMU_n/
DBIU_n
VSSQ
DML_n
DBIL_n
VSSQ
VSS
E
F
VSSQ
VDDQ
DQSL_c
DQL1
VDDQ
ZQ
F
G
VDDQ
DQL0
DQSL_t
VDD
VSS
VDDQ
G
H
VSSQ
DQL4
DQL2
DQL3
DQL5
VSSQ
H
J
VDD
VDDQ
DQL6
DQL7
VDDQ
VDD
J
K
VSS
CKE
ODT
CK_t
CK_c
VSS
K
L
VDD
WE_n/
A14
ACT_n
CS_n
RAS_n
VDD
L
M
VREFCA
BG0
A10/AP
A12/BC_n
CAS_n/
A15
VSS
M
N
VSS
BA0
A4
A3
BA1
TEN
N
P
RESET_n
A6
A0
A1
A5
ALERT_n
P
R
VDD
A8
A2
A9
A7
VPP
R
T
VSS
A11
PAR
NC
A13
VDD
T
1
Ball Locations (x16)
A
B
C
Populated ball
Ball not populated
D
E
F
G
H
Top view
(See the balls through the package)
J
K
L
M
N
P
R
T
-5-
2
3
4
5
6
7
8
9
Rev. 1.4
datasheet
K4A8G165WB
DDR4 SDRAM
3.2 FBGA Package Dimension (x16)
Units : Millimeters
7.50 0.10
A
0.80 x 8 = 6.40
0.80
1.60
#A1 INDEX MARK
3.20
B
96 - 0.48 Solder ball
(Post reflow 0.50 ± 0.05)
0.40
0.80
(Datum B)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
0.80 x15 = 12.00
9 8 7 6 5 4 3 2 1
13.30 0.10
(Datum A)
(0.30)
MOLDING AREA
(0.60)
0.2 M A B
7.50 0.10
13.30 0.10
#A1
0.10MAX
BOTTOM VIEW
0.37 0.05
TOP VIEW
1.10 0.10
-6-
datasheet
K4A8G165WB
Rev. 1.4
DDR4 SDRAM
4. Input/Output Functional Description
[ Table 3 ] Input/Output function description
Symbol
Type
CK_t, CK_c
Input
CKE, (CKE1)
Input
CS_n, (CS1_n)
Input
C0,C1,C2
Input
ODT, (ODT1)
Input
ACT_n
Input
RAS_n/A16. CAS_n/
A15. WE_n/A14
Input
DM_n/DBI_n/TDQS_t,
(DMU_n/DBIU_n),
(DML_n/DBIL_n)
Input/Output
BG0 - BG1
Input
BA0 - BA1
Input
A0 - A17
Input
A10 / AP
Input
A12 / BC_n
Input
RESET_n
Input
DQ
Input / Output
DQS_t, DQS_c,
DQSU_t, DQSU_c,
DQSL_t, DQSL_c
Input / Output
Function
Clock: CK_t and CK_c are differential clock inputs. All address and control input signals are sampled on
the crossing of the positive edge of CK_t and negative edge of CK_c.
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input
buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self-Refresh operation
(all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for Self-Refresh exit.
After VREFCA and Internal DQ Vref have become stable during the power on and initialization sequence,
they must be maintained during all operations (including Self-Refresh). CKE must be maintained high
throughout read and write accesses. Input buffers, excluding CK_t,CK_cSGODT and CKE are disabled
during power-down. Input buffers, excluding CKE, are disabled during Self-Refresh.
Chip Select: All commands are masked when CS_n is registered HIGH. CS_n provides for external Rank
selection on systems with multiple Ranks. CS_n is considered part of the command code.
Chip ID : Chip ID is only used for 3DS for 2,4,8high stack via TSV to select each slice of stacked
component. Chip ID is considered part of the command code
On Die Termination: ODT (registered HIGH) enables RTT_NOM termination resistance internal to the
DDR4 SDRAM. When enabled, ODT is only applied to each DQ, DQS_t, DQS_c and DM_n/DBI_n/
TDQS_t, NU/TDQS_c (When TDQS is enabled via Mode Register A11=1 in MR1) signal for x8
conurations. For x16 conuration ODT is applied to each DQ, DQSU_t, DQSU_c, DQSL_t, DQSL_c,
DMU_n, and DML_n signal. The ODT pin will be ignored if MR1 is programmed to disable RTT_NOM.
Activation Command Input : ACT_n defines the Activation command being entered along with CS_n. The
input into RAS_n/A16, CAS_n/A15 and WE_n/A14 will be considered as Row Address A16, A15 and A14
Command Inputs: RAS_n/A16, CAS_n/A15 and WE_n/A14 (along with CS_n) define the command being
entered. Those pins have multi function. ForG example, for activation with ACT_n Low, those are
Addressing like A16,A15 and A14 but for non-activation command with ACT_n High, those are Command
pins for Read, Write and other command defined in command truth table
Input Data Mask and Data Bus Inversion: DM_n is an input mask signal for write data. Input data is
masked when DM_n is sampled LOW coincident with that input data during a Write access. DM_n is
sampled on both edges of DQS. DM is muxed with DBI function by Mode Register A10,A11,A12 setting in
MR5. For x8 device, the function of DM or TDQS is enabled by Mode Register A11 setting in MR1. DBI_n
is an input/output identifing whether to store/output the true or inverted data. If DBI_n is LOW, the data will
be stored/output after inversion inside the DDR4 SDRAM and not inverted if DBI_n is HIGH. TDQS is only
supported in X8
Bank Group Inputs : BG0 - BG1 define to which bank group an Active, Read, Write or Precharge command
is being applied. BG0 also determines which mode register is to be accessed during a MRS cycle. X4/8
have BG0 and BG1 but X16 has only BG0
Bank Address Inputs: BA0 - BA1 define to which bank an Active, Read, Write or Precharge command is
being applied. Bank address also determines which mode register is to be accessed during a MRS cycle.
Address Inputs: Provide the row address for ACTIVATE Commands and the column address for Read/
Write commands to select one location out of the memory array in the respective bank. (A10/AP, A12/
BC_n, RAS_n/A16, CAS_n/A15 and WE_n/A14 have additional functions, see other rows.The address
inputs also provide the op-code during Mode Register Set commands.A17 is only defined for the x4
conuration.
Auto-precharge: A10 is sampled during Read/Write commands to determine whether Autoprecharge
should be performed to the accessed bank after the Read/Write operation. (HIGH: Autoprecharge; LOW:
no Autoprecharge).A10 is sampled during a Precharge command to determine whether the Precharge
applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is
selected by bank addresses.
Burst Chop: A12 / BC_n is sampled during Read and Write commands to determine if burst chop (on-thefly) will be performed. (HIGH, no burst chop; LOW: burst chopped). See command truth table for details.
Active Low Asynchronous Reset: Reset is active when RESET_n is LOW, and inactive when RESET_n is
HIGH. RESET_n must be HIGH during normal operation. RESET_n is a CMOS rail to rail signal with DC
high and low at 80% and 20% of VDD,
Data Input/ Output: Bi-directional data bus. If CRC is enabled via Mode register then CRC code is added at
the end of Data Burst. Any DQ from DQ0~DQ3 may indicate the internal Vref level during test via Mode
Register Setting MR4 A4=High. During this mode, RTT value should be set to Hi-Z. Refer to vendor
specific datasheets to determine which DQ is used.
Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered in write
data. For the x16, DQSL corresponds to the data on DQL0-DQL7; DQSU corresponds to the data on
DQU0-DQU7. The data strobe DQS_t, DQSL_t and DQSU_t are paired with differential signals DQS_c,
DQSL_c, and DQSU_c, respectively, to provide differential pair signaling to the system during reads and
writes. DDR4 SDRAM supports differential data strobe only and does not support single-ended.
-7-
datasheet
K4A8G165WB
Symbol
Type
TDQS_t, TDQS_c
Output
PAR
Input
ALERT_n
Input/Output
TEN
Input
Rev. 1.4
DDR4 SDRAM
Function
Termination Data Strobe: TDQS_t/TDQS_c is applicable for x8 DRAMs only. When enabled via Mode
Register A11 = 1 in MR1, the DRAM will enable the same termination resistance function on TDQS_t/
TDQS_c that is applied to DQS_t/DQS_c. When disabled via mode register A11 = 0 in MR1, DM/DBI/
TDQS will provide the data mask function or Data Bus Inversion depending on MR5; A11,12,10and
TDQS_c is not used. x4/x16 DRAMs must disable the TDQS function via mode register A11 = 0 in MR1.
Command and Address Parity Input : DDR4 Supports Even Parity check in DRAM with MR setting. Once
it’s enabled via Register in MR5, then DRAM calculates Parity with ACT_n,RAS_n/A16,CAS_n/A15,WE_n/
A14,BG0-BG1,BA0-BA1,A17-A0, and C0-C2 (3DS devices). Input parity should maintain at the rising edge
of the clock and at the same time with command & address with CS_n LOW
Alert : It has multi functions such as CRC error flag , Command and Address Parity error flag as Output
signal. If there is error in CRC, then Alert_n goes LOW for the period time interval and goes back HIGH. If
there is error in Command Address Parity Check, then Alert_n goes LOW for relatively long period until on
going DRAM internal recovery transaction to complete. During Connectivity Test mode, this pin works as
input. Using this signal or not is dependent on system. In case of not connected as Signal, ALERT_n Pin
must be bounded to VDD on board.
Connectivity Test Mode Enable : Required on X16 devices and optional input on x4/x8 with densities equal
to or greater than 8Gb.HIGH in this pin will enable Connectivity Test Mode operation along with other pins.
It is a CMOS rail to rail signal with AC high and low at 80% and 20% of VDD. Using this signal or not is
dependent on System. This pin may be DRAM internally pulled low through a weak pull-down resistor to
VSS.
No Connect: No internal electrical connection is present.
NC
VDDQ
Supply
DQ Power Supply: 1.2 V +/- 0.06 V
VSSQ
Supply
DQ Ground
VDD
Supply
Power Supply: 1.2 V +/- 0.06 V
VSS
Supply
Ground
VPP
Supply
DRAM Activating Power Supply: 2.5V ( 2.375V min , 2.75V max)
VREFCA
Supply
Reference voltage for CA
ZQ
Supply
Reference Pin for ZQ calibration
NOTE Input only pins (BG0-BG1,BA0-BA1, A0-A17, ACT_n, RAS_n/A16, CAS_n/A15, WE_n/A14, CS_n, CKE, ODT, and RESET_n) do not supply termination.
-8-
Rev. 1.4
datasheet
K4A8G165WB
DDR4 SDRAM
5. DDR4 SDRAM Addressing
2 Gb Addressing Table
Configuration
Bank Address
512 Mb x4
256 Mb x8
128 Mb x16
# of Bank Groups
4
4
2
BG Address
BG0~BG1
BG0~BG1
BG0
Bank Address in a BG
BA0~BA1
BA0~BA1
BA0~BA1
Row Address
A0~A14
A0~A13
A0~A13
Column Address
A0~A9
A0~A9
A0~A9
Page size
512B
1KB
2KB
4 Gb Addressing Table
Configuration
Bank Address
1 Gb x4
512 Mb x8
256 Mb x16
# of Bank Groups
4
4
2
BG Address
BG0~BG1
BG0~BG1
BG0
Bank Address in a BG
BA0~BA1
BA0~BA1
BA0~BA1
Row Address
A0~A15
A0~A14
A0~A14
Column Address
A0~A9
A0~A9
A0~A9
Page size
512B
1KB
2KB
8 Gb Addressing Table
Configuration
Bank Address
2 Gb x4
1 Gb x8
512 Mb x16
# of Bank Groups
4
4
2
BG Address
BG0~BG1
BG0~BG1
BG0
Bank Address in a BG
BA0~BA1
BA0~BA1
BA0~BA1
Row Address
A0~A16
A0~A15
A0~A15
Column Address
A0~A9
A0~A9
A0~A9
Page size
512B
1KB
2KB
4 Gb x4
2 Gb x8
1 Gb x16
16 Gb Addressing Table
Configuration
Bank Address
# of Bank Groups
4
4
2
BG Address
BG0~BG1
BG0~BG1
BG0
Bank Address in a BG
BA0~BA1
BA0~BA1
BA0~BA1
Row Address
A0~A17
A0~A16
A0~A16
Column Address
A0~A9
A0~A9
A0~A9
Page size
512B
1KB
2KB
NOTE 1 : Page size is the number of bytes of data delivered from the array to the internal sense amplifiers when an ACTIVE command is registered.
Page size is per bank, calculated as follows:
page size = 2 COLBITS * ORG8
where, COLBITS = the number of column address bits, ORG = the number of I/O (DQ) bits
-9-
Rev. 1.4
datasheet
K4A8G165WB
DDR4 SDRAM
6. Absolute Maximum Ratings
6.1 Absolute Maximum DC Ratings
[ Table 4 ] Absolute Maximum DC Ratings
Symbol
VDD
VDDQ
VPP
VIN, VOUT
TSTG
Parameter
Rating
Units
NOTE
Voltage on VDD pin relative to Vss
-0.3 ~ 1.5
V
1,3
Voltage on VDDQ pin relative to Vss
-0.3 ~ 1.5
V
1,3
Voltage on VPP pin relative to Vss
-0.3 ~ 3.0
V
4
Voltage on any pin except VREFCA relative to Vss
-0.3 ~ 1.5
V
1,3,5
Storage Temperature
-55 to +100
°C
1,2
NOTE :
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.
3. VDD and VDDQ must be within 300 mV of each other at all times;and VREFCA must be not greater than 0.6 x VDDQ, When VDD and VDDQ are less than 500 mV; VREFCA
may be equal to or less than 300 mV
4. VPP must be equal or greater than VDD/VDDQ at all times.
5. Overshoot area above 1.5 V is specified in section 8.3.4, 8.3.5 and section 8.3.6..
6.2 DRAM Component Operating Temperature Range
[ Table 5 ] Temperature Range
Symbol
Parameter
rating
Unit
NOTE
TOPER
Operating Temperature Range
0 to 95
C
1, 2, 3
NOTE :
1. Operating Temperature TOPER is the case surface temperature on the center/top side of the DRAM.
2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0-85C under all operating conditions
3. Some applications require operation of the Extended Temperature Range between 85C and 95C case temperature. Full specifications are guaranteed in this range, but the
following additional conditions apply:
a) Refresh commands must be doubled in frequency, therefore reducing the refresh interval tREFI to 3.9us.
b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature
Range capability (MR2 A6 = 0b and MR2 A7 = 1b), in this case IDD6 current can be increased around 10~20% than normal Temperature range.
7. AC & DC Operating Conditions
[ Table 6 ] Recommended DC Operating Conditions
Rating
Symbol
Parameter
VDD
Supply Voltage
VDDQ
Supply Voltage for Output
1.14
1.2
VPP
Peak-to-Peak Voltage
2.375
2.5
Unit
NOTE
V
1,2,3
1.26
V
1,2,3
2.75
V
3
Min.
Typ.
Max.
1.14
1.2
1.26
NOTE :
1. Under all conditions VDDQ must be less than or equal to VDD.
2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
3. DC bandwidth is limited to 20MHz.
- 10 -
Rev. 1.4
datasheet
K4A8G165WB
DDR4 SDRAM
8. AC & DC Input Measurement Levels
8.1 AC & DC Logic input levels for single-ended signals
[ Table 7 ] Single-ended AC & DC input levels for Command and Address
Symbol
Parameter
VIH.CA(DC75)
DC input logic high
DDR4-1600/1866/2133/2400
DDR4-2666
Unit
Min.
Max.
Min.
Max.
VREFCA+ 0.075
VDD
TBD
TBD
V
NOTE
VIL.CA(DC75)
DC input logic low
VSS
VREFCA-0.075
TBD
TBD
V
VIH.CA(AC100)
AC input logic high
VREF + 0.1
Note 2
TBD
TBD
V
1
VIL.CA(AC100)
AC input logic low
Note 2
VREF - 0.1
TBD
TBD
V
1
VREFCA(DC)
Reference Voltage for ADD, CMD inputs
0.49*VDD
0.51*VDD
TBD
TBD
V
2,3
NOTE :
1. See “Overshoot and Undershoot Specifications” .
2. The AC peak noise on VREFCA may not allow VREFCA to deviate from VREFCA(DC) by more than ± 1% VDD (for reference : approx. ± 12mV)
3. For reference : approx. VDD/2 ± 12mV
8.2 VREF Tolerances
The dc-tolerance limits and ac-noise limits for the reference voltages VREFCA is illustrated in Figure 1. It shows a valid reference voltage VREF(t) as a function of time. (VREF stands for VREFCA and VREFDQ likewise).
VREF(DC) is the linear average of VREF(t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirement in Table 7 on
page 11. Furthermore VREF(t) may temporarily deviate from VREF(DC) by no more than ± 1% VDD.
voltage
VDD
VSS
time
Figure 1. Illustration of VREF(DC) tolerance and VREF ac-noise limits
The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on VREF.
"VREF" shall be understood as VREF(DC), as defined in Figure 1 .
This clarifies, that dc-variations of VREF affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to
which setup and hold is measured. System timing and voltage budgets need to account for VREF(DC) deviations from the optimum position within the
data-eye of the input signals.
This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with VREF ac-noise. Timing
and voltage effects due to ac-noise on VREF up to the specified limit (+/-1% of VDD) are included in DRAM timings and their associated deratings.
- 11 -
Rev. 1.4
datasheet
K4A8G165WB
DDR4 SDRAM
8.3 AC & DC Logic Input Levels for Differential Signals
8.3.1 Differential signals definition
tDVAC
Differential Input Voltage (i.e. DQS-DQS, CK-CK)
VIH.DIFF.AC.MIN
VIH.DIFF.MIN
0.0
half cycle
VIL.DIFF.MAX
VIL.DIFF.AC.MAX
tDVAC
time
Figure 2. Definition of differential ac-swing and "time above ac level" tDVAC
NOTE :
1. Differential signal rising edge from VIL.DIFF.MAX to VIH.DIFF.MIN must be monotonic slope.
2. Differential signal falling edge from VIH.DIFF.MIN to VIL.DIFF.MAX must be monotonic slope.
8.3.2 Differential swing requirement for clock (CK_t - CK_c)
[ Table 8 ] Differential AC & DC Input Levels
Symbol
Parameter
VIHdiff
DDR4 -1600/1866/2133
DDR4 -2400/2666
unit
NOTE
NOTE 3
V
1
TBD
V
1
2 x (VIH(AC) - VREF)
NOTE 3
V
2
NOTE 3
2 x (VIL(AC) - VREF)
V
2
min
max
min
max
differential input high
+0.150
NOTE 3
TBD
VILdiff
differential input low
NOTE 3
-0.150
NOTE 3
VIHdiff(AC)
differential input high ac
2 x (VIH(AC) - VREF)
NOTE 3
NOTE 3
2 x (VIL(AC) - VREF)
VILdiff(AC)
differential input low ac
NOTE:
1. Used to define a differential signal slew-rate.
2. for CK_t - CK_c use VIHCA/VILCA(AC) of ADD/CMD and VREFCA;
3. These values are not defined; however, the differential signals CK_t - CK_c, need to be within the respective limits (VIHCA(DC) max, VILCA(DC)min) for single-ended signals
as well as the limitations for overshoot and undershoot.
- 12 -
Rev. 1.4
datasheet
K4A8G165WB
DDR4 SDRAM
[ Table 9 ] Allowed time before ringback (tDVAC) for CK_t - CK_c
tDVAC [ps] @ |VIH/Ldiff(AC)| = 200mV
Slew Rate [V/ns]
min
max
> 4.0
120
-
4.0
115
-
3.0
110
-
2.0
105
-
1.8
100
-
1.6
95
-
1.4
90
-
1.2
85
-
1.0
80
-
< 1.0
80
-
8.3.3 Single-ended requirements for differential signals
Each individual component of a differential signal (CK_t, CK_c) has also to comply with certain requirements for single-ended signals.
CK_t and CK _c have to approximately reach VSEHmin / VSELmax [approximately equal to the ac-levels { VIH.CA(AC) / VIL.CA(AC)} for ADD/CMD signals]
in every half-cycle.
Note that the applicable ac-levels for ADD/CMD might be different per speed-bin etc. E.g. if Different value than VIH.CA(AC100)/VIL.CA(AC100) is used for
ADD/CMD signals, then these ac-levels apply also for the single-ended signals CK_t and CK _c .
VDD or VDDQ
VSEH min
VSEH
VDD/2 or VDDQ/2
CK
VSEL max
VSEL
VSS or VSSQ
time
Figure 3. Single-ended requirement for differential signals
Note that while ADD/CMD signal requirements are with respect to VREFCA, the single-ended components of differential signals have a requirement with
respect to VDD/2; this is nominally the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For single-ended
components of differential signals the requirement to reach VSELmax, VSEHmin has no bearing on timing, but adds a restriction on the common mode
characteristics of these signals.
- 13 -
Rev. 1.4
datasheet
K4A8G165WB
DDR4 SDRAM
[ Table 10 ] Single-ended levels for CK_t, CK_c
Symbol
Parameter
Single-ended high-level for
VSEH
CK_t , CK_c
Single-ended low-level for
VSEL
CK_t , CK_c
DDR4-1600/1866/2133
Min
Max
DDR4 -2400/2666
Min
Max
Unit
NOTE
(VDD/2)+0.100
NOTE3
TBD
NOTE3
V
1, 2
NOTE3
(VDD/2)-0.100
NOTE3
TBD
V
1, 2
NOTE :
1. For CK_t - CK_c use VIH.CA/VIL.CA(AC) of ADD/CMD;
2. VIH(AC)/VIL(AC) for ADD/CMD is based on VREFCA;
3. These values are not defined, however the single-ended signals CK_t - CK_c need to be within the respective limits (VIH.CA(DC) max, VIL.CA(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot.
8.3.4 Address, Command and Control Overshoot and Undershoot specifications
[ Table 11 ] AC overshoot/undershoot specification for Address, Command and Control pins
Specification
Parameter
DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 DDR4-2666
Unit
Maximum peak amplitude above VDD Absolute Max allowed for overshoot area
0.06
0.06
0.06
0.06
TBD
V
Delta value between VDD Absolute Max and VDD Max allowed for overshoot
area
0.24
0.24
0.24
0.24
TBD
V
Maximum peak amplitude allowed for undershoot area
0.3
0.3
0.3
0.3
TBD
V-ns
Maximum overshoot area per 1tCK Above Absolute Max
0.0083
0.0071
0.0062
0.0055
TBD
V-ns
Maximum overshoot area per 1tCK Between Absolute Max and VDD Max
0.2550
0.2185
0.1914
0.1699
TBD
V-ns
Maximum undershoot area per 1tCK Below VSS
0.2644
0.2265
0.1984
0.1762
TBD
V-ns
(A0-A13,BG0-BG1,BA0-BA1,ACT_n,RAS_n,CAS_n/A15,WE_n/A14,CS_n,CKE,ODT,C2-C0)
Overshoot Area above VDD Absolute Max
VDD Absolute Max
Volts
(V)
VDD
Overshoot Area Between
VDD Absolute Max and VDD Max
1 tCK
VSS
Undershoot Area below VSS
Figure 4. Address, Command and Control Overshoot and Undershoot Definition
- 14 -
Rev. 1.4
datasheet
K4A8G165WB
DDR4 SDRAM
8.3.5 Clock Overshoot and Undershoot Specifications
[ Table 12 ] AC overshoot/undershoot specification for Clock
Specification
Parameter
DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 DDR4-2666
Unit
Maximum peak amplitude above VDD Absolute Max allowed for overshoot
area
0.06
0.06
0.06
0.06
TBD
V
Delta value between VDD Absolute Max and VDD Max allowed for overshoot
area
0.24
0.24
0.24
0.24
TBD
V
Maximum peak amplitude allowed for undershoot area
0.3
0.3
0.3
0.3
TBD
V
Maximum overshoot area per 1UI Above Absolute Max
0.0038
0.0032
0.0028
0.0025
TBD
V-ns
Maximum overshoot area per 1UI Between Absolute Max and VDD Max
0.1125
0.0964
0.0844
0.0750
TBD
V-ns
Maximum undershoot area per 1UI Below VSS
0.1144
0.0980
0.0858
0.0762
TBD
V-ns
(CK_t, CK_c)
Overshoot Area above VDD Absolute Max
VDD Absolute Max
Volts
(V)
Overshoot Area Between
VDD Absolute Max and VDD Max
VDD
1UI
VSS
Undershoot Area below VSS
Figure 5. Clock Overshoot and Undershoot Definition
8.3.6 Data, Strobe and Mask Overshoot and Undershoot Specifications
[ Table 13 ] AC overshoot/undershoot specification for Data, Strobe and Mask
Specification
Parameter
DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 DDR4-2666
Unit
Maximum peak amplitude above Max absolute level of Vin, Vout
0.16
0.16
0.16
0.16
TBD
V
Overshoot area Between Max Absolute level of Vin, Vout and VDDQ Max
0.24
0.24
0.24
0.24
TBD
V
Undershoot area Between Min absolute level of Vin, Vout and VSSQ
0.30
0.30
0.30
0.30
TBD
V
Maximum peak amplitude below Min absolute level of Vin, Vout
0.10
0.10
0.10
0.10
TBD
V
Maximum overshoot area per 1UI Above Max absolute level of Vin, Vout
0.0150
0.0129
0.0113
0.0100
TBD
V-ns
Maximum overshoot area per 1UI Between Max absolute level of Vin,Vout and
VDDQ Max
0.1050
0.0900
0.0788
0.0700
TBD
V-ns
Maximum undershoot area per 1UI Between Min absolute level of Vin,Vout and
VSSQ
0.1050
0.0900
0.0788
0.0700
TBD
V-ns
Maximum undershoot area per 1UI Below Min absolute level of Vin,Vout
0.0150
0.0129
0.0113
0.0100
TBD
V-ns
(DQ, DQS_t, DQS_c, DM_n, DBI_n, TDQS_t, TDQS_c)
Overshoot area above Max absolute level of Vin,Vout
Max absolute level of Vin, Vout
Volts
(V)
VDDQ
Overshoot Area Between
Max absolute level of Vin,Vout and VDDQ Max
1UI
VSSQ
Undershoot area between
Min absolute level of Vin,Vout and VSSQ
Min absolute level of Vin, Vout
Undershoot area below Min absolute level of Vin,Vout
Figure 6. Data, Strobe and Mask Overshoot and Undershoot Definition
- 15 -
Rev. 1.4
datasheet
K4A8G165WB
DDR4 SDRAM
8.4 Slew Rate Definitions
8.4.1 Slew Rate Definitions for Differential Input Signals (CK)
Input slew rate for differential signals (CK_t, CK_c) are defined and measured as shown in Table 14 and Figure 7.
[ Table 14 ] Differential input slew rate definition
Measured
Description
From
Differential input slew rate for rising edge(CK_t - CK_c)
V
Differential input slew rate for falling edge(CK_t - CK_c)
V
IHdiffmin
ILdiffmax
Defined by
To
V
IHdiffmin
VIHdiffmin - VILdiffmax DeltaTRdiff
V
VIHdiffmin - VILdiffmax DeltaTFdiff
ILdiffmax
NOTE :
The differential signal (i.e. CK - CK and DQS - DQS) must be linear between these thresholds.
Differential Input Voltage(i,e, CK_t - CK_c)
Delta TRdiff
V
IHdiffmin
0
V
Delta TFdiff
Figure 7. Differential Input Slew Rate definition for CK, CK
- 16 -
ILdiffmax
K4A8G165WB
Rev. 1.4
datasheet
DDR4 SDRAM
8.4.2 Slew Rate Definition for Single-ended Input Signals ( CMD/ADD )
Delta TRsingle
V
IHCA(AC) Min
V
IHCA(DC) Min
VREFCA(DC)
V
ILCA(DC) Max
V
ILCA(AC) Max
Delta TFsingle
NOTE :
1. Single-ended input slew rate for rising edge = { VIHCA(AC)Min - VILCA(DC)Max } / Delta TR single
2. Single-ended input slew rate for falling edge = { VIHCA(DC)Min - VILCA(AC)Max } / Delta TF single
3. Single-ended signal rising edge from VILCA(DC)Max to VIHCA(DC)Min must be monotonic slope.
4. Single-ended signal falling edge from VIHCA(DC)Min to VILCA(DC)Max must be monotonic slope.
Figure 8. Single-ended Input Slew Rate definition for CMD and ADD
- 17 -
Rev. 1.4
datasheet
K4A8G165WB
DDR4 SDRAM
8.5 Differential Input Cross Point Voltage
To guarantee tight setup and hold times as well as output skew parameters with respect to clock, each cross point voltage of differential input signals
(CK_t, CK_c) must meet the requirements in Table. The differential input cross point voltage VIX is measured from the actual cross point of true and
complement signals to the midlevel between of VDD and VSS.
VDD
CK_t
Vix
VDD/2
Vix
CK_c
VSEL
VSEH
VSS
Figure 9. Vix Definition (CK)
[ Table 15 ] Cross point voltage for differential input signals (CK)
Symbol
DDR4-1600/1866/2133
Parameter
min
max
-
Area of VSEH, VSEL
VSEL =< VDD/2 145mV
VDD/2 - 145mV =<
VSEL =< VDD/2 100mV
VlX(CK)
Differential Input Cross Point Voltage relative to
VDD/2 for CK_t, CK_c
-120mV
-(VDD/2 - VSEL) +
25mV
Symbol
Parameter
VDD/2 + 100mV =<
VSEH =< VDD/2 +
145mV
VDD/2 + 145mV =<
VSEH
(VSEH - VDD/2) 25mV
120mV
DDR4-2400/2666
min
max
-
Area of VSEH, VSEL
TBD
TBD
TBD
TBD
VlX(CK)
Differential Input Cross Point Voltage relative to
VDD/2 for CK_t, CK_c
TBD
TBD
TBD
TBD
- 18 -
Rev. 1.4
datasheet
K4A8G165WB
DDR4 SDRAM
8.6 CMOS rail to rail Input Levels
8.6.1 CMOS rail to rail Input Levels for RESET_n
[ Table 16 ] CMOS rail to rail Input Levels for RESET_n
Parameter
Symbol
Min
Max
Unit
NOTE
AC Input High Voltage
VIH(AC)_RESET
0.8*VDD
VDD
V
6
DC Input High Voltage
VIH(DC)_RESET
0.7*VDD
VDD
V
2
DC Input Low Voltage
VIL(DC)_RESET
VSS
0.3*VDD
V
1
AC Input Low Voltage
VIL(AC)_RESET
VSS
0.2*VDD
V
7
Rising time
TR_RESET
-
1.0
us
4
RESET pulse width
tPW_RESET
1.0
-
us
3,5
NOTE :
1.After RESET_n is registered LOW, RESET_n level shall be maintained below VIL(DC)_RESET during tPW_RESET, otherwise, SDRAM may not be reset.
2. Once RESET_n is registered HIGH, RESET_n level must be maintained above VIH(DC)_RESET, otherwise, SDRAM operation will not be guaranteed until it is reset
asserting RESET_n signal LOW.
3. RESET is destructive to data contents.
4. No slope reversal(ringback) requirement during its level transition from Low to High.
5. This definition is applied only “Reset Procedure at Power Stable”.
6. Overshoot might occur. It should be limited by the Absolute Maximum DC Ratings.
7. Undershoot might occur. It should be limited by Absolute Maximum DC Ratings
tPW_RESET
0.8*VDD
0.7*VDD
0.3*VDD
0.2*VDD
TR_RESET
Figure 10. RESET_n Input Slew Rate Definition
- 19 -
Rev. 1.4
datasheet
K4A8G165WB
DDR4 SDRAM
8.7 AC and DC Logic Input Levels for DQS Signals
8.7.1 Differential signal definition
Figure 11. Definition of differential DQS Signal AC-swing Level
8.7.2 Differential swing requirements for DQS (DQS_t - DQS_c)
[ Table 17 ] Differential AC and DC Input Levels for DQS
Symbol
Parameter
VIHDiffPeak
VILDiffPeak
VIH.DIFF.Peak Voltage
VIL.DIFF.Peak Voltage
DDR4-1600, 1866, 2133
Min
186
Note2
Max
Note2
-186
DDR4-2400
Min
160
Note2
Max
Note2
-160
DDR4-2666
Min
TBD
TBD
Max
TBD
TBD
Unit
Note
mV
mV
1
1
NOTE :
1.Used to define a differential signal slew-rate.
2.These values are not defined; however, the differential signals DQS_t - DQS_c, need to be within the respective limits Overshoot, Undershoot Specification for single-ended
signals.
8.7.3 Peak voltage calculation method
The peak voltage of Differential DQS signals are calculated in a following equation.
VIH.DIFF.Peak Voltage = Max(f(t))
VIL.DIFF.Peak Voltage = Min(f(t))
f(t) = VDQS_t - VDQS_c
- 20 -
K4A8G165WB
datasheet
Rev. 1.4
DDR4 SDRAM
Figure 12. Definition of differential DQS Peak Voltage
8.7.4 Differential Input Cross Point Voltage
To guarantee tight setup and hold times as well as output skew parameters with respect to strobe, the cross point voltage of differential input signals
(DQS_t, DQS_c) must meet the requirements in Table 18. The differential input cross point voltage VIX is measured from the actual cross point of true
and complement signals to the mid level that is VrefDQ.Vix Definition (DQS)
Figure 13. Vix Definition (DQS)
- 21 -
Rev. 1.4
datasheet
K4A8G165WB
DDR4 SDRAM
[ Table 18 ] Cross point voltage for differential input signals (DQS)
DDR4-1600/1866/2133/2400
Symbol
Parameter
Vix_DQS_ratio
DQS Differential input crosspoint
voltage ratio
DDR4-2666
Min
Max
Min
Max
-
25
TBD
TBD
Unit
Note
%
1, 2, 3
NOTE :
1. The base level of Vix_DQS_FR/RF is VrefDQ that is DDR4 SDRAM internal setting value by Vref Training.
2. Vix_DQS_FR is defined by this equation : Vix_DQS_FR = |Min(f(t)) x Vix_DQS_Ratio|
3. Vix_DQS_RF is defined by this equation : Vix_DQS_RF = Max(f(t)) x Vix_DQS_Ratio
8.7.5 Differential Input Slew Rate Definition
Input slew rate for differential signals (DQS_t, DQS_c) are defined and measured as shown in are Figure 11 and Figure 12.
NOTE :
1. Differential signal rising edge from VILDiff_DQS to VIHDiff_DQS must be monotonic slope.
2. Differential signal falling edge from VIHDiff_DQS to VILDiff_DQS must be monotonic slope.
Figure 14. Differential Input Slew Rate Definition for DQS_t, DQS_c
[ Table 19 ] Differential Input Slew Rate Definition for DQS_t, DQS_c
Description
Defined by
From
To
Differential input slew rate for rising edge(DQS_t - DQS_c)
VILDiff_DQS
VIHDiff_DQS
|VILDiff_DQS - VIHDiff_DQS|/DeltaTRdiff
Differential input slew rate for falling edge(DQS_t - DQS_c)
VIHDiff_DQS
VILDiff_DQS
|VILDiff_DQS - VIHDiff_DQS|/DeltaTFdiff
[ Table 20 ] Differential Input Level for DQS_t, DQS_c
Symbol
Parameter
VIHDiff_DQS
VILDiff_DQS
Differntial Input High
Differntial Input Low
DDR4-1600/1866/2133
Min
136
-
Max
-136
DDR4-2400
Min
130
-
DDR4-2666
Max
-130
Min
TBD
TBD
Max
TBD
TBD
Unit
NOTE
mV
mV
[ Table 21 ] Differential Input Slew Rate for DQS_t, DQS_c
Symbol
Parameter
SRIdiff
Differential Intput Slew Rate
DDR4-1600/1866/2133/2400
DDR4-2666
Min
Max
Min
Max
3
18
TBD
TBD
- 22 -
Unit
V/ns
NOTE
Rev. 1.4
datasheet
K4A8G165WB
DDR4 SDRAM
9. AC and DC output Measurement levels
9.1 Output Driver DC Electrical Characteristics
The DDR4 driver supports two different Ron values. These Ron values are referred as strong(low Ron) and weak mode(high Ron). A functional
representation of the output buffer is shown in the figure below. Output driver impedance RON is defined as follows:
The individual pull-up and pull-down resistors (RONPu and RONPd) are defined as follows:
RONPu =
VDDQ -Vout
I out
under the condition that RONPd is off
RONPd =
Vout
I out
under the condition that RONPu is off
Chip In Drive Mode
Output Drive
To
other
circuity
like
RCV, ...
VDDQ
IPu
RONPu
DQ
RONPd
Iout
IPd
Vout
VSSQ
Figure 15. Output driver
- 23 -
Rev. 1.4
datasheet
K4A8G165WB
DDR4 SDRAM
[ Table 22 ] Output Driver DC Electrical Characteristics, assuming RZQ=240ohm; entire operating temperature range;
after proper ZQ calibration
RONNOM
Resistor
Vout
Min
Nom
Max
Unit
NOTE
VOLdc= 0.5*VDDQ
0.8
1
1.1
RZQ/7
1,2
RON34Pd
VOMdc= 0.8* VDDQ
0.9
1
1.1
RZQ/7
1,2
VOHdc= 1.1* VDDQ
0.9
1
1.25
RZQ/7
1,2
1,2
34
RON34Pu
RON48Pd
48
RON48Pu
VOLdc= 0.5* VDDQ
0.9
1
1.25
RZQ/7
VOMdc= 0.8* VDDQ
0.9
1
1.1
RZQ/7
1,2
VOHdc= 1.1* VDDQ
0.8
1
1.1
RZQ/7
1,2
VOLdc= 0.5*VDDQ
0.8
1
1.1
RZQ/5
1,2
VOMdc= 0.8* VDDQ
0.9
1
1.1
RZQ/5
1,2
VOHdc= 1.1* VDDQ
0.9
1
1.25
RZQ/5
1,2
VOLdc= 0.5* VDDQ
0.9
1
1.25
RZQ/5
1,2
VOMdc= 0.8* VDDQ
0.9
1
1.1
RZQ/5
1,2
VOHdc= 1.1* VDDQ
0.8
1
1.1
RZQ/5
1,2
Mismatch between pull-up and
pull-down, MMPuPd
VOMdc= 0.8* VDDQ
-10
-
10
%
1,2,3,4
Mismatch DQ-DQ within byte variation pull-up, MMPudd
VOMdc= 0.8* VDDQ
-
-
10
%
1,2,4
Mismatch DQ-DQ within byte variation pull-dn, MMPddd
VOMdc= 0.8* VDDQ
-
-
10
%
1,2,4
NOTE :
1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity(TBD).
2. Pull-up and pull-dn output driver impedances are recommended to be calibrated at 0.8 * VDDQ. Other calibration schemes may be used to achieve the linearity spec
shown above, e.g. calibration at 0.5 * VDDQ and 1.1 * VDDQ.
3. Measurement definition for mismatch between pull-up and pull-down, MMPuPd : Measure RONPu and RONPD both at 0.8*VDD separately; Ronnom is the nominal Ron
value
MMPuPd =
RONPu -RONPd
RONNOM
*100
4. RON variance range ratio to RON Nominal value in a given component, including DQS_t and DQS_c.
MMPudd =
MMPddd =
RONPuMax -RONPuMin
RONNOM
RONPdMax -RONPdMin
RONNOM
5. This parameter of x16 device is specified for Uper byte and Lower byte.
- 24 -
*100
*100
Rev. 1.4
datasheet
K4A8G165WB
DDR4 SDRAM
9.1.1 Alert_n output Drive Characteristic
A functional representation of the output buffer is shown in the figure below. Output driver impedance RON is defined as follows:
RONPd =
Vout
l Iout l
under the condition that RONPu is off
Alert Driver
DRAM
Alert
RONPd
Iout
IPd
Vout
VSSQ
Resistor
RONPd
Vout
Min
Max
Unit
NOTE
VOLdc= 0.1* VDDQ
0.3
1.2
34Ω
1
VOMdc = 0.8* VDDQ
0.4
1.2
34Ω
1
VOHdc = 1.1* VDDQ
0.4
1.4
34Ω
1
NOTE :
1. VDDQ voltage is at VDDQ DC. VDDQ DC definition is TBD.
9.1.2 Output Driver Characteristic of Connectivity Test ( CT ) Mode
Following Output driver impedance RON will be applied Test Output Pin during Connectivity Test ( CT ) Mode.
The individual pull-up and pull-down resistors (RONPu_CT and RONPd_CT) are defined as follows:
RONPu_CT =
RONPd_CT =
VDDQ-VOUT
l Iout l
VOUT
l Iout l
Chip In Driver Mode
Output Driver
VDDQ
IPu_CT
To
other
circuity
like
RCV,...
RON
Pu_CT
DQ
Iout
RON
Pd_CT
Vout
IPd_CT
VSSQ
Figure 16. Output Driver
- 25 -
datasheet
K4A8G165WB
RONNOM_CT
Rev. 1.4
Resistor
RONPd_CT
34
RONPu_CT
DDR4 SDRAM
Vout
Max
Units
NOTE
VOBdc = 0.2 x VDDQ
1.9
34
1
VOLdc = 0.5 x VDDQ
2.0
34
1
VOMdc = 0.8 x VDDQ
2.2
34
1
VOHdc = 1.1 x VDDQ
2.5
34
1
VOBdc = 0.2 x VDDQ
2.5
34
1
VOLdc = 0.5 x VDDQ
2.2
34
1
VOMdc = 0.8 x VDDQ
2.0
34
1
VOHdc = 1.1 x VDDQ
1.9
34
1
NOTE :
1. Connectivity test mode uses un-calibrated drivers, showing the full range over PVT. No mismatch between pull up and pull down is defined.
9.2 Single-ended AC & DC Output Levels
[ Table 23 ] Single-ended AC & DC output levels
Symbol
Parameter
DDR4-1600/1866/2133/2400/2666
Units
VOH(DC)
DC output high measurement level (for IV curve linearity)
1.1 x VDDQ
V
NOTE
VOM(DC)
DC output mid measurement level (for IV curve linearity)
0.8 x VDDQ
V
VOL(DC)
DC output low measurement level (for IV curve linearity)
0.5 x VDDQ
V
VOH(AC)
AC output high measurement level (for output SR)
(0.7 + 0.15) x VDDQ
V
1
VOL(AC)
AC output low measurement level (for output SR)
(0.7 - 0.15) x VDDQ
V
1
NOTE :
1. The swing of ± 0.15 × VDDQ is based on approximately 50% of the static single-ended output peak-to-peak swing with a driver impedance of RZQ/7Ω and an effective test
load of 50Ω to VTT = VDDQ.
9.3 Differential AC & DC Output Levels
[ Table 24 ] Differential AC & DC output levels
DDR4-1600/1866/2133/2400/2666
Units
NOTE
VOHdiff(AC)
Symbol
AC differential output high measurement level (for output SR)
Parameter
+0.3 x VDDQ
V
1
VOLdiff(AC)
AC differential output low measurement level (for output SR)
-0.3 x VDDQ
V
1
NOTE :
1. The swing of ± 0.3 × VDDQ is based on approximately 50% of the static differential output peak-to-peak swing with a driver impedance of RZQ/7Ω and an effective test load
of 50Ω to VTT = VDDQ at each of the differential outputs.
- 26 -
Rev. 1.4
datasheet
K4A8G165WB
DDR4 SDRAM
9.4 Single-ended Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC) for
single ended signals as shown in Table 25 and Figure 17.
[ Table 25 ] Single-ended output slew rate definition
Measured
Description
Defined by
From
To
Single ended output slew rate for rising edge
VOL(AC)
VOH(AC)
[VOH(AC)-VOL(AC)] / Delta TRse
Single ended output slew rate for falling edge
VOH(AC)
VOL(AC)
[VOH(AC)-VOL(AC)] / Delta TFse
NOTE :
1. Output slew rate is verified by design and characterization, and may not be subject to production test.
VOH(AC)
VTT
VOL(AC)
delta TFse
delta TRse
Figure 17. Single-ended Output Slew Rate Definition
[ Table 26 ] Single-ended output slew rate
Parameter
Single ended output slew rate
Symbol
SRQse
DDR4-1600
DDR4-1866
DDR4-2133
DDR4-2400
Min
Max
Min
Max
Min
Max
Min
Max
Min
DDR4-2666
Max
4
9
4
9
4
9
4
9
TBD
TBD
Units
V/ns
Description: SR: Slew Rate
Q: Query Output (like in DQ, which stands for Data-in, Query-Output)
se: Single-ended Signals
For Ron = RZQ/7 setting
NOTE :
1. In two cases, a maximum slew rate of 12 V/ns applies for a single DQ signal within a byte lane.
-Case 1 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low or low to high) while all remaining DQ signals in the
same byte lane are static (i.e. they stay at either high or low).
-Case 2 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low or low to high) while all remaining DQ signals in the
same byte lane are switching into the opposite direction (i.e. from low to high or high to low respectively). For the remaining DQ signal switching into the opposite direction, the
regular maximum limit of 9 V/ns applies
- 27 -
Rev. 1.4
datasheet
K4A8G165WB
DDR4 SDRAM
9.5 Differential Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOLdiff(AC) and
VOHdiff(AC) for differential signals as shown in Table 27 and Figure 18.
[ Table 27 ] Differential output slew rate definition
Measured
Description
Defined by
From
To
Differential output slew rate for rising edge
VOLdiff(AC)
VOHdiff(AC)
[VOHdiff(AC)-VOLdiff(AC)] / Delta TRdiff
Differential output slew rate for falling edge
VOHdiff(AC)
VOLdiff(AC)
[VOHdiff(AC)-VOLdiff(AC)] /Delta TFdiff
NOTE :
1. Output slew rate is verified by design and characterization, and may not be subject to production test.
VOHdiff(AC)
VTT
VOLdiff(AC)
delta TFdiff
delta TRdiff
Figure 18. Differential Output Slew Rate Definition
[ Table 28 ] Differential output slew rate
Parameter
Differential output slew rate
Symbol
DDR4-1600
DDR4-1866
DDR4-2133
DDR4-2400
DDR4-2666
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
8
18
8
18
8
18
8
18
TBD
TBD
SRQdiff
Description:
SR: Slew Rate
Q: Query Output (like in DQ, which stands for Data-in, Query-Output)
diff: Differential Signals
For Ron = RZQ/7 setting
- 28 -
Units
V/ns
Rev. 1.4
datasheet
K4A8G165WB
DDR4 SDRAM
9.6 Single-ended AC & DC Output Levels of Connectivity Test Mode
Following output parameters will be applied for DDR4 SDRAM Output Signal during Connectivity Test Mode.
[ Table 29 ] Single-ended AC & DC output levels of Connectivity Test Mode
Symbol
Parameter
DDR4-1600/1866/2133 /2400/2666
Unit
Notes
VOH(DC)
DC output high measurement level (for IV curve linearity)
1.1 x VDDQ
V
VOM(DC)
DC output mid measurement level (for IV curve linearity)
0.8 x VDDQ
V
VOL(DC)
DC output low measurement level (for IV curve linearity)
0.5 x VDDQ
V
VOB(DC)
DC output below measurement level (for IV curve linearity)
0.2 x VDDQ
V
VOH(AC)
AC output high measurement level (for output SR)
VTT + (0.1 x VDDQ)
V
1
VOL(AC)
AC output below measurement level (for output SR)
VTT - (0.1 x VDDQ)
V
1
Unit
Notes
NOTE
1. The effective test load is 50Ω terminated by VTT = 0.5 * VDDQ.
VOH(AC)
0.5 * VDDQ
VTT
VOL(AC)
TR_output_CT
TR_output_CT
Figure 19. Output Slew Rate Definition of Connectivity Test Mode
[ Table 30 ] Single-ended output slew rate of Connectivity Test Mode
Parameter
DDR4-1600/1866/2133/2400/2666
Symbol
Min
Max
Output signal Falling time
TF_output_CT
-
10
ns/V
Output signal Rising time
TR_output_CT
-
10
ns/V
9.7 Test Load for Connectivity Test Mode Timing
The reference load for ODT timings is defined in Figure 18.
VDDQ
CT_INPUTS
DQ, DM
DQSL , DQSL
DQSU , DQSU
DQS , DQS
DUT
Rterm = 50 ohm
VSSQ
Timing Reference Points
Figure 20. Connectivity Test Mode Timing Reference Load
- 29 -
0.5*VDDQ
Rev. 1.4
datasheet
K4A8G165WB
DDR4 SDRAM
10. Speed Bin
[ Table 31 ] DDR4-1600 Speed Bins and Operations
Speed Bin
DDR4-1600
CL-nRCD-nRP
11-11-11
Parameter
Symbol
tAA
Internal read command to first data with read DBI enabled
tAA_DBI
ACT to internal read or write delay time
tRCD
PRE command period
tRP
ACT to PRE command period
tRAS
CWL = 9
CWL = 9,11
NOTE
18.00
ns
11
tAA(max) +2nCK
ns
11
-
ns
11
-
ns
11
9 x tREFI
ns
11
-
ns
11
1.6
ns
1,2,3,4,10,13
min
max
13.7513
Internal read command to first data
ACT to ACT or REF command period
Unit
(13.50)5,11
tAA(min) + 2nCK
13.7513
(13.50)5,11
13.7513
(13.50)5,11
35
48.75
tRC
(48.50)5,11
Normal
Read DBI
CL = 9
CL = 11
tCK(AVG)
CL = 10
CL = 12
tCK(AVG)
Reserved
ns
1,2,3,4,10
CL = 10
CL = 12
tCK(AVG)
Reserved
ns
1,2,3,4
1.5
(Optional)5,11
CL = 11
CL = 13
tCK(AVG)
1.25
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