K4B1G0846C-ZCG9

K4B1G04(08/16)46C 1Gb DDR3 SDRAM 1Gb C-die DDR3 SDRAM Specification Revision 1.0 June 2007 INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. * Samsung Electronics reserves the right to change products or specification without notice. Page 1 of 63 Rev. 1.0 June 2007 K4B1G04(08/16)46C 1Gb DDR3 SDRAM History - Revision 0.0 release - Deleted 800Mbps 5-5-5 speed - Timing Parameters by Speed Grade (13.0) - Input/Output Capacitance (11.0) - Revision 1.0 specification release. Revision History Revision 0.0 0.1 1.0 Month January June June Year 2007 2007 2007 Page 2 of 63 Rev. 1.0 June 2007 K4B1G04(08/16)46C 1Gb DDR3 SDRAM Table Contents 1.0 Ordering Information ....................................................................................................................................................4 2.0 Key Features .................................................................................................................................................................4 3.0 Package pinout/Mechanical Dimension & Addressing .............................................................................................5 3.1 x4 Package Pinout (Top view) : 94ball FBGA Package(78balls + 16 balls of support balls) ..........................................5 3.2 x8 Package Pinout (Top view) : 94ball FBGA Package(78balls + 16 balls of support balls) ..........................................6 3.3 x16 Package Pinout (Top view) : 112ball FBGA Package(96balls + 16 balls of support balls) ......................................7 3.4 FBGA Package Dimension (x4) ...................................................................................................................................8 3.5 FBGA Package Dimension (x8) ...................................................................................................................................9 3.6 FBGA Package Dimension (x16) ...............................................................................................................................10 4.0 Input/Output Functional Description ........................................................................................................................11 5.0 DDR3 SDRAM Addressing .........................................................................................................................................12 6.0 Absolute Maximum Ratings .......................................................................................................................................14 6.1 Absolute Maximum DC Ratings ................................................................................................................................14 6.2 DRAM Component Operating Temperature Range ....................................................................................................14 7.0 AC & DC Operating Conditions .................................................................................................................................14 7.1 Recommended DC operating Conditions (SSTL_1.5) .................................................................................................14 8.0 AC & DC Input Measurement Levels .........................................................................................................................15 8.1 AC and DC Logic input levels for single-ended signals .............................................................................................15 8.2 Differential swing requirement for differntial signals ................................................................................................16 8.2.1 Single-ended requirements for differential signals ............................................................................................17 8.3 AC and DC logic input levels for Differential Signals .................................................................................................18 8.4 Differential Input Cross Point Voltage .......................................................................................................................18 8.5 Slew rate definition for Single Ended Input Signals ...................................................................................................19 8.5.1 Input Slew Rate for Input Setup Time (tIS) and Data Setup Time (tDS) ...............................................................19 8.5.2 Input Slew Rate for Input Hold Time (tIH) and Data Hold Time (tDH) ..................................................................19 8.6 Slew rate definition for Differential Input Signals ......................................................................................................19 9.0 AC and DC Output Measurement Levels .................................................................................................................. 20 9.1 Single Ended AC and DC Output Levels ....................................................................................................................20 9.2 Differential AC and DC Output Levels .......................................................................................................................20 9.3.Single Ended Output Slew Rate ................................................................................................................................ 21 9.4 Differential Output Slew Rate ....................................................................................................................................21 9.5 Reference Load for AC Timing and Output Slew Rate ................................................................................................22 9.6 Overshoot/Undershoot Specification ........................................................................................................................23 9.6.1 Address and Control Overshoot and Undershoot specifications .......................................................................23 9.6.2 Clock, Data, Strobe and Mask Overshoot and Undershoot specifications ..........................................................23 9.7 34 ohm Output Driver DC Electrical Characteristics ..................................................................................................24 9.7.1 Output Drive Temperature and Voltage sensitivity ............................................................................................25 9.8 On-Die Termination (ODT) Levels and I-V Characteristics ..........................................................................................25 9.8.1 ODT DC electrical characteristics .....................................................................................................................26 9.8.2 ODT Temperature and Voltage sensitivity ......................................................................................................... 27 9.9 ODT Timing Definitions ............................................................................................................................................ 28 9.9.1 Test Load for ODT Timings ............................................................................................................................... 28 9.9.2 ODT Timing Definition ......................................................................................................................................28 10.0 Idd Specification Parameters and Test Conditions ...............................................................................................31 10.1 IDD Measurement Conditions .................................................................................................................................31 10.2 IDD Specifications ..................................................................................................................................................41 11.0 Input/Output Capacitance ........................................................................................................................................43 12.0 Electrical Characteristics and AC timing for DDR3-800 to DDR3-1600 ................................................................44 12.1 Clock specification .................................................................................................................................................44 12.2 Clock Jitter Specification ........................................................................................................................................45 12.3 Refresh Parameters by Device Density ...................................................................................................................46 12.4 Standard Speed Bins ..............................................................................................................................................46 13.0 Timing Parameters by Speed Grade ....................................................................................................................... 48 Page 3 of 63 Rev. 1.0 June 2007 K4B1G04(08/16)46C 1.0 Ordering Information [ Table 1 ] Samsung DDR3 ordering information table Organization 256Mx4 128Mx8 64Mx16 DDR3-800 (6-6-6) K4B1G0446C-ZCF7 K4B1G0846C-ZCF7 K4B1G1646C-ZCF7 DDR3-1066 (7-7-7/8-8-8) K4B1G0446C-CF8/G8 K4B1G0846C-CF8/G8 K4B1G1646C-CF8/G8 1Gb DDR3 SDRAM DDR3-1333 (8-8-8/9-9-9) K4B1G0446C-ZCG9/H9 K4B1G0846C-ZCG9/H9 K4B1G1646C-ZCG9/H9 Package 94 FBGA 94 FBGA 112 FBGA Note : 1. Speed bin is in order of CL-tRCD-tRP. 2. x4/x8/x16 Package - including 16 support balls 2.0 Key Features [ Table 2 ] 1Gb DDR3 C-die Speed bins Speed tCK(min) CAS Latency tRCD(min) tRP(min) tRAS(min) tRC(min) DDR3-800 6-6-6 2.5 6 15 15 37.5 52.5 7 13.125 13.125 37.5 50.625 7-7-7 1.875 8 15 15 37.5 52.5 8 12 12 36 48 DDR3-1066 8-8-8 8-8-8 1.5 9 13.5 13.5 36 49.5 DDR3-1333 9-9-9 Unit ns tCK ns ns ns ns • JEDEC standard 1.5V ± 0.075V Power Supply • VDDQ = 1.5V ± 0.075V • 400 MHz fCK for 800Mb/sec/pin, 533MHz fCK for 1066Mb/sec/pin, 667MHz fCK for 1333Mb/sec/pin • 8 Banks • Posted CAS • Programmable CAS Latency: 5, 6, 7, 8, 9, 10, (11 for high density only) • Programmable Additive Latency: 0, CL-2 or CL-1 clock • Programmable CAS Write Latency (CWL) = 5 (DDR3-800), 6 (DDR3-1066), 7 (DDR3-1333) • 8-bit pre-fetch • Burst Length: 8 (Interleave without any limit, sequential with starting address “000” only), 4 with tCCD = 4 which does not allow seamless read or write [either On the fly using A12 or MRS] • Bi-directional Differential Data-Strobe • Internal(self) calibration : Internal self calibration through ZQ pin (RZQ : 240 ohm ± 1%) • On Die Termination using ODT pin • Average Refresh Period 7.8us at lower than TCASE 85×C, 3.9us at 85×C < TCASE < 95 ×C • Asynchronous Reset • Package : 94 balls FBGA - x4/x8 (with 16 support balls) 112 balls FBGA - x16 (with 16 support balls) • All of Lead-free products are compliant for RoHS Note : 1. The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation. 2. 1066Mbps CL7 doesn’t have back-ward compatibility with 800Mbps CL5 The 1Gb DDR3 SDRAM C-die is organized as a 32Mbit x 4/16Mbit x 8/ 8Mbit x 16 I/Os x 8banks device. This synchronous device achieves high speed double-data-rate transfer rates of up to 1333Mb/sec/pin (DDR31333) for general applications. The chip is designed to comply with the following key DDR3 SDRAM features such as posted CAS, Programmable CWL, Internal (Self) Calibration, On Die Termination using ODT pin and Asynchronous Reset . All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the crosspoint of differential clocks (CK rising and CK falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and DQS) in a source synchronous fashion. The address bus is used to convey row, column, and bank address information in a RAS/CAS multiplexing style. The DDR3 device operates with a single 1.5V ± 0.075V power supply and 1.5V ± 0.075V VDDQ. The 1Gb DDR3 device is available in 94ball FBGAs(x4/x8) and 112ball FBGA(x16) Note : This data sheet is an abstract of full DDR3 specification and does not cover the common features which are described in “DDR3 SDRAM Device Operation & Timing Diagram”. Page 4 of 63 Rev. 1.0 June 2007 K4B1G04(08/16)46C 3.0 Package pinout/Mechanical Dimension & Addressing 1Gb DDR3 SDRAM 3.1 x4 Package Pinout (Top view) : 94ball FBGA Package(78balls + 16 balls of support balls) 1 A B C D E F G H J K L M N P R T U V W NC NC NC NC NC NC NC NC VSS VSS VDDQ VSSQ VREFDQ NC ODT NC VSS VDD VSS VDD VSS VDD VSSQ DQ2 NC VDDQ VSS VDD CS BA0 A3 A5 A7 RESET NC DQ0 DQS DQS NC RAS CAS WE BA2 A0 A2 A9 A13 NC DM DQ1 VDD NC CK CK A10/AP A15 A12/BC A1 A11 NC VSS VSSQ DQ3 VSS NC VSS VDD ZQ VREFCA BA1 A4 A6 A8 VDD VDDQ VSSQ VSSQ VDDQ NC CKE NC VSS VDD VSS VDD VSS NC NC D E F G H J K L M N P R T NC 2 NC 3 4 NC 5 6 7 8 NC 9 10 NC 11 NC Note1: A1,A2,A4,A8,A10,A11,D1,D11,T1,T11,W1,W2,W4,W8,W10 and W11 balls indicate mechanical support balls with no internal connection 1 2 3 4 5 6 7 8 9 10 11 Ball Locations (x4) A B C Populated ball Ball not populated D E F G H Top view (See the balls through the Package) J K L M N P R T U V W Page 5 of 63 Rev. 1.0 June 2007 K4B1G04(08/16)46C 1Gb DDR3 SDRAM 3.2 x8 Package Pinout (Top view) : 94ball FBGA Package(78balls + 16 balls of support balls) 1 A B C D E F G H J K L M N P R T U V W NC NC NC NC NC NC NC NC VSS VSS VDDQ VSSQ VREFDQ NC ODT NC VSS VDD VSS VDD VSS VDD VSSQ DQ2 DQ6 VDDQ VSS VDD CS BA0 A3 A5 A7 RESET NC DQ0 DQS DQS DQ4 RAS CAS WE BA2 A0 A2 A9 A13 NU/TDQS DM/TDQS DQ1 VDD DQ7 CK CK A10/AP NC A12/BC A1 A11 NC VSS VSSQ DQ3 VSS DQ5 VSS VDD ZQ VREFCA BA1 A4 A6 A8 VDD VDDQ VSSQ VSSQ VDDQ NC CKE NC VSS VDD VSS VDD VSS NC NC D E F G H J K L M N P R T NC 2 NC 3 4 NC 5 6 7 8 NC 9 10 NC 11 NC Note1: A1,A2,A4,A8,A10,A11,D1,D11,T1,T11,W1,W2,W4,W8,W10 and W11 balls indicate mechanical support balls with no internal connection 1 2 3 4 5 6 7 8 9 10 11 Ball Locations (x8) A B C Populated ball Ball not populated D E F G H Top view (See the balls through the Package) J K L M N P R T U V W Page 6 of 63 Rev. 1.0 June 2007 K4B1G04(08/16)46C 1Gb DDR3 SDRAM 3.3 x16 Package Pinout (Top view) : 112ball FBGA Package(96balls + 16 balls of support balls) 1 A B C D E F G H J K L M N P R T U V W Y AA AB NC NC NC NC NC NC NC NC VDDQ VSSQ VDDQ VSSQ VSS VDDQ VSSQ VREFDQ NC ODT NC VSS VDD VSS VDD VSS DQU5 VDD DQU3 VDDQ VSSQ DQL2 DQL6 VDDQ VSS VDD CS BA0 A3 A5 A7 RESET DQU7 VSS DQU1 DMU DQL0 DQSL DQSL DQL4 RAS CAS WE BA2 A0 A2 A9 A13 DQU4 DQSU DQSU DQU0 DML DQL1 VDD DQL7 CK CK A10/AP A15 A12/BC A1 A11 NC VDDQ DQU6 DQU2 VSSQ VSSQ DQL3 VSS DQL5 VSS VDD ZQ VREFCA BA1 A4 A6 A8 VSS VSSQ VDDQ VDD VDDQ VSSQ VSSQ VDDQ NC CKE NC VSS VDD VSS VDD VSS NC NC D E F G H J K L M N P R T U V W NC 2 NC 3 4 NC 5 6 7 8 NC 9 10 NC 11 NC Note1: A1,A2,A4,A8,A10,A11,D1,D11,W1,W11,AB1,AB2,AB4,AB8,AB10 and AB11 balls indicate mechanical support balls with no internal connection 1 A 2 3 4 5 6 7 8 9 10 11 Ball Locations (x16) B C D E Populated ball Ball not populated F G H J K Top view (See the balls through the Package) L M N P R T U V W Y AA AB Page 7 of 63 Rev. 1.0 June 2007 K4B1G04(08/16)46C 3.4 FBGA Package Dimension (x4) 11.00 ± 0.10 0.80 x 10 = 8.00 0.80 1.60 4.00 B A #A1 INDEX MARK 1Gb DDR3 SDRAM 11 10 9 8 7 6 5 4 3 2 1 (Datum A) A B C D E F (Datum B) G H J K L M N P R T U V W 7.20 0.80 x 18 = 14.40 94 - ∅0.45 Solder ball 0.2 M A B MOLDING AREA BOTTOM VIEW 0.10MAX 18.00 ± 0.10 1.10 ± 0.10 0.50 ± 0.05 0.35 ± 0.05 #A1 11.00 ± 0.10 TOP VIEW 0.80 0.80 18.00 ± 0.10 Page 8 of 63 Rev. 1.0 June 2007 K4B1G04(08/16)46C 3.5 FBGA Package Dimension (x8) 11.00 ± 0.10 0.80 x 10 = 8.00 0.80 1.60 4.00 B A #A1 INDEX MARK 1Gb DDR3 SDRAM 11 10 9 8 7 6 5 4 3 2 1 (Datum A) A B C D E F (Datum B) G H J K L M N P R T U V W 7.20 0.80 x 18 = 14.40 94 - ∅0.45 Solder ball 0.2 M A B MOLDING AREA BOTTOM VIEW 0.10MAX 18.00 ± 0.10 1.10 ± 0.10 0.50 ± 0.05 0.35 ± 0.05 #A1 11.00 ± 0.10 TOP VIEW 0.80 0.80 18.00 ± 0.10 Page 9 of 63 Rev. 1.0 June 2007 K4B1G04(08/16)46C 3.6 FBGA Package Dimension (x16) 11.00 ± 0.10 0.80 x 10 = 8.00 0.80 1.60 4.00 B A #A1 INDEX MARK 1Gb DDR3 SDRAM 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G (Datum B) H J K L M N P R T U V W Y AA AB (Datum A) 8.40 0.80 x 21 = 16.80 MOLDING AREA 112 - ∅0.45 Solder ball 0.2 M A B BOTTOM VIEW 0.10MAX 18.00 ± 0.10 1.10 ± 0.10 0.50 ± 0.05 0.35 ± 0.05 #A1 11.00 ± 0.10 TOP VIEW 0.80 0.40 18.00 ± 0.10 Page 10 of 63 Rev. 1.0 June 2007 K4B1G04(08/16)46C 4.0 Input/Output Functional Description [ Table 3 ] Input/Output function description Symbol CK, CK Type Input Function 1Gb DDR3 SDRAM Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operation (all banks idle), or Active Power-Down (Row Active in any bank). CKE is asynchronous for self refresh exit. After VREFCA has become stable during the power on and initialization sequence, it must be maintained during all operations (including SelfRefresh). CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK, ODT and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during Self -Refresh. Chip Select: All commands are masked when CS is registered HIGH. CS provides for external Rank selection on systems with multiple Ranks. CS is considered part of the command code. On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR3 SDRAM. When enabled, ODT is only applied to each DQ, DQS, DQS and DM/TDQS, NU/TDQS (When TDQS is enabled via Mode Register A11=1 in MR1) signal for x8 configurations. The ODT pin will be ignored if the Mode Register (MR1) is programmed to disable ODT. Command Inputs: RAS, CAS and WE (along with CS) define the command being entered. Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coincident with that input data during a Write access. DM is sampled on both edges of DQS. For x8 device, the function of DM or TDQS/TDQS is enabled by Mode Register A11 setting in MR1. Bank Address Inputs: BA0 - BA2 define to which bank an Active, Read, Write or Precharge command is being applied. Bank address also determines if the mode register or extended mode register is to be accessed during a MRS cycle. Address Inputs: Provided the row address for Active commands and the column address for Read/Write commands to select one location out of the memory array in the respective bank. (A10/AP and A12/BC have additional functions, see below) The address inputs also provide the op-code during Mode Register Set commands. Autoprecharge: A10 is sampled during Read/Write commands to determine whether Autoprecharge should be performed to the accessed bank after the Read/Write operation. (HIGH:Autoprecharge; LOW: No Autoprecharge) A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). if only one bank is to be precharged, the bank is selected by bank addresses. Burst Chop:A12 is sampled during Read and Write commands to determine if burst chop(on-the-fly) will be performed. (HIGH : no burst chop, LOW : burst chopped). See command truth table for details Active Low Asynchronous Reset: Reset is active when RESET is LOW, and inactive when RESET is HIGH. RESET must be HIGH during normal operation. RESET is a CMOS rail to rail signal with DC high and low at 80% and 20% of VDD, i.e. 1.20V for DC high and 0.30V for DC low. Data Input/ Output: Bi-directional data bus. Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered in write data. Termination Data Strobe: TDQS/TDQS is applicable for X8 DRAMs only. When enabled via Mode Register A11=1 in MR1, DRAM will enable the same termination resistance function on TDQS/TDQS that is applied to DQS/DQS. When disabled via mode register A11=0 in MR1, DM/TDQS will provide the data mask function and TDQS is not used. No Connect: No internal electrical connection is present. DQ Power Supply: 1.5V +/- 0.075V DQ Ground Power Supply: 1.5V +/- 0.075V Ground Reference voltage for DQ Reference voltage for CA Reference Pin for ZQ calibration CKE Input CS Input ODT Input RAS, CAS, WE DM (DMU), (DML) Input Input BA0 - BA2 Input A0 - A12 Input A10 / AP Input A12 / BC Input RESET DQ DQS, (DQS) TDQS, (TDQS) Input Input/Output Input/Output Output NC VDDQ VSSQ VDD VSS VREFDQ VREFCA ZQ Supply Supply Supply Supply Supply Supply Supply Note : Input only pins (BA0-BA2, A0-A12, RAS, CAS, WE, CS, CKE, ODT and RESET) do not supply termination. Page 11 of 63 Rev. 1.0 June 2007 K4B1G04(08/16)46C 5.0 DDR3 SDRAM Addressing 512Mb Configuration # of Bank Bank Address Auto precharge Row Address Column Address BC switch on the fly Page size *1 1Gb DDR3 SDRAM 128Mb x4 8 BA0 - BA2 A10/AP A0 - A12 A0 - A9,A11 A12/BC 1 KB 64Mb x 8 8 BA0 - BA2 A10/AP A0 - A12 A0 - A9 A12/BC 1 KB 32Mb x16 8 BA0 - BA2 A10/AP A0 - A11 A0 - A9 A12/BC 2 KB * Reference Information : The following tables are address mapping information for other densitites 1Gb Configuration # of Bank Bank Address Auto precharge Row Address Column Address BC switch on the fly Page size *1 256Mb x4 8 BA0 - BA2 A10/AP A0 - A13 A0 - A9,A11 A12/BC 1 KB 128Mb x 8 8 BA0 - BA2 A10/AP A0 - A13 A0 - A9 A12/BC 1 KB 64Mb x16 8 BA0 - BA2 A10/AP A0 - A12 A 0 - A9 A12/BC 2 KB 2Gb Configuration # of Bank Bank Address Auto precharge Row Address Column Address BC switch on the fly Page size 512Mb x4 8 BA0 - BA2 A10/AP A0 - A14 A0 - A9,A11 A12/BC 1 KB 256Mb x 8 8 BA0 - BA2 A10/AP A0 - A14 A0 - A9 A12/BC 1 KB 128Mb x16 8 BA0 - BA2 A10/AP A0 - A13 A 0 - A9 A12/BC 2 KB 4Gb Configuration # of Bank Bank Address Auto precharge Row Address Column Address BC switch on the fly Page size 1Gb x4 8 BA0 - BA2 A10/AP A0 - A15 A0 - A9,A11 A12/BC 1 KB 512Mb x 8 8 BA0 - BA2 A10/AP A0 - A15 A 0 - A9 A12/BC 1 KB 256Mb x16 8 BA0 - BA2 A10/AP A0 - A14 A0 - A 9 A12/BC 2 KB Page 12 of 63 Rev. 1.0 June 2007 K4B1G04(08/16)46C 8Gb Configuration # of Bank Bank Address Auto precharge Row Address Column Address BC switch on the fly Page size 2Gb x4 8 BA0 - BA2 A10/AP A0 - A15 A0 - A9,A11,A13 A12/BC 2 KB 1Gb x 8 8 BA0 - BA2 A10/AP A0 - A15 A0 - A9,A11 A12/BC 2 KB 1Gb DDR3 SDRAM 512Mb x16 8 BA0 - BA2 A10/AP A0 - A15 A0 - A9 A12/BC 2 KB Note 1 : Page size is the number of bytes of data delivered from the array to the internal sense amplifiers when an ACTIVE command is registered. Page size is per bank, calculated as follows: page size = 2 COLBITS * ORG ³ 8 where, COLBITS = the number of column address bits, ORG = the number of I/O (DQ) bits Page 13 of 63 Rev. 1.0 June 2007 K4B1G04(08/16)46C 6.0 Absolute Maximum Ratings 6.1 Absolute Maximum DC Ratings Symbol VDD VDDQ VIN, VOUT TSTG Parameter Voltage on VDD pin relative to Vss Voltage on VDDQ pin relative to Vss Voltage on any pin relative to Vss Storage Temperature Rating -0.4 V ~ 1.975 V -0.4 V ~ 1.975 V -0.4 V ~ 1.975 V -55 to +100 1Gb DDR3 SDRAM Units V V V °C Notes 1,3 1,3 1 [ Table 4 ] Absolute Maximum DC Ratings Note : 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. 3. VDD and VDDQ must be within 300mV of each other at all times;and VREF must be not greater than 0.6xVDDQ, When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV. 6.2 DRAM Component Operating Temperature Range Symbol TOPER Parameter Normal Operating Temperature Range Extended Temperature Range (Optional) rating 0 to 85 85 to 95 Unit °C °C Notes 1,2 1,3 [ Table 5 ] Temperature Range Note : 1. Operating Temperature TOPER is the case surface temperature on the center/top side of the DRAM. For measurement conditions, please refer to the JEDEC document JESD51-2. 2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0-85°C under all operating conditions 3. Some applications require operation of the Extended Temperature Range between 85°C and 95°C case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply: a) Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9us. It is also possible to specify a component with 1X refresh (tREFI to 7.8us) in the Extended Temperature Range. Please refer to supplier data sheet and/or the DIMM SPD for option availability. b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b) or enable the optional Auto Self-Refresh mode (MR2 A6 = 1b and MR2 A7 = 0b). Please refer to the supplier data sheet and/or the DIMM SPD for Auto Self-Refresh option availability, Extended Temperature Range support and tREFI requirements in the Extended Temperature Range. 7.0 AC & DC Operating Conditions 7.1 Recommended DC operating Conditions (SSTL_1.5) Symbol VDD VDDQ Supply Voltage Supply Voltage for Output Parameter Rating Min. 1.425 1.425 Typ. 1.5 1.5 Max. 1.575 1.575 Units V V Notes 1,2 1,2 [ Table 6 ] Recommended DC Operating Conditions Note : 1. Under all conditions VDDQ must be less than or equal to VDD. 2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together. Page 14 of 63 Rev. 1.0 June 2007 K4B1G04(08/16)46C 8.0 AC & DC Input Measurement Levels 8.1 AC and DC Logic input levels for single-ended signals Symbol VIH(DC) VIL(DC) VIH(AC) VIL(AC) VREFDQ(DC) VREFCA(DC) Parameter dc input logic high dc input logic low ac input logic high ac input logic low I/O Reference Voltage(DQ) I/O Reference Voltage(CMD/ADD) DDR3-800/1066/1333 Min. VREF + 100 VSS VREF + 175 0.49*VDDQ 0.49*VDDQ 1Gb DDR3 SDRAM Max. VDD VREF - 100 VREF - 175 0.51*VDDQ 0.51*VDDQ Unit mV mV mV mV V V Notes 1 1 1,2 1,2 3,4 3,4 [ Table 7 ] Single Ended AC and DC input levels Note : 1. For DQ and DM, VREF = VREFDQ . For input only pins except RESET, or VREF = VREFCA 2. See 9.6 "Overshoot and Undershoot specifications" on page 23. 3. The ac peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than ± 1% VDD (for reference : approx. ± 15mV) 4. For reference : approx. VDD/2 ± 15mV The dc-tolerance limits and ac-noise limits for the reference voltages VREFCA and VREFDQ are illustrate in Figure 1. It shows a valid reference voltage VREF(t) as a function of time. (VREF stands for VREFCA and VREFDQ likewise). VREF(DC) is the linear average of VREF(t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requiremts in above table. Furthermore VREF(t) may temporarily deviate from VREF(DC) by no more than ± 1% VDD. voltage VDD VRef(DC) VRef ac-noise VRef(DC) VRef(DC)max VDD/2 VRef(DC)min VSS time Figure 1. Illustration of VREF(DC) tolerance and VREF ac-noise limits The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on VRef. "VRef" shall be understood as VRef(DC), as defined in Figure 1. This clarifies, that dc-variations of VRef affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is measured. System timing and voltage budgets need to account for VRef(DC) deviations from the optimum position within the data-eye of the input signals. This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with VRef ac-noise. Timing and voltage effects due to ac-noise on VRef up to the specified limit (+/-1% of VDD) are included in DRAM timings and their associated deratings. Page 15 of 63 Rev. 1.0 June 2007 K4B1G04(08/16)46C 8.2 Differential swing requirement for differntial signals 1Gb DDR3 SDRAM Figure 2 : Definition of differntial ac-swing and "time above ac level tDVAC tDVAC VIHdiff(ac) min VIHdiff min VIHdiff(dc) min 0.0 VIHdiff(ac) max VIHdiff max VIHdiff(dc) max differential voltage time half cycle time tDVAC CK - CK DQS - DQS [ Table 8 ] Differential swing requirement for clock (CK - CK) and strobe (DQS - DQS) Symbol VIHdiff VILdiff VIHdiff(ac) VIHdiff(ac) Parameter differential input high differential input low differential input high ac differential input low ac DDR3-800 & 1066 & 1033 & 1600 min +0.2 note 3 2 x (VIH(ac)-Vref) note 3 max note 3 -0.2 note 3 2 x (Vref - VIL(ac)) unit V V V V Note 1 1 2 2 Notes: 1. used to define a differential signal slew-rate. 2. for CK - CK use VIH/VIL(ac) of ADD/CMD and VREFCA; for DQS - DQS, DQSL - DQSL, DQSU - DQSU use VIH/VIL(ac) of DQs and VREFDQ; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here. 3. these values are not defined, however they single-ended signals CK, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective limits (VIH(dc) max, VIL(dc)min) for single-ended signals as well as the limitations for overshoot and undershoot. [ Table 9 ] Allowed time before ringback (tDVAC) for CLK - CLK and DQS - DQS. Slew Rate [V/ns] > 4.0 4.0 3.0 2.0 1.8 1.6 1.4 1.2 1.0 < 1.0 tDVAC [ps] @ |VIH/Ldiff(ac)| = 350mV min 75 57 50 38 34 29 22 13 0 0 max - tDVAC [ps] @ |VIH/Ldiff(ac)| = 300mV min 175 170 167 163 162 161 159 155 150 150 max - Page 16 of 63 Rev. 1.0 June 2007 K4B1G04(08/16)46C 8.2.1 Single-ended requirements for differential signals 1Gb DDR3 SDRAM Each individual component of a differential signal (CK, DQS, DQSL, DQSU, CK, DQS, DQSL, or DQSU) has also to comply with certain requirements for single-ended signals. CK and CK have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels ( VIH(ac) / VIL(ac) ) for ADD/CMD signals) in every half-cycle. DQS, DQSL, DQSU, DQS, DQSL have to reach VSEHmin / VSELmax (approximately the ac-levels ( VIH(ac) / VIL(ac) ) for DQ signals) in every half-cycle preceeding and following a valid transition. Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g. if VIH150(ac)/VIL150(ac) is used for ADD/CMD signals, then these ac-levels apply also for the single-ended signals CK and CK VDD or VDDQ VSEH min VSEH VDD/2 or VDDQ/2 CK or DQS VSEL max VSS or VSSQ VSEL time Figure 3: Single-ended requirement for differential signals. Note that while ADD/CMD and DQ signal requirements are with respect to Vref, the single-ended components of differential signals have a requirement with respect to VDD/2; this is nominally the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For single-ended components of differential signals the requirement to reach VSELmax, VSEHmin has no bearing on timing, but adds a restriction on the common mode charateristics of these signals. Page 17 of 63 Rev. 1.0 June 2007 K4B1G04(08/16)46C 8.3 AC and DC logic input levels for Differential Signals [ Table 10 ] Differential DC and AC input levels Symbol VIHdiff VILdiff Parameter Differential input logic high Differential input logic low DDR3-800/1066/1333 Min + 200 Max - 200 1Gb DDR3 SDRAM Unit mV Notes 1 Note : 1. Refer to "Overshoot and Undershoot specifications" on page 23. 8.4 Differential Input Cross Point Voltage To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (CK, CK and DQS, DQS) must meet the requirements in below table. The differential input cross point voltage VIX is measured from the actual cross point of true and complement signal to the midlevel between of VDD and VSS. VDD CK, DQS VIX VDD/2 VIX VIX CK, DQS VSS Figure 4. Vix Definition [ Table 11 ] Cross point voltage for differential input signals (CK, DQS) Symbol VIX Parameter Differential input Cross point voltage relative to VDD/2 DDR3-800/1066/1333/1600 Min -150 Max 150 Unit mV Notes Page 18 of 63 Rev. 1.0 June 2007 K4B1G04(08/16)46C 8.5 Slew rate definition for Single Ended Input Signals 8.5.1 Input Slew Rate for Input Setup Time (tIS) and Data Setup Time (tDS) 1Gb DDR3 SDRAM Setup (tIS and tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VRef and the first crossing of VIH(AC)min. Setup (tIS and tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VRef and the first crossing of VIL(AC)max. 8.5.2 Input Slew Rate for Input Hold Time (tIH) and Data Hold Time (tDH) Hold nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC)max and the first crossing of VRef. Hold (tIH & tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC)min and the first crossing of VRef Description Input slew rate for rising edge Input slew rate for falling edge Input slew rate for rising edge Input slew rate for falling edge Vref Vref Vil(DC)max Vih(DC)min Measured From To Vih(AC)min Vil(AC)max Vref Vref Defined by Vih(AC)min-Vref Delta TRS Vref-Vil(AC)max Delta TFS Vref-Vil(DC)max Delta TFH Vih(DC)min-Vref Delta TRH Applicable for Setup (tIS,tDS) Hold (tIH,tDH) [ Table 12 ] Single Ended Input Slew Rate definition Notes: This nominal slew rate applies for linear signal waveforms. VDDQ VIH(ac) min VSWING(MAX) VIH(dc) min VREF VIL(dc) max VIL(ac) max VSSQ delta TFS delta TRS delta TFH delta TRH VSWING(MAX) VDDQ VIH(ac) min VIH(dc) min VREF VIL(dc) max VIL(ac) max VSSQ < Figure : Input slew rate for setup> < Figure : Input slew rate for Hold> Figure 5. Input Nominal Slew Rate definition for Singel ended Signals 8.6 Slew rate definition for Differential Input Signals Description Measured From To VIHdiffmin VILdiffmax Defined by VIHdiffmin - VILdiffmax Delta TRdiff VIHdiffmin - VILdiffmax Delta TFdiff Differential input slew rate for rising edge (CKVILdiffmax CK and DQS-DQS) Differential input slew rate for falling edge (CKVIHdiffmin CK and DQS-DQS) [ Table 13 ] Differential input slew rate definition Note : The differential signal (i.e. CK - CK and DQS - DQS) must be linear between these thresholds VDDQ VIHdiffmin VSWING(MAX) VREF VILdiffmax VSSQ delta TFdiff delta TRdiff Figure 6. Differential Input Slew Rate definition for DQS, DQS and CK, CK Page 19 of 63 Rev. 1.0 June 2007 K4B1G04(08/16)46C 9.0 AC and DC Output Measurement Levels 9.1 Single Ended AC and DC Output Levels [ Table 14 ] Single Ended AC and DC output levels Symbol VOH(DC) VOM(DC) VOL(DC) VOH(AC) VOL(AC) Parameter DC output high measurement level (for IV curve linearity) DC output mid measurement level (for IV curve linearity) DC output low measurement level (for IV curve linearity) AC output high measurement level (for output SR) AC output low measurement level (for output SR) 1Gb DDR3 SDRAM DDR3-800/1066/1333/1600 0.8 x VDDQ 0.5 x VDDQ 0.2 x VDDQ VTT + 0.1 x VDDQ VTT - 0.1 x VDDQ Units V V V V V Notes 1 1 Note : 1. The swing of +/-0.1xVDDQ is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 34ohms and an effective test load of 25ohms to VTT=VDDQ/2. 9.2 Differential AC and DC Output Levels Symbol VOHdiff(AC) VOLdiff(DC) Parameter AC differential output high measurement level (for output SR) AC differential output low measurement level (for output SR) DDR3-800/1066/1333/1600 +0.2 x VDDQ -0.2 x VDDQ Units V V Notes 1 1 [ Table 15 ] Differential AC and DC output levels Note : 1. The swing of +/-0.2xVDDQ is based on approximately 50% of the static singel ended output high or low swing with a driver impedance of 34ohms and an effective test load of 25ohms to VTT=VDDQ/2 at each of the differential outputs Page 20 of 63 Rev. 1.0 June 2007 K4B1G04(08/16)46C 9.3.Single Ended Output Slew Rate 1Gb DDR3 SDRAM With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC) for single ended signals as shown in Table 16 and figure 7. [ Table 16 ] Single Ended Output slew rate definition Description Single ended output slew rate for rising edge Single ended output slew rate for falling edge Measured From VOL(AC) VOH(AC) DDR3-800 Min 2.5 Max 5 To VOH(AC) VOL(AC) DDR3-1066 Min 2.5 Max 5 DDR3-1333 Min 2.5 Max 5 Defined by VOH(AC)-VOL(AC) Delta TRse VOH(AC)-VOL(AC) Delta TFse DDR3-1600 Min TBD Max 5 Units V/ns Parameter Single ended output slew rate Symbol SRQse [ Table 17 ] Single Ended Output slew rate Note : Output slew rate is verified by design and characterization, and may not be subject to production test. For Ron=RZQ/7 setting VDDQ VOH(AC) VREF VOL(AC) VSSQ delta TFS delta TRS Figure 7. Single Ended Output Slew Rate definition 9.4 Differential Output Slew Rate With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOLdiff(AC) and VOHdiff(AC) for differential signals as shown inTable 18 and figure 8. [ Table 18 ] Differential Output slew rate definition Description Differential output slew rate for rising edge Differential output slew rate for falling edge Measured From VOLdiff(AC) VOHdiff(AC) DDR3-800 Min 5 Max 10 To VOHdiff(AC) VOLdiff(AC) DDR3-1066 Min 5 Max 10 Defined by VOHdiff(AC)-VOLdiff(AC) Delta TRdiff VOHdiff(AC)-VOLdiff(AC) Delta TFdiff DDR3-1333 Min 5 Max 10 DDR3-1600 Min TBD Max 10 Units V/ns Parameter Single ended output slew rate Symbol SRQse [ Table 19 ] Differential Output slew rate Note : Output slew rate is verified by design and characterization, and may not be subject to production test. For Ron=RZQ/7 setting VDDQ VOHdiff(AC) VREF VOLdiff(AC) VSSQ delta TFdiff delta TRdiff Figure 8. Differential Output Slew Rate definition Page 21 of 63 Rev. 1.0 June 2007 K4B1G04(08/16)46C 9.5 Reference Load for AC Timing and Output Slew Rate 1Gb DDR3 SDRAM Figure 9 represents the effective reference load of 25 ohms used in defining the relevant AC timing parameters of the device as well as output slew rate measurements. It is not intended as a precise representation of any particular system environment of a depiction of the actual load presented by a production tester. System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers correlate to their production test conditions, generally one or more coaxial transmission lines terminated at the tester electronics. VDDQ CK/CK DUT DQ DQS DQS VTT = VDDQ/2 25Ω Reference Point Figure 9. Reference Load for AC Timing and Output Slew Rate Page 22 of 63 Rev. 1.0 June 2007 K4B1G04(08/16)46C 9.6 Overshoot/Undershoot Specification 9.6.1 Address and Control Overshoot and Undershoot specifications AC Overshoot/Undershoot Specification for Address and Control Pins (A0-A12, BA0-BA2, CS, RAS, CAS, WE, CKE, ODT) Parameter Maximum peak amplitude allowed for overshoot area (See Figure 8) Maximum peak amplitude allowed for undershoot area (See Figure 8) Maximum overshoot area above VDD (See Figure 8) Maximum undershoot area below VSS (See Figure 8) 1Gb DDR3 SDRAM Specification DDR3-800 0.4V 0.4V 0.67V-ns 0.67V-ns DDR3-1066 0.4V 0.4V 0.5V-ns 0.5V-ns DDR3-1333 0.4V 0.4V 0.4V-ns 0.4V-ns DDR3-1600 0.4V 0.4V 0.33V-ns 0.33V-ns [ Table 20 ] AC overshoot/undershoot specification for Address and Control pins Maximum Amplitude Overshoot Area Volts (V) VDD VSS Maximum Amplitude Time (ns) Undershoot Area Figure 10. Address and Control Overshoot and Undershoot definition 9.6.2 Clock, Data, Strobe and Mask Overshoot and Undershoot specifications AC Overshoot/Undershoot Specification for Clock, Data, Strobe, and Mask Pins (DQ, DQS, DQS, DM, CK, CK) Parameter Maximum peak amplitude allowed for overshoot area (See Figure 9) Maximum peak amplitude allowed for undershoot area (See Figure 9) Maximum overshoot area above VDDQ (See Figure 9) Maximum undershoot area below VSSQ (See Figure 9) Specification DDR3-800 0.4V 0.4V 0.25V-ns 0.25V-ns DDR3-1066 0.4V 0.4V 0.19V-ns 0.19V-ns DDR3-1333 0.4V 0.4V 0.15V-ns 0.15V-ns DDR3-1600 0.4V 0.4V 0.13V-ns 0.13V-ns [ Table 21 ] AC overshoot/undershoot specification for Clock, Data, Strobe and Mask Maximum Amplitude Overshoot Area Volts (V) VDDQ VSSQ Maximum Amplitude Time (ns) Undershoot Area Figure 11. Clock, Data, Strobe and Mask Overshoot and Undershoot definition Page 23 of 63 Rev. 1.0 June 2007 K4B1G04(08/16)46C 9.7 34 ohm Output Driver DC Electrical Characteristics 1Gb DDR3 SDRAM A functional representation of the output buffer is shown below. Output driver impedance RON is defined by the value of external reference resistor RZQ as follows: RON34 = RZQ/7 (Nominal 34ohms +/- 10% with nominal RZQ=240ohm) The individual Pull-up and Pull-down resistors (RONpu and RONpd) are defined as follows VDDQ-Vout RONpu = l Iout l Vout RONpd = l Iout l under the condition that RONpu is turned off under the condition that RONpd is turned off Output Driver : Definition of Voltages and Currents Output Driver VDDQ Ipu To other circuity RON Pu DQ RON Ipd Iout Vout VSSQ Pd Figure 12. Output Driver : Definition of Voltages and Currents [ Table 22 ] Output Driver DC Electrical Characteristics, assuming RZQ=240 ohms ; entire operating temperature range; after proper ZQ calibration RONnom Resistor RON34pd 34Ohms RON34pu Mismatch between Pull-up and Pull-down, MMpupd Vout VOLdc = 0.2 x VDDQ VOMdc = 0.5 x VDDQ VOHdc = 0.8 x VDDQ VOLdc = 0.2 x VDDQ VOMdc = 0.5 x VDDQ VOHdc = 0.8 x VDDQ VOMdc = 0.5 x VDDQ Min 0.6 0.9 0.9 0.9 0.9 0.6 -10 Nom 1.0 1.0 1.0 1.0 1.0 1.0 Max 1.1 1.1 1.4 1.4 1.1 1.1 10 Units RZQ/7 RZQ/7 RZQ/7 RZQ/7 RZQ/7 RZQ/7 % Notes 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,4 Note : 1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity 2. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ = VSS 3. Pull-down and pull-up output driver impedance are recommended to be calibrated at 0.5 X VDDQ. Other calibration schemes may be used to achieve the linearity spec shown above, e.g. calibration at 0.2 X VDDQ and 0.8 X VDDQ 4. Measurement definition for mismatch between pull-up and pull-down, MMpupd: Measure RONpu and RONpd. both at 0.5 X VDDQ: RONpu - RONpd MMpupd = RONnom x 100 Page 24 of 63 Rev. 1.0 June 2007 K4B1G04(08/16)46C 9.7.1 Output Drive Temperature and Voltage sensitivity If temperature and/or voltage change after calibration, the tolerance limits widen according to table below ∆T = T - T(@calibration); ∆V = VDDQ - VDDQ (@calibration); VDD = VDDQ *dRONdT and dRONdV are not subject to production test but are verified by design and characterization [ Table 23 ] Output Driver Sensitivity Definition Min RONPU@VOHDC RON@VOMDC RONPD@VOLDC 0.6 - dRONdTH * |∆T| - dRONdVH * |∆V| 0.9 - dRONdTM * |∆T| - dRONdVM * |∆V| 0.6 - dRONdTL * |∆T| - dRONdVL * |∆V| Max 1Gb DDR3 SDRAM Units RZQ/7 RZQ/7 RZQ/7 1.1 + dRONdTH * |∆T| + dRONdVH * |∆V| 1.1 + dRONdTM * |∆T| + dRONdVM * |∆V| 1.1 + dRONdTL * |∆T| + dRONdVL * |∆V| [ Table 24 ] Output Driver Voltage and Temperature Sensitivity Min dRONdTM dRONdVM dRONdTL dRONdVL dRONdTH dRONdVH 0 0 0 0 0 0 Max 1.5 0.15 1.5 TBD 1.5 TBD Units %/°C %/mV %/°C %/mV %/°C %/mV 9.8 On-Die Termination (ODT) Levels and I-V Characteristics On-Die Termination effective resistance RTT is defined by bits A9, A6 and A2 of MR1 register. ODT is applied to the DQ,DQ, DQS/DQS and TDQS,TDQS (x8 devices only) pins. A functional representation of the on-die termination is shown below. The individual pull-up and pull-down resistors (RTTpu and RTTpd) are defined as follows : VDDQ-Vout RTTpu = l Iout l Vout RTTpd = l Iout l under the condition that RTTpu is turned off under the condition that RTTpd is turned off On-Die Termination : Definition of Voltages and Currents Output Driver VDDQ Ipu To other circuitry like RCV, ... Iout=Ipd-Ipu Pu RTT DQ RTT Ipd Iout Pd Vout VSSQ Figure 13. On-Die Termination : Definitionof Voltages and Currents Page 25 of 63 Rev. 1.0 June 2007 K4B1G04(08/16)46C 9.8.1 ODT DC electrical characteristics 1Gb DDR3 SDRAM Table # provides and overview of the ODT DC electrical characteristics. They values for RTT60pd120, RTT60pu120, RTT120pd240, RTT120pu240, RTT40pd80, RTT40pu80, RTT30pd60, RTT30pu60, RTT20pd40, RTT20pu40 are not specification requirements, but can be used as design guide lines:. MR1 (A9,A6,A2) RTT RESISTOR Vout 0.2XVDDQ RTT120pd240 0.5XVDDQ 0.8XVDDQ (0,1,0) 120 ohm RTT120pu240 0.2XVDDQ 0.5XVDDQ 0.8XVDDQ RTT120 MIN 0.6 0.9 0.9 0.9 0.9 0.6 0.9 0.6 0.9 0.9 0.9 0.9 0.6 0.9 0.6 0.9 0.9 0.9 0.9 0.6 0.9 0.6 0.9 0.9 0.9 0.9 0.6 0.9 0.6 0.9 0.9 0.9 0.9 0.6 0.9 -5 NOM 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 MAX 1.1 1.1 1.4 1.4 1.1 1.1 1.6 1.1 1.1 1.4 1.4 1.1 1.1 1.6 1.1 1.1 1.4 1.4 1.1 1.1 1.6 1.1 1.1 1.4 1.4 1.1 1.1 1.6 1.1 1.1 1.4 1.4 1.1 1.1 1.6 5 UNIT RZQ RZQ RZQ RZQ RZQ RZQ RZQ/2 RZQ/2 RZQ/2 RZQ/2 RZQ/2 RZQ/2 RZQ/2 RZQ/4 RZQ/3 RZQ/3 RZQ/3 RZQ/3 RZQ/3 RZQ/3 RZQ/6 RZQ/4 RZQ/4 RZQ/4 RZQ/4 RZQ/4 RZQ/4 RZQ/8 RZQ/6 RZQ/6 RZQ/6 RZQ/6 RZQ/6 RZQ/6 RZQ/12 % NOTES 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,5 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,5 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,5 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,5 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4 1,2,5 1,2,5,6 VIL(AC) TO VIH(AC) 0.2XVDDQ 0.5XVDDQ 0.8XVDDQ RTT60pd240 (0,0,1) 60 ohm RTT60pu240 0.2XVDDQ 0.5XVDDQ 0.8XVDDQ RTT60 VIL(AC) TO VIH(AC) 0.2XVDDQ 0.5XVDDQ 0.8XVDDQ RTT40pd240 (0,1,1) 40 ohm RTT40pu240 0.2XVDDQ 0.5XVDDQ 0.8XVDDQ RTT40 VIL(AC) TO VIH(AC) 0.2XVDDQ 0.5XVDDQ 0.8XVDDQ RTT60pd240 (1,0,1) 30 ohm RTT60pu240 0.2XVDDQ 0.5XVDDQ 0.8XVDDQ RTT60 VIL(AC) TO VIH(AC) 0.2XVDDQ 0.5XVDDQ 0.8XVDDQ RTT60pd240 (1,0,0) 20 ohm RTT60pu240 0.2XVDDQ 0.5XVDDQ 0.8XVDDQ RTT60 VIL(AC) TO VIH(AC) Deviation of VM w.r.t VDDQ/2, ∆VM [ Table 25 ] ODT DC Electrical characteristics, assuming RZQ=240 ohm +/- 1% entire operating temperature range; after proper ZQ calibration Page 26 of 63 Rev. 1.0 June 2007 K4B1G04(08/16)46C 1Gb DDR3 SDRAM Note : 1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity 2. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ = VSS 3. Pull-down and pull-up ODT resistors are recommended to be calibrated at 0.5XVDDQ. Other calibration schemes may be used to achieve the linearity spec shown above, e.g. calibration at 0.2XVDDQ and 0.8XVDDQ. 4. Not a specification requirement, but a design guide line 5. Measurement definition for RTT: Apply VIH(ac) to pin under test and measure current I(VIH(ac)), then apply VIL(ac) to pin under test and measure current I(VIL(ac)) perspectively VIH(ac) - VIL(ac) RTT = I(VIH(ac)) - I(VIL(ac)) 6. Measurement definition for VM and ∆VM : Measure voltage (VM) at test pin (midpoint) with no load ∆ VM = 2 x VM VDDQ -1 x 100 9.8.2 ODT Temperature and Voltage sensitivity If temperature and/or voltage change after calibration, the tolerance limits widen according to table below ∆T = T - T(@calibration); ∆V = VDDQ - VDDQ (@calibration); VDD = VDDQ [ Table 26 ] ODT Sensitivity Definition Min RTT 0.9 - dRTTdT * |∆T| - dRTTdV * |∆V| Max 1.6 + dRTTdT * |∆T| + dRTTdV * |∆V| Units RZQ/2,4,6,8,12 [ Table 27 ] ODT Voltage and Temperature Sensitivity Min dRTTdT dRTTdV 0 0 Max 1.5 0.15 Units %/°C %/mV These parameters may not be subject to production test. They are verified by design and characterization. Page 27 of 63 Rev. 1.0 June 2007 K4B1G04(08/16)46C 9.9 ODT Timing Definitions 9.9.1 Test Load for ODT Timings Different than for timing measurements, the reference load for ODT timings is defined in Figure 14. 1Gb DDR3 SDRAM VDDQ CK,CK DUTDQ, DM DQS , DQS TDQS , TDQS VTT= VSSQ RTT =25 ohm VSSQ Timing Reference Points BD_REFLOAD_ODT Figure 14. ODT Timing Reference Load 9.9.2 ODT Timing Definition Definitions for tAON, tAONPD, tAOF, tAOFPD and tADC are provided in Table28 and subsequent figures. Measurement reference settings are provided in Table29. [ Table 28 ] ODT Timing Definitions Symbol Begin Point Definition Rising edge of CK - CK defined by the end point of ODTLon Rising edge of CK - CK with ODT being first registered high Rising edge of CK - CK defined by the end point of ODTLoff Rising edge of CK - CK with ODT being first registered low Rising edge of CK - CK defined by the end point of ODTLcnw, ODTLcwn4 of ODTLcwn8 End Point Definition Extrapolated point at VSSQ Extrapolated point at VSSQ End point: Extrapolated point at VRTT_Nom End point: Extrapolated point at VRTT_Nom End point: Extrapolated point at VRTT_Wr and VRTT_Nom respectively Figute Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 tAON tAONPD tAOF tAOFPD tADC [ Table 29 ] Reference Settings for ODT Timing Measurements Measured Parameter RTT_Nom Setting RZQ/4 RZQ/12 RZQ/4 RZQ/12 RZQ/4 RZQ/12 RZQ/4 RZQ/12 RZQ/12 RTT_Wr Setting NA NA NA NA NA NA NA NA RZQ/2 VSW1[V] 0.05 0.10 0.05 0.10 0.05 0.10 0.05 0.10 0.20 VSW2[V] 0.10 0.20 0.10 0.20 0.10 0.20 0.10 0.20 0.30 Note tAON tAONPD tAOF tAOFPD tADC Page 28 of 63 Rev. 1.0 June 2007 K4B1G04(08/16)46C 1Gb DDR3 SDRAM Begin point : Rising edge of CK - CK defined by the end point of ODTLon CK VTT CK tAON TSW2 DQ, DM DQS , DQS TDQS , TDQS TSW1 VSW2 VSW1 VSSQ VSSQ End point Extrapolated point at VSSQ Figure 15. Definition of tAON Begin point : Rising edge of CK - CK with ODT being first registered high CK VTT CK tAONPD TSW2 DQ, DM DQS , DQS TDQS , TDQS TSW1 VSW2 VSW1 VSSQ VSSQ End point Extrapolated point at VSSQ Figure 16. Definition of tAONPD Begin point : Rising edge of CK - CK defined by the end point of ODTLoff CK VTT CK tAOF VRTT_Nom DQ, DM DQS , DQS TDQS , TDQS End point Extrapolated point at VRTT_Nom TSW2 VSW2 VSW1 TSW1 VSSQ TD_TAON_DEF Figure 17. Definition of tAOF Page 29 of 63 Rev. 1.0 June 2007 K4B1G04(08/16)46C 1Gb DDR3 SDRAM Begin point : Rising edge of CK - CK with ODT being first registered low CK VTT CK tAOFPD VRTT_Nom DQ, DM DQS , DQS TDQS , TDQS End point Extrapolated point at VRTT_Nom TSW2 VSW2 VSW1 TSW1 VSSQ Figure 18. Definition of tAOFPD Begin point : Rising edge of CK - CK defined by the end point of ODTLcnw Begin point : Rising edge of CK - CK defined by the end point of ODTLcwn4 or ODTLcwn8 CK VTT CK tADC tADC VRTT_Nom DQ, DM DQS , DQS TDQS , TDQS End point Extrapolated point at VRTT_Nom TSW21 TSW11 VSW1 VSW2 VRTT_Nom TSW22 TSW12 End point Extrapolated point at VRTT_Nom VRTT_Wr End point Extrapolated point at VRTT_Wr VSSQ Figure 19. Definition of tADC Page 30 of 63 Rev. 1.0 June 2007 K4B1G04(08/16)46C 10.0 Idd Specification Parameters and Test Conditions 10.1 IDD Measurement Conditions 1Gb DDR3 SDRAM Within the tables provided further down, an overview about the IDD measurement conditions is provided as follows: [ Table 30 ] Overview of Tables providing IDD Measurement Conditions and DRAM Behavior Table number Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Measurement Conditions IDD0 and IDD1 IDD2N, IDD2Q, IDD2P(0), IDD2P(1) IDD3N and IDD3P IDD4R, IDD4W, IDD7 IDD7 for different speed grades and different tRRD, tFAW conditions IDD5B IDD6, IDD6ET Within the tables about IDD measurement conditions, the following definitions are used: • LOW is defined as VIN = VIHAC(min.); • STABLE is defined as inputs are stable at a HIGH or LOW level • FLOATING is defined as inputs are VREF = VDDQ / 2 • SWITCHING is defined as described in the following 2 tables. [ Table 31 ] Definition of SWITCHING for Address and Command Input Signals SWITCHING for Address (row, column) and Command Signals (CS, RAS, CAS, WE) is defined as: Address (Row, Column): If not otherwise mentioned the inputs are stable at HIGH or LOW during 4 clocks and change then to the opposite value (e.g. Ax Ax Ax Ax Ax Ax Ax Ax Ax Ax Ax Ax ..... please see each IDDx definition for details If not otherwise mentioned the bank addresses should be switched like the row/ column addresses - please see each IDDx definition for details Define D = {CS, RAS, CAS, WE } := {HIGH, LOW, LOW, LOW} Define D = {CS, RAS, CAS, WE } := {HIGH, HIGH,HIGH,HIGH} Command (CS, RAS, CAS, WE): Define Command Background Pattern = D D D D D D D D D D D D ... If other commands are necessary (e.g. ACT for IDD0 or Read for IDD4R) the Background Pattern Command is substituted by the respective CS, RAS, CAS, WE levels of the necessary command. See each IDDx definition for details and figures 1,2,3 as examples. Bank address: [ Table 32 ] Definition of SWITCHING for Data (DQ) SWITCHING for Data (DQ) is defined as Data (DQ) Data Masking (DM) Data DQ is changing between HIGH and LOW every other data transfer (once per clock) for DQ signals, which means that data DQ is stable during one clock; see each IDDx definition for exceptions from this rule and for further details. See figures 1,2,3 as examples. NO Switching; DM must be driven LOW all the time Page 31 of 63 Rev. 1.0 June 2007 K4B1G04(08/16)46C 1Gb DDR3 SDRAM Timing parameters are listed in the following table: [ Table 33 ] For IDD testing the following parameters are utilized. Parameter tCKmin(IDD) CL(IDD) tRCDmin(IDD) tRCmin(IDD) tRASmin(IDD) tRPmin(IDD) tFAW(IDD) tRRD(IDD) tRFC(IDD) - 1Gb x4/x8 x16 x4/x8 x16 Bin DDR3-800 6-6-6 2.5 6 15 52.5 37.5 15 40 50 10 10 110 7 13.13 50.63 37.5 13.13 37.5 50 7.5 10 110 7-7-7 1.875 8 15 52.50 37.5 15 37.5 50 7.5 10 110 8 12 48 36 12 30 45 6.0 7.5 110 DDR3-1066 8-8-8 8-8-8 1.5 9 13.5 49.5 36 13.5 30 45 6.0 7.5 110 ns ns ns ns ns ns ns ns 110 DDR3-1333 9-9-9 Unit ns The following conditions apply: 1. IDD specifications are tested after the device is properly initialized. 2. Input slew rate is specified by AC Parametric test conditions. 3. IDD parameters are specified with ODT and output buffer disabled (MR1 Bit A12). Page 32 of 63 Rev. 1.0 June 2007 K4B1G04(08/16)46C [ Table 34 ] IDD Measurement Conditions for IDD0 and IDD1 Current Operating Current 0 -> One Bank Activate -> Precharge IDD0 1Gb DDR3 SDRAM IDD1 Operating Current 1 -> One Bank Activate -> Read -> Precharge Figure 1 HIGH on tCKmin(IDD) tRCmin(IDD) tRASmin(IDD) n.a. n.a. n.a. n.a. HIGH between. Activate and Precharge Commands SWITCHING as described in Table 2; only exceptions are Activate and Precharge commands; example of IDD0 pattern: HIGH on tCKmin(IDD) tRCmin(IDD) tRASmin(IDD) tRCDmin(IDD) n.a. CL(IDD) 0 HIGH between Activate, Read and Precharge SWITCHING as described in Table 2; only exceptions are Activate, Read and Precharge commands; example of IDD1 pattern: A0 D D D D R0 D D D DD D D DD D P0 (DDR3-800 -555: tRCD = 12.5ns between (A)ctivate and (R)ead to bank 0 ; Definition of D and D: see Table 2) Definition of D and D: See table ##. Name Measurement Condition Timing Diagram Example CKE External Clock tCK tRC tRAS tRCD tRRD CL AL CS Command Inputs (CS, RAS, CAS, WE) A0 D D D D D D D D D D D P0 (DDR3-800: tRAS = 37.5ns between (A)ctivate and (P)recharge to bank 0 ; Definition of D and D: see Table 2) Definition of D and D: See table ##. Row, Column Addresses Bank Addresses Row addresses SWITCHING as described in Table 2; Row addresses SWITCHING as described in Table 2; Address Input A10 must be LOW all the time! Address Input A10 must be LOW all the time! bank address is fixed (bank 0) bank address is fixed (bank 0) Read Data: output data switches every clock, which means that Read data is stable during one clock cycle. To achieve Iout = 0mA the output buffer should be switched off by MR1 Bit A12 set to "1". When there is no read data burst from DRAM the DQ I/O should be FLOATING. off / 1 disabled 8 fixed / MR0 Bits [A1, A0] = {0,0} one ACT-RD-PRE loop all other n.a. Data I/O SWITCHING as described in Table 3 Output Buffer DQ,DQS / MR1 bit A12 Rtt_NOM, Rtt_WR Burst length Active banks Idle banks Precharge Power Down Mode / Mode Register Bit 12 off / 1 disabled n.a. one ACT-PRE loop all other n.a. Page 33 of 63 Rev. 1.0 June 2007 K4B1G04(08/16)46C T0 CK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 1Gb DDR3 SDRAM T14 T15 T16 T17 T18 BA[2:0] 000 ADDR_a[9:0] 000 3FF 000 3FF 000 ADDR_b[10] ADDR_c[13:11] 000 111 000 111 000 CS RAS CAS WE CMD ACT D D D D RD D D D D D D D D D PRE D D D DQ 0 0 1 1 0 0 1 1 DM IDD1 Measurement Loop Figure 20. IDD1 Example (DDR3-800-666, 1Gb x8): Data DQ is shown but the output buffer should be switched off (per MR1 Bit A12 ="1") to achieve Iout = 0mA. Address inputs are split into 3 parts. Page 34 of 63 Rev. 1.0 June 2007 K4B1G04(08/16)46C [ Table 35 ] IDD Measurement Conditions for IDD2N, IDD2P(1), IDD2P(0) and IDD2Q Current IDD2N Precharge Standby Current IDD2P(1) a Precharge Power Down Current Fast Exit MRS A12 Bit = 1 1Gb DDR3 SDRAM IDD2P(0) Precharge Power Down Current Slow Exit MRS A12 Bit = 0 IDD2Q Precharge Quiet Standby Current Name Measurement Condition Timing Diagram Example CKE External Clock tCK tRC tRAS tRCD tRRD CL AL CS Bank Address, Row Addr. and Command Inputs Data inputs Output Buffer DQ,DQS / MR1 bit A12 Rtt_NOM, Rtt_WE Burst length Active banks Idle banks Precharge Power Down Mode / Mode Register Bit a Figure 2 HIGH on tCKmin(IDD) n.a. n.a. n.a. n.a. n.a. n.a. HIGH SWITCHING as described in Table 2 SWITCHING off / 1 disabled n.a. none all LOW on tCKmin(IDD) n.a. n.a. n.a. n.a. n.a. n.a. STABLE STABLE FLOATING off / 1 disabled n.a. none all Fast Exit / 1 (any valid command after tXP1) LOW on tCKmin(IDD) n.a. n.a. n.a. n.a. n.a. n.a. HIGH STABLE FLOATING off / 1 disabled n.a. none all Slow Exit / 0 Slow exit (RD and ODT commands must satisfy tXPDLL-AL) LOW on tCKmin(IDD) n.a. n.a. n.a. n.a. n.a. n.a. STABLE STABLE FLOATING off / 1 disabled n.a. none all n.a. n.a. Note : 1. In DDR3 the MRS Bit 12 defines DLL on/off behavior ONLY for precharge power down. There are 2 different Precharge Power Down states possible : one with DLL on (fast exit, bit 12 = 1) and one with DLL off (slow exit, bit 12 = 0). 2. Because it is an exit after precharge power down the valid commands are: Activate, Refresh, Mode-Register Set, Enter - Self Refresh. T0 CK BA[2:0] ADDR[13:0] CS RAS CAS WE CMD DQ[7:0] DM D 0 0000 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 7 3FFF 0 0000 D D D D D D D D D D FF 00 00 FF FF 00 00 FF FF 00 00 FF FF 00 00 FF FF 00 00 FF FF 00 IDD2N /IDD3N Measurement Loop Figure 21. IDD2N /IDD3N Example (DDR3-800-666, 1Gb X8) Page 35 of 63 Rev. 1.0 June 2007 K4B1G04(08/16)46C [ Table36 ] IDD Measurement Conditions for IDD3N and IDD3P(fast exit) Current Name Measurement Condition Timing Diagram Example CKE External Clock tCK tRC tRAS tRCD tRRD CL AL CS Addr. and cmd Inputs Data inputs Output Buffer DQ,DQS / MR1 bit A12 Rtt_NOM, Rtt_WE Burst length Active banks Idle banks Precharge Power Down Mode / Mode Register Bit a Figure 2 HIGH on tCKmin(IDD) n.a. n.a. n.a. n.a. n.a. n.a. HIGH SWITCHING as described in Table 2 SWITCHING as described in Table 3 off / 1 disabled n.a. all none n.a. IDD3N Active Standby Current 1Gb DDR3 SDRAM IDD3P Active Power-Down Currenta Always Fast Exit LOW on tCKmin(IDD) n.a. n.a. n.a. n.a. n.a. n.a. STABLE STABLE FLOATING off / 1 disabled n.a. all none n.a. (Active Power Down Mode is always "Fast Exit" with DLL on Note : 1. DDR3 will offer only ONE active power down mode with DLL on (-> fast exit). MRS bit 12 will not be used for active power down. Instead bit A12 will be used to switch between two different precharge power down modes. Page 36 of 63 Rev. 1.0 June 2007 K4B1G04(08/16)46C [ Table 37 ] IDD Measurement Conditions for IDD4R, IDD4W and IDD7 Current Name Measurement Condition Timing Diagram Example CKE External Clock tCK tRC tRAS tRCD tRRD CL AL CS Figure 3 HIGH on tCKmin(IDD) n.a. n.a. n.a. n.a. CL(IDD) 0 HIGH btw. valid cmds SWITCHING as described in Table 2; exceptions are Read commands => IDD4R Pattern: R0DDDR1DDDR3DDDR3DDDR4 ..... Rx = Read from bank x; Definition of D and D: see Table 2 column addresses SWITCHING as described in Table 2; Address Input A10 must be LOW all the time! bank address cycling (0 ->1 -> 2 -> 3 ...) Seamless Read Data Burst (BL8): output data switches every clock, which means that Read data is stable during one clock cycle. To achieve Iout = 0mA the output buffer should be switched off by MR1 Bit A12 set to "1". off / 1 1Gb DDR3 SDRAM IDD4R Operating Current Burst Read IDD4W Operating Current Burst Write IDD7 All Bank Interleave Read Current HIGH on tCKmin(IDD) n.a. n.a. n.a. n.a. CL(IDD) 0 HIGH btw. valid cmds SWITCHING as described in Table 2; exceptions are Write commands => IDD4W Pattern: W0DDDW1DDDW2DDDW3DDD W4 ... Wx = Write to bank x; Definition of D and D: see Table 2 column addresses SWITCHING as described in Table 2; Address Input A10 must be LOW all the time! bank address cycling (0 ->1 -> 2 -> 3 ...) Seamless Write Data Burst (BL8): input data switches every clock, which means that Write data is stable during one clock cycle. DM is low all the time. HIGH on tCKmin(IDD) tRCmin(IDD) tRASmin(IDD) tRCDmin(IDD) tRRDmin(IDD) CL(IDD) tRCDmin-1tCK HIGH btw. valid cmds Command Inputs (CS, RAS, CAS, WE) For patterns see Table 9 Row, Column Addresses STABLE during DESELECTs bank address cycling (0 ->1 -> 2 -> 3 ...), see pattern in Table 9 Read Data (BL8): output data switches every clock, which means that Read data is stable during one clock cycle. To achieve Iout = 0mA the output buffer should be switched off by MR1 Bit A12 set to "1". off / 1 Bank Addresses DQ I/O Output Buffer DQ,DQS / MR1 bit A12 off / 1 Rtt_NOM, Rtt_WE Burst length Active banks Idle banks Precharge Power Down Mode / Mode Register Bit disabled 8 fixed / MR0 Bits [A1, A0] = {0,0} disabled 8 fixed / MR0 Bits [A1, A0] = {0,0} disabled 8 fixed / MR0 Bits [A1, A0] = {0,0} all none n.a. all none n.a. all none n.a. Page 37 of 63 Rev. 1.0 June 2007 K4B1G04(08/16)46C T0 CK BA[2:0] ADDR_a[9:0] 000 000 001 3FF 010 000 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 1Gb DDR3 SDRAM T11 T12 T13 001 3FF ADDR_b[10] ADDR_c[13:11] 000 111 000 111 CS RAS CAS WE CMD[2:0] DQ[7:0] DM Start of Measurement Loop RD D D RD D D D RD D D D D RD D 00 00 FF FF 00 00 FF FF 00 00 FF FF 00 00 Figure 22 IDD4R Example (DDR3-800-666,1Gb x8): data DQ is shown but the output buffer should be switched off (per MR1 Bit A12="1") to achieve Iout = 0mA. Address inputs are split into 3 parts. [ Table 38 ] IDD7 Pattern for different Speed Grades and different tRRD, tFAW conditions Speed Mb/s all 800 all all 1066 all all 1333 all all 1600 all x16 40 32 7.5 6 Bin Org. x4/x8 x16 x4/x8 x16 x4/x8 x16 x4/x8 tFAW [ns] 40 50 37.5 50 30 45 30 tFAW [CLK] 16 20 20 27 20 30 24 tRRD [ns] 10 10 7.5 10 6 7.5 6 tRRD [CLK] 4 4 4 6 4 5 5 IDD7 Patterna A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 DD A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7D D A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 DD D D D D A4 RA4 D D A5 RA5 D D A6 RA6 DD A7 RA7 D D D D D D A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 DD D D D D A4 RA4 D D A5 RA5 D D A6 RA6 DD A7 RA7 D D D D D D A0 RA0 D D D D A1 RA1 D D D D A2 RA2 D DD D A3 RA3 D D D D D D D A4 RA4 D D D D A5RA5 D D D D A6 RA6 D D D D A7 RA7 D D D DD D D A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 DD D D D D A4 RA4 D D A5 RA5 D D A6 RA6 DD A7 RA7 D D D D D D A0 RA0 D D D A1 RA1 D D D A2 RA2 D D D A3RA3 D D D D D D D D D D D D D A4 RA4 D D DA5 RA5 D D D A6 RA6 D D D A7 RA7 D D D DD D D D D D D D D A0 RA0 D D D A1 RA1 D D D A2 RA2 D D D A3RA3 D D D D D D D A4 RA4 D D D A5 RA5 D DD A6 RA6 D D D A7 RA7 D D D D D D D A0 RA0 D D D D A1 RA1 D D D D A2 RA2 D DD D A3 RA3 D D D D D D D D D D D D A4 RA4D D D D A5 RA5 D D D D A6 RA6 D D D D A7RA7 D D D D D D D D DDDD Note : 1. A0 = Activation of Bank 0; RA0 = Read with Auto-Precharge of Bank 0; D = Deselect Page 38 of 63 Rev. 1.0 June 2007 K4B1G04(08/16)46C [ Table 39 ] IDD Measurement Conditions for IDD5B Current Name Measurement Condition CKE External Clock tCK tRC tRAS tRCD tRRD tRFC CL AL CS Addr. and cmd Inputs Data inputs Output Buffer DQ,DQS / MR1 bit A12 1Gb DDR3 SDRAM IDD5B Burst Refresh Current HIGH on tCKmin(IDD) n.a. n.a. n.a. n.a. tRFCmin(IDD) n.a. n.a. HIGH btw. valid cmds SWITCHING SWITCHING off / 1 Rtt_NOM, Rtt_WE Burst length Active banks Idle banks Precharge Power Down Mode / Mode Register Bit disabled n.a. Refresh command every tRFC=tRFCmin none n.a. Page 39 of 63 Rev. 1.0 June 2007 K4B1G04(08/16)46C [ Table 40 ] IDD Measurement Conditions for IDD6 and IDD6ET Current Name Measurement Condition Temperature Auto Self Refresh(ASR) / MR2 Bit A6 Self Refresh Temperature Range (SRT) / MR2 Bit A7 CKE External Clock tCK tRC tRAS tRCD tRRD CL AL CS Command Inputs (CS, RAS, CAS, WE) Row, Column Addresses Bank Addresses Data I/O Output Buffer DQ,DQS / MR1 bit A12 1Gb DDR3 SDRAM IDD6 Self-Refresh Current Normal Temperature Range TCASE = 0 .. 85°C TCASE = 85°C Disabled / "0" Normal / "0" LOW OFF; CK and CK at LOW n.a. n.a. n.a. n.a. n.a. n.a. n.a. FLOATING FLOATING FLOATING FLOATING FLOATING off / 1 IDD6ET Self-Refresh Current Extended Temperature Range a TCASE = 0 .. 95°C TCASE = 95°C Disabled / "0" Enabled / "1" LOW OFF; CK and CK at LOW n.a. n.a. n.a. n.a. n.a. n.a. n.a. FLOATING FLOATING FLOATING FLOATING FLOATING off / 1 Rtt_NOM, Rtt_WR Burst length Active banks Idle banks Precharge Power Down Mode / Mode Register Bit 12 disabled n.a. all during self-refresh actions all btw. Self-Refresh actions n.a. disabled n.a. all during self-refresh actions all btw. Self-Refresh actions n.a. Note : 1 .Users should refer to the DRAM supplier datasheet and/or the DIMM SPD to determine if DDR3 SDRAM devices support the following options referred to in this material [ Table 41 ] IDD6 current definition Symbol IDD6 IDD6ET Parameter/Condition Normal Temperature Range Self-Refresh Current : CKE< 0.2V; external clock off, CK and CK at 0V; Other control and address inputs are FLOATING; Data Bus inputs are FLOATING, PASR disabled. Applicable for MR2 setting A6=0 and A7=0. Extended Temperature Range SElf-Refresh Current: CKE