K4C89183AF-GCF5

K4C89183AF 288Mb x18 Network-DRAM2 Specification Version 0.7 -1- REV. 0.7 Jan. 2005 K4C89183AF Revision History Version 0.0 (Oct. 2002) - First Release Version 0.01 (Nov. 2002) - Changed die revision from D-die to F-die - Corrected typo - Corrected DQS to DS and QS(DQS -> DS and QS) in AC timing table and timing diagram. Version 0.1 (Apr. 2003) - Added 800Mbps(400Mhz) product - Changed operating temperature from Ta to Tc. - Changed capacitance of ADDR/CMD/CLK From Min Addr/CMD/CLK 1.5 Max 2.5 Min 1.5 To Max 3.0 - Changed tDSS(DS input Falling Edge to Clock Setup Time) From F6 CL4 CL5 CL6 CL7 0.9 0.9 0.9 FB 0.9 0.9 0.9 F5 1.0 1.0 1.0 G7 0.75 0.75 0.75 0.75 F6 0.75 0.75 0.75 To FB 0.8 0.8 0.8 F5 1.0 1.0 1.0 - - Added CL7 for 800Mbps - Deleted TSOP package outline Version 0.11 (Apr. 2003) - Corrected typo in page 3.(Deleted bi-directional strobe) - Corrected min. Vref to VDDQ/2x95% in page 7 Version 0.2 (Aug. 2003) - Added package physical dimension - Extracted 800Mbps(G7) binning from target spec ( G7 will be added in the future) - Changed DC test condition From IDD1S,IDD2N,IDD2P,IDD5,IDD6 - Changed low frequency spec like below From Unit : ns tCK max@CL=4 tCK max@CL=5 tCK max@CL=6 F6 7.5 7.5 7.5 FB 7.5 7.5 7.5 F5 7.5 7.5 7.5 F6 6.0 6.0 6.0 To FB 6.0 6.0 6.0 F5 6.0 6.0 6.0 To IDD1S,IDD2N,IDD2P,IDD5B,IDD6 IDD4W, IDD4R Changed point Changed condition newly inserted - Changed AC test load picture Version 0.3 (Nov. 2003) - Changed Packge type from die-exposed to full molded - Changed Package code in Partnumber -2- REV. 0.7 Jan. 2005 K4C89183AF Version 0.31 (Mar., 2004) - Corrected typo. in page 7 (Changed operating Temperature to 85’C, case temperature) Version 0.4 (Jun., 2004) - Changed from "target" to "Preliminary" - Changed min. tCK@CL5 to 3.5ns in "-F6" From F6 CL = 4 tCK Clock Cycle Time (min) CL = 5 CL = 6 Version 0.5 (Aug., 2004) - Deleted self-refresh function and BL2 from spec Version 0.51 (Aug., 2004) - Corrected error in page 54, "Package Out line Drawing". (Just 4 balls were missing in drawing) Version 0.6 (Nov., 2004) - Deleted "preliminary" - Changed current value in page 9 Version 0.7 (Jan., 2005) - Deleted the tDQSQA in page 11 - Deleted the tSSK in page 11 4.0 ns 3.33 ns 3.0ns To F6 4.0 ns 3.5 ns 3.0ns -3- REV. 0.7 Jan. 2005 K4C89183AF 4,194,304-WORDS x 4 BANKS x 18-BITS DOUBLE DATA RATE Network-DRAM DESCRIPTION K4C89183AF is a CMOS Double Data Rate Network-DRAM containing 301,989,888 memory cells. K4C89183AF is organized as 4,194,304-words x 4 banks x18 bits. K4C89183AF feature a fully synchronous operation referenced to clock edge whereby all operations are synchronized at a clock input which enables high performance and simple user interface coexistence. K4C89183AF can operate fast core cycle compared with regular DDR SDRAM. K4C89183AF is suitable for Server, Network and other applications where large memory density and low power consumption are required. The Output Driver for Network-DRAM is capable of high quality fast data transfer under light loading condition. FEATURES Parameter CL = 4 tCK Clock Cycle Time (min) tRC Random Read/Write Cycle Time (min) tRAC Random Access Time (min) IDD1S Operating Current (single bank) (max) IDD2P Power Down Current (max) CL = 5 CL = 6 K4C89183AF F6 4.0 ns 3.5 ns 3.0ns 20.0 ns 20.0 ns 320mA 70mA FB 4.5 ns 3.75 ns 3.33 ns 22.5 ns 22.5 ns 300mA 65mA F5 5.0 ns 4.5 ns 4.0 ns 25 ns 25 ns 280mA 60mA • • • • • • • • • • • • • • • • Fully Synchronous Operation - Double Data Rate (DDR) - Data input/output are synchronized with both edges of DS / QS. - Differential Clock (CLK and CLK) inputs - CS, FN and all address input signals are sampled on the positive edge of CLK. - Output data (DQs and QS) is aligned to the crossings of CLK and CLK. Fast clock cycle time of 3.0 ns minimum - Clock : 333 MHz maximum - Data : 666 Mbps/pin maximum Quad Independent Banks operation Fast cycle and Short Latency Uni-directional Data Strobe Distributed Auto-Refresh cycle in 3.9us Power Down Mode Variable Write Length Control Write Latency = CAS Latency-1 Programable CAS Latency and Burst Length - CAS Laatency = 4, 5, 6 - Burst Length = 4 Organization : 4,194,304 words x 4 banks x 18 bits Power Supply Voltage VDD : 2.5V ± 0.125V VDDQ : 1.4V ∼ 1.9V 1.8V CMOS I/O comply with SSTL - 1.8 (half strength driver) and HSTL Package : 60Ball BGA, 1.0mm x 1.0mm Ball pitch Notice : Network-DRAM is trademark of Samsung Electronics., Co LTD -4- REV. 0.7 Jan. 2005 K4C89183AF Pin Names Pin A0 ~ A14 BA0, BA1 DQ0 ~ DQ17 CS FN PD CLK, CLK DS/QS VDD VSS VDDQ VSSQ VREF NC Name Address Input Bank Address Data Input/Output Chip Select Function Control Power Down Control Clock Input C Write/Read data strobe Power (+2.5V) Ground E Power (+1.8V) (for I/O buffer) Ground (for I/O buffer) Reference Voltage No Connection H J K L M N P R DQ9 VREF CLK A12 A11 A8 A5 VSS DS Vss CLK PD A9 A7 A6 A4 QS VDD FN CS BA1 A0 A2 A3 DQ8 A14 A13 NC BA0 A10 A1 VDD F G DQ12 DQ11 DQ10 VssQ VDDQ VssQ VDDQ VssQ VDDQ DQ5 DQ6 DQ7 D DQ14 DQ15 VDDQ DQ13 VssQ DQ4 DQ2 DQ3 B DQ16 VssQ VDDQ DQ1 A 1 Index Vss DQ17 DQ0 VDD 2 3 4 5 6 PIN ASSIGNMENT (TOP VIEW) ball pitch=1.0 x 1.0mm x18 -5- REV. 0.7 Jan. 2005 K4C89183AF Block Diagram CLK CLK PD DLL CLOCK BUFFER To Each Block BANK #3 CS FN COMMAND DECODER CONTROL SIGNAL GENERATOR BANK #2 DATA CONTROL AND LATCH CIRCUIT READ DATA BUFFER WRITE DATA BUFFER DQ BUFFER DQ0 ~ DQ17 BANK #1 BANK #0 ROW DECODER A0 ~ A14 BA0, BA1 ADDRESS BUFFER MODE REGISTER MEMORY CELL ARRAY UPPER ADDRESS LATCH LOWER ADDRESS LATCH COLUMN DECODER REFRESH COUNTER BURST COUNTER WRITE ADDRESS LATCH ADDRESS COMPARATOR DS QS Note : The K4C89183AD configuration is 4 Bank of 32768 x 128 x 18 of cell array with the DQ pins numbered DQ0~DQ17. -6- REV. 0.7 Jan. 2005 K4C89183AF Absolute Maximum Ratings Symbol VDD VDDQ VIN VOUT VREF TOPR TSTG TSOLDER PD IOUT Parameter Power Supply Voltage Power Supply Voltage (for I/O buffer) Input Voltage DQ pin Voltage Input Reference Voltage Operating Temperature Storage Temperature Soldering Temperature(10s) Power Dissipation Short Circuit Output Current Rating -0.3 ~ 3.3 -0.3 ~ VDD + 0.3 -0.3 ~ VDD + 0.3 -0.3 ~ VDDQ + 0.3 -0.3 ~ VDDQ + 0.3 0 ~ 85 -55 ~ 150 260 2 ± 50 Units V V V V V O Notes C C C Case Temp. O O W mA Caution : Conditions outside the limits listed under "ABSOLUTE MAXIMUM RATINGS" may cause permanent damage to the device. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to "ABSOLUTE MAXIMUM RATINGS" conditions for extended periods may affect device reliability. Recommended DC,AC Operating Conditions (Notes : 1) Symbol VDD VDDQ VREF VIH (DC) VIL(DC) VICK (DC) VID (DC) VIH (AC) VIL (AC) VID (AC) VX (AC) VISO (AC) Power Supply Voltage Power Supply Voltage (for I/O Buffer) Input Reference Voltage Input DC high Voltage Input DC Low Voltage Differential Clock DC Input Voltage Input Differential Voltage. CLK and CLK Inputs (DC) Input AC High Voltage Input AC Low Voltage Input Differential Voltage. CLK and CLK Inputs (AC) Differential AC Input Cross Point Voltage Differential Clock AC Middle Level Parameter Min 2.375 1.7 VDDQ/2x95% VREF+0.125 -0.1 -0.1 0.4 VREF+0.2 -0.1 0.55 VDDQ/2-0.125 VDDQ/2-0.125 Typ 2.5 1.8 (Tcase = 0 ~ 85 OC) Max 2.625 1.9 VDDQ/2x105% VDDQ+0.2 VREF-0.125 VDDQ+0.1 VDDQ+0.2 VDDQ+0.2 VREF-0.2 VDDQ+0.2 VDDQ/2+0.125 VDDQ/2+0.125 Units V V V V V V V V V V V V 2 5 5 10 7,10 3,6 4,6 7,10 8,10 9,10 Notes VDDQ/2 - -7- REV. 0.7 Jan. 2005 K4C89183AF Notes: 1. All voltages are referenced to Vss, VssQ. 2. VREF is expected to track variations in VddQ DC level of the transmitting device. Peak to peak AC noise on VREF may not exceed ± 2% of VREF (DC). 3. Overshoot Iimit : VIH(max.) = VddQ + 0.7V with a pulse width