K4D28163HD

K4D28163HD 128M DDR SDRAM 128Mbit DDR SDRAM 2M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM Revision 1.4 August 2002 S amsung Electronics reserves the right to change products or specification without notice. -1- Rev. 1.4(Aug. 2002) K4D28163HD Revision History Revision 1.4 (August 13, 2002) • C hanged ICC3P • Typo corrected • Changed refresh period of K4D28163HD-TC36/40 from 4K/64ms to 4K/32ms. 128M DDR SDRAM Revision 1.3 (May 29, 2002) • A dded K4D28163HD-TC36 (275MHz) Revision 1.2 (May 8, 2002) • T ypo corrected Revision 1.1 (January 7, 2002) • I ncreased Icc2N by 20mA Revision 1.0 (December 22, 2001) • D efined DC spec. Revision 0.4 (December 10, 2001) - Target Spec • R emoved Full page Burst Length from the spec. Revision 0.3 (November 6, 2001) - Target Spec • R emoved K4D28163HD-TC45/55 from the spec. Revision 0.2 (October 25, 2001) - Target Spec • Removed K4D28163HD-TC33/36 from the spec. Revision 0.1 (October 12, 2001) - Target Spec • Changed V DD f rom 3.3V + 1 0% to 3.3V + 5% Revision 0.0 (October 10, 2001) - Target Spec • Defined Target Specification -2- Rev. 1.4(Aug. 2002) K4D28163HD 2M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL FEATURES • 3.3V + 5 % power supply for device operation • 2.5V + 5 % power supply for I/O interface • SSTL_2 compatible inputs/outputs • 4 banks operation • MRS cycle with address key programs -. Read latency 3 (clock) -. Burst length (2, 4 and 8) -. Burst type (sequential & interleave) • All inputs except data & DM are sampled at the positive going edge of the system clock • Differential clock input • No Wrtie-Interrupted by Read Function • 2 DQS’s ( 1DQS / Byte ) 128M DDR SDRAM • Data I/O transactions on both edges of Data strobe • DLL aligns DQ and DQS transitions with Clock transition • Edge aligned data & data strobe output • Center aligned data & data strobe input • DM for write masking only • Auto & Self refresh • 32ms refresh period (4K cycle) for -36/-40 • 64ms refresh period (4K cycle) for -50/-60 • 66pin TSOP-II • Maximum clock frequency up to 275MHz • Maximum data rate up to 550Mbps/pin ORDERING INFORMATION Part NO. K4D28163HD-TC36 K4D28163HD-TC40 K4D28163HD-TC50 K4D28163HD-TC60 Max Freq. 275MHz 250MHz 200MHz 166MHz Max Data Rate 550Mbps/pin 500Mbps/pin 400Mbps/pin 333Mbps/pin SSTL_2 66pin TSOP-II Interface Package GENERAL DESCRIPTION FOR 2M x 16Bit x 4 Bank DDR SDRAM The K4D28163HD is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 2.097,152 words by 16 bits, fabricated with SAMSUNG ’ high performance CMOS technology. Synchronous features with Data Strobe allow s extremely high performance up to 1.1GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications. -3- Rev. 1.4(Aug. 2002) K4D28163HD PIN CONFIGURATION (Top View) 128M DDR SDRAM V DD DQ 0 VD D Q DQ 1 DQ 2 VS S Q DQ 3 DQ 4 VD D Q DQ 5 DQ 6 VS S Q DQ 7 NC VD D Q LDQS NC V DD NC LDM WE CAS RAS CS NC BA 0 BA 1 AP/A1 0 A0 A1 A2 A3 V DD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 VS S DQ 1 5 VS S Q DQ 1 4 DQ 1 3 V DDQ DQ 1 2 DQ 1 1 VS S Q DQ 1 0 DQ 9 V DDQ DQ 8 NC VS S Q UDQS NC VR E F VS S UDM CK CK CKE NC NC A1 1 A9 A8 A7 A6 A5 A4 VS S 66 PIN TSOP(II) (400mil x 875mil) (0.65 mm Pin Pitch) 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 PIN DESCRIPTION C K,CK CKE CS RAS CAS WE LDQS,UDQS LDM,UDM RFU D ifferential Clock Input Clock Enable Chip Select Row Address Strobe Column Address Strobe Write Enable Data Strobe Data Mask Reserved for Future Use BA 0 , BA 1 A 0 ~ A 11 D Q 0 ~ D Q1 5 V DD VS S V DDQ V SSQ NC B ank Select Address Address Input Data Input/Output Power Ground Power for DQ’ s Ground for DQ’ s No Connection -4- Rev. 1.4(Aug. 2002) K4D28163HD INPUT/OUTPUT FUNCTIONAL DESCRIPTION S ymbol Type 128M DDR SDRAM Function The differential system clock Input. CK, CK *1 Input All of the inputs are sampled on the rising edge of the clock except D Q’s and DM ’ that are sampled on both edges of the DQS. s Activates the CK signal when high and deactivates the CK s ignal CKE Input when low. By deactivating the clock, CKE low indicates the Power down mode or Self refresh mode. CS e nables the command decoder when low and disabled the com- CS Input mand decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. RAS Input Latches row addresses on the positive going edge of the CK with RAS l ow. Enables row access & precharge. Latches column addresses on the positive going edge of the CK with CAS l ow. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS , WE a ctive. Data input and output are synchronized with both edge of DQS. For the x16, LDQS corresponds to the data on DQ0-DQ7 ; UDQS corresponds to the data on DQ8-DQ15. Data in Mask. Data In is masked by DM Latency=0 when DM is high in burst write. For the x16, LDM corresponds to the data on DQ0-DQ7 ; UDM correspons to the data on DQ8-DQ15. Data inputs/Outputs are multiplexed on the same pins. Selects which bank is to be active. Row/Column addresses are multiplexed on the same pins. Row addresses : RA 0 ~ RA 1 1, Column addresses : CA 0 ~ C A8. Power and ground for the input buffers and core logic. Isolated power supply and ground for the output buffers to provide improved noise immunity. Reference voltage for inputs, used for SSTL interface. This pin is recommended to be left "No connection" on the device CAS Input WE Input LDQS,(U)DQS Input/Output LDM,UDM DQ 0 ~ D Q 15 BA 0, BA 1 A 0 ~ A 11 V DD/V SS V DDQ/V SSQ V REF NC/RFU Input Input/Output Input Input Power Supply Power Supply Power Supply No connection/ Reserved for future use * 1 : The timing reference point for the differential clocking is the cross point of CK and CK. F or any applications using the single ended clocking, apply V REF t o CK pin. -5- Rev. 1.4(Aug. 2002) K4D28163HD BLOCK DIAGRAM (2Mbit x 16I/O x 4 Bank) 128M DDR SDRAM 16 Intput Buffer I/O Co n tr o l LWE CK, CK Bank Select Data Input Register Serial to parallel LDMi 2Mx16 2 - b it p r e fe tch Ou tp u t B u ffe r S e n se A M P R e fr e sh C o u n te r R o w B u ffe r R o w D e co d e r 2Mx16 2Mx16 2Mx16 32 16 x16 DQi A d d r e ss Re g i ste r CK,CK ADDR Column Decoder L R AS L C BR C o l . B u ffe r Latency & Burst Length S tr o b e G en. Data Strobe Programming Register LCKE LRAS LCBR LWE LCAS LWCBR DLL CK,CK LDMi Timing Register CK,CK CKE CS RAS CAS WE LDM UDM -6- Rev. 1.4(Aug. 2002) K4D28163HD FUNCTIONAL DESCRIPTION • P ower-Up Sequence 128M DDR SDRAM D DR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. 1 . Apply power and keep CKE at low state (All other inputs may be undefined) - Apply VDD before VDDQ . - Apply VDDQ before VREF & VTT 2. Start clock and maintain stable condition for minimum 200us. 3. The minimum of 200us after stable power and clock(CK,CK ) , apply NOP and take CKE to be high . 4. Issue precharge command for all banks of the device. 5. Issue a EMRS command to enable DLL *1 6 . Issue a MRS command to reset DLL. The additional 200 clock cycles are required to lock the DLL. * 1,2 7 . Issue precharge command for all banks of the device. 8. Issue at least 2 or more auto-refresh commands. 9. Issue a mode register set command with A8 to low to initialize the mode register. *1 The additional 200cycles of clock input is required to lock the DLL after enabling DLL. *2 Sequence of 6&7 is regardless of the order. Power up & Initialization Sequence 0 CK,CK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 ~ ~ ~~ ~ Command ~ precharge ALL Banks EMRS MRS DLL Reset precharge ALL Banks 1st Auto Refresh 2nd Auto Refresh ~~ ~~ t RP 2 Clock min. 2 Clock min. tRP tRFC t RFC Mode ~ ~ 2 Clock min. Any Command Register Set Inputs must be stable for 200us ~ ~ 200 Clock min. -7- Rev. 1.4(Aug. 2002) K4D28163HD MODE REGISTER SET(MRS) 128M DDR SDRAM The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS l atency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for proper operation. The mode register is written by asserting low on CS , RAS , CAS a nd WE (The DDR SDRAM should be in active mode with CKE already high prior to writing into the mode register). The state of address pins A 0 ~ A 1 1 a nd BA 0, BA 1 i n the same cycle as CS , RAS , CAS a nd W E g oing low is written in the mode register. Minimum two clock cycles are requested to complete the write operation in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0 ~ A2, addressing mode uses A 3, CAS l atency(read latency from column address) uses A 4 ~ A 6. A 7 i s used for test mode. A 8 is used for DLL reset. A 7, A 8, BA 0 a nd BA 1 m ust be set to low for normal MRS operation. Refer to the table for specific codes for various burst length, addressing modes and CAS l atencies. BA 1 BA 0 A1 1 A1 0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A ddress Bus RFU 0 RFU DLL TM CAS Latency BT Burst Length Mode Register DLL A8 0 1 DLL Reset No Yes Test Mode A7 0 1 mode Normal Test Burst Type A3 0 1 Type Sequential Interleave Burst Length C AS Latency BA 0 0 1 An ~ A0 MRS EMRS A6 0 0 0 0 * RFU(Reserved for future use) should stay "0" during MRS cycle. 1 1 1 1 MRS Cycle 0 CK, CK Command NOP Precharge All Banks NOP NOP MRS A2 Latency Reserved Reserved Reserved 3 Reserved Reserved Reserved Reserved 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Burst Type Sequential Reserve 2 4 8 Reserve Reserve Reserve Reserve Interleave Reserve 2 4 8 Reserve Reserve Reserve Reserve A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 1 2 3 4 5 6 7 8 NOP Any Command NOP NOP tRP tMRD=2 t CK *1 : MRS can be issued only at all banks precharge state. *2 : Minimum t RP i s required to issue MRS command. -8- Rev. 1.4(Aug. 2002) K4D28163HD EXTENDED MODE REGISTER SET(EMRS) 128M DDR SDRAM The extended mode register stores the data for enabling or disabling DLL and selecting output driver strength. The default value of the extended mode register is not defined, therefore the extened mode register must be written after power up for enabling or disabling DLL. The extended mode register is written by asserting low on CS , RAS, CAS, WE and high on BA0(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register). The state of address pins A0, A2 ~ A5, A7 ~ A11 and BA1 in the same cycle as CS , RAS, CAS and WE going low are written in the extended mode register. A1 and A6 are used for setting driver strength to normal, weak or matched impedance. Two clock cycles are required to complete the write operation in the extended mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. A0 is used for DLL enable or disable. "High" on BA0 is used for EMRS. All the other address pins except A0,A1,A6 and BA0 must be set to low for proper EMRS operation. Refer to the table for specific codes. BA1 BA 0 A1 1 A1 0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A ddress Bus Extended M ode Register RFU 1 RFU D.I.C RFU D.I.C DLL BA 0 0 1 An ~ A0 MRS EMRS A6 0 1 A1 1 1 Output Driver Impedence Control Weak Matched A0 0 1 DLL Enable Enable Disable * 1 : RFU(Reserved for future use) should stay "0" during EMRS cycle. -9- Rev. 1.4(Aug. 2002) K4D28163HD ABSOLUTE MAXIMUM RATINGS P arameter Voltage on any pin relative to Vss Voltage on V DD s upply relative to Vss Voltage on V DD s upply relative to Vss Storage temperature Power dissipation Short circuit current Symbol V IN, V OUT V DD V DDQ T STG PD IOS Value -0.5 ~ 3.6 -1.0 ~ 3.6 -0.5 ~ 3.6 -55 ~ +150 1.0 50 128M DDR SDRAM Unit V V V °C W mA N ote : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. POWER & DC OPERATING CONDITIONS(SSTL_2 In/Out) Recommended operating conditions(Voltage referenced to V SS=0V, T A =0 to 65 ° C) P arameter Device Supply voltage Output Supply voltage Reference voltage Termination voltage Input logic high voltage Input logic low voltage Output logic high voltage Output logic low voltage Input leakage current Output leakage current Symbol V DD V DDQ V REF Vtt V IH(DC) V IL(DC) VO H V OL IIL IOL Min 3.135 2.375 0.49*V DDQ V REF-0.04 V REF+0.15 -0.30 Vtt+0.76 -5 -5 Typ 3.3 2.50 V REF - Max 3.465 2.625 0.51*V DDQ V REF+0.04 V DDQ +0.30 V REF-0.15 Vtt-0.76 5 5 Unit V V V V V V V V uA uA Note 1 1 2 3 4 5 IO H=-15.2mA IOL =+15.2mA 6 6 Note : 1. Under all conditions V DDQ m ust be less than or equal to V DD . 2. V REF i s expected to equal 0.50*V DDQ o f the transmitting device and to track variations in the DC level of the same. Peak to peak noise on the V REF m ay not exceed + 2 % of the DC value. Thus, from 0.50*V DDQ, VREF i s allowed + 2 5mV for DC error and an additional + 2 5mV for AC noise. 3. V tt o f the transmitting device must track V REF o f the receiving device. 4. V I H(max.)= V DDQ + 1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate. 5 . V IL(mim.)= -1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate. 6. For any pin under test input of 0V < V IN < V DD i s acceptable. For all other pins that are not under test V I N=0V. - 10 - Rev. 1.4(Aug. 2002) K4D28163HD DC CHARACTERISTICS Recommended operating conditions Unless Otherwise Noted, T A =0 to 65° C) 128M DDR SDRAM Version Parameter Operating Current (One Bank Active) Precharge Standby Current in Power-down mode Precharge Standby Current in Non Power-down mode Active Standby Current power-down mode Active Standby Current in in Non Power-down mode Operating Current ( Burst Mode) Refresh Current Self Refresh Current Symbol Test Condition -36 ICC1 Burst Lenth=2 t RC ≥ tRC(min) IOL =0mA, tCC= tCC(min) CKE ≤ V IL (max), t CC= t CC(min) CKE ≥ V I H(min), CS ≥ V I H(min), tCC= tCC(min) CKE ≤ V IL(max), tCC= tCC(min) CKE ≥ V IH(min), CS ≥ V IH(min), tCC= tCC (min) 70 100 65 90 200 -40 190 -50 170 -60 165 mA 1 Unit Note ICC2 P ICC2 N ICC3 P 5 60 75 60 70 mA mA mA ICC3 N ICC4 ICC5 ICC6 130 380 250 120 350 220 2 110 310 210 90 280 200 mA mA mA mA tRC ≥ tRFC(min) tRC ≥ tRFC(min) Page Burst, All Banks activated. tRC ≥ tRFC(min) CKE ≤ 0 .2V Note : 1 . Measured with outputs open. AC INPUT OPERATING CONDITIONS Recommended operating conditions(Voltage referenced to V SS =0V, V DD=3.3V+ 5%, V DDQ=2.5V+ 5 %,T A=0 to 65 ° C) P arameter Input High (Logic 1) Voltage; DQ Input Low (Logic 0) Voltage; DQ Clock Input Differential Voltage; CK and CK Clock Input Crossing Point Voltage; CK and CK Symbol V IH V IL V ID V IX Min V REF +0.35 0.7 0.5*VDDQ-0.2 Typ - Max V REF -0.35 V DDQ+0.6 0.5*V DDQ +0.2 Unit V V V V Note 1 2 Note : 1. V I D i s the magnitude of the difference between the input level on CK and the input level on CK 2. The value of V IX i s expected to equal 0.5*VDDQ o f the transmitting device and must track variations in the DC level of the same - 11 - Rev. 1.4(Aug. 2002) K4D28163HD AC OPERATING TEST CONDITIONS Parameter Input reference voltage for CK(for single ended) CK and CK s ignal maximum peak swing CK signal minimum slew rate Input Levels(V IH /V IL) Input timing measurement reference level Output timing measurement reference level Output load condition ( V DD =3.3V ±5%, T A = 0 to 65 ° C) Value 0.50*V DDQ 1.5 1.0 V REF +0.35/V REF -0.35 V REF V tt See Fig.1 V tt =0.5*V DDQ 128M DDR SDRAM Unit V V V/ns V V V Note R T=50 Ω Output Z 0=50 Ω V REF =0.5*VDDQ C LOAD =30pF (Fig. 1) Output Load Circuit CAPACITANCE ( V DD =3.3V, T A = 25° C, f=1MHz) Symbol C IN1 C IN2 C IN3 C OUT C IN4 Parameter Input capacitance( C K, CK ) Input capacitance(A 0 ~A11 , BA0 ~BA1 ) Input capacitance ( C KE, CS , RAS ,CAS , WE ) Data & DQS input/output capacitance(DQ 0~ D Q31) Input capacitance(DM0 ~ DM3) Min 1.0 1.0 1.0 1.0 1.0 Max 5.0 4.0 4.0 6.5 6.5 Unit pF pF pF pF pF DECOUPLING CAPACITANCE GUIDE LINE Recommended decoupling capacitance added to power line at board. P arameter Decoupling Capacitance between V DD a nd V SS Decoupling Capacitance between V DDQ a nd V SSQ Symbol C DC1 C DC2 Value 0.1 + 0.01 0.1 + 0.01 Unit uF uF Note : 1. V DD a nd V DDQ p ins are separated each other. All V DD p ins are connected in chip. All VDDQ p ins are connected in chip. 2. V SS a nd V SSQ p ins are separated each other All V SS p ins are connected in chip. All V SSQ p ins are connected in chip. - 12 - Rev. 1.4(Aug. 2002) K4D28163HD AC CHARACTERISTICS Parameter CK cycle time CK high level width CK low level width DQS out access time from CK Output access time from CK Data strobe edge to Dout edge Read preamble Read postamble CK to valid DQS-in DQS-In setup time DQS-in hold time DQS write postamble DQS-In high level width DQS-In low level width Address and Control input setup Address and Control input hold DQ and DM setup time to DQS DQ and DM hold time to DQS Clock half period CL=3 128M DDR SDRAM Symbol -36 Min 3.6 0.45 0.45 -0.6 -0.6 0.9 0.4 0.85 0 0.35 0.4 0.4 0.4 0.9 0.9 0.4 0.4 tCLmin or tCHmin tHP-0.4 -40 Max 6 0.55 0.55 0.6 0.6 0.4 1.1 0.6 1.15 0.6 0.6 0.6 - -50 Max 7 0.55 0.55 0.6 0.6 0.4 1.1 0.6 1.15 0.6 0.6 0.6 - -60 Max 10 0.55 0.55 0.7 0.7 0.45 1.1 0.6 1.2 0.6 0.6 0.6 - Min 4.0 0.45 0.45 -0.6 -0.6 0.9 0.4 0.85 0 0.35 0.4 0.4 0.4 0.9 0.9 0.4 0.4 tCLmin or tCHmin tHP-0.4 Min 5.0 0.45 0.45 -0.7 -0.7 0.9 0.4 0.8 0 0.3 0.4 0.4 0.4 1.0 1.0 0.45 0.45 tCLmin or tCHmin tHP-0.45 Min 6.0 0.45 0.45 -0.75 -0.75 0.9 0.4 0.75 0 0.25 0.4 0.4 0.4 1.1 1.1 0.5 0.5 tCLmin or tCHmin tHP-0.5 Max 10 0.55 0.55 0.75 0.75 0.5 1.1 0.6 1.25 0.6 0.6 0.6 - Unit Note ns tCK tCK ns ns ns tCK tCK tCK ns tCK tCK tCK tCK ns ns ns ns ns ns 1 1 1 tCK tCH tCL tDQSCK tAC tDQSQ tRPRE tRPST tDQSS tWPRES tWPREH tWPST tDQSH tDQSL tIS tI H tDS tDH tHP Data output hold time from DQS tQ H N ote 1 : - The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data strobe and all data associated with that data strobe are coincidentally valid. - The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst case output vaild window even then the clock duty cycle applied to the device is better than 45/55% - A new AC timing term, tQH which stands for data output hold time from DQS is difined to account for clock duty cycle variation and replaces tDV - tQHmin = tHP-X where . tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL) . X=A frequency dependent timing allowance account for tDQSQmax - 13 - Rev. 1.4(Aug. 2002) K4D28163HD AC CHARACTERISTICS (I) P arameter Row cycle time Refresh row cycle time Row active time RAS to CAS delay Row precharge time Row active to Row active Last data in to Row precharge @Normal Precharge Last data in to Row precharge @Auto Precharge Last data in to Read command Col. address to Col. address Mode register set cycle time Auto precharge write recovery + Precharge Exit self refresh to read comPower down exit time Refresh interval time 128M DDR SDRAM -36 Min 15 17 10 5 5 2 3 3 2 1 2 8 200 1tCK+tIS 7.8 Symbol -40 Max 100K - -50 Max 100K - -60 Max 100K - Min 14 16 9 5 5 2 3 3 2 1 2 8 200 1tCK+tIS 7.8 Min 12 14 8 4 4 2 2 3 2 1 2 7 200 1tCK+tIS 15.6 Min 10 12 7 3 3 2 2 3 2 1 2 6 200 1tCK+tIS 15.6 Max 100K - Unit Note tRC tRFC tRAS tRCD tRP tRRD tWR tWR_A tCDLR tCCD tMRD tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK ns us 1 1 1 tDAL tXSR tPDEX tREF N ote : 1. For normal write operation, even numbers of Din are to be written inside DRAM AC CHARACTERISTICS (II) K 4D28163HD-TC36 Frequency Cas Latency 275MHz ( 3.6ns ) 3 250MHz ( 4.0ns ) 3 200MHz ( 5.0ns ) 3 166MHz ( 6.0ns ) 3 (Unit : Number of Clock) tRC 15 14 12 10 tRFC 17 16 14 12 tRAS 10 9 8 7 tRCD 5 5 4 3 tRP 5 5 4 3 tRRD 2 2 2 2 tDAL 8 8 7 6 Unit tCK tCK tCK tCK K4D28163HD-TC40 Frequency Cas Latency 250MHz ( 4.0ns ) 3 200MHz ( 5.0ns ) 3 166MHz ( 6.0ns ) 3 tRC 14 12 10 tRFC 16 14 12 tRAS 9 8 7 tRCD 5 4 3 tRP 5 4 3 tRRD 2 2 2 tDAL 8 7 6 Unit tCK tCK tCK K4D28163HD-TC50 Frequency Cas Latency 200MHz ( 5.0ns ) 3 166MHz ( 6.0ns ) 3 tRC 12 10 tRFC 14 12 tRAS 8 7 tRCD 4 3 tRP 4 3 tRRD 2 2 tDAL 7 6 Unit tCK tCK - 14 - Rev. 1.4(Aug. 2002) K4D28163HD 128M DDR SDRAM K4D28163HD-TC60 Frequency Cas Latency 166MHz ( 6.0ns ) 3 tRC 10 tRFC 12 tRAS 7 tRCD 3 tRP 3 tRRD 2 tDAL 6 Unit tCK Simplified Timing @ BL=4 0 CK, CK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 B A [ 1 : 0 ] BAa BAa BAa BAa BAb BAa BAb A10/AP Ra Ra Ra Rb ADDR (A0~A11) Ra Ca Ra Rb Ca Cb WE DQS DQ Da0 Da1 Da2 Da3 Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 DM COMMAND ACTIVEA WRITEA PRECH ACTIVEA ACTIVEB WRITEA WRITEB tRCD tRAS tRC tRP tRRD Normal Write Burst (@ BL=4) Multi Bank Interleaving Write Burst (@ BL=4) - 15 - Rev. 1.4(Aug. 2002) K4D28163HD PACKAGE DIMENSIONS (66pin TSOP-II) 128M DDR SDRAM U nits : Millimeters ( 0. 80 ) ( 0. 50 ) (10 × ) (10 ×) 0.125 +0.075 -0.035 (0 .5 0 ) 0 ×~8 × (R 0 (R 0 .2 5) #66 #34 1 0 .1 6± 0 .1 0 (1 .5 0 ) #1 (1.50) #33 0 .6 65 ± 0. 05 0 .2 10 ± 0. 05 1 .0 0± 0 .1 0 ( 0 .8 0) 0. 15 ) 0. 05 M I N (0.71) 0.65TYP 0.65± 0.08 0.30 ±0.08 (10× ) 0.10 MAX [ 0.075 MAX ] (4 (R 0 .1 ×) 5) NOTE 1. ( ) IS REFERENCE 2. [ ] IS ASS ’Y OUT QUALITY (R - 16 - Rev. 1.4(Aug. 2002) .2 (10× ) 1 .2 0 M AX 22.22 0.10 ± 0.25TYP 0 .4 5~ 0 .7 5 5) 1 1. 76 ± 0. 20 ( 10 .7 6 )