K4D551638F-TC50

Target Spec K4D551638F-TC 256M GDDR SDRAM 256Mbit GDDR SDRAM 4M x 16Bit x 4 Banks Graphic Double Data Rate Synchronous DRAM Revision 1.7 June 2004 Samsung Electronics reserves the right to change products or specification without notice. -1- Rev 1.7 (June 2004) Target Spec K4D551638F-TC Revision History Revision 1.7 (June 15, 2004) - Target Spec • Changed VDD/VDDQ of K4D551638F-TC33 from 2.8V + 0.1V to 2.8V(min)/2.95V(max) 256M GDDR SDRAM Revision 1.6 (March 31, 2004) - Target Spec • AC Changes : Refer to the AC characteristics of page 13 and 14. Revision 1.5 (March 18, 2004) - Target Spec • Added K4D551638F-TC33 in the data sheet. Revision 1.4 (February 27, 2004) - Target Spec • Added K4D551638F-TC36/40 in the data sheet. Revision 1.3 (December 5, 2003) • Changed VDD/VDDQ of K4D551638F-TC50 from 2.5V + 5% to 2.6V + 0.1V Revision 1.2 (November 11, 2003) • "Wrtie-Interrupted by Read Function" is supported Revision 1.1 (October 13, 2003) • Defined ICC7 value Revision 1.0 (October 10, 2003) • Defined DC spec • Changed part number of 16Mx16 GDDR F-die from K4D561638F-TC to K4D551638F-TC. Revision 0.1 (October 2, 2003) - Target Spec • Added Lead free package part number in the data sheet. • Removed K4D561638F-TC40 from the data sheet. Revision 0.0 (July 2, 2003) - Target Spec • Defined Target Specification -2- Rev 1.7 (June 2004) Target Spec K4D551638F-TC 256M GDDR SDRAM 4M x 16Bit x 4 Banks Graphic Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL FEATURES • 2.6V + 0.1V power supply for device operation • 2.6V + 0.1V power supply for I/O interface • SSTL_2 compatible inputs/outputs • 4 banks operation • MRS cycle with address key programs -. Read latency 3 (clock) -. Burst length (2, 4 and 8) -. Burst type (sequential & interleave) • All inputs except data & DM are sampled at the positive going edge of the system clock • Differential clock input • No Write-Interrupted by Read Function • 2 DQS’s ( 1DQS / Byte ) • Data I/O transactions on both edges of Data strobe • DLL aligns DQ and DQS transitions with Clock transition • Edge aligned data & data strobe output • Center aligned data & data strobe input • DM for write masking only • Auto & Self refresh • 64ms refresh period (8K cycle) • 66pin TSOP-II • Maximum clock frequency up to 300MHz • Maximum data rate up to 600Mbps/pin ORDERING INFORMATION Part NO. K4D551638F-TC33 K4D551638F-TC36 K4D551638F-TC40 K4D551638F-TC50 K4D551638F-TC60* Max Freq. 300MHz 275MHz 250MHz 200MHz 166MHz Max Data Rate 600Mbps/pin 550Mbps/pin 500Mbps/pin 400Mbps/pin 333Mbps/pin SSTL_2 66pin TSOP-II Interface Package 1. K4D551638F-LC is the Lead Free package part number. 2. For the K4D551638F-TC60, VDD & VDDQ = 2.5V + 5% 3. For the K4D551638F-TC36, VDD & VDDQ = 2.8V + 0.1V 4. For the K4D551638F-TC33, VDD & VDDQ = 2.8V ~ 2.95V GENERAL DESCRIPTION FOR 4M x 16Bit x 4 Bank GDDR SDRAM The K4D551638F is 268,435,456 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 4,194,304 words by 16 bits, fabricated with SAMSUNG’s high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 1.1GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications. -3- Rev 1.7 (June 2004) Target Spec K4D551638F-TC PIN CONFIGURATION (Top View) VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDDQ LDQS NC VDD NC LDM WE CAS RAS CS NC BA0 BA1 AP/A10 A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSSQ UDQS NC VREF VSS UDM CK CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS 256M GDDR SDRAM 66 PIN TSOP(II) (400mil x 875mil) (0.65 mm Pin Pitch) 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 PIN DESCRIPTION CK,CK CKE CS RAS CAS WE L(U)DQS L(U)DM RFU Differential Clock Input Clock Enable Chip Select Row Address Strobe Column Address Strobe Write Enable Data Strobe Data Mask Reserved for Future Use BA0, BA1 A0 ~A12 DQ0 ~ DQ15 VDD VSS VDDQ VSSQ NC VREF Bank Select Address Address Input Data Input/Output Power Ground Power for DQ’s Ground for DQ’s No Connection Reference voltage -4- Rev 1.7 (June 2004) Target Spec K4D551638F-TC INPUT/OUTPUT FUNCTIONAL DESCRIPTION Symbol CK, CK*1 Input Type Function The differential system clock Input. All of the inputs are sampled on the rising edge of the clock except DQ’s and DM’s that are sampled on both edges of the DQS. Activates the CK signal when high and deactivates the CK signal when low. By deactivating the clock, CKE low indicates the Power down mode or Self refresh mode. CS enables the command decoder when low and disabled the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. Latches row addresses on the positive going edge of the CK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active. Data input and output are synchronized with both edge of DQS. For the x16, LDQS corresponds to the data on DQ0-DQ7 ; UDQS corresponds to the data on DQ8-DQ15. Data in Mask. Data In is masked by DM Latency=0 when DM is high in burst write. For the x16, LDM corresponds to the data on DQ0-DQ7 ; UDM correspons to the data on DQ8-DQ15. Data inputs/Outputs are multiplexed on the same pins. Selects which bank is to be active. Row/Column addresses are multiplexed on the same pins. Row addresses : RA0 ~ RA12, Column addresses : CA0 ~ CA8. Power and ground for the input buffers and core logic. Isolated power supply and ground for the output buffers to provide improved noise immunity. Reference voltage for inputs, used for SSTL interface. This pin is recommended to be left "No connection" on the device 256M GDDR SDRAM CKE Input CS Input RAS CAS WE Input Input Input LDQS,UDQS Input/Output LDM,UDM DQ0 ~ DQ15 BA0, BA1 A0 ~ A12 VDD/VSS VDDQ/VSSQ VREF NC/RFU Input Input/Output Input Input Power Supply Power Supply Power Supply No connection/ Reserved for future use *1 : The timing reference point for the differential clocking is the cross point of CK and CK. For any applications using the single ended clocking, apply VREF to CK pin. -5- Rev 1.7 (June 2004) Target Spec K4D551638F-TC BLOCK DIAGRAM (4Mbit x 16I/O x 4 Bank) 256M GDDR SDRAM 16 Intput Buffer I/O Control LWE LDMi CK, CK Bank Select Data Input Register Serial to parallel 4Mx16 Output Buffer 2-bit prefetch Sense AMP Refresh Counter Row Buffer Row Decoder 4Mx16 4Mx16 4Mx16 32 16 x16 DQi Address Register CK,CK ADDR Column Decoder LCBR LRAS Col. Buffer Latency & Burst Length Strobe Gen. Data Strobe Programming Register LCKE LRAS LCBR LWE LCAS LWCBR DLL CK,CK LDMi Timing Register CK,CK CKE CS RAS CAS WE LDM UDM -6- Rev 1.7 (June 2004) Target Spec K4D551638F-TC FUNCTIONAL DESCRIPTION • Power-Up Sequence DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. 1. Apply power and keep CKE at low state (All other inputs may be undefined) - Apply VDD before VDDQ . - Apply VDDQ before VREF & VTT 2. Start clock and maintain stable condition for minimum 200us. 3. The minimum of 200us after stable power and clock(CK,CK ), apply NOP and take CKE to be high . 4. Issue precharge command for all banks of the device. 5. Issue a EMRS command to enable DLL *1 6. Issue a MRS command to reset DLL. The additional 200 clock cycles are required to lock the DLL. *1,2 7. Issue precharge command for all banks of the device. 8. Issue at least 2 or more auto-refresh commands. 9. Issue a mode register set command with A8 to low to initialize the mode register. *1 The additional 200cycles of clock input is required to lock the DLL after enabling DLL. *2 Sequence of 6&7 is regardless of the order. 256M GDDR SDRAM Power up & Initialization Sequence 0 CK,CK tRP 2 Clock min. 2 Clock min. precharge ALL Banks 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 tRP 1st Auto Refresh tRFC 2nd Auto Refresh tRFC Mode 2 Clock min. Any Command Command precharge ALL Banks EMRS MRS DLL Reset ~ Register Set Inputs must be stable for 200us 200 Clock min. * When the operating frequency is changed, DLL reset should be required again. After DLL reset again, the minimum 200 cycles of clock input is needed to lock the DLL. -7- Rev 1.7 (June 2004) 메마른 뼈들에 생기를 주닮도록 ( 주수아 ) 하나님의 마음 ( 주찬양 ) Day of Eligah Target Spec K4D551638F-TC MODE REGISTER SET(MRS) The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for proper operation. The mode register is written by asserting low on CS, RAS, CAS and WE(The DDR SDRAM should be in active mode with CKE already high prior to writing into the mode register). The state of address pins A0 ~ A12 and BA0, BA1 in the same cycle as CS, RAS, CAS and WE going low is written in the mode register. Minimum two clock cycles are requested to complete the write operation in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0 ~ A2, addressing mode uses A3, CAS latency(read latency from column address) uses A4 ~ A6. A7 is used for test mode. A8 is used for DLL reset. A7,A8, BA0 and BA1 must be set to low for normal MRS operation. Refer to the table for specific codes for various burst length, addressing modes and CAS latencies. BA1 RFU BA0 0 A12 A11 A10 A9 A8 DLL A7 TM A6 A5 A4 A3 BT A2 A1 A0 Address Bus 256M GDDR SDRAM RFU CAS Latency Burst Length Mode Register DLL A8 0 1 DLL Reset No Yes Test Mode A7 0 1 mode Normal Test Burst Type A3 0 1 Type Sequential Interleave Burst Length CAS Latency BA0 0 1 An ~ A0 MRS EMRS A6 0 0 0 0 * RFU(Reserved for future use) should stay "0" during MRS cycle. 1 1 1 1 MRS Cycle 0 CK, CK Command NOP Precharge All Banks NOP NOP MRS A2 Latency Reserved Reserved Reserved 3 Reserved Reserved Reserved Reserved 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Burst Type Sequential Reserve 2 4 8 Reserve Reserve Reserve Reserve Interleave Reserve 2 4 8 Reserve Reserve Reserve Reserve A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 1 2 3 4 5 6 7 8 NOP Any Command NOP NOP tRP tMRD=2 tCK *1 : MRS can be issued only at all banks precharge state. *2 : Minimum tRP is required to issue MRS command. -8- Rev 1.7 (June 2004) Target Spec K4D551638F-TC EXTENDED MODE REGISTER SET(EMRS) The extended mode register stores the data for enabling or disabling DLL and selecting output driver strength. The default value of the extended mode register is not defined, therefore the extened mode register must be written after power up for enabling or disabling DLL. The extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA0(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register). The state of address pins A0, A2 ~ A5, A7 ~ A12 and BA1 in the same cycle as CS, RAS, CAS and WE going low are written in the extended mode register. A1 and A6 are used for setting driver strength to normal, weak or matched impedance. Two clock cycles are required to complete the write operation in the extended mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. A0 is used for DLL enable or disable. "High" on BA0 is used for EMRS. All the other address pins except A0,A1,A6 and BA0 must be set to low for proper EMRS operation. Refer to the table for specific codes. BA1 RFU BA0 1 A12 A11 A10 RFU A9 A8 A7 A6 D.I.C A5 A4 RFU A3 A2 A1 D.I.C A0 DLL 256M GDDR SDRAM Address Bus Extended Mode Register BA0 0 1 An ~ A0 MRS EMRS A6 0 0 1 1 A1 0 1 0 1 Output Driver Impedence Control Full Weak Matched N/A 100% 60% 30% Do not use A0 0 1 DLL Enable Enable Disable *1 : RFU(Reserved for future use) should stay "0" during EMRS cycle. -9- Rev 1.7 (June 2004) Target Spec K4D551638F-TC ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Voltage on VDDQ supply relative to Vss Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD VDDQ TSTG PD IOS Value -0.5 ~ 3.6 -1.0 ~ 3.6 -0.5 ~ 3.6 -55 ~ +150 2.0 50 Unit V V V °C W mA 256M GDDR SDRAM Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. POWER & DC OPERATING CONDITIONS(SSTL_2 In/Out) Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 65°C) Parameter Device Supply voltage Output Supply voltage Reference voltage Termination voltage Input logic high voltage Input logic low voltage Output logic high voltage Output logic low voltage Input leakage current Output leakage current Symbol VDD VDDQ VREF Vtt VIH(DC) VIL(DC) VOH VOL IIL IOL Min 2.5 2.5 0.49*VDDQ VREF-0.04 VREF+0.15 -0.30 Vtt+0.76 -5 -5 Typ 2.6 2.6 VREF - Max 2.7 2.7 0.51*VDDQ VREF+0.04 VDDQ+0.30 VREF-0.15 Vtt-0.76 5 5 Unit V V V V V V V V uA uA Note 1, 7 1 2 3 4 5 IOH=-15.2mA IOL=+15.2mA 6 6 Note : 1. Under all conditions VDDQ must be less than or equal to VDD. 2. VREF is expected to equal 0.50*VDDQ of the transmitting device and to track variations in the DC level of the same. Peak to peak noise on the VREF may not exceed + 2% of the DC value. Thus, from 0.50*VDDQ, VREF is allowed + 25mV for DC error and an additional + 25mV for AC noise. 3. Vtt of the transmitting device must track VREF of the receiving device. 4. VIH(max.)= VDDQ +1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate. 5. VIL(mim.)= -1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate. 6. For any pin under test input of 0V < VIN < VDD is acceptable. For all other pins that are not under test VIN=0V. 7. For the K4D551638F-TC60 , VDD & VDDQ =2.5V + 5% , For the K4D551638F-TC36 , VDD & VDDQ =2.8V + 0.1V and For the K4D551638F-TC33 , VDD & VDDQ = 2.8V ~ 2.95V - 10 - Rev 1.7 (June 2004) Target Spec K4D551638F-TC Recommended operating conditions Unless Otherwise Noted, TA=0 to 65°C) Version Parameter Operating Current (One Bank Active) Precharge Standby Current in Power-down mode Precharge Standby Current in Non Power-down mode Active Standby Current power-down mode Active Standby Current in in Non Power-down mode Operating Current (Burst Mode) Refresh Current Self Refresh Current Operating Current (4Bank Interleaving) Symbol Test Condition -33 ICC1 ICC2P ICC2N ICC3P ICC3N ICC4 ICC5 ICC6 ICC7 Burst Lenth=2 tRC ≥ tRC(min) IOL=0mA, tCC= tCC(min) CKE ≤ VIL(max), tCC= tCC(min) CKE ≥ VIH(min), CS ≥ VIH(min), tCC= tCC(min) CKE ≤ VIL(max), tCC= tCC(min) CKE ≥ VIH(min), CS ≥ VIH(min), tCC= tCC(min) TBD TBD TBD TBD TBD TBD TBD TBD TBD -36 TBD TBD TBD TBD TBD TBD TBD TBD TBD -40 TBD TBD TBD TBD TBD TBD TBD TBD TBD -50 150 4 25 55 75 250 200 3 380 -60 125 3 20 35 56 200 180 3 350 mA mA mA mA mA mA mA mA mA 2 1 Unit Note 256M GDDR SDRAM DC CHARACTERISTICS tRC ≥ tRFC(min)tRC ≥ tRFC(min) Page Burst, All Banks activated. tRC ≥ tRFC(min) CKE ≤ 0.2V Burst Length=4, tRC ≥ tRFC(min) IOL=0mA, tCC = tCC(min) Note : 1. Measured with outputs open. 2. Refresh period is 64ms AC INPUT OPERATING CONDITIONS Recommended operating conditions(Voltage referenced to VSS=0V, VDD=2.6V+ 0.1V, VDDQ=2.6V+ 0.1V ,TA=0 to 65°C) Parameter Input High (Logic 1) Voltage; DQ Input Low (Logic 0) Voltage; DQ Clock Input Differential Voltage; CK and CK Clock Input Crossing Point Voltage; CK and CK Symbol VIH VIL VID VIX Min VREF+0.35 0.7 0.5*VDDQ-0.2 Typ - Max VREF-0.35 VDDQ+0.6 0.5*VDDQ+0.2 Unit V V V V Note 1 2 Note : 1. VID is the magnitude of the difference between the input level on CK and the input level on CK 2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same - 11 - Rev 1.7 (June 2004) Target Spec K4D551638F-TC 256M GDDR SDRAM AC OPERATING TEST CONDITIONS (VDD=2.6V ± 0.1V, TA= 0 to 65°C) Parameter Input reference voltage for CK(for single ended) CK and CK signal maximum peak swing CK signal minimum slew rate Input Levels(VIH/VIL) Input timing measurement reference level Output timing measurement reference level Output load condition Value 0.50*VDDQ 1.5 1.0 VREF+0.35/VREF-0.35 VREF Vtt See Fig.1 Vtt=0.5*VDDQ Unit V V V/ns V V V Note RT=50Ω Output Z0=50Ω CLOAD=30pF VREF =0.5*VDDQ (Fig. 1) Output Load Circuit CAPACITANCE (VDD=2.6V, TA= 25°C, f=1MHz) Parameter Input capacitance( CK, CK ) Input capacitance(A0~A12, BA0~BA1) Input capacitance ( CKE, CS, RAS,CAS, WE ) Data & DQS input/output capacitance(DQ0~DQ15) Input capacitance(DM0 ~ DM3) Symbol CIN1 CIN2 CIN3 COUT CIN4 Min 1.0 1.0 1.0 1.0 1.0 Max 5.0 4.0 4.0 6.5 6.5 Unit pF pF pF pF pF DECOUPLING CAPACITANCE GUIDE LINE Recommended decoupling capacitance added to power line at board. Parameter Decoupling Capacitance between VDD and VSS Decoupling Capacitance between VDDQ and VSSQ Symbol CDC1 CDC2 Value 0.1 + 0.01 0.1 + 0.01 Unit uF uF Note : 1. VDD and VDDQ pins are separated each other. All VDD pins are connected in chip. All VDDQ pins are connected in chip. 2. VSS and VSSQ pins are separated each other All VSS pins are connected in chip. All VSSQ pins are connected in chip. - 12 - Rev 1.7 (June 2004) Target Spec K4D551638F-TC AC CHARACTERISTICS Parameter CK cycle time CL=3 CK high level width CK low level width DQS out access time from CK Output access time from CK Data strobe edge to Dout edge Read preamble Read postamble CK to valid DQS-in DQS-In setup time DQS-in hold time DQS write postamble DQS-In high level width DQS-In low level width Address and Control input setup Address and Control input hold DQ and DM setup time to DQS DQ and DM hold time to DQS Clock half period 256M GDDR SDRAM Symbol tCK tCH tCL tDQSCK tAC tDQSQ tRPRE tRPST tDQSS tWPRES tWPREH tWPST tDQSH tDQSL tIS tIH tDS tDH tHP -33 Min 3.3 0.45 0.45 -0.6 -0.6 0.9 0.4 0.85 0 0.35 0.4 0.4 0.4 0.9 0.9 0.35 0.35 tCLmin or tCHmin tHP0.35 -36 Max 10 0.55 0.55 0.6 0.6 0.35 1.1 0.6 1.15 0.6 0.6 0.6 - -40 Max 10 0.55 0.55 0.6 0.6 0.4 1.1 0.6 1.15 0.6 0.6 0.6 - -50 Max 10 0.55 0.55 0.6 0.6 0.4 1.1 0.6 1.15 0.6 0.6 0.6 - -60 Max 10 0.55 0.55 0.55 0.65 0.4 1.1 0.6 1.28 0.6 - Min 3.6 0.45 0.45 -0.6 -0.6 0.9 0.4 0.85 0 0.35 0.4 0.4 0.4 0.9 0.9 0.4 0.4 tCLmin or tCHmin tHP-0.4 Min 4.0 0.45 0.45 -0.6 -0.6 0.9 0.4 0.85 0 0.35 0.4 0.4 0.4 0.9 0.9 0.4 0.4 tCLmin or tCHmin tHP-0.4 Min 5.0 0.45 0.45 -0.55 -0.65 0.9 0.4 0.72 0 0.25 0.4 0.35 0.35 0.6 0.6 0.4 0.4 tCLmin or tCHmin tHP-0.5 Min 6.0 0.45 0.45 -0.6 -0.7 0.9 0.4 0.75 0 0.25 0.4 0.35 0.35 0.8 0.8 0.45 0.45 tCLmin or tCHmin tHP0.55 Max 12 0.55 0.55 0.6 0.7 0.45 1.1 0.6 1.25 0.6 - Unit Note ns tCK tCK ns ns ns tCK tCK tCK ns tCK tCK tCK tCK ns ns ns ns ns ns 1 1 1 Data output hold time from DQS tQH Note 1 : - The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data strobe and all data associated with that data strobe are coincidentally valid. - The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst case output vaild window even then the clock duty cycle applied to the device is better than 45/55% - A new AC timing term, tQH which stands for data output hold time from DQS is difined to account for clock duty cycle variation and replaces tDV - tQHmin = tHP-X where . tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL) . X=A frequency dependent timing allowance account for tDQSQmax - 13 - Rev 1.7 (June 2004) Target Spec K4D551638F-TC AC CHARACTERISTICS (I) Parameter Row cycle time Refresh row cycle time Row active time RAS to CAS delay for Read RAS to CAS delay for Write Row precharge time Row active to Row active Last data in to Row precharge @Normal Precharge Last data in to Row precharge @Auto Precharge Last data in to Read command Col. address to Col. address Mode register set cycle time Auto precharge write recovery + Precharge Exit self refresh to read command Power down exit time Refresh interval time 256M GDDR SDRAM -33 Min 15 17 10 5 3 5 3 3 3 3 1 2 8 200 3tCK +tIS 7.8 Symbol tRC tRFC tRAS tRCDRD tRCDWR tRP tRRD tWR tWR_A tCDLR tCCD tMRD tDAL tXSR tPDEX tREF -36 Max Min 15 17 10 5 3 5 3 3 3 2 1 2 8 200 3tCK +tIS 7.8 -40 Max Min 13 15 9 4 2 4 3 3 3 2 1 2 7 200 3tCK +tIS 7.8 -50 Max Min 12 14 8 4 2 4 2 3 3 2 1 2 7 200 1tCK +tIS 7.8 -60 Max Min 10 12 7 3 2 3 2 3 3 1 1 2 6 200 1tCK +tIS 7.8 Max 100K - Unit Note tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK ns us 1 1 1 100K - 100K - 100K - 100K - Note : 1. For normal write operation, even numbers of Din are to be written inside DRAM AC CHARACTERISTICS (II) (Unit : Number of Clock) K4D551638D-TC33 Frequency Cas Latency 300MHz ( 3.3ns ) 3 tRC 15 tRFC 17 tRAS 10 tRCDRD tRCDWR 5 3 tRP 5 tRRD 3 tDAL 8 Unit tCK K4D551638D-TC36 Frequency Cas Latency 275MHz ( 3.6ns ) 3 tRC 15 tRFC 17 tRAS 10 tRCDRD tRCDWR 5 3 tRP 5 tRRD 3 tDAL 8 Unit tCK K4D551638D-TC40 Frequency Cas Latency 250MHz ( 4.0ns ) 3 200MHz ( 5.0ns ) 3 tRC 13 12 tRFC 15 14 tRAS 9 8 tRCDRD tRCDWR 4 2 4 2 tRP 4 4 tRRD 3 3 tDAL 7 7 Unit tCK tCK K4D551638D-TC50 Frequency Cas Latency 200MHz ( 5.0ns ) 3 tRC 12 tRFC 14 tRAS 8 tRCDRD tRCDWR 4 2 tRP 4 tRRD 3 tDAL 7 Unit tCK K4D551638D-TC60 Frequency Cas Latency 166MHz ( 6.0ns ) 3 tRC 10 tRFC 12 tRAS 7 tRCDRD tRCDWR 3 2 tRP 3 tRRD 2 tDAL 6 Unit tCK - 14 - Rev 1.7 (June 2004) Target Spec K4D551638F-TC Write Interrupted by a Read & DM A burst write can be interrupted by a read command of any bank. The DQ’s must be in the high impedance state at least one clock cycle before the interrupting read data appear on the outputs to avoid data contention. When the read command is registered, any residual data from the burst write cycle must be masked by DM. The delay from the last data to read command (tCDLR) is required to avoid the data contention DRAM inside. Data that are presented on the DQ pins before the read command is initiated will actually be written to the memory. Read command interrupting write can not be issued at the next clock edge of that of write command. 256M GDDR SDRAM < Burst Length=8, CAS Latency=3 > 0 CK CK Command DQS CAS Latency=3 DQ ′s tDQSSmin NOP WRITE NOP NOP NOP READ NOP NOP NOP 1 2 3 4 5 6 7 8 tDQSSmax tWPRES*5 Din 0 Din 1 Din 2 Din 3 tCDLR Din 4 Din 5 Din 6 Din 7 Dout 0 Dout 1 tCDLR DQS CAS Latency=3 DQ ′s DM tWPRES*5 Din 0 Din 1 Din 2 Din 3 Din 4 Din 5 Din 6 Din 7 Dout 0 Dout 1 The following function established how a Read command may interrupt a Write burst and which input data is not written into the memory. 1. For Read commands interrupting a Write burst, the minimum Write to Read command delay is 2 clock cycles. The case where the Write to Read delay is 1 clock cycle is disallowed 2. For Read commands interrupting a Write burst, the DM pin must be used to mask the input data words whcich immediately precede the interrupting Read operation and the input data word which immediately follows the interrupting Read operation 3. For all cases of a Read interrupting a Write, the DQ and DQS buses must be released by the driving chip (i.e., the memory controller) in time to allow the buses to turn around before the DDR SDRAM drives them during a read operation. 4. If input Write data is masked by the Read command, the DQS input is ignored by the DDR SDRAM. * This function is only supported in 200/166MHz. - 15 - Rev 1.7 (June 2004) Target Spec K4D551638F-TC PACKAGE DIMENSIONS (66pin TSOP-II) 256M GDDR SDRAM Units : Millimeters (0.80) (0.50) (10×) (10×) 0.125 +0.075 -0.035 (0.50) (R 0.2 5) #66 #34 10.16±0.10 (1.50) #1 (1.50) #33 0.665±0.05 0.210±0.05 (0.80) (R 0. 15 ) 0.05 MIN (0.71) 0.65TYP 0.65±0.08 0.30±0.08 (10×) 0.10 MAX [ 0.075 MAX ] (R 5) (4× ) NOTE 1. ( ) IS REFERENCE 2. [ ] IS ASS’Y OUT QUALITY 0×~8× - 16 - Rev 1.7 (June 2004) 0. 25 ) (R 0.1 (10×) 1.20MAX 22.22±0.10 1.00±0.10 0.25TYP 0.45~0.75 11.76±0.20 (10.76)