K4E6E304ED-EGCG

Rev. 1.0, Feb. 2019 K4E6E304ED 16Gb DDP LPDDR3 SDRAM 178FBGA, 11x11.5 512M x32 (32M x32 x 8banks) This document and all information provided herein (collectively, "Information") is provided on an "AS-IS" basis and remains the sole and exclusive property of Samsung Electronics. You must keep all Information in strict confidence and trust, and must not, directly or indirectly, in any way, disclose, make accessible, post on the internet, reveal, report, publish, disseminate or transfer any Information to any third party. You must not reproduce or copy Information, without first obtaining express written permis sion from Samsung Electronics. You must not use, or allow use of, any Information in any manner whatsoever, except to inter nally evaluate the Information. You must restrict access to Information to those of your employees who have a bonafide need -to-know for such purpose and are bound by obligations at least as restrictive as this clause. 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Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. For updates or additional information about Samsung products, contact your nearest Samsung office. All brand names, trademarks and registered trademarks belong to their respective owners. © 2019 Samsung Electronics Co., Ltd. All rights reserved. -1- datasheet K4E6E304ED-EGCG Rev. 1.0 LPDDR3 SDRAM Revision History Revision No. History Draft Date Remark Editor 0.0 - First version for target specification. 23th Aug, 2018 Target J.Y.Bae 0.5 - Preliminary datasheet. 16th Jan, 2019 Preliminary J.Y.Bae 19th Feb, 2019 Final J.Y.Bae - Update IDD spec table. 1. Update IDD values. 2. Change IDD power Supply : VDD1/VDD2/VDDQ,VDDCA -> VDD1/VDD2,VDDCA/VDDQ 1.0 - Final datasheet. - Correct a note4 in IDD Specifications. : Measured currents are the summation of VDDQ and VDDCA. -> Measured currents are the summation of VDD2 and VDDCA. SAMSUNG -2- datasheet K4E6E304ED-EGCG Rev. 1.0 LPDDR3 SDRAM Table Of Contents 16Gb DDP LPDDR3 SDRAM 1.0 COMPARISION BETWEEN LPDDR2 AND LPDDR3 ....................................................................................................................... 5 2.0 KEY FEATURE.................................................................................................................................................................................. 7 3.0 ORDERING INFORMATION ............................................................................................................................................................. 8 4.0 PACKAGE DIMENSION & PIN DESCRIPTION ................................................................................................................................ 9 4.1 LPDDR3 SDRAM Package Dimension...........................................................................................................................................9 4.2 LPDDR3 SDRAM Package Ballout.................................................................................................................................................10 4.3 Functional Block Diagram...............................................................................................................................................................11 4.4 LPDDR3 Pad Definition and Description ........................................................................................................................................12 5.0 FUNCTIONAL DESCRIPTION .......................................................................................................................................................... 13 6.0 LPDDR3 SDRAM ADDRESSING...................................................................................................................................................... 13 6.1 Simplified LPDDR3 State Diagram .................................................................................................................................................14 6.2 Mode Register Definition ................................................................................................................................................................15 6.2.1 Mode Register Assignment and Definition in LPDDR3 SDRAM..............................................................................................15 7.0 TRUTH TABLES................................................................................................................................................................................ 22 7.1 Command truth table ......................................................................................................................................................................22 7.2 CKE Truth Table .............................................................................................................................................................................24 7.3 State Truth Table ............................................................................................................................................................................25 7.4 Data mask truth table......................................................................................................................................................................27 8.0 ABSOLUTE MAXIMUM RATINGS .................................................................................................................................................... 28 9.0 AC & DC OPERATING CONDITIONS .............................................................................................................................................. 29 9.1 Recommended DC Operating Conditions ......................................................................................................................................29 9.2 Input Leakage Current ....................................................................................................................................................................29 9.3 Operating Temperature Range.......................................................................................................................................................29 SAMSUNG 10.0 AC AND DC INPUT MEASUREMENT LEVELS ............................................................................................................................. 30 10.1 AC and DC Logic Input Levels for Single-Ended Signals .............................................................................................................30 10.1.1 AC and DC Input Levels for Single-Ended CA and CS_n Signals.........................................................................................30 10.2 AC and DC Input Levels for CKE..................................................................................................................................................30 10.2.1 AC and DC Input Levels for Single-Ended Data Signals .......................................................................................................30 10.3 Vref Tolerances ............................................................................................................................................................................31 10.4 Input Signal...................................................................................................................................................................................32 10.5 AC and DC Logic Input Levels for Differential Signals .................................................................................................................33 10.5.1 Differential signal definition ....................................................................................................................................................33 10.5.2 Differential swing requirements for clock (CK_t - CK_c) and strobe (DQS_t - DQS_c).........................................................34 10.5.3 Single-ended requirements for differential signals.................................................................................................................35 10.6 Differential Input Cross Point Voltage...........................................................................................................................................36 10.7 Slew Rate Definitions for Single-Ended Input Signals ..................................................................................................................37 10.8 Slew Rate Definitions for Differential Input Signals ......................................................................................................................37 11.0 AC AND DC OUTPUT MEASUREMENT LEVELS ......................................................................................................................... 38 11.1 Single Ended AC and DC Output Levels ......................................................................................................................................38 11.2 Differential AC and DC Output Levels ..........................................................................................................................................38 11.3 Single Ended Output Slew Rate ...................................................................................................................................................39 11.4 Differential Output Slew Rate .......................................................................................................................................................40 11.5 Overshoot and Undershoot Specifications ...................................................................................................................................41 12.0 OUTPUT BUFFER CHARACTERISTICS ....................................................................................................................................... 42 12.1 HSUL_12 Driver Output Timing Reference Load .........................................................................................................................42 13.0 RONPU AND RONPD RESISTOR DEFINITION ............................................................................................................................ 43 13.1 RONPU and RONPD Characteristics with ZQ Calibration ...........................................................................................................44 13.2 Output Driver Temperature and Voltage Sensitivity .....................................................................................................................44 13.3 RONPU and RONPD Characteristics without ZQ Calibration ......................................................................................................45 13.4 RZQ I-V Curve ..............................................................................................................................................................................46 13.5 ODT Levels and I-V Characteristics .............................................................................................................................................48 14.0 INPUT/OUTPUT CAPACITANCE ................................................................................................................................................... 49 15.0 IDD SPECIFICATION PARAMETERS AND TEST CONDITIONS.................................................................................................. 50 15.1 IDD Measurement Conditions.......................................................................................................................................................50 15.2 IDD Specifications ........................................................................................................................................................................52 15.3 IDD Spec Table ............................................................................................................................................................................55 16.0 ELECTRICAL CHARACTERISTICS AND AC TIMING ................................................................................................................... 57 16.1 Clock Specification .......................................................................................................................................................................57 16.1.1 Definition for tCK(avg) and nCK.............................................................................................................................................57 16.1.2 Definition for tCK(abs)............................................................................................................................................................57 16.1.3 Definition for tCH(avg) and tCL(avg)......................................................................................................................................57 -3- K4E6E304ED-EGCG datasheet Rev. 1.0 LPDDR3 SDRAM 16.1.4 Definition for tJIT(per) ............................................................................................................................................................57 16.1.5 Definition for tJIT(cc)..............................................................................................................................................................58 16.1.6 Definition for tERR(nper)........................................................................................................................................................58 16.1.7 Definition for duty cycle jitter tJIT(duty)..................................................................................................................................58 16.1.8 Definition for tCK(abs), tCH(abs) and tCL(abs) .....................................................................................................................58 16.2 Period Clock Jitter.........................................................................................................................................................................59 16.2.1 Clock period jitter effects on core timing parameters.............................................................................................................59 16.2.1.1 Cycle time de-rating for core timing parameters ............................................................................................................59 16.2.1.2 Clock Cycle de-rating for core timing parameters ..........................................................................................................59 16.2.2 Clock jitter effects on Command/Address timing parameters ................................................................................................59 16.2.3 Clock jitter effects on Read timing parameters ......................................................................................................................60 16.2.3.1 tRPRE ............................................................................................................................................................................60 16.2.3.2 tLZ(DQ), tHZ(DQ), tDQSCK, tLZ(DQS), tHZ(DQS) .......................................................................................................60 16.2.3.3 tQSH, tQSL ....................................................................................................................................................................60 16.2.3.4 tRPST.............................................................................................................................................................................60 16.2.4 Clock jitter effects on Write timing parameters ......................................................................................................................60 16.2.4.1 tDS, tDH .........................................................................................................................................................................60 16.2.4.2 tDSS, tDSH ....................................................................................................................................................................60 16.2.4.3 tDQSS ............................................................................................................................................................................61 16.3 LPDDR3 Refresh Requirements by Device Density.....................................................................................................................61 16.4 AC Timing .....................................................................................................................................................................................62 16.5 CA and CS_n Setup, Hold and Derating ......................................................................................................................................67 16.6 Data Setup, Hold and Slew Rate Derating ...................................................................................................................................73 SAMSUNG -4- datasheet K4E6E304ED-EGCG Rev. 1.0 LPDDR3 SDRAM 1.0 COMPARISION BETWEEN LPDDR2 AND LPDDR3 Feature Items LPDDR2 LPDDR3 CLK scheme Differential (CLK/CLKB) ← Data scheme DDR Single-ended, Bi-Directional ← DQS scheme Differential (DQS/DQSB), Bi-Directional ← ADD / CMD scheme DDR ← State Diagram As is Refer to the Datasheet Command Truth Table As is No support BST State for bank n to Bank n/m As is No support BST / Interrupt Data mask Truth Table As is ← I/O Interface HSUL_12 ← Burst Length 4(Default), 8, 16 8 Burst Type Sequential, Interleave Sequential No Wrap Support (BL4) No support 8 8 Organization # of Bank ×16/×32 ← Data Mask Support (Write) ← Refresh mode All Bank Refresh / Per Bank Refresh / Self Refresh ← Row Addressing(x32) SAMSUNG Column Bank Refer to the Datasheet Refer to the Datasheet 667/800/1066 1600/1866/2133 Refer to the Datasheet Refer to the Datasheet ← Refresh Requirements Speed bin [Mbps] Read/Write latency AC Parameter Core Parameters IO Parameters CA / CS_n / Setup / Hold / Deratin Data Setup / Hold / Deratin Special Function Power Supply IDD Specification Parameters and Test Conditions Temperature PASR Support TCSR Support ← Deep Power Down Support No Support Configurable D/S Support ← ZQ Calibration Support ← DQ Calibration Support ←1) CA Calibration N/A Support Write Leveling N/A Support VDD1 [V] 1.70 ~ 1.95 ← VDD2 [V] 1.14 ~ 1.30 ← VDDQ [V] 1.14 ~ 1.30 ← VDDCA [V] 1.14 ~ 1.30 ← IDD Measurement Conditions As is ← IDD Specification As is ← General [C] -25 ~ 85 ← Extended [C] -25 ~ 105 ← -5- datasheet K4E6E304ED-EGCG LPDDR3 SDRAM Items LPDDR2 LPDDR3 General As is ← Support MR0 DI2) Support MR1 BL/WC/nWR2) Support MR2 RL & WL, nWRE2) Support MR3 DS2) Modified Mode Register Set Rev. 1.0 MR4 Refresh Rate Support (0.5×tREFI)2) MR8 I/O width, Type2) Support Adding RONpu/RONpd Characteristics MR41/42/48 N/A MR2 OP7(Write Leveling) w/ ZQ Calibration As is ← w/o ZQ Calibration As is ← Temperature and Voltage Sensitivity As is ← RZQI-V Curve As is ← As is ← VDD1 [V] -0.4 ~ 2.3 ← VDD2 [V] -0.4 ~ 1.6 ← VDDQ [V] -0.4 ~ 1.6 ← VDDCA [V] -0.4 ~ 1.6 ← VIN/VOUT [V] -0.4 ~ 1.6 ← Tstg [C] -55 ~ 125 ← Input leakage As is ← CA and CS_n pins AC : VREF +/- 0.22V DC : VREF +/- 0.13V AC : VREF ± 0.150V / ±0.135V (1600/1866,2133) DC : VREF ± 0.10V / ± 0.10V (1600/1866,2133) CKE pin 0.2×VDDCA ~ 0.8×VDDCA ← DQ pins AC : VREF +/- 0.22V DC : VREF +/- 0.13V AC : VREF ± 0.15V/ ±0.135V(1600/1866,2133) DC : VREF ± 0.10V/0.10V (1600/1866,2133) 3) Input/Output Capacitance Absolute maximum DC ratings N/A SAMSUNG AC/DC Logic Input Levels for Single-ended Signals VREF_CA/DQ tolerance 0.49×VDDQ ~ 0.51×VDDQ ← VIHdiff/VILdiff (AC/DC) tDVAC As is ← VSEH/VSEL(AC) As is ← VIXCA/VIXDQ As is ← VILdiff /VIHdiff (Max/Min) As is ← VOHdiff / VOLdiff (AC) As is ← IOZ As is ← MMPUPD As is ← VOHdiff / VOLdiff (AC) As is ← Signal ended output Slew Rate VOH/VOL(AC/DC) As is ← SROse As is ← Differential Output Slew Rate VOHdiff/VOLdiff(AC) As is ← SRQdiff As is ← Maximum Amplitude As is ← Maximum Area As is VDD/VSS : 0.1 [V-ns] As is ← AC/DC Logic Input Levels for Differential Differential Input Cross Point Voltage Input/Output Operating con- Slew Rate definitions for Differential dition AC/DC Output levels for Differential AC/DC Output levels for Differential Overshoot / Undershoot HSUL_12 Driver Output Timing NOTE : 1) DQ out data are same in a byte. 2) These items are modified from LPDDR2 specification. Please refer to 15Mode Register Definition. 3) The parameter applies to both die and package. -6- datasheet K4E6E304ED-EGCG Rev. 1.0 LPDDR3 SDRAM LPDDR3 SDRAM SPECIFICATION 16G DDP = 256M x 32 (32M x 32 x 8 banks) + 256M x 32 (32M x 32 x 8 banks) 178FBGA, 11x11.5 2.0 KEY FEATURE • Double-data rate architecture; two data transfers per clock cycle • Bidirectional data strobes (DQS_t, DQS_c), These are transmitted/received with data to be used in capturing data at the receiver • Differential clock inputs (CK_t and CK_c) • Differential data strobes (DQS_t and DQS_c) • Commands & addresses entered on both positive and negative CK edges; data and data mask referenced to both edges of DQS • 8 internal banks for concurrent operation • Data mask (DM) for write data • Burst Length: 8 • Burst Type: Sequential • Read & Write latency : Refer to Table 46 LPDDR3 AC Timing Table • Auto Precharge option for each burst access • Configurable Drive Strength • All Bank Refresh, Per Bank Refresh and Self Refresh • Partial Array Self Refresh and Temperature Compensated Self Refresh • Write Leveling • CA Calibration • HSUL_12 compatible inputs • VDD1/VDD2/VDDQ/VDDCA : 1.8V/1.2V/1.2V / 1.2V • No DLL : CK to DQS is not synchronized • Edge aligned data output, center aligned data input • Operating Temperature : -25 ~ 85C • On Die Termination using ODT pin • 2/CS, 2CKE SAMSUNG -7- Rev. 1.0 datasheet K4E6E304ED-EGCG LPDDR3 SDRAM 3.0 ORDERING INFORMATION Part No. Org. Package Temperature Max Frequency Interface K4E6E304ED-EGCG x32 178FBGA_11x11.5 Tc = -25 ~ 85C 2133Mbps (tCK=0.937ns) HSUL_12 NOTE : 1) 2133Mbps is backward compatible to 1866Mbps. K4 E 6E 30 4 E D - E G CG Samsung Speed Mobile DRAM Memory CG: 0.937ns@RL16, tRCD18ns, tRP18ns Device Type Temp, Power E : LPDDR3 SDRAM G : -25 ~ 85C (Standard) Density, Refresh Package 6E : 16G, 8K/32ms E : 178-FBGA Organization Generation 30 : x32 (2/CS, 2CKE) Bank 4 : 8Bank SAMSUNG D : 5th Generation Interface, VDD, VDDQ E : HSUL_12, 1.8V, 1.2V, 1.2V, 1.2V -8- Rev. 1.0 datasheet K4E6E304ED-EGCG LPDDR3 SDRAM 4.0 PACKAGE DIMENSION & PIN DESCRIPTION 4.1 LPDDR3 SDRAM Package Dimension 178-Ball Fine pitch Ball Grid Array Package (measured in millimeters) 11.00 ± 0.10 A 0.08MAX C Units:millimeters 0.80 x 12 = 9.60 #A1 INDEX 4.80 0.80 0.80 B 13 C 12 11 10 9 8 7 6 5 4 3 2 1 A B 0.65 C #A1 D E 0.65 11.50 ± 0.10 11.50 ± 0.10 0.65 x 16 = 10.40 F G H J SAMSUNG K L N P R T U 0.22 0.05 0.80 0.10 178-0.310.05 Post Reflow (*Solder Ball 0.30)  0.2 M A B TOP VIEW SIDE VIEW -9- BOTTOM VIEW 5.20 M Rev. 1.0 datasheet K4E6E304ED-EGCG LPDDR3 SDRAM 4.2 LPDDR3 SDRAM Package Ballout 178Ball FBGA 1 2 3 4 5 6 7 8 9 10 11 12 13 A DNU DNU VDD1 VDD1 VDD1 VDD1 NB VDD2 VDD2 VDD1 VDDQ DNU DNU B DNU VSS ZQ NC VSS VSSQ NB DQ31 DQ30 DQ29 DQ28 VSSQ DNU C CA9 VSSCA NC VSS VSSQ NB DQ27 DQ26 DQ25 DQ24 VDDQ D CA8 VSSCA VDD2 VDD2 VDD2 NB DM3 DQ15 E CA7 CA6 VSS VSS VSSQ NB VDDQ DQ14 DQ13 DQ12 VDDQ F VDDCA CA5 VSSCA VSS VSSQ NB DQ11 DQ10 DQ9 DQ8 VSSQ G VDDCA VSSCA VSSCA VDD2 VSSQ NB DM1 VSSQ VDDCA VRef(CA) VDD2 VDD2 NB VDDQ VDDQ H VSS J CK_c K VSS DQS3_t DQS3_c VSSQ DQS1_t DQS1_c VDDQ VSSQ VDDQ SAMSUNG VDD2 CK_t VSSCA VDD2 VDD2 NB ODT1) VDDQ CKE0 CKE1 VDD2 VDD2 NB VDDQ NC L VDDCA CS0_n CS1_n VDD2 VSS NB DM0 VSSQ M VDDCA CA4 VSSCA VSS VSSQ NB DQ4 DQ5 DQ6 DQ7 VSSQ N CA2 CA3 VSS VSS VSSQ NB VDDQ DQ1 DQ2 DQ3 VDDQ P CA1 VSSCA VDD2 VDD2 VDD2 NB DM2 DQ0 R CA0 NC VSS VSS VSSQ NB DQ20 DQ21 DQ22 DQ23 VDDQ VDDQ VRef(DQ) VSSQ VDDQ VSS VDD2 DQS0_t DQS0_c VDDQ DQS2_t DQS2_c VSSQ T DNU VSS VSS VSS VSS VSSQ NB DQ16 DQ17 DQ18 DQ19 VSSQ DNU U DNU DNU VDD1 VDD1 VDD1 VDD1 NB VDD2 VDD2 VDD1 VDDQ DNU DNU [Top View] NOTE : 1) In case ODT function is not used, ODT pin should be considered as NC. ODT will be connected to rank 0. The ODT Input to rank 1 (if 2nd rank is present) will be connected to Ground in the package. - 10 - Power Ground ODT NB ZQ DNU/NC datasheet K4E6E304ED-EGCG Rev. 1.0 LPDDR3 SDRAM 4.3 Functional Block Diagram VDD1 VDD2 VDDCA VDDQ CS0_n, CKE0 Chip 0 : 256Mb x32 CK_t, CK_c DM0~DM3 CA0~CA9 CS1_n, CKE1 DQS0_t~DQS3_t DQS0_c~DQS3_c Chip 1 : 256Mb x32 DQ0~DQ31, ZQ VRef VRef (DQ) (CA) VSS VSSCA VSSQ SAMSUNG - 11 - datasheet K4E6E304ED-EGCG Rev. 1.0 LPDDR3 SDRAM 4.4 LPDDR3 Pad Definition and Description [Table 1] Pad Definition and Description Name Type Description Input Clock: CK_t and CK_c are differential clock inputs. All Double Data Rate (DDR) CA inputs are sampled on both positive and negative edge of CK. Single Data Rate (SDR) inputs, CS_n and CKE, are sampled at the positive Clock edge. Clock is defined as the differential pair, CK_t and CK_c. The positive Clock edge is defined by the crosspoint of a rising CK_t and a falling CK_c. The negative Clock edge is defined by the crosspoint of a falling CK_t and a rising CK_c. CKE Input Clock Enable: CKE HIGH activates and CKE LOW deactivates internal clock signals and therefore device input buffers and output drivers. Power savings modes are entered and exited through CKE transitions. CKE is considered part of the command code. See Command Truth table for command code descriptions. CKE is sampled at the positive Clock edge. CS_n Input Chip Select: CS_n is considered part of the command code. See Command Truth table for command code descriptions. CS_n is sampled at the positive Clock edge. CA0 - CA9 Input DDR Command/Address Inputs: Uni-directional command/address bus inputs. CA is considered part of the command code. See Command Truth table for command code descriptions. DQ0 - DQ15 (x16) DQ0 - DQ31 (x32) I/O CK_t, CK_c DQS0_t-DQS1_t DQS0_c-DQS1_c (x16) DQS0_t-DQS3_t DQS0_c-DQS3_c (x32) Data Inputs/Outputs: Bi-directional data bus Data Strobes (Bi-directional, Differential): The data strobe is bi-directional (used for read and write data) and differential (DQS_t and DQS_c). It is output with read data and input with write data. DQS is edge-aligned to read data and centered with write data. I/O For x16, DQS0_t and DQS0_c correspond to the data on DQ0 - DQ7; DQS1_t and DQS1_c to the data on DQ8 - DQ15. For x32, DQS0_t and DQS0_c correspond to the data on DQ0 - DQ7, DQS1_t and DQS1_c to the data on DQ8 - DQ15, DQS2_t and DQS2_c to the data on DQ16 - DQ23, DQS3_t and DQS3_c to the data on DQ24 - DQ31. SAMSUNG Input Data Mask: DM is the input mask signal for write data. Input data is masked when DM is sampled HIGH coincident with that input data during a Write access. DM is sampled on both edges of DQS. Although DM is for input only, the DM loading shall match the DQ and DQS_t (or DQS_c). DM0 - DM1 (x16) DM0 - DM3 (x32) Input ODT Input VDD1 Supply Core Power Supply 1: Core power supply. For x16 and x32 devices, DM0 is the input data mask signal for the data on DQ0-7, DM1 is the input data mask signal for the data on DQ8-15. For x32 device, DM2 is the input data mask signal for the data on DQ16-23 and DM3 is the input data mask signal for the data on DQ24-31. On Die Termination: This signal enables and disables termination on the DRAM DQ bus according to the specified mode register settings. VDD2 Supply Core Power Supply 2: Core power supply. VDDCA Supply Input Receiver Power Supply: Power supply for CA0-9, CKE, CS_n, CK_t, and CK_c input buffers. VDDQ Supply I/O Power Supply: Power supply for Data input/output buffers. VREF (CA) Supply Reference Voltage for CA Command and Control Input Receiver: Reference voltage for all CA0-9, CKE, CS_n, CK_t, and CK_c input buffers. VREF (DQ) Supply Reference Voltage for DQ Input Receiver: Reference voltage for all data input buffers. VSS Supply Ground VSSCA Supply Ground for Input Receivers VSSQ Supply I/O Ground: Ground for data input/output buffers ZQ I/O Reference Pin for Output Drive Strength Calibration NOTE : 1) Data includes DQ and DM. - 12 - datasheet K4E6E304ED-EGCG Rev. 1.0 LPDDR3 SDRAM 5.0 FUNCTIONAL DESCRIPTION LPDDR3-SDRAM is a high-speed synchronous DRAM device internally configured as an 8-Bank memory. This device contains the following number of bits: 8Gb has 8,589,934,592 bits LPDDR3 devices use a double data rate architecture on the Command/Address (CA) bus to reduce the number of input pins in the system. The 10-bit CA bus contains command, address, and bank information. Each command uses one clock cycle, during which command information is transferred on both the positive and negative edge of the clock. These devices also use a double data rate architecture on the DQ pins to achieve high speed operation. The double data rate architecture is essentially an 8n prefetch architecture with an interface designed to transfer two data bits per DQ every clock cycle at the I/O pins. A single read or write access for the LPDDR3 SDRAM effectively consists of a single 8n-bit wide, one clock cycle data transfer at the internal DRAM core and eight corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins. Read and write accesses to the LPDDR3 SDRAMs are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an Activate command, which is then followed by a Read or Write command. The address and BA bits registered coincident with the Activate command are used to select the row and the Bank to be accessed. The address bits registered coincident with the Read or Write command are used to select the Bank and the starting column location for the burst access. Prior to normal operation, the LPDDR3 SDRAM must be initialized. The following section provides detailed information covering device initialization, register definition, command description and device operation. 6.0 LPDDR3 SDRAM ADDRESSING [Table 2] LPDDR3 SDRAM Addressing Items 8Gb Number of Banks 8 Bank Addresses BA0-BA2 SAMSUNG 3.9 tREFI(us) 2) ×32 Row Addresses R0-R14 3) C0-C9 Column Addresses 1), 3) NOTE : 1) The least-significant column address C0 is not transmitted on the CA bus, and is implied to be zero. 2) tREFI values for all bank refresh is Tc = -25~85C, Tc means Operating Case Temperature 3) Row and Column Address values on the CA bus that are not used are “don’t care.” - 13 - Rev. 1.0 datasheet K4E6E304ED-EGCG LPDDR3 SDRAM 6.1 Simplified LPDDR3 State Diagram LPDDR3-SDRAM state diagram provides a simplified illustration of allowed state transitions and the related commands to control them. For a complete definition of the device behavior, the information provided by the state diagram should be integrated with the truth tables and timing specification. The truth tables provide complementary information to the state diagram, they clarify the device behavior and the applied restrictions when considering the actual state of all the banks. For the command definition, see datasheet of [Command Definition & Timing Diagram]. Power Applied Resetting MR Reading Automatic Sequence Power On Command Sequence Reset Self Refreshing MRR SREF Resetting PD Resetting Power Down PDX Reset Idle MR Reading MRR SREFX REF Idle1) MRW PDX MR Writing2) ACT Refreshing PD Idle Power Down SAMSUNG Active Power Down Active MR Reading MRR PDX PR, PRA PD Active Writing Reading WRA RDA WRA3) ACT = Activate PR(A) = Precharge (All) Writing WR(A) = Write (with Autoprecharge) with RD(A) = Read (with Autoprecharge) Autoprecharge MRW = Mode Register Write MRR = Mode Register Read Reset = Reset is achieved through MRW command PD = Enter Power Down PDX = Exit Power Down SREF = Enter Self Refresh SREFX = Exit Self Refresh REF = Refresh RD3) RD WR WR3) RDA3) PR, PRA Reading with Autoprecharge Precharging Figure 1. LPDDR3: Simplified Bus Interface State Diagram NOTE : 1) In the Idle state, all banks are precharged. 2) In the case of MRW to enter CA Training mode or Write Leveling Mode, the state machine will not automatically return to the Idle state. In these cases an additional MRW command is required to exit either operating mode and return to the Idle state. See sections “CA Training” or “Write Leveling”. 3) Terminated bursts are not allowed. For these state transitions, the burst operation must be completed before the transition can occur. 4) Use caution with this diagram. It is intended to provide a floorplan of the possible state transitions and commands to control them, not all details. In particular, situations involving more than one bank are not captured in full detail. - 14 - Rev. 1.0 datasheet K4E6E304ED-EGCG LPDDR3 SDRAM 6.2 Mode Register Definition 6.2.1 Mode Register Assignment and Definition in LPDDR3 SDRAM Table 3 shows the mode registers for LPDDR3 SDRAM. Each register is denoted as “R” if it can be read but not written, “W” if it can be written but not read, and “R/W” if it can be read and written. A Mode Register Read command is used to read a mode register. A Mode Register Write command is used to write a mode register. [Table 3] Mode Register Assignment in LPDDR3 SDRAM MR# MA Function Access OP7 OP6 OP5 0 00H Device Info. R (RFU) WL (Set B) (RFU) 1 01H Device Feature 1 W 2 02H Device Feature 2 W 3 03H I/O Config-1 W 4 04H Refresh Rate R 5 05H Basic Config-1 R LPDDR3 Manufacturer ID 6 06H Basic Config-2 R Revision ID1 7 07H Basic Config-3 R Revision ID2 8 08H Basic Config-4 R 9 09H Test Mode W Vendor-Specific Test Mode 10 0AH IO Calibration W Calibration Code 11 0BH 12:15 0CH~0FH 16 10H PASR_Bank W PASR Bank Mask 17 11H PASR_Seg W PASR Segment Mask 18-31 12H-1FH (Reserved) 32 20H DQ Calibration Pattern A 33:39 21H~27H (Do Not Use) 40 28H 41 OP4 WL Select OP2 RZQI (optional) nWR (for AP) WR Lev OP3 (RFU) (RFU) BL nWRE RL & WL (RFU) Refresh Rate Density Type SAMSUNG (RFU) (reserved) DAI DS I/O width ODT Feature PD CTL DQ ODT (RFU) (RFU) R See "DQ Calibration" on Operations & Timing Diagram. DQ Calibration Pattern B R See "DQ Calibration" on Operations & Timing Diagram. 29H CA Training 1 W See "Mode Register Write-CA Training Mode". 42 2AH CA Training 2 W See "Mode Register Write-CA Training Mode". 43:47 2BH~2FH (Do Not Use) 48 30H CA Training 3 W See "Mode Register Write-CA Training Mode". 49:62 31H~3EH (Reserved) 63 3FH Reset 64:255 40H~FFH (Reserved) (RFU) W X (RFU) NOTE : 1) RFU bits shall be set to ‘0’ during Mode Register writes. 2) RFU bits shall be read as ‘0’ during Mode Register reads. 3) All Mode Registers that are specified as RFU or write-only shall return undefined data when read and DQS_t, DQS_c shall be toggled. 4) All Mode Registers that are specified as RFU shall not be written. 5) See vendor device datasheets for details on vendor-specific mode registers. 6) Writes to read-only registers shall have no impact on the functionality of the device. - 15 - OP0 (RFU) (RFU) TUF OP1 Rev. 1.0 datasheet K4E6E304ED-EGCG LPDDR3 SDRAM MR0_Device Information (MA = 00H) : OP7 OP6 OP5 (RFU) WL (Set B) Support (RFU) DAI (Device Auto-Initialization Status) OP4 OP3 OP2 RZQI (Optional) Read-only Read-only OP WL (Set B) Support Read-only OP OP0 (RFU) DAI 0B: DAI complete 1B: DAI still in progress OP RZQI (Built in Self Test for RZQ Information) OP1 00B: RZQ self test not supported 01B: ZQ-pin may connect to VDDCA or float 10B: ZQ-pin may short to GND 11B: ZQ-pin self test completed, no error condition detected (ZQ-pin may not connect to VDDCA or float nor short to GND) 1-4 WL (Set B) Option Support 0B: DRAM does not support WL (Set B) 1B: DRAM supports WL (Set B) NOTE : 1) RZQI, if supported, will be set upon completion of the MRW ZQ Initialization Calibration command. 2) If ZQ is connected to VDDCA to set default calibration, OP[4:3] shall be set to 01. If ZQ is not connected to VDDCA, either OP[4:3] = 01 or OP[4:3] =10 might indicate a ZQpin assembly error. It is recommended that the assembly error is corrected. 3) In the case of possible assembly error (either OP[4:3]=01 or OP[4:3]=10 per Note 4), the LPDDR3 device will default to factory trim settings for RON, and will ignore ZQ calibration commands. In either case, the system may not function as intended. 4) In the case of the ZQ self-test returning a value of 11b, this result indicates that the device has detected a resistor connection to the ZQ pin. However, this result cannot be used to validate the ZQ resistor value or that the ZQ resistor tolerance meets the specified limits (i.e 240-Ω +/- 1%). MR1_Device Feature 1 (MA = 01H) : SAMSUNG OP7 OP6 OP5 OP4 nWR (for AP) BL Write-only OP3 OP2 OP1 (RFU) OP0 BL 011B: BL8 (default) All others: Reserved OP If nWRE (MR2 OP) = 0: 100B: nWR=6 110B: nWR=8 111B: nWR=9 nWR 1) Write-only If nWRE (MR2 OP) = 1: 000B: nWR=10 (default) 001B: nWR=11 010B: nWR=12 100B: nWR=14 110B: nWR=16 All others: Reserved OP NOTE : 1) Programmed value in nWR register is the number of clock cycles which determines when to start internal precharge operation for a write burst with AP enabled. It is determined by RU(tWR/tCK). [Table 4] Burst Sequence C2 C1 C0 0B 0B 0B 0B 1B 0B 1B 0B 0B 1B 1B 0B BL 8 Burst Cycle Number and Burst Address Sequence 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 2 3 4 5 6 7 0 1 4 5 6 7 0 1 2 3 6 7 0 1 2 3 4 5 NOTE : 1) C0 input is not present on CA bus. It is implied zero. 2) The burst address represents C2 - C0. - 16 - datasheet K4E6E304ED-EGCG Rev. 1.0 LPDDR3 SDRAM MR2_Device Feature 2 (MA = 02H): OP7 OP6 OP5 OP4 WR Lev WL Select (RFU) nWRE OP3 OP2 OP1 OP0 RL & WL If OP =0 (WL Set A, default) 0100B: RL = 6 / WL = 3 (≤ 400 MHz) 0110B: RL = 8 / WL = 4 (≤ 533 MHz) 0111B: RL = 9 / WL = 5 (≤ 600 MHz) 1000B: RL = 10 / WL = 6 (≤ 667 MHz, default) 1001B: RL = 11 / WL = 6 (≤ 733 MHz) 1010B: RL = 12 / WL = 6 (≤ 800 MHz) 1100B: RL = 14 / WL = 8 (≤ 933 MHz) 1110B: RL = 16 / WL = 8 (≤ 1066MHz) All others: Reserved RL & WL Write-only OP If OP =1 (WL Set B, optional2)) 0100B: RL = 6 / WL = 3 (≤ 400 MHz) 0110B: RL = 8 / WL = 4 (≤ 533 MHz) 0111B: RL = 9 / WL = 5 (≤ 600 MHz) 1000B: RL = 10 / WL = 8 (≤ 667 MHz, default) 1001B: RL = 11 / WL = 9 (≤ 733 MHz) 1010B: RL = 12 / WL = 9 (≤ 800 MHz) 1100B: RL = 14 / WL = 11 (≤ 933 MHz) SAMSUNG 1110B: RL = 16 / WL = 13 (≤ 1066MHz) All others: reserved nWRE Write-only OP WL Select Write-only OP WR Leveling Write-only OP 0B: Enable nWR programming ≤ 9 1B: Enable nWR programming > 9 (default) 0B: Select WL Set A (default) 1B: Select WL Set B (optional2)) 0B: Disable (default) 1B: Enable NOTE : 1) See MR0, OP 2) See MR0, OP MR3_I/O Configuration 1 (MA = 03H): OP7 OP6 OP5 OP4 OP3 (RFU) DS Write-only OP OP2 OP1 OP0 DS 0001B: 34.3-Ω typical pull-down/pull-up 0010B: 40-Ω typical pull-down/pull-up (default) 0011B: 48-Ω typical pull-down/pull-up 0100B: Reserved for 60Ω typical pull-down/pull-up 0110B: Reserved for 80Ω typical pull-down/pull-up 1001B: 34.3Ω typical pull-down, 40Ω typical pull-up 1010B: 40Ω typical pull-down, 48Ω typical pull-up 1011B: 34.3Ω typical pull-down, 48Ω typical pull-up All others: Reserved - 17 - datasheet K4E6E304ED-EGCG Rev. 1.0 LPDDR3 SDRAM MR4_Device Temperature (MA = 04H) OP7 OP6 OP5 TUF OP4 OP3 (RFU) SDRAM Refresh Rate Read-only OP Temperature Update Flag (TUF) Read-only OP OP2 OP1 OP0 SDRAM Refresh Rate 000B: SDRAM Low temperature operating limit exceeded 001B: 4× tREFI, 4× tREFIpb, 4× tREFW 010B: 2× tREFI, 2× tREFIpb, 2× tREFW 011B: 1× tREFI, 1× tREFIpb, 1× tREFW (