K4F640412D

K4F660412D,K4F640412D 16M x 4bit CMOS Dynamic RAM with Fast Page Mode DESCRIPTION CMOS DRAM This is a family of 16,777,216 x 4 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -50 or -60), power consumption(Normal or Low power) are optional features of this family. All of this family have CAS -before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 16Mx4 Fast Page Mode DRAM family is fabricated using Samsung ′s advanced CMOS process to realize high band-width, low power consumption and high reliability. FEATURES • Part Identification - K4F660412D-JC/L(3.3V, 8K Ref., SOJ) - K4F640412D-JC/L(3.3V, 4K Ref., SOJ) - K4F660412D-TC/L(3.3V, 8K Ref., TSOP) - K4F640412D-TC/L(3.3V, 4K Ref., TSOP) • Fast Page Mode operation • CAS -before-RAS refresh capability • RAS -only and Hidden refresh capability • Self-refresh capability (L-ver only) • Fast parallel test mode capability • LVTTL(3.3V) compatible inputs and outputs • Active Power Dissipation Unit : mW Speed -45 -50 -60 • Refresh Cycles Part NO. K4F660412D* K4F640412D Refresh cycle 8K 4K Refresh time Normal 64ms L-ver 128ms RAS CAS W Control Clocks Vcc Vss • Early Write or output enable controlled write • JEDEC Standard pinout • Available in Plastic SOJ and TSOP(II) packages • +3.3V±0.3V power supply 4K 432 396 360 8K 324 288 252 FUNCTIONAL BLOCK DIAGRAM VBB Generator Refresh Control Refresh Counter Memory Array 16,777,216 x 4 Cells Sense Amps & I/O * Access mode & RAS only refresh mode : 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.) CAS-before-RAS & Hidden refresh mode : 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.) • Performance Range Speed -45 -50 -60 Refresh Timer Row Decoder Data in Buffer DQ0 to DQ3 Data out Buffer OE tRAC 45ns 50ns 60ns tCAC 12ns 13ns 15ns tRC 80ns 90ns 110ns tPC 31ns 35ns 40ns A0~A12 (A0~A11)*1 A0~A10 (A0~A11)*1 Row Address Buffer Col. Address Buffer Column Decoder Note) *1 : 4K Refresh SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. K4F660412D,K4F640412D CMOS DRAM PIN CONFIGURATION (Top Views) • K4F660412D-J • K4F640412D-J VCC DQ0 DQ1 N.C N.C N.C N.C W RAS A0 A1 A2 A3 A4 A5 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VSS DQ3 DQ2 N.C N.C N.C CAS OE A12(N.C)* A11 A10 A9 A8 A7 A6 VSS VCC DQ0 DQ1 N.C N.C N.C N.C W RAS A0 A1 A2 A3 A4 A5 VCC • K4F660412D-T • K4F640412D-T 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VSS DQ3 DQ2 N.C N.C N.C CAS OE A12(N.C)* A11 A10 A9 A8 A7 A6 VSS (J : 400mil SOJ) (T : 400mil TSOP(II)) * (N.C) : N.C for 4K Refresh product Pin Name A0 - A12 A0 - A11 DQ0 - 3 VSS RAS CAS W OE VCC N.C Pin Function Address Inputs(8K Product) Address Inputs(4K Product) Data In/Out Ground Row Address Strobe Column Address Strobe Read/Write Input Data Output Enable Power(+3.3V) No Connection K4F660412D,K4F640412D ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to VSS Voltage on V CC supply relative to VSS Storage Temperature Power Dissipation Short Circuit Output Current Symbol VIN,VOUT VCC Tstg PD IOS Address Rating -0.5 to +4.6 -0.5 to +4.6 -55 to +150 1 50 CMOS DRAM Units V V °C W mA * Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA= 0 to 70°C) Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min 3.0 0 2.0 -0.3 *2 Typ 3.3 0 Max 3.6 0 Vcc+0.3*1 0.8 Units V V V V *1 : Vcc+1.3V at pulse width≤15ns which is measured at VCC *2 : -1.3 at pulse width≤15ns which is measured at V SS DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.) Parameter Input Leakage Current (Any input 0≤VIN≤VCC+0.3V, all other pins not under test=0 Volt) Output Leakage Current (Data out is disabled, 0V≤VOUT ≤VCC) Output High Voltage Level(IOH =-2mA) Output Low Voltage Level(I OL=2mA) Symbol II(L) IO(L) VOH VOL Min -5 -5 2.4 Max 5 5 0.4 Units uA uA V V K4F660412D,K4F640412D DC AND OPERATING CHARACTERISTICS (Continued) Symbol Power Speed K4F660412D ICC1 Don′t care Normal L Don′t care -45 -50 -60 Don′t care -45 -50 -60 -45 -50 -60 Don′t care -45 -50 -60 Don′t care Don′t care 90 80 70 1 1 90 80 70 70 60 50 0.5 200 120 110 100 350 350 Max K4F640412D 120 110 100 1 1 120 110 100 70 60 50 0.5 200 120 110 100 350 350 CMOS DRAM Units mA mA mA mA mA mA mA mA mA mA mA mA uA mA mA mA uA uA ICC2 ICC3 ICC4 Don′t care Normal L Don′t care L L ICC5 ICC6 ICC7 ICCS ICC1* : Operating Current (RAS and CAS, Address cycling @tRC=min.) ICC2 : Standby Current (RAS=CAS =W=VIH ) ICC3* : RAS-only Refresh Current (CAS=V IH, RAS, Address cycling @tRC=min.) ICC4* : Fast Page Mode Current (RAS=VIL, CAS, Address cycling @ tPC=min.) ICC5 : Standby Current (RAS=CAS =W=VCC-0.2V) ICC6* : CAS-Before-RAS Refresh Current (RAS and CAS cycling @ tRC=min) ICC7 : Battery back-up current, Average power supply current, Battery back-up mode Input high voltage(VIH)=V CC-0.2V, Input low voltage(VIL)=0.2V, CAS =CAS -before-RAS cycling or 0.2V, W, OE =VIH , Address=Don′t care, DQ=Open, TRC=31.25us ICCS : Self Refresh Current RAS =CAS=0.2V, W=OE=A0 ~ A12(A11)=VCC-0.2V or 0.2V, DQ0 ~ DQ3=VCC-0.2V, 0.2V or Open *Note : ICC1 , ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In I CC1, ICC3 and ICC6, address can be changed maximum once while RAS=V IL. In I CC4, address can be changed maximum once within one fast page mode cycle time, tPC. K4F660412D,K4F640412D CAPACITANCE (TA=25°C, VCC=3.3V, f=1MHz) Parameter Input capacitance [A0 ~ A12] Input capacitance [RAS, CAS , W, OE ] Output capacitance [DQ0 - DQ3] Symbol CIN1 CIN2 C DQ Min - CMOS DRAM Max 5 7 7 Units pF pF pF AC CHARACTERISTICS (0°C≤TA≤70°C, See note 2) Parameter Random read or write cycle time Read-modify-write cycle time Access time from RAS Access time from CAS Access time from column address CAS to output in Low-Z Output buffer turn-off delay Transition time (rise and fall) RAS precharge time RAS pulse width RAS hold time CAS hold time CAS pulse width RAS to CAS delay time RAS to column address delay time CAS to RAS precharge time Row address set-up time Row address hold time Column address set-up time Column address hold time Column address to RAS lead time Read command set-up time Read command hold time referenced to CAS Read command hold time referenced to RAS Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data set-up time Data hold time Symbol Test condition : VCC=3.3V±0.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V -45 Min Max Min 90 133 45 12 23 0 0 1 25 45 12 45 12 18 13 5 0 8 0 8 23 0 0 0 8 8 13 12 0 10 10K 33 22 10K 13 50 0 0 1 30 50 13 50 13 20 15 5 0 10 0 10 25 0 0 0 10 10 15 13 0 10 10K 37 25 10K 13 50 50 13 25 0 0 1 40 60 15 60 15 20 15 5 0 10 0 10 30 0 0 0 10 10 15 15 0 10 10K 45 30 10K 13 50 -50 Max Min 110 153 60 15 30 -60 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 9 9 8 8 4 10 3,4,10 3,4,5 3,10 3 6 2 Units Note tRC tRWC tRAC tCAC tAA tCLZ tOFF tT tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCH tWP tRWL tCWL tDS tDH 80 115 K4F660412D,K4F640412D AC CHARACTERISTICS (Continued) Parameter Refresh period (Normal) Refresh period (L-ver) Write command set-up time CAS to W delay time RAS to W delay time Column address to W delay time CAS precharge W delay time CAS set-up time (CAS -before-RAS refresh) CAS hold time (CAS -before-RAS refresh) RAS to CAS precharge time Access time from CAS precharge Fast Page mode cycle time Fast Page mode read-modify-write cycle time CAS precharge time (Fast page cycle) RAS pulse width (Fast page cycle) RAS hold time from CAS precharge OE access time OE to data delay Output buffer turn off delay time from OE OE command hold time Write command set-up time (Test mode in) Write command hold time (Test mode in) W to RAS precharge time (C-B-R refresh) W to RAS hold time (C-B-R refresh) RAS pulse width (C-B-R self refresh) RAS precharge time (C-B-R self refresh) CAS hold time (C-B-R self refresh) Symbol Min -45 Max 64 128 0 32 67 43 48 5 10 5 26 31 70 9 45 28 12 12 0 12 10 15 10 10 100 80 -50 13 13 0 13 10 15 10 10 100 90 -50 13 200K 35 76 10 50 30 13 13 0 15 10 15 10 10 100 110 -50 200K 0 36 73 48 53 5 10 5 30 40 85 10 60 35 Min -50 Max 64 128 0 38 83 53 60 5 10 5 Min -60 CMOS DRAM Units Max 64 128 ms ms ns ns ns ns ns ns ns ns 35 ns ns ns ns Note tREF tREF tWCS tCWD tRWD tAWD tCPWD tCSR tCHR tRPC tCPA tPC tPRWC tCP tRASP tRHCP tOEA tOED tOEZ tOEH tWTS tWTH tWRP tWRH tRASS tRPS tCHS 7 7 7 7 3 200K ns ns 15 ns ns 3 13 ns ns ns ns ns ns us ns ns 6 11 11 13,14,15 13,14,15 13,14,15 K4F660412D,K4F640412D TEST MODE CYCLE Parameter Random read or write cycle time Read-modify-write cycle time Access time from RAS Access time from CAS Access time from column address RAS pulse width CAS pulse width RAS hold time CAS hold time Column Address to RAS lead time CAS to W delay time RAS to W delay time Column Address to W delay time Fast Page mode cycle time Fast Page mode read-modify-write cycle time RAS pulse width (Fast Page cycle) Access time from CAS precharge OE access time OE to data delay OE command hold time Symbol Min -45 Max Min 95 138 50 17 28 50 17 17 50 28 37 72 48 36 75 50 200K 31 17 17 17 18 18 10K 10K 55 18 18 55 30 41 78 53 40 81 55 200K 35 18 18 20 55 18 30 10K 10K 65 20 20 65 35 43 88 58 45 90 65 -50 Max Min 115 160 65 20 35 -60 CMOS DRAM ( Note 11 ) Units Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 200K 40 20 ns ns ns ns ns 3 3 7 7 7 3,4,10,12 3,4,5,12 3,10,12 Note tRC tRWC tRAC tCAC tAA tRAS tCAS tRSH tCSH tRAL tCWD tRWD tAWD tPC tPRWC tRASP tCPA tOEA tOED tOEH 85 120 10K 10K K4F660412D,K4F640412D NOTES CMOS DRAM 1. An initial pause of 200us is required after power-up followed by any 8 ROR or CBR cycles before proper device operation is achieved. 2. VIH(min) and V IL(max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and V IL(max) and are assumed to be 5ns for all inputs. 3. Measured with a load equivalent to 1 TTL load and 100pF. 4. Operation within the tRCD(max) limit insures that tRAC (max) can be met. tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. 5. Assumes that tRCD≥tRCD(max). 6. tOFF(min)and tOEZ(max) define the time at which the output achieves the open circuit condition and are not referenced V oh or Vol. 7. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameters. They are included in the data sheet as electric characteristics only. If tWCS≥tWCS(min), the cycles is an early write cycle and the data output will remain high impedance for the duration of the cycle. If tCWD≥tCWD(min), tRWD≥tRWD(min) and tAWD ≥tAWD(min), then the cycle is a read-modify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the condition of the data out is indeterminate. 8. Either tRCH or tRRH must be satisfied for a read cycle. 9. These parameters are referenced to the CAS falling edge in early write cycles and to the W falling edge in read-modify-write cycles. 10. Operation within the tRAD (max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only. If tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA. 11. These specifications are applied in the test mode. 12. In test mode read cycle, the value of tRAC , tAA, tCAC is delayed by 2ns to 5ns for the specified values. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. 13. If tRASS≥100us, then RAS precharge time must use tRPS instead of tRP. 14. For RAS-only-Refresh and Burst CAS -before-RAS refresh, 4096 cycles(4K/8K) of burst refresh must be executed within 64ms before and after self refresh, in order to meet refresh specification. 15. For distributed CAS -before-RAS with 15.6us interval, CBR refresh should be executed with in 15.6us immediately before and after self refresh in order to meet refresh specification. K4F660412D,K4F640412D READ CYCLE CMOS DRAM tRC tRAS RAS VIH VIL - tRP tCSH tCRP CAS VIH VIL - tRCD tRSH tCAS tRAL tCAH COLUMN ADDRESS tCRP tRAD tASR A VIH VIL - tRAH tASC ROW ADDRESS tRCS W VIH VIL - tRCH tRRH tOFF tAA tOEZ tOEA tCAC OE VIH VIL - DQ0 ~ DQ3(7) VOH VOL - tRAC OPEN tCLZ DATA-OUT Don′t care Undefined K4F660412D,K4F640412D WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN CMOS DRAM tRAS RAS VIH VIL - tRC tRP tCSH tCRP CAS VIH VIL - tRCD tRSH tCAS tRAL tCAH COLUMN ADDRESS tCRP tRAD tASR A VIH VIL - tRAH tASC ROW ADDRESS tCWL tRWL tWCS W VIH VIL - tWCH tWP OE VIH VIL - DQ0 ~ DQ3(7) VIH VIL - tDS tDH DATA-IN Don′t care Undefined K4F660412D,K4F640412D WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : DOUT = OPEN CMOS DRAM tRAS RAS VIH VIL - tRC tRP tCSH tCRP CAS VIH VIL - tRCD tRSH tCAS tRAL tCAH COLUMN ADDRESS tCRP tRAD tASR tRAH tASC A VIH VIL - ROW ADDRESS tCWL tRWL W VIH VIL - tWP OE VIH VIL - tOED tDS tOEH tDH DATA-IN DQ0 ~ DQ3(7) VIH VIL - Don′t care Undefined K4F660412D,K4F640412D READ - MODIFY - WRTIE CYCLE CMOS DRAM tRWC tRAS RAS VIH VIL - tRP tCRP CAS VIH VIL - tRCD tRAD tRAH tRSH tCAS tCAH tCSH tASR VIH VIL - tASC COLUMN ADDRESS A ROW ADDR tAWD tCWD W VIH VIL - tRWL tCWL tWP OE VIH VIL - tRWD tOEA tCLZ tCAC tAA tRAC VALID DATA-OUT tOED tOEZ tDS tDH VALID DATA-IN DQ0 ~ DQ3(7) VI/OH VI/OL - Don′t care Undefined K4F660412D,K4F640412D FAST PAGE READ CYCLE CMOS DRAM tRASP RAS VIH VIL ¡ó tRP tRHCP tCRP CAS VIH VIL - tPC tRCD tCAS tRAD tASC tCSH tCAH COLUMN ADDRESS tCP tCAS ¡ó tCP tRSH tCAS tASR A VIH VIL ROW ADDR tRAH tASC tCAH ¡ó ¡ó tASC tCAH COLUMN ADDRESS COLUMN ADDRESS tRCS W VIH VIL - tRCH tRCS ¡ó tRAL tRCS tRRH tRCH tCAC tOEA OE VIH VIL - tCAC tOEA ¡ó ¡ó tCAC tOEA tAA DQ0 ~ DQ3(7) VOH VOL - tAA tOEZ VALID DATA-OUT tRAC tCLZ tOFF tCLZ tOEZ VALID DATA-OUT tAA tOFF tCLZ VALID DATA-OUT tOFF tOEZ Don′t care Undefined K4F660412D,K4F640412D FAST PAGE WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN CMOS DRAM tRASP RAS VIH VIL ¡ó tRP tRHCP tCRP CAS VIH VIL - tPC tRCD tCAS tRAD tASC tCP tPC tCP tCAS ¡ó tRSH tCAS tRAL tASR A VIH VIL - tRAH tCSH tCAH COLUMN ADDRESS tASC tCAH ¡ó ¡ó tASC tCAH ROW ADDR COLUMN ADDRESS COLUMN ADDRESS tWCS W VIH VIL - tWCH tWP tCWL tWCS tWP tWCH ¡ó tWCS tWCH tWP tCWL tRWL tCWL ¡ó ¡ó OE VIH VIL - DQ0 ~ DQ3(7) VIH VIL - tDS tDH tDS tDH ¡ó tDS tDH VALID DATA-IN VALID DATA-IN VALID DATA-IN ¡ó Don′t care Undefined K4F660412D,K4F640412D FAST PAGE READ - MODIFY - WRITE CYCLE CMOS DRAM tRASP RAS VIH VIL - tRP tCSH tRCD tRSH tCP tCAS tRAD tRAH tASR tASC COL. ADDR tCRP tCAS tPRWC CAS VIH VIL - tCAH tRAL tASC COL. ADDR tCAH A VIH VIL - ROW ADDR tRCS W VIH VIL - tRWL tCWL tWP tCWD tAWD tRWD tOEA tOED tCAC tAA tOEZ tDH tDS tCWD tAWD tCPWD tOEA tCAC tAA tOEZ tOED tDH tDS tCWL tWP OE VIH VIL - DQ0 ~ DQ3(7) VI/OH VI/OL - tRAC tCLZ tCLZ VALID DATA-OUT VALID DATA-IN VALID DATA-OUT VALID DATA-IN Don′t care Undefined K4F660412D,K4F640412D RAS - ONLY REFRESH CYCLE NOTE : W, OE , DIN = Don′t care DOUT = OPEN tRC CMOS DRAM tRAS RAS VIH VIL - tRP tCRP CAS VIH VIL - tRPC tCRP tASR A VIH VIL ROW ADDR tRAH CAS - BEFORE - RAS REFRESH CYCLE NOTE : OE, A = Don′t care tRC tRP RAS VIH VIL - tRAS tRP tRPC tCP tRPC tCSR tWRP tWRH tCHR CAS VIH VIL - W VIH VIL - DQ0 ~ DQ3(7) VOH VOL - tOFF OPEN Don′t care Undefined K4F660412D,K4F640412D HIDDEN REFRESH CYCLE ( READ ) CMOS DRAM tRC tRAS RAS VIH VIL - tRC tRP tRAS tRP tCRP CAS VIH VIL - tRCD tRSH tCHR tRAD tASR A VIH VIL - tRAH tASC tCAH COLUMN ADDRESS ROW ADDRESS tRAL tRCS W VIH VIL - tWRH tAA OE VIH VIL - tOEA tCAC tOFF tOEZ DATA-OUT DQ0 ~ DQ3(7) VOH VOL - tRAC OPEN tCLZ Don′t care Undefined K4F660412D,K4F640412D HIDDEN REFRESH CYCLE ( WRITE ) NOTE : DOUT = OPEN CMOS DRAM tRC RAS VIH VIL - tRC tRP tRAS tRP tRAS tCRP CAS VIH VIL - tRCD tRAD tRSH tCHR tASR A VIH VIL - tRAH tASC tCAH COLUMN ADDRESS ROW ADDRESS tRAL VIH VIL - tWRH tWRP tWCS tWP tWCH W OE VIH VIL - tDS DQ0 ~ DQ3(7) VIH VIL - tDH DATA-IN Don′t care Undefined K4F660412D,K4F640412D CAS - BEFORE - RAS SELF REFRESH CYCLE NOTE : OE , A = Don′t care CMOS DRAM tRP RAS VIH VIL - tRASS tRPS tRPC tCHS tRPC tCP CAS VIH VIL - tCSR DQ0 ~ DQ3(7) VOH VOL - tOFF OPEN tWRP tWRH W VIH VIL - TEST MODE IN CYCLE NOTE : OE, A = Don′t care tRC tRP RAS VIH VIL - tRAS tRP tRPC tCP tRPC tCSR tWTS tWTH tCHR CAS VIH VIL - W VIH VIL - DQ0 ~ DQ3(7) VOH VOL - tOFF OPEN Don′t care Undefined K4F660412D,K4F640412D PACKAGE DIMENSION 32 SOJ 400mil CMOS DRAM Units : Inches (millimeters) #32 0.435 (11.06) 0.445 (11.30) 0.400 (10.16) 0.360 (9.15) 0.380 (9.65) 0.010 (0.25) TYP 0.018 (0.45) 0.030 (0.75) 0~8 O 0.006 (0.15) 0.012 (0.30) #1 0.027 (0.69) MIN 0.841 (21.36) MAX 0.820 (20.84) 0.830 (21.08) 0.148 (3.76) MAX 0.026 (0.66) 0.032 (0.81) 0.015 (0.38) 0.021 (0.53) 0.0375 (0.95) 0.050 (1.27) 32 TSOP(II) 400mil Units : Inches (millimeters) 0.455 (11.56) 0.471 (11.96) 0.400 (10.16) 0.004 (0.10) 0.010 (0.25) 0.841 (21.35) MAX 0.821 (20.85) 0.829 (21.05) 0.047 (1.20) MAX 0.037 (0.95) 0.050 (1.27) 0.002 (0.05) MIN 0.012 (0.30) 0.020 (0.50)