K4F6E3S4HM-MGCJ

Rev. 1.0, Jan. 2018 K4F6E3S4HM 16Gb LPDDR4 SDRAM 200FBGA, 10x15 64Mb x16DQ x8banks x2channels This document and all information provided herein (collectively, "Information") is provided on an "AS-IS" basis and remains the sole and exclusive property of Samsung Electronics. You must keep all Information in strict confidence and trust, and must not, directly or indirectly, in any way, disclose, make accessible, post on the internet, reveal, report, publish, disseminate or transfer any Information to any third party. You must not reproduce or copy Information, without first obtaining express written permis sion from Samsung Electronics. You must not use, or allow use of, any Information in any manner whatsoever, except to inter nally evaluate the Information. You must restrict access to Information to those of your employees who have a bonafide need -to-know for such purpose and are bound by obligations at least as restrictive as this clause. In order to receive Information, you must agree to the foregoing and to indemnify Samsung for any failure to strictly comply therewith. If you do not agree, please do not accept any receipt of Information. SAMSUNG vincent.chen@to-top.com.hk datasheet SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE. Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind. This document and all information discussed herein remain the sole and exclusive property of Samsung Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or otherwise. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. For updates or additional information about Samsung products, contact your nearest Samsung office. All brand names, trademarks and registered trademarks belong to their respective owners. © 2018 Samsung Electronics Co., Ltd.GG All rights reserved. -1- datasheet K4F6E3S4HM-MGCJ Rev. 1.0 LPDDR4 SDRAM Revision History Revision No. History Draft Date Remark Editor 0.0 - First version for target specification. 26th Jul, 2016 Target J.Y.Bae 0.5 - Preliminary datasheet. 27th Sep, 2017 Preliminary J.Y.Bae - Update JEDEC JESD209-4B. - Remove 4266Mbps. - Correct ball name from ZQ_a to ZQ. - Update Mode Register Definition. 1. MR0 OP[5] : PPR -> RFU 2. Add MR7 OP[0] for Single ended mode 3. Add MR51 for Single Ended RDQS, WDQS, Clock. 0.6 - Update IDD spec values. 1st Nov, 2017 Preliminary J.Y.Bae 1.0 - Final datasheet. 2nd Jan, 2018 Final J.Y.Bae SAMSUNG vincent.chen@to-top.com.hk -2- K4F6E3S4HM-MGCJ datasheet Rev. 1.0 LPDDR4 SDRAM Table Of Contents 16Gb LPDDR4 SDRAM 1.0 COMPARISION BETWEEN LPDDR3 AND LPDDR4 ....................................................................................................................... 5 2.0 KEY FEATURE.................................................................................................................................................................................. 7 3.0 ORDERING INFORMATION ............................................................................................................................................................. 8 4.0 PACKAGE DIMENSION & PIN DESCRIPTION ................................................................................................................................ 9 4.1 LPDDR4 SDRAM Package Dimension...........................................................................................................................................9 4.2 LPDDR4 SDRAM Package Ballout.................................................................................................................................................10 4.3 PAD Definition And Description ......................................................................................................................................................11 4.4 Functional Block Diagram...............................................................................................................................................................11 4.5 LPDDR4 Pad Definition and Description ........................................................................................................................................12 4.5.1 Dual channel per die device.....................................................................................................................................................12 5.0 FUNCTIONAL DESCRIPTION .......................................................................................................................................................... 13 5.1 LPDDR4 SDRAM Addressing.........................................................................................................................................................13 5.2 Simplified LPDDR4 State Diagram .................................................................................................................................................14 5.3 Mode Register Definition ...............................................................................................................................................................16 5.3.1 Mode Register Assignment and Definition in LPDDR4 SDRAM.............................................................................................16 6.0 TRUTH TABLES................................................................................................................................................................................ 36 6.1 CKE Truth Tables ...........................................................................................................................................................................38 6.2 State Truth Table ............................................................................................................................................................................39 7.0 ABSOLUTE MAXIMUM DC RATINGS .............................................................................................................................................. 41 8.0 AC & DC OPERATING CONDITIONS .............................................................................................................................................. 42 8.1 Recommended DC Operating Conditions ......................................................................................................................................42 8.2 Input Leakage Current ....................................................................................................................................................................42 8.3 Input/Output Leakage Current ........................................................................................................................................................42 8.4 Operating Temperature Range.......................................................................................................................................................42 9.0 AC AND DC INPUT/OUTPUT MEASUREMENT LEVELS................................................................................................................ 43 9.1 1.1V High speed LVCMOS (HS_LLVCMOS) .................................................................................................................................43 9.1.1 Standard specifications............................................................................................................................................................43 9.1.2 DC electrical characteristics.....................................................................................................................................................43 9.1.2.1 LPDDR4 Input Level for CKE............................................................................................................................................43 9.1.2.2 LPDDR4 Input Level for Reset_n and ODT_CA ...............................................................................................................43 9.1.3 AC Over/Undershoot................................................................................................................................................................44 9.1.3.1 LPDDR4 AC Over/Undershoot..........................................................................................................................................44 9.2 Differential Input Voltage ................................................................................................................................................................45 9.2.1 Differential Input Voltage for CK ..............................................................................................................................................45 9.2.2 Peak voltage calculation method .............................................................................................................................................46 9.2.3 Single-Ended Input Voltage for Clock ......................................................................................................................................47 9.2.4 Differential Input Slew Rate Definition for Clock ......................................................................................................................48 9.2.5 Differential Input Cross Point Voltage for Clock.......................................................................................................................49 9.2.6 Differential Input Voltage for DQS............................................................................................................................................50 9.2.7 Peak voltage calculation method .............................................................................................................................................51 9.2.8 Single-Ended Input Voltage for DQS .......................................................................................................................................52 9.2.9 Differential Input Slew Rate Definition for DQS .......................................................................................................................53 9.3 Differential Input Cross Point Voltage for DQS...............................................................................................................................54 9.4 Input Level For ODT(ca) Input ........................................................................................................................................................55 9.5 Single Ended Output Slew Rate .....................................................................................................................................................55 9.6 Differential Output Slew Rate .........................................................................................................................................................56 9.7 Overshoot and Undershoot for LVSTL ...........................................................................................................................................57 9.8 LPDDR4 Driver Output Timing Reference Load.............................................................................................................................58 9.9 LVSTL (Low Voltage Swing Terminated Logic) IO System ............................................................................................................59 SAMSUNG vincent.chen@to-top.com.hk 10.0 INPUT/OUTPUT CAPACITANCE ................................................................................................................................................... 61 11.0 IDD SPECIFICATION PARAMETERS AND TEST CONDITIONS.................................................................................................. 62 11.1 IDD Measurement Conditions.......................................................................................................................................................62 11.2 IDD Specifications ........................................................................................................................................................................78 11.3 IDD Spec Table ............................................................................................................................................................................81 12.0 AC AND DC OUTPUT MEASUREMENT LEVELS ......................................................................................................................... 83 12.1 Single Ended AC and DC Output Levels ......................................................................................................................................83 12.2 Pull Up/Pull Down Driver Characteristics and Calibration ............................................................................................................84 13.0 ELECTRICAL CHARACTERISTICS AND AC TIMING ................................................................................................................... 85 13.1 Clock Specification .......................................................................................................................................................................85 13.1.1 Definition for tCK(avg) and nCK.............................................................................................................................................85 13.1.2 Definition for tCK(abs)............................................................................................................................................................85 13.1.3 Definition for tCH(avg) and tCL(avg)......................................................................................................................................85 -3- K4F6E3S4HM-MGCJ datasheet Rev. 1.0 LPDDR4 SDRAM 13.1.4 Definition for tCH(abs) and tCL(abs)......................................................................................................................................85 13.1.5 Definition for tJIT(per) ............................................................................................................................................................85 13.1.6 Definition for tJIT(cc)..............................................................................................................................................................86 13.1.7 Definition for tERR(nper)........................................................................................................................................................86 13.1.8 Definition for duty cycle jitter tJIT(duty)..................................................................................................................................86 13.1.9 Definition for tCK(abs), tCH(abs) and tCL(abs) .....................................................................................................................86 13.2 Period Clock Jitter.........................................................................................................................................................................87 13.2.1 Clock period jitter effects on core timing parameters.............................................................................................................87 13.2.1.1 Cycle time de-rating for core timing parameters ............................................................................................................87 13.2.1.2 Clock Cycle de-rating for core timing parameters ..........................................................................................................87 13.2.2 Clock jitter effects on Command/Address timing parameters ................................................................................................87 13.2.3 Clock jitter effects on Read timing parameters ......................................................................................................................88 13.2.3.1 tRPRE ............................................................................................................................................................................88 13.2.3.2 tLZ(DQ), tHZ(DQ), tDQSCK, tLZ(DQS), tHZ(DQS) .......................................................................................................88 13.2.3.3 tQSH, tQSL ....................................................................................................................................................................88 13.2.3.4 tRPST.............................................................................................................................................................................88 13.2.4 Clock jitter effects on Write timing parameters ......................................................................................................................88 13.2.4.1 tDS, tDH .........................................................................................................................................................................88 13.2.4.2 tDSS, tDSH ....................................................................................................................................................................88 13.2.4.3 tDQSS ............................................................................................................................................................................89 13.3 LPDDR4 Refresh Requirement ....................................................................................................................................................89 13.4 AC Timing .....................................................................................................................................................................................90 13.5 CA Rx Voltage and Timing ...........................................................................................................................................................95 13.6 DRAM Data Timing.......................................................................................................................................................................98 13.7 DQ Rx Voltage And Timing...........................................................................................................................................................101 SAMSUNG vincent.chen@to-top.com.hk -4- Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM 1.0 COMPARISION BETWEEN LPDDR3 AND LPDDR4 Feature Items LPDDR3 LPDDR4 CLK scheme Differential (CLK/CLKB) ˥ Data scheme DDR Single-ended, Bi-Directional ˥ DQS scheme Differential (DQS/DQSB), Bi-Directional ˥ ADD / CMD scheme DDR SDR State Diagram Refer to the Datasheet Refer to the Datasheet Command Truth Table No support BST Refer to the Datasheet Data mask Truth Table As is ˥ I/O Interface HSUL_12 LVSTL_11 Burst Length 8 16, 32(OTF) Burst Type Sequential ˥ No Wrap No support ˥ 8 ˥ # of Bank per channel Organization per channel x16/x32 x16 Data Mask Support (Write) Support (Masked Write) Refresh mode Auto / Self Refresh ˥ Masked Write N/A Support DBI N/A Support Row Addressing Refer to the Datasheet (CA0 ~ CA9 1clock DDR based) Refer to the datasheet (8Gb per channel) (CA0 ~ CA5 4clock SDR based) 1600/1866 3200/3733/4266 SAMSUNG Column Bank Refresh Requirements Speed bin [Mbps] vincent.chen@to-top.com.hk Read/Write latency AC Parameter Core Parameters IO Parameters Refer to the Datasheet Refer to the datasheet Support ˥ CA / CS / Setup / Hold / Deratin Data Setup / Hold / Deratin PASR Special Function TCSR Support ˥ Deep Power Down No Support N/A Configurable D/S Support ˥ ZQ Calibration Support ˥ 1) DQ Calibration Power Supply Support Refer to the datasheet CA Calibration Support ˥ Write Leveling Support ˥ VDD1 [V] 1.70 ~ 1.95 ˥ VDD2 [V] 1.14 ~ 1.30 1.06 ~ 1.17 VDDQ [V] 1.14 ~ 1.30 1.06 ~ 1.17 VDDCA [V] 1.14 ~ 1.30 N/A IDD Specification Parameters and Test Conditions IDD Measurement Conditions As is BL16 based IDD Specification As is Refer to the datasheet Temperature General [’C] -25 ~ 85 ˥ -5- datasheet K4F6E3S4HM-MGCJ Rev. 1.0 LPDDR4 SDRAM Items LPDDR3 LPDDR4 w/ ZQ Calibration As is ˥ w/o ZQ Calibration As is ˥ w/ VOH Calibration N/A Support w/o VOH Calibration N/A Support Temperature and Voltage Sensitivity As is ˥ RZQI-V Curve As is ˥ Refer to the Datasheet Refer to the Datasheet VDD1 [V] -0.4 ~ 2.3 -0.4 ~ 2.1 VDD2 [V] -0.4 ~ 1.6 -0.4 ~ 1.5 VDDQ [V] -0.4 ~ 1.6 -0.4 ~ 1.5 VDDCA [V] -0.4 ~ 1.6 N/A VIN/VOUT [V] -0.4 ~ 1.6 -0.4 ~ 1.5 Tstg [’C] -55 ~ 125 ˥ Input leakage [uA] As is -2 ~ 2 CA and CS pins AC : VREF ± 0.150V / ± 0.135V (1600/1866) DC : VREF ± 0.10V/0.10V (1600/1866) VREF(CA), Internal VREF 0.65×VDDCA ~ 0.35×VDDCA AC : 0.75×VDD2 @ Min VDD2+0.2 @ Max DC : 0.65×VDD2 @ Min VDD2+0.2 @ Max DQ pins AC : VREF ± 0.15V/0.135V (1600/1866) DC : VREF ± 0.10V/0.10V (1600/1866) VREF(DQ), Internal VREF VREF_CA/DQ tolerance 0.49×VDDQ ~ 0.51×VDDQ Internal VREF Pull-down Pull-up Characteristics Input/Output Capacitance1) Absolute maximum DC ratings AC/DC Logic Input Levels for Single-ended Signals CKE pin SAMSUNG AC/DC Logic Input Levels for Differential Input/Output Operating con- Differential Input Cross dition Point Voltage Slew Rate definitions for Differential VIHdiff/VILdiff (AC/DC) tDVAC vincent.chen@to-top.com.hk Differential Output Slew Overshoot / Undershoot TBD As is TBD VIXCA/VIXDQ As is TBD VILdiff /VIHdiff (Max/Min) As is TBD VOHdiff / VOLdiff (AC) As is TBD IOZ As is -5 ~ 5 AC/DC Output levels for Differential Single ended output Slew As is VSEH/VSEL(AC) MMPUPD As is TBD VOH/VOL(AC/DC) As is TBD SRQse As is 3.5 ~ 9.0 VOHdiff/VOLdiff(AC) As is TBD SRQdiff As is 7.0 ~ 18.0 Maximum Amplitude As is ˥ Maximum Area VDD/VSS : 0.1[V-ns] ˥ HSUL_12 LVSTL_11 Driver Output Timing NOTE: 1) The parameter applies to both die and package. -6- datasheet K4F6E3S4HM-MGCJ Rev. 1.0 LPDDR4 SDRAM LPDDR4 SDRAM SPECIFICATION 16G = 64M x16DQ x8banks x2channels 200FBGA, 10x15 2.0 KEY FEATURE • Double-data rate architecture; two data transfers per clock cycle • Bidirectional data strobes (DQS_t, DQS_c), These are transmitted/received with data to be used in capturing data at the receiver • Differential clock inputs (CK_t and CK_c) • Differential data strobes (DQS_t and DQS_c) • Commands & addresses entered positive CK edges; data and data mask referenced to both edges of DQS • 2channel composition per die • 8 internal banks for each channel • DMI Pin : DBI (Data Bus Inversion) when normal write and read operation, Data mask (DM) for masked write when DBI off - Counting # of DQ’s 1 for masked write when DBI on • Burst Length: 16, 32 (OTF) • Burst Type: Sequential • Read & Write latency : Refer to Table 64 LPDDR4 AC Timing Table • Auto Precharge option for each burst access • Configurable Drive Strength • Refresh and Self Refresh Modes • Partial Array Self Refresh and Temperature Compensated Self Refresh • Write Leveling • CA Calibration • Internal VREF and VREF training • FIFO based write/read training • MPC (Multi Purpose Command) • LVSTL (Low Voltage Swing Terminated Logic) IO • VDD1/VDD2/VDDQ : 1.8V/1.1V/1.1V • VSSQ Termination • No DLL : CK to DQS is not synchronized • Edge aligned data output, write training for data input center align • Refresh rate : 3.9us SAMSUNG vincent.chen@to-top.com.hk -7- Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM 3.0 ORDERING INFORMATION Part No. Org. Package Temperature Max Frequency Interface K4F6E3S4HM-MGCJ 2Ch, x16/Ch 10x15 200-FBGA Tc = -25 ~ 85C 3733Mbps (tCK=0.536ns) LVSTL_11 NOTE : 1) 3733Mbps is backward compatible to 3200Mbps. K4 F 6E 3S 4 H M - M G CJ Speed Samsung CJ: 0.536ns@RL32,tRCD18ns, tRP18ns Mobile DRAM Memory Device Type Temp, Power F : LPDDR4 SDRAM G : -25C ~ 85C (Standard) Density, Refresh Package 6E : 16G, 8K/32ms M : 200-FBGA (10x15) Organization Generation M : 1st Generation 3S : x32 (Mono LPDDR4) Bank 4 : 8Bank SAMSUNG Interface, VDD1, VDD2,VDDQ H : LVSTL_11, 1.8V/1.1V/1.1V vincent.chen@to-top.com.hk -8- datasheet K4F6E3S4HM-MGCJ Rev. 1.0 LPDDR4 SDRAM 4.0 PACKAGE DIMENSION & PIN DESCRIPTION 200-Ball Fine pitch Ball Grid Array Package (measured in millimeters) 10.00±0.10 A B 0.10 MAX C 4.1 LPDDR4 SDRAM Package Dimension Units:millimeters C 15.00±0.10 #A1 INDEX MARK TOP VIEW SIDE VIEW SAMSUNG #A1 INDEX MARK 12 11 10 A B C D E F G H J K L M N P R T U V W Y AA AB 9 8 7 6 5 4 3 2 1 6.825 0.975 0.65 x 21 = 13.65 0.65 vincent.chen@to-top.com.hk 0.80 1.20 4.40 200-0.31±0.05 Post Reflow (*Solder Ball 0.30)  0.15 M A B 0.80 x 11 = 8.80 -9- BOTTOM VIEW 0.22±0.05 0.90±0.10 datasheet K4F6E3S4HM-MGCJ Rev. 1.0 LPDDR4 SDRAM 4.2 LPDDR4 SDRAM Package Ballout 200Ball FBGA 1 2 3 4 5 6 7 8 9 10 11 12 A DNU DNU VSS VDD2 ZQ NB NB NC VDD2 VSS DNU DNU B DNU DQ0_a VDDQ DQ7_a VDDQ NB NB VDDQ DQ15_a VDDQ DQ8_a DNU C VSS DQ1_a DMI0_a DQ6_a VSS NB NB VSS DQ14_a DMI1_a DQ9_a VSS D VDDQ VSS DQS0_t_a VSS VDDQ NB NB VDDQ VSS DQS1_t_a VSS VDDQ E VSS DQ2_a DQS0_c_a DQ5_a VSS NB NB VSS F VDD1 DQ3_a VDDQ DQ4_a VDD2 NB NB VDD2 DQ12_a VDDQ DQ11_a VDD1 G VSS ODT_CA_a1) VSS VDD1 VSS NB NB VSS VDD1 VSS DNU VSS H VDD2 CA0_a NC CS_a VDD2 NB NB VDD2 CA2_a CA3_a CA4_a VDD2 J VSS CA1_a VSS CKE_a NC NB NB CK_t_a CK_c_a VSS CA5_a VSS K VDD2 VSS VDD2 VSS DNU NB NB DNU VSS VDD2 VSS VDD2 L NB NB NB NB NB NB NB NB NB NB NB NB M NB NB NB NB NB NB NB NB NB NB NB NB N VDD2 VSS VDD2 VSS DNU NB NB DNU VSS VDD2 VSS VDD2 P VSS CA1_b VSS CKE_b NC NB NB CK_t_b CK_c_b VSS CA5_b VSS R VDD2 CA0_b NC CS_b VDD2 NB NB VDD2 CA2_b CA3_b CA4_b VDD2 T VSS ODT_CA_b1) VSS VDD1 VSS NB NB VSS VDD1 VSS RESET_n VSS U VDD1 DQ3_b DQ4_b VDD2 NB NB VDD2 DQ12_b VDDQ DQ11_b VDD1 V VSS DQ2_b DQS0_c_b DQ5_b VSS NB NB VSS W VDDQ VSS DQS0_t_b VSS VDDQ NB NB VDDQ VSS DQS1_t_b VSS VDDQ Y VSS DQ1_b DMI0_b DQ6_b VSS NB NB VSS DQ14_b DMI1_b DQ9_b VSS AA DNU DQ0_b VDDQ DQ7_b VDDQ NB NB VDDQ DQ15_b VDDQ DQ8_b DNU AB DNU DNU VSS VDD2 VSS NB NB VSS VDD2 VSS DNU DNU DQ13_a DQS1_c_a DQ10_a SAMSUNG VDDQ vincent.chen@to-top.com.hk DQ13_b DQS1_c_b DQ10_b VSS VSS [Top View] Channel A Ground ODT_CA RESET_n ZQ NB DNU NOTE : 1) ODT(CA)_[x] balls are wired to ODT(CA)_[x] pads of Rank 0 DRAM die. ODT(CA)_[x] pads for other ranks (if present) are disabled in the package. - 10 - Channel B Power datasheet K4F6E3S4HM-MGCJ Rev. 1.0 LPDDR4 SDRAM 4.3 PAD Definition And Description Pin Name Pin Function Channel-A Pin Name Pin Function Channel-B CK_t_a, CK_c_a System Differential Clock CK_t_b, CK_c_b System Differential Clock CKE_a Clock Enable CKE_b Clock Enable CS_a Chip Select CS_b Chip Select CA[5:0]_a DDR Command / Address Inputs CA[5:0]_b DDR Command / Address Inputs DMI[1:0]_a Input Data Inversion DMI[1:0]_b Input Data Inversion DQS[1:0]_t_a Data Strobe Bi-directional DQS[1:0]_t_b Data Strobe Bi-directional DQS[1:0]_c_a Data Strobe Complementary DQS[1:0]_c_b Data Strobe Complementary DQ[15:0]_a Data Inputs / Outputs DQ[15:0]_b Data Inputs / Outputs ODT_CA_a On die termination ODT_CA_b On die termination RESET_n RESET Pin Name Pin Function Common Pin Name Pin Function Common DNU Do Not Use VDD1 Core Power Supply 1 VDD2 Core Power Supply 2 VDDQ I/O Power Supply VSS Ground ZQ Reference Pin for Output Driver Strength Calibration SAMSUNG 4.4 Functional Block Diagram VDD2 VDDQ VDD1 vincent.chen@to-top.com.hk CK_t_a, CK_c_a Ch. A 8Gb x16 LPDDR4 DQ[15:0]_a DQS[1:0]_t_a DQS[1:0]_c_a DMI[1:0]_a ZQ Ch. B 8Gb x16 LPDDR4 DQ[15:0]_b DQS[1:0]_t_b DQS[1:0]_c_b DMI[1:0]_b CKE_a CS_a CA[5:0]_a ODT_CA_a Reset_n CK_t_b CK_c_b CKE_b CS_b CA[5:0]_b ODT_CA_b VSS - 11 - datasheet K4F6E3S4HM-MGCJ Rev. 1.0 LPDDR4 SDRAM 4.5 LPDDR4 Pad Definition and Description 4.5.1 Dual channel per die device [Table 1] Pad Definition and Description for Dual channel Symbol Type Description CK_t_A CK_c_A CK_t_B CK_c_B Input Clock: CK_t and CK_c are differential clock inputs. All address, command, and control input signals are sampled on the crossing of the positive edge of CK_t and the negative edge of CK_c. AC timings for CA parameters are referenced to CK. Each channel (A & B) has its own clock pair. CKE_A CKE_B Input Clock Enable: CKE HIGH activates and CKE LOW deactivates the internal clock circuits, input buffers, and output drivers. Power-saving modes are entered and exited via CKE transitions. CKE is part of the command code. Each channel (A & B) has its own CKE signal. CS_A, CS_B Input Chip Select: CS is part of the command code. Each channel (A & B) has its own CS signal. CA[5:0]_A CA[5:0]_B Input Command/Address Inputs: CA signals provide the Command and Address inputs according to the Command Truth Table. Each channel (A&B) has its own CA signals. ODT_CA_A ODT_CA_B Input CA ODT Control: The ODT_CA pin is used in conjunction with the Mode Register to turn on/off the On-Die-Termination for CA pins. DQ[15:0]_A DQ[15:0]_B I/O Data Inputs/Outputs: Bi-direction data bus I/O Data Strobe: DQS_t and DQS_c are bi-directional differential output clock signals used to strobe data during a READ or WRITE. The Data Strobe is generated by the DRAM for a READ and is edge-aligned with Data. The Data Strobe is generated by the Memory Controller for a WRITE and must arrive prior to Data. Each byte of data has a Data Strobe signal pair. Each channel (A & B) has its own DQS strobes. DMI[1:0]_A DMI[1:0]_B I/O Data Mask Inversion: DMI is a bi-directional signal which is driven HIGH when the data on the data bus is inverted, or driven LOW when the data is in its normal state. Data Inversion can be disabled via a mode register setting. Each byte of data has a DMI signal. Each channel (A & B) has its own DMI signals. This signal is also used along with the DQ signals to provide write data masking information to the DRAM. The DMI pin function - Data Inversion or Data mask - depends on Mode Register setting. ZQ Reference Calibration Reference: Used to calibrate the output drive strength and the termination resistance. There is one ZQ pin per die. The ZQ pin shall be connected to VDDQ through a 240Ω ± 1% resistor. VDDQ,VDD1, VDD2 Supply DQS[1:0]_t_A DQS[1:0]_c_A DQS[1:0]_t_B DQS[1:0]_c_B SAMSUNG Power Supplies: Isolated on the die for improved noise immunity. vincent.chen@to-top.com.hk VSS, VSSQ GND Ground Reference: Power supply ground reference. RESET_n Input RESET: When asserted LOW, the RESET_n signal resets all channels of the die. There is one RESET_n pad per die. NOTE : 1) "_A" and "_B" indicate DRAM channel "_A" pads are present in all devices. "_B" pads are present in dual channel SDRAM devices only. - 12 - Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM 5.0 FUNCTIONAL DESCRIPTION LPDDR4-SDRAM is a high-speed synchronous DRAM device internally configured with either 1 or 2 channels. Dual channel is comprised of 8-banks with from 2Gb to 16Gb per channel density. The configuration for channel density that is greater than 16Gb is still TBD1). These devices contain the following number of bits: Dual-channel SDRAM devices contain the following number of bits: 16Gb has 17,179,869,184 bits LPDDR4 devices use a 2 or 4 clocks architecture on the Command/Address (CA) bus to reduce the number of input pins in the system. The 6-bit CA bus contains command, address, and bank information. Each command uses 1, 2 or 4 clock cycle, during which command information is transferred on the positive edge of the clock. See command truth table for details. These devices use a double data rate architecture on the DQ pins to achieve high speed operation. The double data rate architecture is essentially an 16n prefetch architecture with an interface designed to transfer two data bits per DQ every clock cycle at the I/O pins. A single read or write access for the LPDDR4 SDRAM effectively consists of a single 16n-bit wide, one clock cycle data transfer at the internal DRAM core and eight corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins. Read and write accesses to the LPDDR4 SDRAMs are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an Activate command, which is then followed by a Read, Write or Mask Write command. The address and BA bits registered coincident with the Activate command are used to select the row and the Bank to be accessed. The address bits registered coincident with the Read, Write or Mask Write command are used to select the Bank and the starting column location for the burst access. Prior to normal operation, the LPDDR4 SDRAM must be initialized. The following section provides detailed information covering device initialization, register definition, command description and device operation. 5.1 LPDDR4 SDRAM Addressing [Table 2] LPDDR4 SDRAM x16 mode Addressing for Dual Channel SDRAM Device Memory Density (per Die) 16Gb SAMSUNG Memory Density (per x16 channel) Configuration 8Gb 64Mb x 16DQ x 8 banks x 2 channels Number of Channels (per die) Number of Banks (per channel) Array Pre-Fetch (bits, per channel) 2 vincent.chen@to-top.com.hk 8 256 Number of Rows (per Channel) 65,536 Number of Columns (fetch boundaries) 64 Page Size (Bytes) 2048 Channel Density (Bits per channel) 8,589,934,592 Total Density (Bits per die) 17,179,869,184 Bank Addresses x16 BA0-BA2 Row Addresses 2) R0 - R15 Column Addresses 1), 2) C0-C9 Burst Starting Address Boundary 64 - bit NOTE : 1) The lower two column addresses (C0-C1) are assumed to be “zero” and are not transmitted on the CA bus. 2) Row and Column Address values on the CA bus that are not used for a particular density is required to at valid logic levels. - 13 - Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM 5.2 Simplified LPDDR4 State Diagram LPDDR4-SDRAM state diagram provides a simplified illustration of allowed state transitions and the related commands to control them. For a complete definition of the device behavior, the information provided by the state diagram should be integrated with the truth tables and timing specification. The truth tables provide complementary information to the state diagram, they clarify the device behavior and the applied restrictions when considering the actual state of all the banks. For the command definition, see datasheet of [Command Definition & Timing Diagram]. Command Sequence Automatic Sequence Power On t_n se Re = L SR Power Down L E= CK Reset CK H E= All Bank Refresh REF Idle SRX =L KE C KE MRW MRW MRR Idle Power Down MRR MPC MPC Based Training MRW ACT C MRR MRW MRW =H MPC Per Bank Refresh REF MRW MPC SRE MRR MPC MRW Self Refresh MRR MRW MRW MRW MPC Based Training MRW MPC Based Training n t_ se Re = H Command Bus Training MPC Based Training MRR Command Bus Training MRR MRR MRW SAMSUNG Activating MRW Active Power Down MRW vincent.chen@to-top.com.hk CK E= CK E= MPC Based Training MRR MRR L MRW H MRW Bank Active WR or MWR REF Per Bank Refresh RD RD WR or MWR Write or MWR MRR RDA WRA or MWRA RDA PRE or PREA Write or MWR with AutoPrecharge MPC Based Training MRR Read WRA or MWRA MPC PRE or PREA PRE or PREA Precharging Read with AutoPrecharge PRE(A) = Precharge (All) ACT = Activate WR(A) = Write (with Autoprecharge) MWR(A) = Mask-Write (with Autoprecharge) RD(A) = Read (with Autoprecharge) MRW = Mode Register Write MRR = Mode Register Read "CKE=L" = Enter Power Down "CKE=H" = Exit Power Down SRE = Enter Self Refresh SRX = Exit Self Refresh REF = Refresh MPC = Multi-Purpose Command (w/NOP) Figure 1. LPDDR4: Simplified Bus Interface State Diagram-1 - 14 - datasheet K4F6E3S4HM-MGCJ Rev. 1.0 LPDDR4 SDRAM A) FIFO Based Write / Read Timing MPC MPC MPC Write FIFO MPC Based Training MPC MPC MRW Read FIFO MPC MRW MRW B) Read DQ Calibration MPC MPC DQ Calibration C) ZQ CAL Start MPC ZQ Calibration Start D) ZQ CAL Latch MPC ZQ Calibration Latch SAMSUNG Figure 2. LPDDR4: Simplified Bus Interface State Diagram -2 NOTE : 1) From the Self-Refresh state the device can enter Power-Down, MRR, MRW, or MPC states. See the section on Self-Refresh for more information. 2) In IDLE state, all banks are precharged. 3) In the case of a MRW command to enter a training mode, the state machine will not automatically return to the IDLE state at the conclusion of training. See the applicable training section for more information. 4) In the case of a MPC command to enter a training mode, the state machine may not automatically return to the IDLE state at the conclusion of training. See the applicable training section for more information. 5) This simplified State Diagram is intended to provide an overview of the possible state transitions and the commands to control them. In particular, situations involving more than one bank, the enabling or disabling of on-die termination, and some other events are not captured in full detail. 6) States that have an “automatic return” and can be accessed from more than one prior state (Ex. MRW from either Idle or Active states) will return to the state from when they were initiated (Ex. MRW from Idle will return to Idle). 7) The RESET_n pin can be asserted from any state, and will cause the SDRAM to go to the Reset State. The diagram shows RESET applied from the Power-On as an example, but the Diagram should not be construed as a restriction on RESET_n. vincent.chen@to-top.com.hk - 15 - Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM 5.3 Mode Register Definition 5.3.1 Mode Register Assignment and Definition in LPDDR4 SDRAM [Table 3] shows the mode registers for LPDDR4 SDRAM. Each register is denoted as “R” if it can be read but not written, “W” if it can be written but not read, and “R/W” if it can be read and written. A Mode Register Read command is used to read a mode register. A Mode Register Write command is used to write a mode register. [Table 3] Mode Register Assignment in LPDDR4 SDRAM MR# MA Function Access OP7 0 00H Device Info. R CATR 1 2 01H 02H Device Feature 1 Device Feature 2 OP6 OP5 OP4 (RFU) OP3 RZQI OP1 nWR0 RDPRE0 WRPRE0 RPST1 nWR1 RDPRE1 WRPRE1 WL Select0 WL0 RL0 WL Select1 WL1 RL1 DBI-WR0 DBI-RD0 PDDS0 DBI-WR1 DBI-RD1 PDDS1 PPR Pro- WR PST PU-CAL0 tection WR PST PU-CAL1 WR Lev 03H I/O Configuration-1 W 4 04H Refresh Rate R/W 5 05H Basic Configuration-1 R LPDDR4 Manufacturer ID 6 06H Basic Configuration-2 R Revision ID-1 7 07H Basic Configuration-3 R 8 08H Basic Configuration-4 R 9 09H Test Mode W 10 0AH IO Calibration W 11 0BH ODT Feature W (RFU) 12 0CH VREF(ca) Setting/Range R/W (RFU) 13 0DH CBT,RPT,VRO,VRCG, RRO, DM_DIS,FSPWR,FSP-OP W 14 0EH VREF(dq) Setting/Range R/W 15 0FH Lower-Byte Invert for DQ Calibration W Lower-Byte Invert Register for DQ Calibration 16 10H PASR_Bank W PASR Bank Mask 17 11H PASR_Segment W PASR Segment Mask 18 12H IT-LSB R DQS Oscillator Count-LSB 19 13H IT-MSB R DQS Oscillator Count-MSB 20 14H Upper-Byte Invert for DQ Calibration W Upper-Byte Invert Register for DQ Calibration 21 15H RFU N/A (RFU) 16H Refresh mode BL 3 22 OP0 (RFU) RPST0 W W OP2 TUF Thermal Offset PPRE SR Abort Refresh Rate SAMSUNG Single ended mode Revision ID-2 I/O width Density Type Vendor Specific Test Register vincent.chen@to-top.com.hk ODT Feature W ZQRESET (RFU) CA ODT0 DQ ODT0 (RFU) CA ODT1 DQ ODT1 VR-CA0 VREF0(ca) VR-CA1 VREF1(ca) FSP-OP FSP-WR DM_DIS RRO VRCG VRO (RFU) VR-DQ0 VREF0(DQ) (RFU) VR-DQ1 VREF1(DQ) (RFU) - 16 - RPT ODTDCA0 ODTECS0 ODTECK0 SoC ODT0 ODTDCA1 ODTECS1 ODTECK1 SoC ODT1 CBT Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM [Table 3] Mode Register Assignment in LPDDR4 SDRAM MR# MA Function Access 23 17H DQS interval timer run time W 24 18H TRR R/W TRR Mode 25 19H PPR Resource R Bank 7 26:29 1AH : 1DH RFU N/A Reserved for Future Use 30 1EH Reserved for Testing N/A Reserved for Testing-SDRAM will ignore 31 1FH RFU N/A Reserved for Future Use 32 20H DQ Calibration Pattern A W DQ Calibration Pattern "A" (default = 5AH) 33:38 21H~26H (Do Not Use) NA Do Not Use 39 27H Reserved for Testing N/A Reserved for Testing-SDRAM will ignore 40 28H DQ Calibration Pattern B W DQ Calibration Pattern "B" (default = 3CH) 41:47 29H~2FH (Do Not Use) NA Do Not Use 48:50 30H~32H RFU NA (RFU) 51 33H Single Ended RDQS, WDQS, CLK W 52:63 34H~3FH RFU NA OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 DQS interval timer run time setting Unlimited MAC TRR Mode BAn Bank 6 Bank 5 (RFU) Bank 4 Bank 3 Single ended Clock MAC Value Bank 2 Single ended WDQS Bank 1 Bank 0 Single ended RDQS (RFU) (RFU) SAMSUNG NOTE : 1) RFU bits shall be set to ‘0’ during writes. 2) RFU bits shall be read as ‘0’ during reads. 3) All mode registers that are specified as RFU or write-only shall return undefined data when read and DQS_t, DQS_c shall be toggled. 4) All mode registers that are specified as RFU shall not be written. 5) Writes to read-only registers shall have no impact on the functionality of the device. vincent.chen@to-top.com.hk - 17 - Applied when FSP = 0 Applied when FSP = 1 Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM MR0_Device Information (MA = 00H) : OP7 CATR Function Register Type Refresh mode RZQI (Built-in Self-Test for RZQ) CATR (CA Terminating Rank) OP6 OP5 (RFU) OP3 RZQI Operand OP[0] Read-only OP4 OP[4:3] OP[7] OP2 OP1 (RFU) OP0 Refresh mode Data Notes 0B: Both legacy & modified refresh mode supported 1B: Only modified refresh mode supported 00B: RZQ self-test not supported 01B: ZQ-pin may connect to VSSQ or float 10B: ZQ-pin may short to VDDQ 11B: ZQ-pin self test completed, no error condition detected (ZQ-pin may not connect to VSSQ or float, nor short to VDDQ) 0B: CA for this rank is not terminated 1B: CA for this rank can be terminated 1,2,3,4 5 NOTE : 1) RZQI MR value, if supported, will be valid after the following sequence: a. Completion of MPC ZQCAL Start command to either channel. b. Completion of MPC ZQCAL Latch command to either channel then tZQLAT is satisfied. RZQI value will be lost after Reset. 2) If the ZQ-pin is connected to VSSQ to set default calibration, OP[4:3] shall be set to 01B. If the ZQ-pin is not connected to VSSQ, either OP[4:3] = 01B or OP[4:3] =10B might indicate a ZQ-pin assembly error. It is recommended that the assembly error is corrected. 3) In the case of possible assembly error, the LPDDR4-SDRAM device will default to factory trim settings for RON, and will ignore ZQ calibration commands. In either case, the device may not function as intended. 4) In ZQ self-test returns OP[4:3] = 11B, the device has detected a resistor connected to the ZQ pin. However, this result cannot be used to validate the ZQ resistor value or that the ZQ resistor tolerance meets the specified limits (i.e., 240-Ω +/- 1%). 5) OP[7] is set at power-up, according to the state of the CA-ODT pad on the die and the state of MR11 OP[4:6]. If the CA ODT pad is tied LOW, then the die will not terminate the CA bus and MR0 OP[7]=0B, regardless of the state of ODTECA (MR11 OP[4:6]). If the CA-ODT pad is tied HIGH and ODTE-CA is enabled (MR11 OP[4:6] is valid), then this bit will be set (MR0 OP[7]=1B) and the die will terminate the CA bus. SAMSUNG vincent.chen@to-top.com.hk - 18 - Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM MR1_Device Feature 1 (MA = 01H) : OP7 OP6 OP5 RPST Function Register Type BL (Burst Length) OP4 nWR (for AP) OP3 OP2 OP1 RD-PRE WR-PRE Operand OP[1:0] OP0 BL Data Notes 00B : BL=16 Sequential (default) 01B : BL=32 Sequential 10B : BL=16 or 32 Sequential (on-the-fly) All others: Reserved 1,7 5,6 WR-PRE (WR Pre-amble Length) OP[2] 0B : Reserved 1B : WR Pre-amble = 2×tCK RD-PRE (RD Pre-amble Type) OP[3] 0B : RD Pre-amble = Static (default) 1B : RD Pre-amble = Toggle 3,5,6 000B: nWR = 6 (default) 001B: nWR = 10 010B: nWR = 16 011B: nWR = 20 100B: nWR = 24 101B: nWR = 30 110B: nWR = 34 111B: nWR = 40 2,5,6 0B : RD Post-amble = 0.5×tCK (default) 1B : RD Post-amble = 1.5×tCK 4,5,6 Write-only nWR (Write-Recovery for AutoPrecharge commands) OP[6:4] RPST (RD Post-Amble Length) OP[7] NOTE : 1) Burst length on-the-fly can be set to either BL=16 or BL=32 by setting the “BL” bit in the command operands. See the Command Truth Table. 2) The programmed value of nWR is the number of clock cycles the LPDDR4-SDRAM device uses to determine the starting point of an internal Precharge operation after a Write burst with AP (auto-precharge) enabled. See "Read and Write Latencies" later in this section. 3) For Read operations this bit must be set to select between a “toggling” pre-amble and a “Non-toggling” pre-amble. See the Read Preamble and Postamble section in Operation timing for a drawing of each type of pre-amble. 4) OP[7] provides an optional READ post-amble with an additional rising and falling edge of DQS_t. The optional postamble cycle is provided for the benefit of certain memory controllers. 5) There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1. Only the registers for the set point determined by the state of the FSP-WR bit (MR13 OP[6]) will be read from with an MRR command to this MR address. 6) There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1. The device will operate only according to the values stored in the registers for the active set point, i.e., the set point determined by the state of the FSP-OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be ignored by the device, and may be changed without affecting device operation. 7) Supporting the two physical registers for Burst Length: MR1 OP[1:0] as optional feature. Applications requiring support of both vendor options shall assure that both FSPOP[0] and FSP-OP[1] are set to the same code. Refer to vendor datasheets for detail. SAMSUNG vincent.chen@to-top.com.hk [Table 4] Read and Write Latencies for x16 mode Read Latency [nCK] Write Latency [nCK] nRTP [nCK] Lower Clock Frequency Limit [MHz] (Greater than) Upper Clock Frequency Limit [MHz] (Same or less than) 8 10 266 No DBI w/ DBI Set "A" Set "B" nWR [nCK] 6 6 4 4 6 10 12 6 8 10 8 266 533 14 16 8 12 16 8 533 800 20 22 10 18 20 8 800 1066 24 28 12 22 24 10 1066 1333 28 32 14 26 30 12 1333 1600 32 36 16 30 34 14 1600 1866 36 40 18 34 40 16 1866 2133 Notes 1,2,3,4,5,6 NOTE : 1) The LPDDR4-SDRAM device should not be operated at a frequency above the Upper Frequency Limit, or below the Lower Frequency Limit, shown for each RL, WL, nRTP, or nWR value. 2) DBI for Read operations is enabled in MR3 OP[6]. When MR3 OP[6]=0B, then the “No DBI” column should be used for Read Latency. When MR3 OP[6]=1B, then the “w/DBI” column should be used for Read Latency. 3) Write Latency Set “A” and Set “B” is determined by MR2 OP[6]. When MR2 OP[6]=0B, then Write Latency Set “A” should be used. When MR2 OP[6]=1B, then Write Latency Set “B” should be used. 4) The programmed value of nWR is the number of clock cycles the LPDDR4-SDRAM device uses to determine the starting point of an internal Precharge operation after a Write burst with AP (auto precharge). It is determined by RU(tWR/tCK). 5) The programmed value of nRTP is the number of clock cycles the LPDDR4-SDRAM device uses to determine the starting point of an internal Precharge operation after a Read burst with AP (auto precharge). It is determined by RU(tRTP/tCK). 6) nRTP shown in this table is valid for BL16 only. For BL32, the SDRAM will add 8 clocks to the nRTP value before starting a precharge. - 19 - Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM [Table 5] Burst Sequence for READ BL BT C4 C3 C2 C1 C0 16 seq 32 seq Burst Cycle Number and Burst Address Sequence 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 V 0B 0B 0B 0B 0 1 2 3 4 5 6 7 8 V 0B 1B 0B 0B 4 5 6 7 8 9 A V 1B 0B 0B 0B 8 9 A V 1B 1B 0B 0B C D E 9 A B C D E F B C D E F 0 1 3 B C D E F 0 1 2 3 4 5 6 7 F 0 1 2 3 4 5 6 7 8 9 A B 8 9 A B C D E F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 2 0B 0B 0B 0B 0B 0 1 2 3 4 5 6 7 0B 0B 1B 0B 0B 4 5 6 7 8 9 A B C D E F 0 1 2 3 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 10 11 12 13 0B 1B 0B 0B 0B 8 9 A B C D E F 0 1 2 3 4 5 6 7 18 19 1A 1B 1C 1D 1E 1F 10 11 12 13 14 15 16 17 F 3 4 5 6 7 8 9 A B 1C 1D 1E 1F 10 11 12 13 14 15 16 17 18 19 1A 1B 0B 1B 1B 0B 0B C D E 0 1 2 1B 0B 0B 0B 0B 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 0 1 2 3 4 5 6 7 1B 0B 1B 0B 0B 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 10 11 12 13 4 5 6 7 8 9 A B C D E 1B 1B 0B 0B 0B 18 19 1A 1B 1C 1D 1E 1F 10 11 12 13 14 15 16 17 8 9 A B C D E F 0 1 2 3 4 5 6 7 F 3 4 5 6 7 8 9 A B 1B 1B 1B 0B 0B 1C 1D 1E 1F 10 11 12 13 14 15 16 17 18 19 1A 1B C D E 0 1 2 8 9 A B C D E F F 3 0 1 2 NOTE : 1) C0-C1 are assumed to be '0', and are not transmitted on the command bus. 2) The starting burst address is on 64-bit (4n) boundaries. [Table 6] Burst Sequence for Write BL BT C4 C3 C2 C1 C0 Burst Cycle Number and Burst Address Sequence 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SAMSUNG 16 seq V 0 0 0 0 0 1 2 3 4 5 6 7 8 9 A B C D E F 32 seq 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 A B C D E F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F NOTE : 1) C0-C1 are assumed to be '0', and are not transmitted on the command bus. 2) The starting address is on 256-bit (16n) boundaries for Burst length 16. 3) The starting address is on 512-bit (32n) boundaries for Burst length 32. 4) C2-C3 shall be set to '0' for all Write operations. vincent.chen@to-top.com.hk - 20 - Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM MR2_Device Feature 2 (MA = 02H): Function OP7 OP6 WR Lev WLS Register Type OP5 OP4 OP3 OP2 WL OP1 OP0 RL Operand Data Notes RL & nRTP for DBI-RD Disabled (MR3 OP[6]=0B) 000B: RL=6, nRTP=8 (Default) 001B: RL=10, nRTP=8 010B: RL=14, nRTP=8 011B: RL=20, nRTP=8 100B: RL=24, nRTP=10 101B: RL=28, nRTP=12 110B: RL=32, nRTP=14 111B: RL=36, nRTP=16 RL (Read latency) OP[2:0] 1,3,4 RL & nRTP for DBI-RD Enabled (MR3 OP[6]=1B) 000B: RL= 6, nRTP=8 001B: RL= 12, nRTP=8 010B: RL= 16, nRTP=8 011B: RL= 22, nRTP=8 100B: RL= 28, nRTP=10 101B: RL= 32, nRTP=12 110B: RL= 36, nRTP=14 111B: RL= 40, nRTP=16 SAMSUNG WL Set “A” (MR2 OP[6]=0B) 000B: WL=4 (Default) Write-only 001B: WL=6 010B: WL=8 011B: WL=10 vincent.chen@to-top.com.hk 100B: WL=12 101B: WL=14 110B: WL=16 WL (Write latency) 111B: WL=18 OP[5:3] 1,3,4 WL Set “B” (MR2 OP[6]=1B) 000B: WL=4 001B: WL=8 010B: WL=12 011B: WL=18 100B: WL=22 101B: WL=26 110B: WL=30 111B: WL=34 WLS (Write latency set) OP[6] WR Leveling OP[7] 0B: WL Set “A” (default) 1B: WL Set “B” 0B: Disabled (default) 1B: Enabled 1,3,4 2 NOTE : 1) See Latency Code Frequency Table for allowable frequency ranges for RL/WL/nWR/nRTP. 2) After a MRW to set the Write Leveling Enable bit (OP[7]=1B), the LPDDR4-SDRAM device remains in the MRW state until another MRW command clears the bit (OP[7]=0B). No other commands are allowed until the Write Leveling Enable bit is cleared. 3) There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1. Only the registers for the set point determined by the state of the FSP-WR bit (MR13 OP[6]) will be written to with an MRW command to this MR address, or read from with an MRR command to this address. 4) There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1. The device will operate only according to the values stored in the registers for the active set point, i.e., the set point determined by the state of the FSP-OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be ignored by the device, and may be changed without affecting device operation. - 21 - Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM MR3_I/O Configuration 1 (MA = 03H): Function OP7 OP6 DBI-WR DBI-RD Register Type OP5 OP4 OP3 PDDS OP2 OP1 OP0 PPRP WR PST PU-CAL Operand Data PU-Cal (Pull-up Calibration Point) OP[0] 0B: VDDQ/2.5 1B: VDDQ/3 (default) WR PST (WR Post-Amble Length) OP[1] 0B: WR Post-amble = 0.5×tCK (default) 1B: WR Post-amble = 1.5×tCK (Vendor specific function) Post Package Repair Protection OP[2] 0B: PPR protection disabled (default) 1B: PPR protection enabled Notes 1,4 2,3,5 6 OP[5:3] 000B: RFU 001B: RZQ/1 010B: RZQ/2 011B: RZQ/3 100B: RZQ/4 101B: RZQ/5 110B: RZQ/6 (default) 111B: Reserved 1,2,3 DBI-RD (DBI-Read Enable) OP[6] 0B: Disabled (default) 1B: Enabled 2,3 DBI-WR (DBI-Write Enable) OP[7] 0B: Disabled (default) 1B: Enabled 2,3 PDDS (Pull-Down Drive Strength) Write-only NOTE : 1) All values are “typical”. The actual value after calibration will be within the specified tolerance for a given voltage and temperature. Re-calibration may be required as voltage and temperature vary. 2) There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1. Only the registers for the set point determined by the state of the FSP-WR bit (MR13 OP[6]) will be written to with an MRW command to this MR address, or read from with an MRR command to this address. 3) There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1. The device will operate only according to the values stored in the registers for the active set point, i.e., the set point determined by the state of the FSP-OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be ignored by the device, and may be changed without affecting device operation. 4) For dual channel devices, PU-CAL setting is required as the same value for both Ch.A and Ch.B before issuing ZQ Cal start command. 5) Refer to the supplier data sheet for vender specific function. 1.5×tCK apply > 1.6GHz clock. 6) If MR3 OP[2] is set to 1b then PPR protection mode is enabled. The PPR Protection bit is a sticky bit and can only be set to 0b by a power on reset. MR4 OP[4] controls entry to PPR Mode. If PPR protection is enabled then DRAM will not allow writing of 1 to MR4 OP[4]. SAMSUNG vincent.chen@to-top.com.hk - 22 - Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM MR4_Refresh rate (MA = 04H) Function OP7 OP6 TUF Thermal Offset Register Type OP5 OP4 OP3 PPRE SR Abort OP2 OP1 OP0 Refresh Rate Operand Data Notes 000B: SDRAM Low temperature operating limit exceeded 001B: 4x refresh 010B: 2x refresh 011B: 1x refresh (default) 100B: 0.5x refresh 101B: 0.25x refresh, no de-rating 110B: 0.25x refresh, with de-rating 111B: SDRAM High temperature operating limit exceeded 1,2,3,4 7,8,9 Refresh Rate Read-only OP[2:0] SR Abort (Self Refresh Abort) Write-only OP[3] 0B : Disable (default) 1B : Enable 9,11 PPRE (Post-package repair entry/exit) Write-only OP[4] 0B: Exit PPR mode (default) 1B: Enter PPR mode 5,9 00B: No offset, 0~5C gradient (default) 01B: 5C offset, 5~10C gradient 10B: 10C offset, 10~15C gradient 11B: Reserved 10 Thermal Offset (Vender Specific Function) Write-only OP[6:5] TUF (Temperature Update Flag) Read-only OP[7] 0B: No change in OP[2:0] since last MR4 read (default) 1B: Change in OP[2:0] since last MR4 read 6,7,8 NOTE : 1) The refresh rate for each MR4 OP[2:0] setting applies to tREFI, tREFIpb and tREFW. OP[2:0]=011B corresponds to a device temperature of 85°C. Other values require either a longer (2x, 4x) refresh interval at lower temperatures, or a shorter (0.5x, 0.25x) refresh interval at higher temperatures. If OP[2]=1B, the device temperature is greater than 85°C. 2) At higher temperatures (>85°C), AC timing derating may be required. If derating is required the LPDDR4-SDRAM will set OP[2:0]=110B. See derating timing requirements in the AC Timing section. 3) DRAM vendors may or may not report all of the possible settings over the operating temperature range of the device. Each vendor guarantees that their device will work at any temperature within the range using the refresh interval requested by their device. 4) The device may not operate properly when OP[2:0]=000B or 111B. 5) Post-package repair can be entered or exited by writing to OP[4]. 6) When OP[7]=1B, the refresh rate reported in OP[2:0] has changed since the last MR4 read. A mode register read from MR4 will reset OP[7] to ‘0’. 7) OP[7]=0B at power-up. OP[2:0] bits are valid after initialization sequence (Te). 8) See the section on “Temperature Sensor” for information on the recommended frequency of reading MR4. 9) OP[6:3] bits that can be written in this register. All other bits will be ignored by the DRAM during a MRW to this register. 10) Refer to the supplier data sheet for vender specific function. 11) Self refresh abort feature is available for higher density devices starting with 12Gb device. SAMSUNG vincent.chen@to-top.com.hk MR5_Basic Configuration 1 (MA = 05H): OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 LPDDR4 Manufacturer ID Function Register Type Operand LPDDR4 Manufacturer ID Read-only OP[7:0] Data Notes 0000 0001B : Samsung MR6_Basic Configuration 2 (MA = 06H): OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Revision ID-1 Function LPDDR4 Revision ID-1 Register Type Read-only Operand OP[7:0] Data 0000 0110B : G-version NOTE : 1) MR6 is vendor specific. - 23 - Notes 1 Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM MR7_Basic Configuration 3 (MA = 07H): OP7 OP6 OP5 OP4 OP3 OP2 OP1 Revision ID-2 Function Register Type Operand LPDDR4 Revision ID-2 Single ended mode Data OP[7:1] Read-only OP0 Single ended mode OP[0] Notes 0000 000B 1 0B : No support for Single ended mode 1B : Support for Single ended mode 2 NOTE : 1) MR7 is vendor specific. 2) Support for Single Ended Mode is optional. If supported, Single Ended Write DQS, Read DQS and CK can be enabled in MR51. MR8_Basic Configuration 4 (MA = 08H) : OP7 OP6 OP5 I/O width Function Register Type Type OP3 OP2 OP1 Density OP0 Type Operand Data OP[1:0] 00B: S16 SDRAM (16n pre-fetch) All Others: Reserved OP[5:2] 0000B: 4Gb dual channel die 0001B: 6Gb dual channel die 0010B: 8Gb dual channel die 0011B: 12Gb dual channel die 0100B: 16Gb dual channel die 0101B: 24Gb dual channel die 0110B: 32Gb dual channel die All Others: Reserved Read-only Density OP4 Notes SAMSUNG 00B: x16 (per channel) All Others : Reserved vincent.chen@to-top.com.hk I/O width OP[7:6] MR9_Test Mode (MA = 09H): OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 OP1 OP0 Vendor-specific Test Register NOTE : 1) Only 00H should be written to this register. MR10_IO Calibration (MA = 0AH): OP7 OP6 OP5 OP4 OP3 OP2 ZQReset (RFU) Function ZQ-Reset Register Type Write-only Operand OP[0] Data 0B: Normal Operation (Default) 1B: ZQ Reset Notes 1,2 NOTE : 1) See ZQCal Timing Parameters for calibration latency and timing in AC Timing table. 2) If the ZQ-pin is connected to VDDQ through RZQ, either the ZQ calibration function or default calibration (via ZQ-Reset) is supported. If the ZQ-pin is connected to VSS, the device operates with default calibration, and ZQ calibration commands are ignored. In both cases, the ZQ connection shall not change after power is applied to the device. - 24 - Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM MR11_ODT Feature (MA = 0BH): OP7 (RFU) Function Register Type DQ ODT (DQ Bus Receiver OnDie-Termination) OP6 OP5 OP3 (RFU) Operand OP2 OP1 OP0 DQ ODT Data Notes OP[2:0] 000B: Disable (Default) 001B: RZQ/1 010B: RZQ/2 011B: RZQ/3 100B: RZQ/4 101B: RZQ/5 110B: RZQ/6 111B: RFU 1,2,3 OP[6:4] 000B: Disable (Default) 001B: RZQ/1 010B: RZQ/2 011B: RZQ/3 100B: RZQ/4 101B: RZQ/5 110B: RZQ/6 111B: RFU 1,2,3 Write-only CA ODT (CA Bus Receiver OnDie-Termination) OP4 CA ODT NOTE : 1) All values are “typical”. The actual value after calibration will be within the specified tolerance for a given voltage and temperature. Re-calibration may be required as voltage and temperature vary. 2) There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1. Only the registers for the set point determined by the state of the FSP-WR bit (MR13 OP[6]) will be written to with an MRW command to this MR address, or read from with an MRR command to this address. 3) There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1. The device will operate only according to the values stored in the registers for the active set point, i.e., the set point determined by the state of the FSP-OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be ignored by the device, and may be changed without affecting device operation. SAMSUNG vincent.chen@to-top.com.hk - 25 - Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM MR12_VREF(CA) Setting/Range (MA = 0CH): Function OP7 OP6 (RFU) VR-CA Register Type VREF(CA) (VREF(CA) Setting) OP5 OP4 OP3 OP2 Read/Write VR-CA (VREF(CA) Range) OP[6] OP0 VREF(CA) Operand OP[5:0] OP1 Data Notes 000000B: -- Thru . 110010B: See table below All Others: Reserved 1,2,3,5 ,6 0B: VREF(CA) Range[0] enabled 1B: VREF(CA) Range[1] enabled (default) 1,2,4,5 ,6 NOTE : 1) This register controls the VREF(CA) levels. Refer to Table 7, VREF Settings for Range[0] and Range[1]. 2) A read to this register places the contents of OP[7:0] on DQ[7:0]. Any RFU bits and unused DQ’s shall be set to ‘0’. See the section on MRR Operation. 3) A write to OP[5:0] sets the internal VREF(CA) level for FSP[0] when MR13 OP[6]=0B, or sets FSP[1] when MR13 OP[6]=1B. The time required for VREF(CA) to reach the set level depends on the step size from the current level to the new level. See the section on VREF(CA) training for more information. 4) A write to OP[6] switches the LPDDR4-SDRAM between two internal VREF(CA) ranges. The range (Range[0] or Range[1]) must be selected when setting the VREF(CA) register. The value, once set, will be retained until overwritten, or until the next power-on or RESET event. 5) There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1. Only the registers for the set point determined by the state of the FSP-WR bit (MR13 OP[6]) will be written to with an MRW command to this MR address, or read from with an MRR command to this address. 6) There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1. The device will operate only according to the values stored in the registers for the active set point, i.e., the set point determined by the state of the FSP-OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be ignored by the device, and may be changed without affecting device operation. [Table 7] VREF Settings for Range[0] and Range[1] Function Operand Range[0] Values (%of VDD2) 000000B: 10.0% 000001B: 10.4% 000010B: 10.8% 000011B: 11.2% 000100B: 11.6% 000101B: 12.0% 000110B: 12.4% 000111B: 12.8% 001000B: 13.2% 001001B: 13.6% 001010B: 14.0% 001011B: 14.4% 001100B: 14.8% 001101B: 15.2% 001110B: 15.6% 001111B: 16.0% 010000B: 16.4% 010001B: 16.8% 010010B: 17.2% 010011B: 17.6% 010100B: 18.0% 010101B: 18.4% 010110B: 18.8% 010111B: 19.2% 011000B: 19.6% 011001B: 20.0% Range[1] Values (%of VDD2) 011010B: 20.4% 011011B: 20.8% 011100B: 21.2% 011101B: 21.6% 011110B: 22.0% 011111B: 22.4% 100000B: 22.8% 100001B: 23.2% 100010B: 23.6% 100011B: 24.0% 100100B: 24.4% 100101B: 24.8% 100110B: 25.2% 100111B: 25.6% 101000B: 26.0% 101001B: 26.4% 101010B: 26.8% 101011B: 27.2% 101100B: 27.6% 101101B: 28.0% 101110B: 28.4% 101111B: 28.8% 110000B: 29.2% 110001B: 29.6% 110010B: 30.0% All Others: Reserved 000000B: 22.0% 000001B: 22.4% 000010B: 22.8% 000011B: 23.2% 000100B: 23.6% 000101B: 24.0% 000110B: 24.4% 000111B: 24.8% 001000B: 25.2% 001001B: 25.6% 001010B: 26.0% 001011B: 26.4% 001100B: 26.8% 001101B: 27.2% (Default) 001110B: 27.6% 001111B: 28.0% 010000B: 28.4% 010001B: 28.8% 010010B: 29.2% 010011B: 29.6% 010100B: 30.0% 010101B: 30.4% 010110B: 30.8% 010111B: 31.2% 011000B: 31.6% 011001B: 32.0% 011010B: 32.4% 011011B: 32.8% 011100B: 33.2% 011101B: 33.6% 011110B: 34.0% 011111B: 34.4% 100000B: 34.8% 100001B: 35.2% 100010B: 35.6% 100011B: 36.0% 100100B: 36.4% 100101B: 36.8% 100110B: 37.2% 100111B: 37.6% 101000B: 38.0% 101001B: 38.4% 101010B: 38.8% 101011B: 39.2% 101100B: 39.6% 101101B: 40.0% 101110B: 40.4% 101111B: 40.8% 110000B: 41.2% 110001B: 41.6% 110010B: 42.0% All Others: Reserved Notes SAMSUNG vincent.chen@to-top.com.hk VREF Settings for MR12 OP[5:0] 1,2,3 NOTE: 1) These values may be used for MR12 OP[5:0] to set the VREF(CA) levels in the LPDDR4-SDRAM. 2) The range may be selected in the MR12 register by setting OP[6] appropriately. 3) The MR12 registers represents either FSP[0] or FSP[1]. Two frequency-set-points each for CA and DQ are provided to allow for faster switching between terminated and unterminated operation, or between different high-frequency setting which may use different terminations values. - 26 - Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM MR13_CBT,RPT,VRO,VRCG,RRO,DM_DIS,FSP-WR, FSP-OP (MA = 0DH): OP7 OP6 FSP-OP FSP-WR Function Register Type OP5 OP4 OP3 OP2 OP1 OP0 DMD RRO VRCG VRO RPT CBT Operand Data Notes CBT (Command Bus Training) OP[0] 0B: Normal Operation (default) 1B: Command Bus Training Mode Enabled RPT (Read Preamble Training Mode) OP[1] 0B: Disable (default) 1B: Enable VRO (VREF Output) OP[2] 0B: Normal operation (default) 1B: Output the VREF(CA) and VREF(DQ) values on DQ bits 2 VRCG (VREF Current Generator) OP[3] 0B: Normal operation (default) 1B: VREF fast response (high current) mode 3 OP[4] 0B: Disable codes 001 and 010 in MR4 OP[2:0] 1B: Enable all codes in MR4 OP[2:0] DMD (Data Mask Disable) OP[5] 0B: Data Mask Operation Enabled (default) 1B: Data Mask Operation Disabled 6 FSP-WR (Frequency Set Point Write/Read) OP[6] 0B: Frequency-Set-Point [0] (default) 1B: Frequency-Set-Point [1] 7 FSP-OP (Frequency Set Point Operation Mode) OP[7] 0B: Frequency-Set-Point [0] (default) 1B: Frequency-Set-Point [1] 8 RRO (Refresh Rate Option) Write-only 1 4,5 NOTE : 1) A write to set OP[0]=1B causes the LPDDR4-SDRAM to enter the Command Bus training mode. When OP[0]=1B and CKE goes LOW, commands are ignored and the contents of CA[5:0] are mapped to the DQ bus. CKE must be brought HIGH before doing a MRW to clear this bit (OP[0]=0B) and return to normal operation. See the Command Bus Training section for more information. 2) When set, the LPDDR4-SDRAM will output the VREF(CA) and VREF(DQ) voltages on DQ pins. Only the “active” frequency-set-point, as defined by MR13 OP[7], will be output on the DQ pins. This function allows an external test system to measure the internal VREF levels. The DQ pins used for VREF output are vendor specific. 3) When OP[3]=1B, the VREF circuit uses a high-current mode to improve VREF settling time. 4) MR13 OP[4] RRO bit is valid only when MR0 OP[0]= 1B. For LPDDR4 devices with MR0 OP[0] = 0B, MR4 OP[2:0] bits are not dependent on MR13 OP4. 5) When OP[4] = 0B, only 001B and 010B in MR4 OP[2:0] are disabled. LPDDR4 devices must report 011B instead of 001B or 010B in this case. Controller should follow the refresh mode reported by MR4 OP[2:0], regardless of RRO setting. TCSR function does not depend on RRO setting. 6) When enabled (OP[5]=0B) data masking is enabled for the device. When disabled (OP[5]=1B), masked write command is illegal. See LPDDR4 Data Mask (DM) and Data Bus Inversion (DBIdc) Function in operation timing datasheet. 7) FSP-WR determines which frequency-set-point registers are accessed with MRW commands for the following functions such as VREF(CA) Setting, VREF(CA) Range, VREF(DQ) Setting, VREF(DQ) Range. For more information, refer to Frequency Set Point section in operations and timing spec. 8) FSP-OP determines which frequency-set-point register values are currently used to specify device operation for the following functions such as VREF(CA) Setting, VREF(CA) Range, VREF(DQ) Setting, VREF(DQ) Range. For more information, refer to Frequency Set Point section in operations and timing spec. SAMSUNG vincent.chen@to-top.com.hk - 27 - Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM MR14_VREF(DQ) Setting/Range (MA = 0EH): Function OP7 OP6 (RFU) VR(DQ) Register Type VREF(DQ) (VREF(DQ) Setting) OP5 OP4 OP3 OP2 Read/Write VREF(DQ) (VREF(DQ) Range) OP[6] OP0 VREF(DQ) Operand OP[5:0] OP1 Data Notes 000000B: -- Thru . 110010B: See table below All Others: Reserved 1,2,3,5 ,6 0B: VREF(DQ) Range [0] enabled 1B: VREF(DQ) Range [1] enabled (default) 1,2,4,5 ,6 NOTE : 1) This register controls the VREF(DQ) levels for Frequency-Set-Point[1:0]. Values from either VR(DQ)[0] or VR(DQ)[1] may be selected by setting OP[6] appropriately. 2) A read (MRR) to this register places the contents of OP[7:0] on DQ[7:0]. Any RFU bits and unused DQ’s shall be set to ‘0’. See the section on MRR Operation. 3) A write to OP[5:0] sets the internal VREF(DQ) level for FSP[0] when MR13 OP[6]=0B, or sets FSP[1] when MR13 OP[6]=1B. The time required for VREF(DQ) to reach the set level depends on the step size from the current level to the new level. See the section on VREF(DQ) training for more information. 4) A write to OP[6] switches the LPDDR4-SDRAM between two internal VREF(DQ) ranges. The range (Range[0] or Range[1]) must be selected when setting the VREF(DQ) register. The value, once set, will be retained until overwritten, or until the next power-on or RESET event. 5) There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1. Only the registers for the set point determined by the state of the FSP-WR bit (MR13 OP[6]) will be written to with an MRW command to this MR address, or read from with an MRR command to this address. 6) There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1. The device will operate only according to the values stored in the registers for the active set point, i.e., the set point determined by the state of the FSP-OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be ignored by the device, and may be changed without affecting device operation. [Table 8] VREF Settings for Range[0] and Range[1] Function Operand Range[0] Values (%of VDDQ) 000000B: 10.0% 000001B: 10.4% 000010B: 10.8% 000011B: 11.2% 000100B: 11.6% 000101B: 12.0% 000110B: 12.4% 000111B: 12.8% 001000B: 13.2% 001001B: 13.6% 001010B: 14.0% 001011B: 14.4% 001100B: 14.8% 001101B: 15.2% 001110B: 15.6% 001111B: 16.0% 010000B: 16.4% 010001B: 16.8% 010010B: 17.2% 010011B: 17.6% 010100B: 18.0% 010101B: 18.4% 010110B: 18.8% 010111B: 19.2% 011000B: 19.6% 011001B: 20.0% Range[1] Values (%of VDDQ) 011010B: 20.4% 011011B: 20.8% 011100B: 21.2% 011101B: 21.6% 011110B: 22.0% 011111B: 22.4% 100000B: 22.8% 100001B: 23.2% 100010B: 23.6% 100011B: 24.0% 100100B: 24.4% 100101B: 24.8% 100110B: 25.2% 100111B: 25.6% 101000B: 26.0% 101001B: 26.4% 101010B: 26.8% 101011B: 27.2% 101100B: 27.6% 101101B: 28.0% 101110B: 28.4% 101111B: 28.8% 110000B: 29.2% 110001B: 29.6% 110010B: 30.0% All Others: Reserved 000000B: 22.0% 000001B: 22.4% 000010B: 22.8% 000011B: 23.2% 000100B: 23.6% 000101B: 24.0% 000110B: 24.4% 000111B: 24.8% 001000B: 25.2% 001001B: 25.6% 001010B: 26.0% 001011B: 26.4% 001100B: 26.8% 001101B: 27.2% (Default) 001110B: 27.6% 001111B: 28.0% 010000B: 28.4% 010001B: 28.8% 010010B: 29.2% 010011B: 29.6% 010100B: 30.0% 010101B: 30.4% 010110B: 30.8% 010111B: 31.2% 011000B: 31.6% 011001B: 32.0% 011010B: 32.4% 011011B: 32.8% 011100B: 33.2% 011101B: 33.6% 011110B: 34.0% 011111B: 34.4% 100000B: 34.8% 100001B: 35.2% 100010B: 35.6% 100011B: 36.0% 100100B: 36.4% 100101B: 36.8% 100110B: 37.2% 100111B: 37.6% 101000B: 38.0% 101001B: 38.4% 101010B: 38.8% 101011B: 39.2% 101100B: 39.6% 101101B: 40.0% 101110B: 40.4% 101111B: 40.8% 110000B: 41.2% 110001B: 41.6% 110010B: 42.0% All Others: Reserved Notes SAMSUNG vincent.chen@to-top.com.hk VREF Settings for MR14 OP[5:0] 1,2,3 NOTE: 1) These values may be used for MR14 OP[5:0] to set the VREF(DQ) levels in the LPDDR4-SDRAM. 2) The range may be selected in the MR14 register by setting OP[6] appropriately. 3) The MR14 registers represents either FSP[0] or FSP[1]. Two frequency-set-points each for CA and DQ are provided to allow for faster switching between terminated and unterminated operation, or between different high-frequency setting which may use different terminations values. - 28 - Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM MR15_Lower-Byte Invert for DQ Calibration (MA = 0FH): OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Lower-Byte Invert Register for DQ Calibration Function Register Type Operand Data Notes The following values may be written for any operand OP[7:0], and will be applied to the corresponding DQ locations DQ[7:0] within a byte lane: Lower-Byte Invert for DQ Calibration Write-only OP[7:0] 1,2,3 0B: Do not invert 1B: Invert the DQ Calibration patterns in MR32 and MR40 Default value for OP[7:0]=55H NOTE : 1) This register will invert the DQ Calibration pattern found in MR32 and MR40 for any single DQ, or any combination of DQ’s. Example: If MR15 OP[7:0]=00010101B, then the DQ Calibration patterns transmitted on DQ[7,6,5,3,1] will not be inverted, but the DQ Calibration patterns transmitted on DQ[4,2,0] will be inverted. 2) DMI[0] is not inverted, and always transmits the “true” data contained in MR32/MR40. 3) No Data Bus Inversion (DBI) function is enacted during DQ Read Calibration, even if DBI is enabled in MR3-OP[6]. [Table 9] MR15 Invert Register Pin Mapping PIN DQ0 DQ1 DQ2 DQ3 DMI0 DQ4 DQ5 DQ6 DQ7 MR15 OP0 OP1 OP2 OP3 NO-Invert OP4 OP5 OP6 OP7 MR16_PASR_Bank Mask (MA = 010H): OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 PASR Bank Mask Function Bank [7:0] Mask SAMSUNG Register Type Operand Write-only OP[7:0] Data 0B: Bank Refresh Enabled (default) : Unmasked 1B: Bank Refresh disabled : Masked vincent.chen@to-top.com.hk OP Bank Mask 8-Bank SDRAM 0 XXXXXXX1 Bank 0 1 XXXXXX1X Bank 1 2 XXXXX1XX Bank 2 3 XXXX1XXX Bank 3 4 XXX1XXXX Bank 4 5 XX1XXXXX Bank 5 6 X1XXXXXX Bank 6 7 1XXXXXXX Bank 7 NOTE : 1) When a mask bit is asserted (OP[n]=1), refresh to that bank is disabled. 2) PASR bank-masking is on a per-channel basis. The two channels on the die may have different bank masking in dual channel devices. - 29 - Notes 1 Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM MR17_PASR Segment Mask (MA = 011H): for x16 mode OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 PASR Segment Mask Function PASR Segment Mask Segment OP Register Type Operand Write-only OP[7:0] Segment Mask Data Notes 0B: Segment Refresh enabled (default) 1B: Segment Refresh disabled 2Gb per channel 3Gb per channel 4Gb per channel 6Gb per channel 8Gb per channel 12Gb per channel 16Gb per channel R13:11 R14:12 R14:12 R15:13 R15:13 R16:14 R16:14 110B Not Allowed 110B 0 0 XXXXXXX1 000B 1 1 XXXXXX1X 001B 2 2 XXXXX1XX 010B 3 3 XXXX1XXX 011B 4 4 XXX1XXXX 100B 5 5 XX1XXXXX 101B 6 6 X1XXXXXX 110B 7 7 1XXXXXXX 111B Not Allowed 110B 111B Not Allowed 111B 111B NOTE : 1) This table indicates the range of row addresses in each masked segment. "X" is don’t care for a particular segment. 2) PASR segment-masking is on a per-channel basis. The two channels on the die may have different segment masking in dual channel devices. 3) For 3Gb, 6Gb and 12Gb per channel densities, OP[7:6] must always be LOW (=00B). SAMSUNG MR18_IT-LSB (MA = 12H) : OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 vincent.chen@to-top.com.hk DQS Oscillator Count-LSB Function DQS Oscillator (WR Training DQS Oscillator) Register Type Operand Read-only OP[7:0] Data Notes 0-255 LSB DRAM DQS Oscillator Count 1,2,3 NOTE : 1) MR18 reports the LSB bits of the DRAM DQS Oscillator count. The DRAM DQS Oscillator count value is used to train DQS to the DQ data valid window. The value reported by the DRAM in this mode register can be used by the memory controller to periodically adjust the phase of DQS relative to DQ. 2) Both MR18 and MR19 must be read (MRR) and combined to get the value of the DQS Oscillator count. 3) A new MPC [Start DQS Oscillator] should be issued to reset the contents of MR18/MR19. MR19_IT-MSB (MA = 13H) : OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 DQS Oscillator Count-MSB Function DQS Oscillator (WR Training DQS Oscillator) Register Type Operand Read-only OP[7:0] Data 0-255 MSB DRAM DQS Oscillator Count Notes 1,2,3 NOTE : 1) MR19 reports the MSB bits of the DRAM DQS Oscillator count. The DRAM DQS Oscillator count value is used to train DQS to the DQ data valid window. The value reported by the DRAM in this mode register can be used by the memory controller to periodically adjust the phase of DQS relative to DQ. 2) Both MR18 and MR19 must be read (MRR) and combined to get the value of the DQS Oscillator count. 3) A new MPC [Start DQS Oscillator] should be issued to reset the contents of MR18/MR19. - 30 - Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM MR20_Upper-Byte Invert for DQ Calibration (MA = 14H): OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Upper-Byte Invert Register for DQ Calibration Function Register Type Operand Data Notes The following values may be written for any operand OP[7:0], and will be applied to the corresponding DQ locations DQ[15:8] within a byte lane: Upper-Byte Invert for DQ Calibration Write-only OP[7:0] 1,2 0B: Do not invert 1B: Invert the DQ Calibration patterns in MR32 and MR40 Default value for OP[7:0] = 55H NOTE: 1) This register will invert the DQ Calibration pattern found in MR32 and MR40 for any single DQ, or any combination of DQ’s. Example: If MR20 OP[7:0]=00010101B, then the DQ Calibration patterns transmitted on DQ[15,14,13,11,9] will not be inverted, but the DQ Calibration patterns transmitted on DQ[12,10,8] will be inverted. 2) DMI[1] is not inverted, and always transmits the “true” data contained in MR32/MR40. 3) No Data Bus Inversion (DBI) function is enacted during DQ Read Calibration, even if DBI is enabled in MR3-OP[6]. [Table 10] MR20 Invert Register Pin Mapping PIN DQ8 DQ9 DQ10 DQ11 DMI1 DQ12 DQ13 DQ14 DQ15 MR20 OP0 OP1 OP2 OP3 NO-Invert OP4 OP5 OP6 OP7 MR21_(RFU) (MA = 015H): SAMSUNG vincent.chen@to-top.com.hk - 31 - Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM MR22_ODT Feature (MA = 16H): OP7 OP6 (RFU) Function Register Type SoC ODT (Controller ODT Value for VOH calibration) ODTE-CK (CK ODT enabled for non-terminating rank) OP5 OP4 OP3 ODTDCA ODTECS ODTECK Operand OP[2:0] Write-only OP2 OP1 OP0 SoC ODT Data 000B: Disable (Default) 001B: RZQ/1 010B: RZQ/2 011B: RZQ/3 100B: RZQ/4 101B: RZQ/5 110B: RZQ/6 111B: RFU Notes 1,2,3 OP[3] 0B : ODT-CK Over-ride Disabled (Default) 1B : ODT-CK Over-ride Enabled 2,3,4,6 ,8 ODTE-CS (CS ODT enable for nonterminating rank) OP[4] 0B: ODT-CS Over-ride Disabled (Default) 1B: ODT-CS Over-ride Enabled 2,3,5,6 ,8 ODTD-CA (CA ODT termination disable) OP[5] 0B: ODT-CA Obeys ODT_CA bond pad (default) 1B: ODT-CA Disabled 2,3,6,7 ,8 NOTE : 1) All values are “typical”. 2) There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1. Only the registers for the set point determined by the state of the FSP-WR bit (MR13 OP[6]) will be written to with an MRW command to this MR address, or read from with an MRR command to this address. 3) There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1. The device will operate only according to the values stored in the registers for the active set point, i.e., the set point determined by the state of the FSP-OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be ignored by the device, and may be changed without affecting device operation. 4) When OP[3]=1B, then the CK signals will be terminated to the value set by MR11 OP[6:4] regardless of the state of the ODT_CA bond pad. This overrides the ODT_CA bond pad for configurations where CA is shared by two or more DRAMs but CK is not, allowing CK to terminate on all DRAMs. 5) When OP[4]=1B, then the CS signal will be terminated to the value set by MR11 OP[6:4] regardless of the state of the ODT_CA bond pad. This overrides the ODT_CA bond pad for configurations where CA is shared by two or more DRAMs but CS is not, allowing CS to terminate on all DRAMs. 6) For system configurations where the CK, CS, and CA signals are shared between packages, the package design should provide for the ODT_CA ball to be bonded on the system board outside of the memory package. This provides the necessary control of the ODT function for all die with shared Command Bus signals. 7) When OP[5]=0B, CA[5:0] will terminate when the ODT_CA bond pad is HIGH and MR11 OP[6:4] is VALID, and disables termination when ODT_CA is LOW or MR11-OP[6:4] is disabled. When OP[5]=1B, termination for CA[5:0] is disabled, regardless of the state of the ODT_CA bond pad or MR11 OP[6:4]. 8) To ensure proper operation in a multi-rank configuration, when CA, CK or CS ODT is enabled via MR11 OP[6:4] and also via MR22 or CA-ODT pad setting, the rank providing ODT will continue to terminate the command bus in all DRAM states including Active Self-refresh, Self-refresh Power-down, Active Power-down and Precharge Powerdown. SAMSUNG vincent.chen@to-top.com.hk - 32 - Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM MR23_DQS Interval Timer Run Time (MA = 17H): OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 DQS interval timer run time setting Function Register Type Operand Data Notes 00000000B: DQS interval timer stop via MPC Command (Default) 00000001B: DQS timer stops automatically at 16th clocks after timer start 00000010B: DQS timer stops automatically at 32nd clocks after timer start 00000011B: DQS timer stops automatically at 48th clocks after timer start DQS interval timer run time Write-only 00000100B: DQS timer stops automatically at 64th clocks after timer start -------------- Thru ---------------------- OP[7:0] 1,2 00111111B: DQS timer stops automatically at (63X16)th clocks after timer start 01XXXXXXB: DQS timer stops automatically at 2048th clocks after timer start 10XXXXXXB: DQS timer stops automatically at 4096th clocks after timer start 11XXXXXXB: DQS timer stops automatically at 8192nd clocks after timer start NOTE : 1) MPC command with OP[6:0]=1001101B (Stop DQS Interval Oscillator) stops DQS interval timer in case of MR23 OP[7:0] = 00000000B. 2) MPC command with OP[6:0]=1001101B (Stop DQS Interval Oscillator) is illegal with non-zero values in MR23 OP[7:0]. MR24_TRR (MA = 18H): OP7 TRR Mode Function OP6 OP5 OP4 OP3 OP2 TRR mode BAn OP0 MAC Value SAMSUNG Register Type Operand Data 000B: Unknown when bit OP3 =0 1) Unlimited when bit OP3=1 2) 001B: 700K 010B: 600K 011B: 500K 100B: 400K 101B: 300K 110B: 200K 111B: Reserved vincent.chen@to-top.com.hk MAC Value OP[2:0] Read-only Unlimited MAC OP[3] TRR Mode BAn OP[6:4] Write-only TRR Mode OP1 Unlimited MAC OP[7] 0B: OP[2:0] define MAC value 1B: Unlimited MAC value 2), 3) 000B: Bank 0 001B: Bank 1 010B: Bank 2 011B: Bank 3 100B: Bank 4 101B: Bank 5 110B: Bank 6 111B: Bank 7 0B: Disabled (default) 1B: Enabled NOTE : 1) Unknown means that the device is not tested for tMAC and pass/fail value in unknown. 2) There is no restriction to number of activates. 3) MR24 OP [2:0] is set to ZERO. - 33 - Notes Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM MR25_PPR Resources (MA = 19H): Mode Register 25 contains one bit of readout per bank indicating that at least one resource is available for Post Package Repair programming. Function PPR Resource OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Bank 7 Bank 6 Bank 5 Bank 4 Bank 3 Bank 2 Bank 1 Bank 0 Register Type Read-only Operand Data Notes 0B : PPR Resource is not available 1B : PPR Resource is available OP[7:0] MR26-29_(RFU) (MA = 1AH - 1DH): MR30_Reserved for Testing (MA = 1EH): OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Valid 0 or 1 Function Register Type Operand SDRAM will ignore Write-only OP[7:0] Data Notes Don’t care 1 NOTE : 1) This register is reserved for testing purposes. The logical data values written to OP[7:0] shall have no effect on SDRAM operation, however timings need to be observed as for any other MR access command. MR31_(RFU) (MA = 1FH): SAMSUNG MR32_DQ Calibration Pattern A (MA=20H): OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 vincent.chen@to-top.com.hk DQ Calibration Pattern “A” (default = 5AH) Function Return DQ Calibration Pattern MR32 + MR40 Register Type Write Operand Data Notes OP[7:0] XB: An MPC command with OP[6:0]=1000011B causes the device to return the DQ Calibration Pattern contained in this register and (followed by) the contents of MR40. A default pattern “5AH” is loaded at power-up or RESET, or the pattern may be overwritten with a MRW to this register. The contents of MR15 and MR20 will invert the data pattern for a given DQ (See MR15 for more information) MR33:38_(Do Not Use) (MA = 21H-26H): MR39_Reserved for Testing (MA = 27H): OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Valid 0 or 1 Function Register Type Operand SDRAM will ignore Write-only OP[7:0] Data Don’t care Notes 1 NOTE : 1) This register is reserved for testing purposes. The logical data values written to OP[7:0] shall have no effect on SDRAM operation, however timings need to be observed as for any other MR access command. - 34 - Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM MR40_DQ Calibration Pattern B (MA=28H): OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 DQ Calibration Pattern “B” (default = 3CH) Function Return DQ Calibration Pattern MR32 + MR40 Register Type Write-only Operand Data Notes OP[7:0] XB: A default pattern “3CH” is loaded at power-up or RESET, or the pattern may be overwritten with a MRW to this register. See MR32,for more information. 1,2,3 NOTE : 1) The pattern contained in MR40 is concatenated to the end of MR32 and transmitted on DQ[15:0] and DMI[1:0] when DQ Read Calibration is initiated via a MPC command. The pattern transmitted serially on each data lane, organized “little endian” such that the low-order bit in a byte is transmitted first. If the data pattern in MR40 is 27H, then the first bit transmitted with be a ‘1’, followed by ‘1’, ‘1’, ‘0’, ‘0’, ‘1’, ‘0’, and ‘0’. The bit stream will be 00100111B. 2) MR15 and MR20 may be used to invert the MR32/MR40 data patterns on the DQ pins. See MR15 and MR22 for more information. Data is never inverted on the DMI[1:0] pins. 3) The data pattern is not transmitted on the DMI[1:0] pins if DBI-RD is disabled via MR3 OP[6]. 4) No Data Bus Inversion (DBI) function is enacted during DQ Read Calibration, even if DBI is enabled in MR3 OP[6]. MR41:47_ (Do Not Use)(MA = 29H-2FH): MR48:50_(RFU) (MA = 30H - 32H) : MR51_Single Ended RDQS, WDQS, Clock (MA = 33H) : OP7 OP6 OP5 (RFU) Function Single ended RDQS Single ended WDQS OP4 OP3 OP2 OP1 OP0 Single ended Clock Single ended WDQS Single ended RDQS (RFU) SAMSUNG Register Type Operand Notes 1,2,3,4 ,5, vincent.chen@to-top.com.hk OP[2] 0B: Differential Write DQS (Default) 1B: Single ended Write DQS 1,2,3,4 ,6 OP[3] 0B: Differential Clock (Default), CK_t /CK_c 1B: Single ended Clock, Only CK_t 1,2,3,4 ,7 OP[1] Write-only Data 0B: Differential Read DQS (Default) 1B: Single ended Read DQS Single ended Clock NOTE : 1) The features described in MR51 are optional. Please check the vendor for the availability. 2) Device support for single ended mode features (MR51 OP[3:1]) is indicated in MR0 OP[5] 3) There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1. Only the registers for the set point determined by the state of the FSP-WR bit (MR13 OP[6]) will be written to with an MRW command to this MR address. 4) There are two physical registers assigned to each bit of this MR parameter, designated set point 0 and set point 1. The device will operate only according to the values stored in the registers for the active set point, i.e., the set point determined by the state of the FSP-OP bit (MR13 OP[7]). The values in the registers for the inactive set point will be ignored by the device, and may be changed without affecting device operation. 5) When single ended RDQS mode is enabled (MR51 OP[1] =1b), DRAM drives Read DQSB low or Hi-Z. 6) When single ended WDQS mode is enabled (MR51 OP[2] =1b), Write DQSB is required to be at a valid logic level. A valid Write DQSB signal will meet this requirement. 7) When single ended Clock mode is enabled (MR51 OP[3] =1b), CK_c is required to be the valid level required to be at a valid logic level. A valid CK_c signal will meet this requirement. When DRAM is operating with single-ended mode, both CLKB and write DQSB shall be on "Low" state at all times whereas read DQSB is always on "HiZ" state. Refer to the table below. CLK Write DQS Read DQS Differential Mode Single-Ended Mode CLK Valid Valid CLKB Valid 0 DQS Valid Valid DQSB Valid 0 DQS Valid Valid DQSB Valid Hi-Z MR52:63_(RFU) (MA = 34H - 3FH) : - 35 - Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM 6.0 TRUTH TABLES Operation or timing that is not specified is illegal, and after such an event, in order to guarantee proper operation, the LPDDR4 device must be reset or power-cycled and then restarted through the specified initialization sequence before normal operation can continue. CKE signal has to be held High when the commands listed in the command truth table input. [Table 11] Command truth table SDR Command Pins SDR CA pins (6) SDRAM Command CS Deselect (DES) L Multi-Purpose Command (MPC) H L L L L L OP6 R1 L OP0 OP1 OP2 OP3 OP4 OP5 R2 Precharge (PRE) (Per Bank, All Bank) H L L L L H AB R1 L BA0 BA1 BA2 V V V R2 Refresh (REF) (Per Bank, All Bank) H L L L H L AB R1 L BA0 BA1 BA2 V V V R2 H L L L H H V R1 Self Refresh Entry (SRE) Write-1 (WR-1) Self Refresh Exit (SRX) Mask Write-1 (MWR-1) RFU Read-1 (RD-1) CAS-2 (Write-2, Mask Write-2, Read-2, MRR-2, MPC) RFU RFU CA0 CA1 CA2 CA3 CA4 CA5 X L V CK_t edge Notes R1 1,2 R2 H L L H L L BL R1 L BA0 BA1 BA2 V C9 AP R2 H L L H L H V R1 V L R2 H L L H H L L R1 L BA0 BA1 BA2 V C9 AP R2 H L L H H H V R1 SAMSUNG V L R2 H L H L L L BL R1 L BA0 BA1 BA2 V C9 AP R2 L H L L H C8 R1 L C2 C3 C4 C5 C6 C7 R2 H L H L H L V R1 H vincent.chen@to-top.com.hk L H V L H L R2 H H V V L R1 R2 Mode Register Write-1 (MRW-1) H L H H L L OP7 R1 L MA0 MA1 MA2 MA3 MA4 MA5 R2 Mode Register Write-2 (MRW-2) H L H H L H OP6 R1 L OP0 OP1 OP2 OP3 OP4 OP5 R2 Mode Register Read-1 (MRR-1) H L H H H L V R1 L MA0 MA1 MA2 MA3 MA4 MA5 R2 H L H H H H V R1 RFU Activate-1 (ACT-1) Activate-2 (ACT-2) V L R2 H H L R12 R13 R14 R15 R1 L BA0 BA1 BA2 V R10 R11 R2 H H H R6 R7 R8 R9 R1 L R0 R1 R2 R3 R4 R5 R2 - 36 - 1,9 1,2,3,4 1,2,3,4 1,2 1,2,3,6,7,9 1,2 1,2,3,5,6,9 1,2 1,2,3,6,7,9 1,8,9 1,2 1,2 1,11 1,11 1,2,12 1,2 1,2,3,10 1,10,13 K4F6E3S4HM-MGCJ datasheet Rev. 1.0 LPDDR4 SDRAM NOTE: 1) All LPDDR4 commands except for Deselect are 2 clock cycle long and defined by states of CS and CA[5:0] at the first rising edge of clock. Deselect command is 1 clock cycle long. 2) “V” means “H” or “L” (a defined logic level). “X” means don’t care in which case CA[5:0] can be floated. 3) Bank addresses BA[2:0] determine which bank is to be operated upon. 4) AB “HIGH” during Precharge or Refresh command indicates that command must be applied to all banks and bank address is a don’t care. 5) Mask Write-1 command supports only BL 16. For Mark Write-1 command, CA5 must be driven LOW on first rising clock cycle (R1). 6) AP “HIGH” during Write-1, Mask Write-1 or Read-1 commands indicates that an auto-precharge will occur to the bank associated with the Write, Mask Write or Read command. 7) If Burst Length on-the-fly is enabled, BL “HIGH” during Write-1 or Read-1 command indicates that Burst Length should be set on-the-Fly to BL=32. BL “LOW” during Write-1 or Read-1 command indicates that Burst Length should be set on-the-fly to BL=16. If Burst Length on-the-fly is disabled, then BL must be driven to defined logic level “H” or “L”. 8) For CAS-2 commands (Write-2 or Mask Write-2 or Read-2 or MRR-2 or MPC (Only Write FIFO, Read FIFO & Read DQ Calibration), C[1:0] are not transmitted on the CA[5:0] bus and are assumed to be zero. Note that for CAS-2 Write-2 or CAS-2 Mask Write-2 command, C[3:2] must be driven LOW. 9) Write-1 or Mask Write-1 or Read-1 or Mode Register Read-1 or MPC (Only Write FIFO, Read FIFO & Read DQ Calibration) command must be immediately followed by CAS2 command consecutively without any other command in between. Write-1 or Mask Write-1 or Read-1 or mode register Read-1 or MPC (Only Write FIFO, Read FIFO & Read DQ Calibration) command must be issued first before issuing CAS-2 command. MPC (Only Start & Stop DQS Oscillator, Start & Latch ZQ Calibration) commands do not require CAS-2 command; they require two additional DES or NOP commands consecutively before issuing any other commands. 10) Activate-1 command must be immediately followed by Activate-2 command consecutively without any other command in between. Activate-1 command must be issued first before issuing Activate-2 command. Once Activate-1 command is issued, Activate-2 command must be issued before issuing another Activate-1 command. 11) MRW-1 command must be immediately followed by MRW-2 command consecutively without any other command in between. MRW-1 command must be issued first before issuing MRW-2 command. 12) MRR-1 command must be immediately followed by CAS-2 command consecutively without any other command in between. MRR-1 command must be issued first before issuing CAS-2 command. SAMSUNG vincent.chen@to-top.com.hk - 37 - datasheet K4F6E3S4HM-MGCJ Rev. 1.0 LPDDR4 SDRAM 6.1 CKE Truth Tables [Table 12] LPDDR4 : CKE Table 1), 2), 3), 4), 8) CKEn-1 CKEn Command n Operation Device Next State L L X Maintain Active Power Down Active Power Down L H Deselect Exit Active Power Down Active L L X Maintain Idle Power Down Idle Power Down L H Deselect Exit Idle Power Down Idle L L X Maintain power-down state within Self Refresh Self Refresh L H Deselect Exit SREF power-down, enable command decode Self Refresh 5,6,7 H L Deselect Enter SREF Power-Down, disable command decode Self Refresh 5,7 H H See Note 7 See Note 7 Self Refresh 7 Bank(s) Active H L Deselect Enter Active Power Down Active Power Down 5 All Banks Idle H L Deselect Enter Idle Power Down Idle Power Down 5, 8 Command Entry H H Device Current State Active Power Down Notes 5,6 Idle Power Down Self Refresh 5,6 Refer to the Command Truth Table SAMSUNG NOTE : 1) CKE is a strictly asynchronous input, and as such, has no relationship to CK. 2) “X” means “don’t care.” 3) “Current State” is the state of the LPDDR4-SDRAM prior to a toggle of CKE. 4) “CKEn-1” is the logic state of CKE prior to a CKE toggle event, and “CKEn” is the state of CKE after the toggle event. 5) “Deselect” is the only valid command that can be present on the bus when CKE is toggled. 6) Power-Down exit time (tXP) should elapse before a command other than Deselect is issued. The clock must toggle at least twice during the tXP period, and must be stable before issuing a command. 7) When the device is in Self.Refresh, only MRR, MRW, or MPC commands are allowed. Certain restrictions apply to changing register contents via a MRW command during SREF. See MRW section for more information. 8) In the case of ODT disabled, all DQ output shall be Hi-Z. In the case of ODT enabled, all DQ shall be terminated to VSSQ. vincent.chen@to-top.com.hk - 38 - datasheet K4F6E3S4HM-MGCJ Rev. 1.0 LPDDR4 SDRAM 6.2 State Truth Table The truth tables provide complementary information to the state diagram, they clarify the device behavior and the applied restrictions when considering the actual state of all banks. [Table 13] Current State Bank n - Command to Bank n Current State Command Any NOP ACTIVATE Idle Active Refreshing (Per Bank) 6 Refresh (All Bank) Begin to refresh Refreshing (All Bank) 7 MR Writing 7 MRW Write value to Read value from Idle MR Reading Deactivate row in bank or banks Precharging 8, 13 Read Select column, and start read burst Reading 10 Write Select column, and start write burst Writing 10 MRR Precharge Writing NOTES Begin to refresh MRR Reading Select and activate row Next State Current State Refresh (Per Bank) Precharge Row Active Operation Continue previous operation Read value from Active MR Reading Deactivate row in bank or banks Read Select column, and start new read burst Write Select column, and start write burst Write Select column, and start new write burst Read Select column, and start read burst Precharging 8 Reading 9, 10 Writing 9, 10, 11 Writing 9, 10 Reading 9, 10, 12 NOTE : 1) The table applies when both CKEn-1 and CKEn are HIGH, and after tXSR or tXP has been met if the previous state was Self Refresh or Power Down. 2) All states and sequences not shown are illegal or reserved. 3) Current State Definitions: - Idle: The bank or banks have been precharged, and tRP has been met. - Active: A row in the bank has been activated, and tRCD has been met. No data bursts / accesses and no register accesses are in progress. - Reading: A Read burst has been initiated, with Auto Precharge disabled. - Writing: A Write burst has been initiated, with Auto Precharge disabled. 4) The following states must not be interrupted by a command issued to the same bank. NOP commands or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other banks are determined by its current state and , and according to . - Precharging: starts with the registration of a Precharge command and ends when tRP is met. Once tRP is met, the bank will be in the idle state. - Row Activating: starts with registration of an Activate command and ends when tRCD is met. Once tRCD is met, the bank will be in the ‘Active’ state. - Read with AP Enabled: starts with the registration of the Read command with Auto Precharge enabled and ends when tRP has been met. Once tRP has been met, the bank will be in the idle state. - Write with AP Enabled: starts with registration of a Write command with Auto Precharge enabled and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. 5) The following states must not be interrupted by any executable command; NOP commands must be applied to each positive clock edge during these states. - Refreshing (Per Bank): starts with registration of a Refresh (Per Bank) command and ends when tRFCpb is met. Once tRFCpb is met, the bank will be in an ‘idle’ state. - Refreshing (All Bank): starts with registration of an Refresh (All Bank) command and ends when tRFCab is met. Once tRFCab is met, the device will be in an ‘all banks idle’ state. - Idle MR Reading: starts with the registration of a MRR command and ends when tMRR has been met. Once tMRR has been met, the bank will be in the Idle state. - Active MR Reading: starts with the registration of a MRR command and ends when tMRR has been met. Once tMRR has been met, the bank will be in the Active state. - Idle MR Writing: starts with the registration of a MRW command and ends when tMRW has been met. Once tMRW has been met, the bank will be in the Idle state. - Active MR Writing: starts with the registration of a MRW command and ends when tMRW has been met. Once tMRW has been met, the bank will be in the Active state. - Precharging All: starts with the registration of a Precharge-All command and ends when tRP is met. Once tRP is met, the bank will be in the idle state. 6) Bank-specific; requires that the bank is idle and no bursts are in progress. 7) Not bank-specific; requires that all banks are idle and no bursts are in progress. 8) This command may or may not be bank specific. If all banks are being precharged, they must be in a valid state for precharging. 9) A command other than NOP should not be issued to the same bank while a Read or Write burst with Auto Precharge is enabled. 10) The new Read or Write command could be Auto Precharge enabled or Auto Precharge disabled. 11) A Write command may be applied after the completion of the Read burst; burst terminates are not permitted. 12) A Read command may be applied after the completion of the Write burst, burst terminates are not permitted. 13) If a Precharge command is issued to a bank in the Idle state, tRP shall still apply. SAMSUNG vincent.chen@to-top.com.hk - 39 - datasheet K4F6E3S4HM-MGCJ Rev. 1.0 LPDDR4 SDRAM [Table 14] Current State Bank n - Command to Bank m Current State of Bank n Command for Bank m Any NOP Continue previous operation Idle Any Any command allowed to Bank m Activate Read Row Activating, Active, or Precharging Reading (Autoprecharge disabled) Write Precharge Select column, and start read burst from Bank m Write Select column, and start write burst to Bank m Select and activate row in Bank m Deactivate row in bank or banks Read Select column, and start read burst from Bank m Write Select column, and start write burst to Bank m Activate Select and activate row in Bank m Deactivate row in bank or banks Read Select column, and start read burst from Bank m Write Select column, and start write burst to Bank m Activate Precharge Writing/Masked Writing with Autoprecharge Select column, and start write burst to Bank m Deactivate row in bank or banks Read Precharge Reading with Autoprecharge Select and activate row in Bank m Select column, and start read burst from Bank m Read value from Activate Next State for Bank m Select and activate row in Bank m Deactivate row in bank or banks Active 6 Reading 7 Writing 7 Precharging 8 Idle MR Reading or Active MR Reading 9,10, Reading 7 Writing 7,12 Active Precharging 8 Reading 7,14 Writing 7 Active Precharging Select column, and start read burst from Bank m Write Select column, and start write burst to Bank m Activate Select and activate row in Bank m 7,13 Writing 7,12,13 Active Precharging 8 Reading 7,13,14 Writing 7,13 Active vincent.chen@to-top.com.hk Deactivate row in bank or banks 8 Reading SAMSUNG Read Precharge NOTES Current State of Bank m MRR Precharge Writing/Masked Writing (Autoprecharge disabled) Operation Precharging 8 NOTE : 1) The table applies when both CKEn-1 and CKEn are HIGH, and after tXSR or tXP has been met if the previous state was Self Refresh or Power Down. 2) All states and sequences not shown are illegal or reserved. 3) Current State Definitions: - Idle: The bank has been precharged, and tRP has been met. - Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. - Reading: A Read burst has been initiated, with Auto Precharge disabled. - Writing: A Write burst has been initiated, with Auto Precharge disabled 4) Refresh, Self-Refresh, and Mode register Write commands may only be issued when all bank are idle. 5) The following states must not be interrupted by any executable command; NOP commands must be applied during each clock cycle while in these states: - Idle MR Reading: starts with the registration of a MRR command and ends when tMRR has been met. Once tMRR has been met, the bank will be in the Idle state. - Active MR Reading: starts with the registration of a MRR command and ends when tMRR has been met. Once tMRR has been met, the bank will be in the Active state. - Idle MR Writing: starts with the registration of a MRW command and ends when tMRW has been met. Once tMRW has been met, the bank will be in the Idle state. - Active MR Writing: starts with the registration of a MRW command and ends when tMRW has been met. Once tMRW has been met, the bank will be in the Active state. 6) tRRD must be met between Activate command to Bank n and a subsequent Activate command to Bank m. Additionally, in the case of multiple banks activated, tFAW must be satisfied. 7) Reads or Writes listed in the Command column include Reads and Writes with Auto Precharge enabled and Reads and Writes with Auto Precharge disabled. 8) This command may or may not be bank specific. If all banks are being precharged, they must be in a valid state for precharging. 9) MRR is allowed during the Row Activating state (Row Activating starts with registration of an Activate command and ends when tRCD is met.) 10) MRR is allowed during the Precharging state. (Precharging starts with registration of a Precharge command and ends when tRP is met.) 11) The next state for Bank m depends on the current state of Bank m (Idle, Row Activating, Precharging, or Active). The reader shall note that the state may be in transition when a MRR is issued. Therefore, if Bank m is in the Row Activating state and Precharging, the next state may be Active and Precharge dependent upon tRCD and tRP respectively. 12) A Write command may be applied after the completion of the Read burst, burst terminates are not permitted. 13) Read with auto precharge enabled or a Write with Auto Precharge enabled may be followed by any valid command to other banks provided that the timing restrictions described in the Precharge & Auto Precharge clarification table are followed. 14) A Read command may be applied after the completion of the Write burst, burst terminates are not permitted. - 40 - Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM 7.0 ABSOLUTE MAXIMUM DC RATINGS Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. [Table 15] Absolute Maximum DC Ratings Symbol Min Max Units Notes VDD1 supply voltage relative to VSS Parameter VDD1 -0.4 2.1 V 1 VDD2 supply voltage relative to VSS VDD2 -0.4 1.5 V 1 VDDQ supply voltage relative to VSSQ VDDQ -0.4 1.5 V 1 VIN, VOUT -0.4 1.5 V TSTG -55 125 C Voltage on any ball except VDD1 relative to VSS Storage Temperature 2 NOTE : 1) See Power Ramp for relationships between power supplies. 2) Storage Temperature is the case surface temperature on the center/top side of the LPDDR4 device. For the measurement conditions, please refer to JESD51-2 standard. SAMSUNG vincent.chen@to-top.com.hk - 41 - Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM 8.0 AC & DC OPERATING CONDITIONS 8.1 Recommended DC Operating Conditions [Table 16] Recommended DC Operating Conditions Symbol DRAM VDD1 LPDDR4 Unit Notes 1.95 V 1,2 1.10 1.17 V 1,2,3 1.10 1.17 V 2,3 Min Typ Max Core 1 Power 1.70 1.80 VDD2 Core 2 Power / Input Buffer Power 1.06 VDDQ I/O Buffer Power 1.06 NOTE : 1) VDD1 uses significantly less current than VDD2. 2) The voltage range is for DC voltage only. DC is defined as the voltage supplied at the DRAM and is inclusive of all noise up to 20MHz at the DRAM package ball. 3) VdIVW and TdIVW limits described elsewhere in this document apply for voltage noise on supply voltages of up to 45mV (peak-to-peak) from DC to 20MHz. 8.2 Input Leakage Current [Table 17] Input Leakage Current Parameter/Condition Symbol Min Max Unit Notes Input Leakage current IL -4 4 uA 1,2 NOTE : 1) For CK_t, CK_c, CKE, CS, CA, ODT_CA and RESET_n. Any input 0V ≤ VIN ≤ VDD2 (All other pins not under test = 0V). 2) CA ODT is disabled for CK_t, CK_c, CS, and CA. 8.3 Input/Output Leakage Current SAMSUNG [Table 18] Input/Output Leakage Current Parameter/Condition Symbol Min. Max. Unit Notes Input/Output Leakage current IOZ -5 5 uA 1,2 vincent.chen@to-top.com.hk NOTE : 1) For DQ, DQS_t, DQS_c and DMI. Any I/O 0V ≤ VOUT ≤ VDDQ. 2) I/Os status are disabled: High Impedance and ODT Off. 8.4 Operating Temperature Range [Table 19] Operating Temperature Range Parameter/Condition Symbol Min Max Unit Standard TOPER -25 85 C NOTE : 1) Operating Temperature is the case surface temperature on the center top side of the LPDDR4 device. For the measurement conditions, please refer to JESD51-2. 2) Either the device case temperature rating or the temperature sensor (See "Temperature Sensor" on [Command Definition & Timing Diagram]) may be used to set an appropriate refresh rate, determine the need for AC timing de-rating and/or monitor the operating temperature. When using the temperature sensor, the actual device case temperature may be higher than the TOPER rating that applies for the Standard or Extended Temperature Ranges. For example, TCASE may be above 85C when the temperature sensor indicates a temperature of less than 85C. - 42 - Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM 9.0 AC AND DC INPUT/OUTPUT MEASUREMENT LEVELS 9.1 1.1V High speed LVCMOS (HS_LLVCMOS) 9.1.1 Standard specifications All voltages are referenced to ground except where noted. 9.1.2 DC electrical characteristics 9.1.2.1 LPDDR4 Input Level for CKE This definition applies to CKE_A/B. [Table 20] LPDDR4 Input Level for CKE Parameter Symbol Min. Max. Unit Note Input high level (AC) VIH(AC) 0.75 × VDD2 VDD2 + 0.2 V 1 Input low level (AC) VIL(AC) -0.2 0.25 × VDD2 V 1 Input high level (DC) VIH(DC) 0.65 × VDD2 VDD2 + 0.2 V Input low level (DC) VIL(DC) -0.2 0.35 × VDD2 V NOTE : 1) Refer LPDDR4 AC Over/Undershoot section. SAMSUNG Figure 3. LPDDR4 Input AC timing definition for CKE 1-1). AC level is guaranteed transition point. 1-2). DC level is hysteresis. 9.1.2.2 LPDDR4 Input Level for Reset_n and ODT_CA vincent.chen@to-top.com.hk This definition applies to Reset_n and ODT_CA. [Table 21] LPDDR4 Input Level for Reset_n and ODT_CA Parameter Symbol Min. Input high level VIH 0.80 × VDD2 VDD2 + 0.2 V 1 Input low level VIL -0.2 0.20× VDD2 V 1 NOTE : 1) Refer LPDDR4 AC Over/Undershoot section. Figure 4. LPDDR4 Input AC timing definition for Reset_n and ODT_CA - 43 - Max. Unit Note datasheet K4F6E3S4HM-MGCJ Rev. 1.0 LPDDR4 SDRAM 9.1.3 AC Over/Undershoot 9.1.3.1 LPDDR4 AC Over/Undershoot [Table 22] LPDDR4 AC Over/Undershoot Parameter Specification Maximum peak amplitude allowed for overshoot area. 0.35V Maximum peak amplitude allowed for undershoot area. 0.35V Maximum overshoot area above VDD/VDDQ. 0.8V-ns Maximum undershoot area below VSS/VSSQ. 0.8V-ns Maximum Amplitude Overshoot Area VDD Volts VSS (V) Maximum Amplitude Undershoot Area Time (ns) SAMSUNG Figure 5. AC Overshoot and Undershoot Definition for Address and Control Pins vincent.chen@to-top.com.hk - 44 - Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM 9.2 Differential Input Voltage 9.2.1 Differential Input Voltage for CK The minimum input voltage need to satisfy both Vindiff_CK and Vindiff_CK /2 specification at input receiver and their measurement period is 1tCK. Vindiff_CK is the peak to peak voltage centered on 0 volts differential and Vindiff_CK /2 is max and min peak voltage from 0V. Figure 6. CK Differential Input Voltage SAMSUNG [Table 23] CK differential input voltage Data Rate Parameter CK differential input voltage Symbol 1600/1866 a) 2133/2400/3200 3733 Min Max Min Max Min Max 420 - 380 - 360 - vincent.chen@to-top.com.hk Vindiff_CK NOTE: 1) The peak voltage of Differential CK signals is calculated in a following equation. Vindiff_CK = (Max Peak Voltage) - (Min Peak Voltage) Max Peak Voltage = Max(f(t)) Min Peak Voltage = Min(f(t)) f(t) = VCK_t - VCK_c a) The following requirements apply for DQ operating frequencies at or below 1333Gbps for all speed bins for the first column 1600/1866. - 45 - Unit Note mV 1 datasheet K4F6E3S4HM-MGCJ Rev. 1.0 LPDDR4 SDRAM 9.2.2 Peak voltage calculation method The peak voltage of Differential Clock signals are calculated in a following equation. VIH.DIFF.Peak Voltage = Max(f(t)) VIL.DIFF.Peak Voltage = Min(f(t)) f(t) = VCK_t - VCK_c SAMSUNG Figure 7. Definition of differential Clock Peak Voltage NOTE: 1) VREFCA is LPDDR4 SDRAM internal setting value by VREF Training. vincent.chen@to-top.com.hk - 46 - Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM 9.2.3 Single-Ended Input Voltage for Clock The minimum input voltage need to satisfy both Vinse_CK, Vinse_CK_High/Low specification at input receiver. Figure 8. Clock Single-Ended Input Voltage SAMSUNG NOTE: 1) VREFCA is LPDDR4 SDRAM internal setting value by VREF Training. [Table 24] Clock Single-Ended input voltage vincent.chen@to-top.com.hk Data Rate Parameter Symbol 1600/1866 1) 2133/2400/3200 Unit 3733 Min Max Min Max Min Max Vinse_CK 210 - 190 - 180 - mV Clock Single-Ended input voltage High from VREFDQ Vinse_CK_High 105 - 95 - 90 - mV Clock Single-Ended input voltage Low from VREFDQ Vinse_CK_Low 105 - 95 - 90 - mV Clock Single-Ended input voltage NOTE : 1) The following requirements apply for DQ operating frequencies at or below 1333Gbps for all speed bins for the first column 1600/1866. - 47 - Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM 9.2.4 Differential Input Slew Rate Definition for Clock Input slew rate for differential signals (CK_t, CK_c) are defined and measured as shown in Figure 9. and the following Tables. Figure 9. Differential Input Slew Rate Definition for CK_t, CK_c NOTE : 1) Differential signal rising edge from VILdiff_CK to VIHdiff_CK must be monotonic slope. 2) Differential signal falling edge from VIHdiff_CK to VILdiff_CK must be monotonic slope. SAMSUNG [Table 25] Differential Input Slew Rate Definition for CK_t, CK_c Description From To Defined by Differential input slew rate for rising edge (CK_t - CK_c) VILdiff_CK VIHdiff_CK |VILdiff_CK - VIHdiff_CK|/DeltaTRdiff Differential input slew rate for falling edge (CK_t - CK_c) VIHdiff_CK VILdiff_CK |VILdiff_CK - VIHdiff_CK|/DeltaTFdiff vincent.chen@to-top.com.hk [Table 26] Differential Input Level for CK_t, CK_c Data Rate Parameter Symbol 1600/1866 1) 2133/2400/3200 3733 Unit Min Max Min Max Min Max Differential Input High VIHdiff_CK 175 - 155 - 145 - mV Differential Input Low VILdiff_CK - -175 - -155 - -145 mV Note NOTE : 1) The following requirements apply for DQ operating frequencies at or below 1333Gbps for all speed bins for the first column 1600/1866. [Table 27] Differential Input Slew Rate for CK_t, CK_c Data Rate Parameter Differential Input Slew Rate for Clock Symbol SRIdiff_CK 1600/1866 2133/2400/3200 3733 Unit Min Max Min Max Min Max 2 14 2 14 2 14 - 48 - V/ns Note Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM 9.2.5 Differential Input Cross Point Voltage for Clock The cross point voltage of differential input signals (CK_t, CK_c) must meet the requirements in [Table 28]. The differential input cross point voltage VIX is measured from the actual cross point of true and complement signals to the mid level that is VREFCA. SAMSUNG Figure 10. Vix Definition (Clock) NOTE : 1) The base level of Vix_CK_FR/RF is VREFCA that is LPDDR4 SDRAM internal setting value by VREF Training. [Table 28] Cross point voltage for differential input signals (Clock) vincent.chen@to-top.com.hk Data Rate Parameter Clock Differential input cross point voltage ratio 1600/1866 a) Symbol Vix_CK_ratio 2133/2400/3200 3733 Min Max Min Max Min Max - 25 - 25 - 25 NOTE : 1) Vix_CK_Ratio is defined by this equation: Vix_CK_Ratio = Vix_CK_FR/|Min(f(t))| 2) Vix_CK_Ratio is defined by this equation: Vix_CK_Ratio = Vix_CK_RF/Max(f(t)) a) The following requirements apply for DQ operating frequencies at or below 1333Gbps for all speed bins for the first column 1600/1866. - 49 - Unit Note % 1,2 Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM 9.2.6 Differential Input Voltage for DQS The minimum input voltage need to satisfy both Vindiff_DQS and Vindiff_DQS /2 specification at input receiver and their measurement period is 1UI(tCK/ 2). Vindiff_DQS is the peak to peak voltage centered on 0 volts differential and Vindiff_DQS /2 is max and min peak voltage from 0V. Figure 11. DQS Differential Input Voltage SAMSUNG [Table 29] DQS differential input voltage Data Rate Parameter DQS differential input Symbol 1600/1866 a) 2133/2400/3200 3733 vincent.chen@to-top.com.hk Vindiff_DQS Min Max Min Max Min Max 360 - 360 - 340 - NOTE : 1) The peak voltage of Differential DQS signals is calculated in a following equation. Vindiff_DQS = (Max Peak Voltage) - (Min Peak Voltage) Max Peak Voltage = Max(f(t)) Min Peak Voltage = Min(f(t)) f(t) = VDQS_t - VDQS_c a) The following requirements apply for DQ operating frequencies at or below 1333Gbps for all speed bins for the first column 1600/1866. - 50 - Unit Note mV 1 datasheet K4F6E3S4HM-MGCJ Rev. 1.0 LPDDR4 SDRAM 9.2.7 Peak voltage calculation method The peak voltage of Differential DQS signals are calculated in a following equation. VIH.DIFF.Peak Voltage = Max(f(t)) VIL.DIFF.Peak Voltage = Min(f(t)) f(t) = VDQS_t - VDQS_c SAMSUNG Figure 12. Definition of differential DQS Peak Voltage NOTE : 1) VrefDQ is LPDDR4 SDRAM internal setting value by Vref Training. vincent.chen@to-top.com.hk - 51 - Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM 9.2.8 Single-Ended Input Voltage for DQS The minimum input voltage need to satisfy both Vinse_DQS, Vinse_DQS_High/Low specification at input receiver. Figure 13. DQS Single-Ended Input Voltage SAMSUNG NOTE : 1) VrefDQ is LPDDR4 SDRAM internal setting value by Vref Training. [Table 30] DQS Single-Ended input voltage Data Rate Parameter vincent.chen@to-top.com.hk DQS Single-Ended input voltage Symbol 1600/1866 a) 2133/2400/3200 3733 Unit Min Max Min Max Min Max Vinse_DQS 180 - 180 - 170 - mV DQS Single-Ended input voltage High from VrefDQ Vinse_DQS_High 90 - 90 - 85 - mV DQS Single-Ended input voltage Low from VrefDQ Vinse_DQS_Low 90 - 90 - 85 - mV NOTE : 1) The following requirements apply for DQ operating frequencies at or below 1333Gbps for all speed bins for the first column 1600/1866. - 52 - Note Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM 9.2.9 Differential Input Slew Rate Definition for DQS Input slew rate for differential signals (DQS_t, DQS_c) are defined and measured as shown in Figure 14. and [Table 31]. Figure 14. Differential Input Slew Rate Definition for DQS_t, DQS_c SAMSUNG NOTE : 1) Differential signal rising edge from VILdiff_DQS to VIHdiff_DQS must be monotonic slope. 2) Differential signal falling edge from VIHdiff_DQS to VILdiff_DQS must be monotonic slope. [Table 31] Differential Input Slew Rate Definition for DQS_t, DQS_c Description vincent.chen@to-top.com.hk From To Defined by Differential input slew rate for rising edge (DQS_t - DQS_c) VILdiff_DQS VIHdiff_DQS |VILdiff_DQS - VIHdiff_DQS|/DeltaTRdiff Differential input slew rate for falling edge (DQS_t - DQS_c) VIHdiff_DQS VILdiff_DQS |VILdiff_DQS - VIHdiff_DQS|/DeltaTFdiff [Table 32] Differential Input Level for DQS_t, DQS_c Data Rate Parameter Symbol 1600/1866 1) 2133/2400/3200 3733 Unit Min Max Min Max Min Max Differential Input High VIHdiff_DQS 140 - 140 - 120 - mV Differential Input Low VILdiff_DQS - -140 - -140 - -120 mV Note NOTE : 1) The following requirements apply for DQ operating frequencies at or below 1333Gbps for all speed bins for the first column 1600/1866. [Table 33] Differential Input Slew Rate for DQS_t, DQS_c Data Rate Parameter Differential Input Slew Rate Symbol SRIdiff 1600/1866 2133/2400/3200 3733 Unit Min Max Min Max Min Max 2 14 2 14 2 14 - 53 - V/ns Note Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM 9.3 Differential Input Cross Point Voltage for DQS The cross point voltage of differential input signals (DQS_t, DQS_c) must meet the requirements in [Table 35]. The differential input cross point voltage VIX is measured from the actual cross point of true and complement signals to the mid level that is VREFDQ. SAMSUNG Figure 15. Vix Definition (DQS) NOTE : 1) The base level of Vix_DQS_FR/RF is VrefDQ that is LPDDR4 SDRAM internal setting value by Vref Training. vincent.chen@to-top.com.hk [Table 34] Cross point voltage for differential input signals (DQS) Data Rate Parameter DQS Differential input crosspoint voltage ratio Symbol Vix_DQS_ratio 1600/1866 3) 2133/2400/3200 3733 Min Max Min Max Min Max - 20 - 20 - 20 NOTE : 1) Vix_DQS_Ratio is defined by this equation: Vix_DQS_Ratio = Vix_DQS_FR/|Min(f(t))| 2) Vix_DQS_Ratio is defined by this equation: Vix_DQS_Ratio = Vix_DQS_RF/Max(f(t)) 3) The following requirements apply for DQ operating frequencies at or below 1333Gbps for all speed bins for the first column 1600/1866. - 54 - Units Notes % 1,2 Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM 9.4 Input Level For ODT(ca) Input [Table 35] LPDDR4 Input Level for ODT(ca) Symbol Min Max Unit VIHODT ODT Input High Level 0.75 × VDD2 VDD2 + 0.2 V VILODT ODT Input Low Level -0.2 0.25 × VDD2 V Note 9.5 Single Ended Output Slew Rate Delta TRse VOH(AC) VCent VOL(AC) Delta TFse Figure 16. Single Ended Output Slew Rate Definition SAMSUNG [Table 36] Output Slew Rate (single-ended) Value Parameter vincent.chen@to-top.com.hk Single-ended Output Slew Rate (VOH = VDDQ/3) Symbol SRQse Output slew-rate matching Ratio (Rise to Fall) Units Min1) Max2) 3.5 9.0 V/ns 0.8 1.2 - Description: SR: Slew Rate Q: Query Output (like in DQ, which stands for Data-in, Query-Output) se: Single-ended Signals NOTE : 1) Measured with output reference load. 2) The ratio of pull-up to pull-down slew rate is specified for the same temperature and voltage, over the entire temperature and voltage range. For a given output, it represents the maximum difference between pull-up and pull-down drivers due to process variation. 3) The output slew rate for falling and rising edges is defined and measured between VOL(AC) = 0.2×VOH(DC) and VOH(AC)=0.8×VOH(DC). 4) Slew rates are measured under average SSO conditions, with 50% of DQ signals per data byte switching. - 55 - Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM 9.6 Differential Output Slew Rate Delta TRdiff 0 Delta TFdiff Figure 17. Differential Output Slew Rate Definition [Table 37] Differential Output Slew Rate Value Parameter Symbol Differential Output Slew Rate (VOH = VDDQ/3) Units SRQdiff Min Max 7.0 18.0 Description: SR: Slew Rate Q: Query Output (like in DQ, which stands for Data-in, Query-Output) diff: Differential Signals SAMSUNG NOTE : 1) Measured with output reference load. 2) The output slew rate for falling and rising edges is defined and measured between VOL(AC)=-0.8×VOH(DC) and VOH(AC)=0.8×VOH(DC). 3) Slew rates are measured under average SSO conditions, with 50% of DQ signals per data byte switching. vincent.chen@to-top.com.hk - 56 - V/ns Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM 9.7 Overshoot and Undershoot for LVSTL [Table 38] AC Overshoot/Undershoot Specification Data Rate Parameter 1600 1866 3200 3733 Units Maximum peak amplitude allowed for overshoot area. (See Figure 18.) Max 0.3 0.3 0.3 0.3 V Maximum peak amplitude allowed for undershoot area. (See Figure 18.) Max 0.3 0.3 0.3 0.3 V Maximum overshoot area above VDD. (See Figure 18.) Max 0.1 0.1 0.1 0.1 V-ns Maximum undershoot area below VSS. (See Figure 18.) Max 0.1 0.1 0.1 0.1 V-ns NOTE : 1) VDD2 stands for VDD for CA[5:0], CK_t, CK_c, CS_n, CKE and ODT. VDD stands for VDDQ for DQ, DMI, DQS_t and DQS_c. 2) VSS stands for VSS for CA[5:0], CK_t, CK_c, CS_n, CKE and ODT. VSS stands for VSSQ for DQ, DMI, DQS_t and DQS_c. 3) Maximum peak amplitude values are referenced from actual VDD and VSS values. 4) Maximum area values are referenced from maximum operating VDD and VSS values. Maximum Amplitude Overshoot Area VDD Volts VSS (V) SAMSUNG Maximum Amplitude Undershoot Area Time (ns) Figure 18. Overshoot and Undershoot Definition vincent.chen@to-top.com.hk - 57 - K4F6E3S4HM-MGCJ datasheet Rev. 1.0 LPDDR4 SDRAM 9.8 LPDDR4 Driver Output Timing Reference Load These ‘Timing Reference Loads’ are not intended as a precise representation of any particular system environment or a depiction of the actual load presented by a production tester. System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers correlate to their production test conditions, generally one or more coaxial transmission lines terminated at the tester electronics. DRAM 50  Figure 19. Driver Output Reference Load for Timing and Slew Rate NOTE : 1) All output timing parameter values are reported with respect to this reference load. This reference load is also used to report slew rate. SAMSUNG vincent.chen@to-top.com.hk - 58 - Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM 9.9 LVSTL (Low Voltage Swing Terminated Logic) IO System LVSTL I/O cell is comprised of pull-up, pull-down driver and a terminator. The basic cell is shown in Figure 20 . VDDQ PULL-UP DQ ODT Enabled when receiving PULL-DOWN VSSQ VSSQ Figure 20. LVSTL I/O Cell To ensure that the target impedance is achieved the LVSTL I/O cell is designed to calibrated as below procedure. 1) First calibrate the pull-down device against a 240 Ohm resister to VDDQ via the ZQ pin • Set Strength Control to minimum setting • Increase drive strength until comparator detects data bit is less than VDDQ/2. • NMOS pull-down device is calibrated to 240 Ohms SAMSUNG vincent.chen@to-top.com.hk VDDQ 240 Ohms Comparator VDDQ/3 N Strength control [N-1:0] VSSQ Figure 21. pull-down calibration 2) Then calibrate the pull-up device against the calibrated pull-down device. • Set VOH target and NMOS controller ODT replica via MRS (VOH can be automatically controlled by ODT MRS) • Set Strength Control to minimum setting • Increase drive strength until comparator detects data bit is greater than VOH target • NMOS pull-up device is now calibrated to VOH target - 59 - datasheet K4F6E3S4HM-MGCJ Rev. 1.0 LPDDR4 SDRAM VDDQ N Strength control [N-1:0] Comparator VOH target Calibrated NMOS PD control + ODT information Controller ODT replica could be 60 Ohm, 120 Ohm, via MRS setting. VSSQ Figure 22. pull-up calibration SAMSUNG vincent.chen@to-top.com.hk - 60 - datasheet K4F6E3S4HM-MGCJ Rev. 1.0 LPDDR4 SDRAM 10.0 INPUT/OUTPUT CAPACITANCE [Table 39] Input/Output Capacitance Parameter Symbol Input capacitance, CK_t and CK_c CCK Input capacitance delta, CK_t and CK_c CDCK Input capacitance, all other input-only pins CI Input capacitance delta, all other input-only pins CDI Input/output capacitance, DQ, DMI, DQS_t and DQS_c CIO Input/output capacitance delta, DQS_t and DQS_c CDDQS Input/output capacitance delta, DQ and DMI CDIO Input/output capacitance ZQ pin CZQ Min/Max Value Min 1.6 Max 2.7 Min 0.0 Max 0.2 Min 1.6 Max 2.7 Min -0.3 Max 0.3 Min 1.8 Max 2.6 Min 0.0 Max 0.2 Min -0.5 Max 0.5 Min 6.2 Max 9.2 Unit Notes pF 1,2 pF 1,2,3 pF 1,2,4 pF 1,2,5 pF 1,2,6 pF 1,2,7 pF 1,2,8 pF 1,2 NOTE : 1) This parameter applies to both die and package. 2) This parameter is not subject to production test. It is verified by design and characterization. The capacitance is measured according to JEP147 (Procedure for measuring input capacitance using a vector network analyzer (VNA) with VDD1, VDD2, VDDQ, VSS, VSSQ applied and all other pins floating. 3) Absolute value of CCK_t - CCK_c. 4) CI applies to CS_n, CKE, CA0-CA5. 5) CDI = CI - 0.5 × (CCK_t + CCK_c) 6) DMI loading matches DQ and DQS. 7) Absolute value of CDQS_t and CDQS_c. 8) CDIO = CIO - 0.5 × (CDQS_t + CDQS_c) in byte-lane. SAMSUNG vincent.chen@to-top.com.hk - 61 - Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM 11.0 IDD SPECIFICATION PARAMETERS AND TEST CONDITIONS 11.1 IDD Measurement Conditions The following definitions are used within the IDD measurement tables unless stated otherwise: LOW: VIN  VIL(DC) MAX HIGH: VIN  VIH(DC) MIN STABLE: Inputs are stable at a HIGH or LOW level SWITCHING: See Table 40 andGTable 41. [Table 40] Definition of Switching for CA Input Signals Switching for CA CK_t edge R1 R2 R3 R4 R5 R6 R7 R8 CKE HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH CS LOW LOW LOW LOW LOW LOW LOW LOW CA0 HIGH LOW LOW LOW LOW HIGH HIGH HIGH CA1 HIGH HIGH HIGH LOW LOW LOW LOW HIGH CA2 HIGH LOW LOW LOW LOW HIGH HIGH HIGH CA3 HIGH HIGH HIGH LOW LOW LOW LOW HIGH CA4 HIGH LOW LOW LOW LOW HIGH HIGH HIGH CA5 HIGH HIGH HIGH LOW LOW LOW LOW HIGH NOTE : 1) CS must always be driven LOW. 2) 50% of CA bus is changing between HIGH and LOW once per clock for the CA bus. 3) The above pattern is used continuously during IDD measurement for IDD values that require switching on the CA bus. SAMSUNG [Table 41] CA pattern for IDD4R for BL=16 Clock Cycle Number N CKE CS HIGH HIGH Command Read-1 CA0 CA1 CA2 CA3 CA4 CA5 L H L L L L vincent.chen@to-top.com.hk N+1 HIGH LOW L H L L L L N+2 HIGH L H L L H L N+3 HIGH LOW L L L L L L N+4 HIGH LOW DES L L L L L L N+5 HIGH LOW DES L L L L L L N+6 HIGH LOW DES L L L L L L N+7 HIGH LOW DES L L L L L L N+8 HIGH HIGH L H L L L L N+9 HIGH LOW L H L L H L N+10 HIGH HIGH L H L L H H N+11 HIGH LOW H H H H H H N+12 HIGH LOW DES L L L L L L N+13 HIGH LOW DES L L L L L L N+14 HIGH LOW DES L L L L L L N+15 HIGH LOW DES L L L L L L HIGH CAS-2 Read-1 CAS-2 NOTE : 1) BA[2:0] = 010B, CA[9:4] = 000000B or 111111B, Burst Order CA[3:2] = 00B or 11B (Same as LPDDR3 IDD4R Spec) 2) Difference from LPDDR3 Spec : CA pins are kept low with DES CMD to reduce ODT current. - 62 - Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM [Table 42] CA pattern for IDD4W for BL=16 Clock Cycle Number CKE CS N HIGH HIGH N+1 HIGH LOW N+2 HIGH HIGH N+3 HIGH LOW N+4 HIGH LOW N+5 HIGH N+6 Command CA0 CA1 CA2 CA3 CA4 CA5 L L H L L L L H L L L L L H L L H L L L L L L L DES L L L L L L LOW DES L L L L L L HIGH LOW DES L L L L L L N+7 HIGH LOW DES L L L L L L N+8 HIGH HIGH L L H L L L N+9 HIGH LOW L H L L H L N+10 HIGH HIGH L H L L H H N+11 HIGH LOW L L H H H H N+12 HIGH LOW DES L L L L L L N+13 HIGH LOW DES L L L L L L N+14 HIGH LOW DES L L L L L L N+15 HIGH LOW DES L L L L L L Write-1 CAS-2 Write-1 CAS-2 SAMSUNG NOTE : 1) BA[2:0] = 010B, CA[9:4] = 000000B or 111111B (Same as LPDDR3 IDD4W Spec.) 2) Difference from LPDDR3 Spec : 1-No burst ordering 2-CA pins are kept low with DES CMD to reduce ODT current. vincent.chen@to-top.com.hk - 63 - Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM [Table 43] Data Pattern for IDD4W (DBI off) for BL=16 DBI OFF Case DQ[7] DQ[6] DQ[5] DQ[4] DQ[3] DQ[2] DQ[1] DQ[0] DBI No. of 1’s BL0 1 1 1 1 1 1 1 1 0 8 BL1 1 1 1 1 0 0 0 0 0 4 BL2 0 0 0 0 0 0 0 0 0 0 BL3 0 0 0 0 1 1 1 1 0 4 BL4 0 0 0 0 0 0 1 1 0 2 BL5 0 0 0 0 1 1 1 1 0 4 BL6 1 1 1 1 1 1 0 0 0 6 BL7 1 1 1 1 0 0 0 0 0 4 BL8 1 1 1 1 1 1 1 1 0 8 BL9 1 1 1 1 0 0 0 0 0 4 BL10 0 0 0 0 0 0 0 0 0 0 BL11 0 0 0 0 1 1 1 1 0 4 BL12 0 0 0 0 0 0 1 1 0 2 BL13 0 0 0 0 1 1 1 1 0 4 BL14 1 1 1 1 1 1 0 0 0 6 BL15 1 1 BL16 1 1 BL17 1 1 BL18 0 0 BL19 0 BL20 SAMSUNG 1 1 0 0 0 0 0 4 1 1 1 1 0 0 0 6 1 1 0 0 0 0 0 4 0 0 0 0 1 1 0 2 0 0 0 1 1 1 1 0 4 0 0 0 0 0 0 0 0 0 0 BL21 0 0 0 0 1 1 1 1 0 4 BL22 1 1 1 1 1 1 1 1 0 8 BL23 1 1 1 1 0 0 0 0 0 4 BL24 0 0 0 0 0 0 1 1 0 2 BL25 0 0 0 0 1 1 1 1 0 4 BL26 1 1 1 1 1 1 0 0 0 6 BL27 1 1 1 1 0 0 0 0 0 4 BL28 1 1 1 1 1 1 1 1 0 8 BL29 1 1 1 1 0 0 0 0 0 4 BL30 0 0 0 0 0 0 0 0 0 0 BL31 0 0 0 0 1 1 1 1 0 4 No. of 1’s 16 16 16 16 16 16 16 16 vincent.chen@to-top.com.hk NOTE: 1) Simplified pattern compared with last showing. Same data pattern was applied to DQ[4], DQ[5], DQ[6], DQ[7] for reducing complexity for IDD4W/R pattern programming. - 64 - Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM [Table 44] Data Pattern for IDD4R (DBI off) for BL=16 DBI OFF Case DQ[7] DQ[6] DQ[5] DQ[4] DQ[3] DQ[2] DQ[1] DQ[0] DBI No. of 1’s BL0 1 1 1 1 1 1 1 1 0 8 BL1 1 1 1 1 0 0 0 0 0 4 BL2 0 0 0 0 0 0 0 0 0 0 BL3 0 0 0 0 1 1 1 1 0 4 BL4 0 0 0 0 0 0 1 1 0 2 BL5 0 0 0 0 1 1 1 1 0 4 BL6 1 1 1 1 1 1 0 0 0 6 BL7 1 1 1 1 0 0 0 0 0 4 BL8 1 1 1 1 1 1 1 1 0 8 BL9 1 1 1 1 0 0 0 0 0 4 BL10 0 0 0 0 0 0 0 0 0 0 BL11 0 0 0 0 1 1 1 1 0 4 BL12 0 0 0 0 0 0 1 1 0 2 BL13 0 0 0 0 1 1 1 1 0 4 BL14 1 1 1 1 1 1 0 0 0 6 BL15 1 1 1 1 0 0 0 0 0 4 BL16 1 1 1 1 1 1 1 1 0 8 BL17 1 1 BL18 0 BL19 SAMSUNG vincent.chen@to-top.com.hk 1 1 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 4 BL20 1 1 1 1 1 1 0 0 0 6 BL21 1 1 1 1 0 0 0 0 0 4 BL22 0 0 0 0 0 0 1 1 0 2 BL23 0 0 0 0 1 1 1 1 0 4 BL24 0 0 0 0 0 0 0 0 0 0 BL25 0 0 0 0 1 1 1 1 0 4 BL26 1 1 1 1 1 1 1 1 0 8 BL27 1 1 1 1 0 0 0 0 0 4 BL28 0 0 0 0 0 0 1 1 0 2 BL29 0 0 0 0 1 1 1 1 0 4 BL30 1 1 1 1 1 1 0 0 0 6 BL31 1 1 1 1 0 0 0 0 0 4 No. of 1’s 16 16 16 16 16 16 16 16 NOTE: 1) Same data pattern was applied to DQ[4], DQ[5], DQ[6], DQ[7] for reducing complexity for IDD4W/R pattern programming. - 65 - Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM [Table 45] Data Pattern for IDD4W (DBI on) for BL=16 DBI ON Case DQ[7] DQ[6] DQ[5] DQ[4] DQ[3] DQ[2] DQ[1] DQ[0] DBI No. of 1’s BL0 0 0 0 0 0 0 0 0 1 1 BL1 1 1 1 1 0 0 0 0 0 4 BL2 0 0 0 0 0 0 0 0 0 0 BL3 0 0 0 0 1 1 1 1 0 4 BL4 0 0 0 0 0 0 1 1 0 2 BL5 0 0 0 0 1 1 1 1 0 4 BL6 0 0 0 0 0 0 1 1 1 3 BL7 1 1 1 1 0 0 0 0 0 4 BL8 0 0 0 0 0 0 0 0 1 1 BL9 1 1 1 1 0 0 0 0 0 4 BL10 0 0 0 0 0 0 0 0 0 0 BL11 0 0 0 0 1 1 1 1 0 4 BL12 0 0 0 0 0 0 1 1 0 2 BL13 0 0 0 0 1 1 1 1 0 4 BL14 0 0 0 0 0 0 1 1 1 3 BL15 1 1 BL16 0 0 BL17 1 1 BL18 0 0 BL19 0 BL20 SAMSUNG 1 1 0 0 0 0 0 4 0 0 0 0 1 1 1 3 1 1 0 0 0 0 0 4 0 0 0 0 1 1 0 2 0 0 0 1 1 1 1 0 4 0 0 0 0 0 0 0 0 0 0 BL21 0 0 0 0 1 1 1 1 0 4 BL22 0 0 0 0 0 0 0 0 1 1 BL23 1 1 1 1 0 0 0 0 0 4 BL24 0 0 0 0 0 0 1 1 0 2 BL25 0 0 0 0 1 1 1 1 0 4 BL26 0 0 0 0 0 0 1 1 1 3 BL27 1 1 1 1 0 0 0 0 0 4 BL28 0 0 0 0 0 0 0 0 1 1 BL29 1 1 1 1 0 0 0 0 0 4 BL30 0 0 0 0 0 0 0 0 0 0 BL31 0 0 0 0 1 1 1 1 0 4 No. of 1’s 8 8 8 8 8 8 16 16 8 vincent.chen@to-top.com.hk DBI enabled burst - 66 - Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM [Table 46] Data Pattern for IDD4R (DBI on) for BL=16 DBI ON Case DQ[7] DQ[6] DQ[5] DQ[4] DQ[3] DQ[2] DQ[1] DQ[0] DBI No. of 1’s BL0 0 0 0 0 0 0 0 0 1 1 BL1 1 1 1 1 0 0 0 0 0 4 BL2 0 0 0 0 0 0 0 0 0 0 BL3 0 0 0 0 1 1 1 1 0 4 BL4 0 0 0 0 0 0 1 1 0 2 BL5 0 0 0 0 1 1 1 1 0 4 BL6 0 0 0 0 0 0 1 1 1 3 BL7 1 1 1 1 0 0 0 0 0 4 BL8 0 0 0 0 0 0 0 0 1 1 BL9 1 1 1 1 0 0 0 0 0 4 BL10 0 0 0 0 0 0 0 0 0 0 BL11 0 0 0 0 1 1 1 1 0 4 BL12 0 0 0 0 0 0 1 1 0 2 BL13 0 0 0 0 1 1 1 1 0 4 BL14 0 0 0 0 0 0 1 1 1 3 BL15 1 1 1 1 0 0 0 0 0 4 BL16 0 0 0 0 0 0 0 0 1 1 BL17 1 1 1 1 0 0 0 0 0 4 BL18 0 0 0 0 0 0 0 0 0 0 BL19 0 0 0 0 1 1 1 1 0 4 BL20 0 0 0 0 0 0 1 1 1 3 BL21 1 1 1 1 0 0 0 0 0 4 BL22 0 0 0 0 0 0 1 1 0 2 BL23 0 0 0 0 1 1 1 1 0 4 BL24 0 0 0 0 0 0 0 0 0 0 BL25 0 0 0 0 1 1 1 1 0 4 BL26 0 0 0 0 0 0 0 0 1 1 BL27 1 1 1 1 0 0 0 0 0 4 BL28 0 0 0 0 0 0 1 1 0 2 BL29 0 0 0 0 1 1 1 1 0 4 BL30 0 0 0 0 0 0 1 1 1 3 BL31 No. of 1’s 1 1 1 1 0 0 0 0 0 4 8 8 8 8 8 8 16 16 8 SAMSUNG vincent.chen@to-top.com.hk - 67 - Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM [Table 47] CA pattern for IDD4R for BL=32 Clock Cycle Number CKE CS N HIGH HIGH N+1 HIGH LOW N+2 HIGH HIGH N+3 HIGH LOW N+4 HIGH LOW N+5 HIGH N+6 Command CA0 CA1 CA2 CA3 CA4 CA5 L H L L L L L H L L L L L H L L H L L L L L L L DES L L L L L L LOW DES L L L L L L HIGH LOW DES L L L L L L N+7 HIGH LOW DES L L L L L L N+8 HIGH LOW DES L L L L L L N+9 HIGH LOW DES L L L L L L N+10 HIGH LOW DES L L L L L L N+11 HIGH LOW DES L L L L L L N+12 HIGH LOW DES L L L L L L N+13 HIGH LOW DES L L L L L L N+14 HIGH LOW DES L L L L L L N+15 HIGH LOW DES L L L L L L HIGH HIGH L H L L L L HIGH LOW L H L L H L L H L L H H H H L H H H Read-1 CAS-2 N+18 SAMSUNG N+19 HIGH N+20 HIGH LOW DES L L L L L L N+21 HIGH LOW DES L L L L L L N+22 HIGH LOW DES L L L L L L N+23 HIGH LOW DES L L L L L L N+24 HIGH LOW DES L L L L L L N+25 HIGH LOW DES L L L L L L N+26 HIGH LOW DES L L L L L L N+27 HIGH LOW DES L L L L L L N+28 HIGH LOW DES L L L L L L N+29 HIGH LOW DES L L L L L L N+30 HIGH LOW DES L L L L L L N+31 HIGH LOW DES L L L L L L N+16 N+17 HIGH HIGH Read-1 vincent.chen@to-top.com.hk LOW CAS-2 NOTE : 1) BA[2:0] = 010B, CA[9:5] = 00000B or 11111B, Burst Order CA[4:2] = 000B or 111B. - 68 - Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM [Table 48] CA pattern for IDD4W for BL=32 Clock Cycle Number CKE CS N HIGH HIGH N+1 HIGH LOW N+2 HIGH HIGH N+3 HIGH LOW N+4 HIGH LOW N+5 HIGH N+6 Command CA0 CA1 CA2 CA3 CA4 CA5 L L H L L L L H L L L L L H L L H L L L L L L L DES L L L L L L LOW DES L L L L L L HIGH LOW DES L L L L L L N+7 HIGH LOW DES L L L L L L N+8 HIGH LOW DES L L L L L L N+9 HIGH LOW DES L L L L L L N+10 HIGH LOW DES L L L L L L N+11 HIGH LOW DES L L L L L L N+12 HIGH LOW DES L L L L L L N+13 HIGH LOW DES L L L L L L N+14 HIGH LOW DES L L L L L L N+15 HIGH LOW DES L L L L L L HIGH HIGH L L H L L L HIGH LOW L H L L H L L H L L H H L L L H H H Write-1 CAS-2 N+18 SAMSUNG N+19 HIGH N+20 HIGH LOW DES L L L L L L N+21 HIGH LOW DES L L L L L L N+22 HIGH LOW DES L L L L L L N+23 HIGH LOW DES L L L L L L N+24 HIGH LOW DES L L L L L L N+25 HIGH LOW DES L L L L L L N+26 HIGH LOW DES L L L L L L N+27 HIGH LOW DES L L L L L L N+28 HIGH LOW DES L L L L L L N+29 HIGH LOW DES L L L L L L N+30 HIGH LOW DES L L L L L L N+31 HIGH LOW DES L L L L L L N+16 N+17 HIGH HIGH Write-1 vincent.chen@to-top.com.hk LOW CAS-2 NOTE : 1) BA[2:0] = 010B, CA[9:5] = 00000B or 11111B. - 69 - Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM [Table 49] Data Pattern for IDD4W (DBI off) for BL=32 DBI OFF Case DQ[7] DQ[6] DQ[5] DQ[4] DQ[3] DQ[2] DQ[1] DQ[0] DBI No. of 1’s BL0 1 1 1 1 1 1 1 1 0 8 BL1 1 1 1 1 0 0 0 0 0 4 BL2 0 0 0 0 0 0 0 0 0 0 BL3 0 0 0 0 1 1 1 1 0 4 BL4 0 0 0 0 0 0 1 1 0 2 BL5 0 0 0 0 1 1 1 1 0 4 BL6 1 1 1 1 1 1 0 0 0 6 BL7 1 1 1 1 0 0 0 0 0 4 BL8 1 1 1 1 1 1 1 1 0 8 BL9 1 1 1 1 0 0 0 0 0 4 BL10 0 0 0 0 0 0 0 0 0 0 BL11 0 0 0 0 1 1 1 1 0 4 BL12 0 0 0 0 0 0 1 1 0 2 BL13 0 0 0 0 1 1 1 1 0 4 BL14 1 1 1 1 1 1 0 0 0 6 BL15 1 1 1 1 0 0 0 0 0 4 BL16 1 1 1 1 1 1 0 0 0 6 BL17 1 1 BL18 0 BL19 SAMSUNG vincent.chen@to-top.com.hk 1 1 0 0 0 0 0 4 0 0 0 0 0 1 1 0 2 0 0 0 0 1 1 1 1 0 4 BL20 0 0 0 0 0 0 0 0 0 0 BL21 0 0 0 0 1 1 1 1 0 4 BL22 1 1 1 1 1 1 1 1 0 8 BL23 1 1 1 1 0 0 0 0 0 4 BL24 0 0 0 0 0 0 1 1 0 2 BL25 0 0 0 0 1 1 1 1 0 4 BL26 1 1 1 1 1 1 0 0 0 6 BL27 1 1 1 1 0 0 0 0 0 4 BL28 1 1 1 1 1 1 1 1 0 8 BL29 1 1 1 1 0 0 0 0 0 4 BL30 0 0 0 0 0 0 0 0 0 0 BL31 0 0 0 0 1 1 1 1 0 4 BL32 1 1 1 1 1 1 1 1 0 8 BL33 1 1 1 1 0 0 0 0 0 4 BL34 0 0 0 0 0 0 0 0 0 0 BL35 0 0 0 0 1 1 1 1 0 4 - 70 - Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM [Table 49] Data Pattern for IDD4W (DBI off) for BL=32 DBI OFF Case DQ[7] DQ[6] DQ[5] DQ[4] DQ[3] DQ[2] DQ[1] DQ[0] DBI No. of 1’s BL36 0 0 0 0 0 0 1 1 0 2 BL37 0 0 0 0 1 1 1 1 0 4 BL38 1 1 1 1 1 1 0 0 0 6 BL39 1 1 1 1 0 0 0 0 0 4 BL40 1 1 1 1 1 1 1 1 0 8 BL41 1 1 1 1 0 0 0 0 0 4 BL42 0 0 0 0 0 0 0 0 0 0 BL43 0 0 0 0 1 1 1 1 0 4 BL44 0 0 0 0 0 0 1 1 0 2 BL45 0 0 0 0 1 1 1 1 0 4 BL46 1 1 1 1 1 1 0 0 0 6 BL47 1 1 1 1 0 0 0 0 0 4 BL48 1 1 1 1 1 1 0 0 0 6 BL49 1 1 1 1 0 0 0 0 0 4 BL50 0 0 0 0 0 0 1 1 0 2 BL51 0 0 0 0 1 1 1 1 0 4 BL52 0 0 0 0 0 0 0 0 0 0 BL53 0 0 0 0 1 1 1 1 0 4 BL54 1 1 1 1 1 1 1 1 0 8 BL55 1 1 1 1 0 0 0 0 0 4 BL56 0 0 0 0 0 0 1 1 0 2 BL57 0 0 0 0 1 1 1 1 0 4 BL58 1 1 1 1 1 1 0 0 0 6 BL59 1 1 1 1 0 0 0 0 0 4 BL60 1 1 1 1 1 1 1 1 0 8 BL61 1 1 1 1 0 0 0 0 0 4 BL62 0 0 0 0 0 0 0 0 0 0 BL63 0 0 0 0 1 1 1 1 0 4 No. of 1’s 32 32 32 32 32 32 32 32 SAMSUNG vincent.chen@to-top.com.hk NOTE : 1) Simplified pattern compared with last showing. Same data pattern was applied to DQ[4], DQ[5], DQ[6], DQ[7] for reducing complexity for IDD4W/R pattern programming. - 71 - Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM [Table 50] Data Pattern for IDD4R (DBI off) for BL=32 DBI OFF Case DQ[7] DQ[6] DQ[5] DQ[4] DQ[3] DQ[2] DQ[1] DQ[0] DBI No. of 1’s BL0 1 1 1 1 1 1 1 1 0 8 BL1 1 1 1 1 0 0 0 0 0 4 BL2 0 0 0 0 0 0 0 0 0 0 BL3 0 0 0 0 1 1 1 1 0 4 BL4 0 0 0 0 0 0 1 1 0 2 BL5 0 0 0 0 1 1 1 1 0 4 BL6 1 1 1 1 1 1 0 0 0 6 BL7 1 1 1 1 0 0 0 0 0 4 BL8 1 1 1 1 1 1 1 1 0 8 BL9 1 1 1 1 0 0 0 0 0 4 BL10 0 0 0 0 0 0 0 0 0 0 BL11 0 0 0 0 1 1 1 1 0 4 BL12 0 0 0 0 0 0 1 1 0 2 BL13 0 0 0 0 1 1 1 1 0 4 BL14 1 1 1 1 1 1 0 0 0 6 BL15 1 1 1 1 0 0 0 0 0 4 BL16 1 1 1 1 1 1 0 0 0 6 BL17 1 1 1 1 0 0 0 0 0 4 BL18 0 0 0 0 0 0 1 1 0 2 BL19 0 0 0 0 1 1 1 1 0 4 BL20 0 0 0 0 0 0 0 0 0 0 BL21 0 0 0 0 1 1 1 1 0 4 BL22 1 1 1 1 1 1 1 1 0 8 BL23 1 1 1 1 0 0 0 0 0 4 BL24 0 0 0 0 0 0 1 1 0 2 BL25 0 0 0 0 1 1 1 1 0 4 BL26 1 1 1 1 1 1 0 0 0 6 BL27 1 1 1 1 0 0 0 0 0 4 BL28 1 1 1 1 1 1 1 1 0 8 BL29 1 1 1 1 0 0 0 0 0 4 BL30 0 0 0 0 0 0 0 0 0 0 BL31 0 0 0 0 1 1 1 1 0 4 BL32 0 0 0 0 0 0 1 1 0 2 BL33 0 0 0 0 1 1 1 1 0 4 BL34 1 1 1 1 1 1 0 0 0 6 SAMSUNG vincent.chen@to-top.com.hk - 72 - Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM [Table 50] Data Pattern for IDD4R (DBI off) for BL=32 DBI OFF Case DQ[7] DQ[6] DQ[5] DQ[4] DQ[3] DQ[2] DQ[1] DQ[0] DBI No. of 1’s BL35 1 1 1 1 0 0 0 0 0 4 BL36 1 1 1 1 1 1 1 1 0 8 BL37 1 1 1 1 0 0 0 0 0 4 BL38 0 0 0 0 0 0 0 0 0 0 BL39 0 0 0 0 1 1 1 1 0 4 BL40 0 0 0 0 0 0 1 1 0 2 BL41 0 0 0 0 1 1 1 1 0 4 BL42 1 1 1 1 1 1 0 0 0 6 BL43 1 1 1 1 0 0 0 0 0 4 BL44 1 1 1 1 1 1 1 1 0 8 BL45 1 1 1 1 0 0 0 0 0 4 BL46 0 0 0 0 0 0 0 0 0 0 BL47 0 0 0 0 1 1 1 1 0 4 BL48 1 1 1 1 1 1 1 1 0 8 BL49 1 1 1 1 0 0 0 0 0 4 BL50 0 0 0 0 0 0 0 0 0 0 BL51 0 0 0 0 1 1 1 1 0 4 BL52 1 1 1 1 1 1 0 0 0 6 BL53 1 1 1 1 0 0 0 0 0 4 BL54 0 0 0 0 0 0 1 1 0 2 BL55 0 0 0 0 1 1 1 1 0 4 BL56 0 0 0 0 0 0 0 0 0 0 BL57 0 0 0 0 1 1 1 1 0 4 BL58 1 1 1 1 1 1 1 1 0 8 BL59 1 1 1 1 0 0 0 0 0 4 BL60 0 0 0 0 0 0 1 1 0 2 BL61 0 0 0 0 1 1 1 1 0 4 BL62 1 1 1 1 1 1 0 0 0 6 BL63 1 1 1 1 0 0 0 0 0 4 No. of 1’s 32 32 32 32 32 32 32 32 SAMSUNG vincent.chen@to-top.com.hk NOTE : 1) Same data pattern was applied to DQ[4], DQ[5], DQ[6], DQ[7] for reducing complexity for IDD4W/R pattern programming. - 73 - Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM [Table 51] Data Pattern for IDD4W (DBI on) for BL=32 DBI ON Case DQ[7] DQ[6] DQ[5] DQ[4] DQ[3] DQ[2] DQ[1] DQ[0] DBI No. of 1’s BL0 0 0 0 0 0 0 0 0 1 1 BL1 1 1 1 1 0 0 0 0 0 4 BL2 0 0 0 0 0 0 0 0 0 0 BL3 0 0 0 0 1 1 1 1 0 4 BL4 0 0 0 0 0 0 1 1 0 2 BL5 0 0 0 0 1 1 1 1 0 4 BL6 0 0 0 0 0 0 1 1 1 3 BL7 1 1 1 1 0 0 0 0 0 4 BL8 0 0 0 0 0 0 0 0 1 1 BL9 1 1 1 1 0 0 0 0 0 4 BL10 0 0 0 0 0 0 0 0 0 0 BL11 0 0 0 0 1 1 1 1 0 4 BL12 0 0 0 0 0 0 1 1 0 2 BL13 0 0 0 0 1 1 1 1 0 4 BL14 0 0 0 0 0 0 1 1 1 3 BL15 1 1 1 1 0 0 0 0 0 4 BL16 0 0 0 0 0 0 1 1 1 3 BL17 1 1 1 1 0 0 0 0 0 4 BL18 0 0 0 0 0 0 1 1 0 2 BL19 0 0 0 0 1 1 1 1 0 4 BL20 0 0 0 0 0 0 0 0 0 0 BL21 0 0 0 0 1 1 1 1 0 4 BL22 0 0 0 0 0 0 0 0 1 1 BL23 1 1 1 1 0 0 0 0 0 4 BL24 0 0 0 0 0 0 1 1 0 2 BL25 0 0 0 0 1 1 1 1 0 4 BL26 0 0 0 0 0 0 1 1 1 3 BL27 1 1 1 1 0 0 0 0 0 4 BL28 0 0 0 0 0 0 0 0 1 1 BL29 1 1 1 1 0 0 0 0 0 4 BL30 0 0 0 0 0 0 0 0 0 0 BL31 0 0 0 0 1 1 1 1 0 4 BL32 0 0 0 0 0 0 0 0 1 1 BL33 1 1 1 1 0 0 0 0 0 4 BL34 0 0 0 0 0 0 0 0 0 0 BL35 0 0 0 0 1 1 1 1 0 4 BL36 0 0 0 0 0 0 1 1 0 2 SAMSUNG vincent.chen@to-top.com.hk - 74 - Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM [Table 51] Data Pattern for IDD4W (DBI on) for BL=32 DBI ON Case DQ[7] DQ[6] DQ[5] DQ[4] DQ[3] DQ[2] DQ[1] DQ[0] DBI No. of 1’s BL37 0 0 0 0 1 1 1 1 0 4 BL38 0 0 0 0 0 0 1 1 1 3 BL39 1 1 1 1 0 0 0 0 0 4 BL40 0 0 0 0 0 0 0 0 1 1 BL41 1 1 1 1 0 0 0 0 0 4 BL42 0 0 0 0 0 0 0 0 0 0 BL43 0 0 0 0 1 1 1 1 0 4 BL44 0 0 0 0 0 0 1 1 0 2 BL45 0 0 0 0 1 1 1 1 0 4 BL46 0 0 0 0 0 0 1 1 1 3 BL47 1 1 1 1 0 0 0 0 0 4 BL48 0 0 0 0 0 0 1 1 1 3 BL49 1 1 1 1 0 0 0 0 0 4 BL50 0 0 0 0 0 0 1 1 0 2 BL51 0 0 0 0 1 1 1 1 0 4 BL52 0 0 BL53 0 0 BL54 0 0 BL55 1 1 BL56 0 0 BL57 0 BL58 SAMSUNG 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 4 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 4 0 0 0 0 1 1 0 2 0 0 0 1 1 1 1 0 4 0 0 0 0 0 0 1 1 1 3 BL59 1 1 1 1 0 0 0 0 0 4 BL60 0 0 0 0 0 0 0 0 1 1 BL61 1 1 1 1 0 0 0 0 0 4 BL62 0 0 0 0 0 0 0 0 0 0 BL63 0 0 0 0 1 1 1 1 0 4 No. of 1’s 16 16 16 16 16 16 32 32 16 vincent.chen@to-top.com.hk DBI enabled burst - 75 - Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM [Table 52] Data Pattern for IDD4R (DBI on) for BL=32 DBI ON Case DQ[7] DQ[6] DQ[5] DQ[4] DQ[3] DQ[2] DQ[1] DQ[0] DBI No. of 1’s BL0 0 0 0 0 0 0 0 0 1 1 BL1 1 1 1 1 0 0 0 0 0 4 BL2 0 0 0 0 0 0 0 0 0 0 BL3 0 0 0 0 1 1 1 1 0 4 BL4 0 0 0 0 0 0 1 1 0 2 BL5 0 0 0 0 1 1 1 1 0 4 BL6 0 0 0 0 0 0 1 1 1 3 BL7 1 1 1 1 0 0 0 0 0 4 BL8 0 0 0 0 0 0 0 0 1 1 BL9 1 1 1 1 0 0 0 0 0 4 BL10 0 0 0 0 0 0 0 0 0 0 BL11 0 0 0 0 1 1 1 1 0 4 BL12 0 0 0 0 0 0 1 1 0 2 BL13 0 0 0 0 1 1 1 1 0 4 BL14 0 0 0 0 0 0 1 1 1 3 BL15 1 1 1 1 0 0 0 0 0 4 BL16 0 0 BL17 1 1 BL18 0 0 BL19 0 0 BL20 0 0 BL21 0 BL22 0 BL23 SAMSUNG 0 0 0 0 1 1 1 3 1 1 0 0 0 0 0 4 0 0 0 0 1 1 0 2 0 0 1 1 1 1 0 4 vincent.chen@to-top.com.hk 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 4 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 4 BL24 0 0 0 0 0 0 1 1 0 2 BL25 0 0 0 0 1 1 1 1 0 4 BL26 0 0 0 0 0 0 1 1 1 3 BL27 1 1 1 1 0 0 0 0 0 4 BL28 0 0 0 0 0 0 0 0 1 1 BL29 1 1 1 1 0 0 0 0 0 4 BL30 0 0 0 0 0 0 0 0 0 0 BL31 0 0 0 0 1 1 1 1 0 4 BL32 0 0 0 0 0 0 1 1 0 2 BL33 0 0 0 0 1 1 1 1 0 4 BL34 0 0 0 0 0 0 1 1 1 3 BL35 1 1 1 1 0 0 0 0 0 4 BL36 0 0 0 0 0 0 0 0 1 1 BL37 1 1 1 1 0 0 0 0 0 4 BL38 0 0 0 0 0 0 0 0 0 0 BL39 0 0 0 0 1 1 1 1 0 4 BL40 0 0 0 0 0 0 1 1 0 2 BL41 0 0 0 0 1 1 1 1 0 4 - 76 - Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM [Table 52] Data Pattern for IDD4R (DBI on) for BL=32 DBI ON Case DQ[7] DQ[6] DQ[5] DQ[4] DQ[3] DQ[2] DQ[1] DQ[0] DBI No. of 1’s BL42 0 0 0 0 0 0 1 1 1 3 BL43 1 1 1 1 0 0 0 0 0 4 BL44 0 0 0 0 0 0 0 0 1 1 BL45 1 1 1 1 0 0 0 0 0 4 BL46 0 0 0 0 0 0 0 0 0 0 BL47 0 0 0 0 1 1 1 1 0 4 BL48 0 0 0 0 0 0 0 0 1 1 BL49 1 1 1 1 0 0 0 0 0 4 BL50 0 0 0 0 0 0 0 0 0 0 BL51 0 0 0 0 1 1 1 1 0 4 BL52 0 0 0 0 0 0 1 1 1 3 BL53 1 1 1 1 0 0 0 0 0 4 BL54 0 0 0 0 0 0 1 1 0 2 BL55 0 0 0 0 1 1 1 1 0 4 BL56 0 0 0 0 0 0 0 0 0 0 BL57 0 0 0 0 1 1 1 1 0 4 0 0 BL58 0 0 BL59 1 1 BL60 0 0 BL61 0 0 1 1 1 0 1 0 0 0 0 0 0 0 0 4 0 0 0 0 1 1 0 2 0 0 1 1 1 1 0 4 SAMSUNG BL62 0 0 0 0 0 0 1 1 3 1 1 vincent.chen@to-top.com.hk 1 BL63 1 1 0 0 0 0 0 4 No. of 1’s 16 16 16 16 16 16 32 32 16 - 77 - datasheet K4F6E3S4HM-MGCJ Rev. 1.0 LPDDR4 SDRAM 11.2 IDD Specifications IDD values are for the entire operating voltage range, and all of them are for the entire standard range, with the exception of IDD6ET which is for the entire elevated temperature range. [Table 53] LPDDR4 IDD Specification Parameters and Operating Conditions Parameter/Condition Operating one bank active-precharge current: tCK = tCKmin; tRC = tRCmin; CKE is HIGH; CS is LOW between valid commands; CA bus inputs are switching; Data bus inputs are stable ODT disabled Idle power-down standby current: tCK = tCKmin; CKE is LOW; CS is LOW; All banks are idle; CA bus inputs are switching; Data bus inputs are stable ODT disabled Idle power-down standby current with clock stop: CK_t =LOW, CK_c =HIGH; CKE is LOW; CS is LOW; All banks are idle; CA bus inputs are stable; Data bus inputs are stable ODT disabled Symbol Power Supply Notes IDD01 VDD1 1,10,11 IDD02 VDD2 1,10,11 IDD0Q VDDQ 1,3,10,11 IDD2P1 VDD1 1,10,11 IDD2P2 VDD2 1,10,11 IDD2PQ VDDQ 1,3,10,11 IDD2PS1 VDD1 1,10,11 IDD2PS2 VDD2 1,10,11 IDD2PSQ VDDQ 1,3,10,11 SAMSUNG Idle non power-down standby current: tCK = tCKmin; CKE is HIGH; CS is LOW; All banks are idle; CA bus inputs are switching; Data bus inputs are stable ODT disabled IDD2N1 VDD1 1,10,11 IDD2N2 VDD2 1,10,11 vincent.chen@to-top.com.hk Idle non power-down standby current with clock stopped: CK_t = LOW; CK_c = HIGH; CKE is HIGH; CS is LOW; All banks are idle; CA bus inputs are stable; Data bus inputs are stable ODT disabled Active power-down standby current: tCK = tCKmin; CKE is LOW; CS is LOW; One bank is active; CA bus inputs are switching; Data bus inputs are stable ODT disabled Active power-down standby current with clock stop: CK_t = LOW, CK_c = HIGH; CKE is LOW; CS is LOW; One bank is active; CA bus inputs are stable; Data bus inputs are stable ODT disabled - 78 - IDD2NQ VDDQ 1,3,10,11 IDD2NS1 VDD1 1,10,11 IDD2NS2 VDD2 1,10,11 IDD2NSQ VDDQ 1,3,10,11 IDD3P1 VDD1 1,10,11 IDD3P2 VDD2 1,10,11 IDD3PQ VDDQ 1,3,10,11 IDD3PS1 VDD1 1,10,11 IDD3PS2 VDD2 1,10,11 IDD3PSQ VDDQ 1,4,10,11 datasheet K4F6E3S4HM-MGCJ Rev. 1.0 LPDDR4 SDRAM [Table 53] LPDDR4 IDD Specification Parameters and Operating Conditions Parameter/Condition Active non-power-down standby current: tCK = tCKmin; CKE is HIGH; CS is LOW; One bank is active; CA bus inputs are switching; Data bus inputs are stable ODT disabled Active non-power-down standby current with clock stopped: CK_t=LOW, CK_c=HIGH; CKE is HIGH; CS is LOW; One bank is active; CA bus inputs are stable; Data bus inputs are stable ODT disabled Operating burst READ current: tCK = tCKmin; CS is LOW between valid commands; One bank is active; BL = 16 or 32; RL = RL(MIN); CA bus inputs are switching; 50% data change each burst transfer ODT disabled Operating burst WRITE current: tCK = tCKmin; CS is LOW between valid commands; One bank is active; BL = 16 or 32; WL = WLmin; CA bus inputs are switching; 50% data change each burst transfer ODT disabled Symbol Power Supply Notes IDD3N1 VDD1 1,10,11 IDD3N2 VDD2 1,10,11 IDD3NQ VDDQ 1,4,10,11 IDD3NS1 VDD1 1,10,11 IDD3NS2 VDD2 1,10,11 IDD3NSQ VDDQ 1,4,10,11 IDD4R1 VDD1 1,10,11 IDD4R2 VDD2 1,10,11 IDD4RQ VDDQ 1,5,10,11 IDD4W1 VDD1 1,10,11 IDD4W2 VDD2 1,10,11 SAMSUNG All-bank REFRESH Burst current: tCK = tCKmin; CKE is HIGH between valid commands; tRC = tRFCabmin; Burst refresh; CA bus inputs are switching; Data bus inputs are stable; ODT disabled IDD4WQ VDDQ IDD51 VDD1 1,10,11 IDD52 VDD2 1,10,11 IDD5Q VDDQ 1,4,10,11 IDD5AB1 VDD1 1,10,11 IDD5AB2 VDD2 1,10,11 IDD5ABQ VDDQ 1,4,10,11 IDD5PB1 VDD1 1,10,11 IDD5PB2 VDD2 1,10,11 IDD5PBQ VDDQ 1,4,10,11 IDD61 VDD1 6,7,9,10,11 IDD62 VDD2 6,7,9,10,11 IDD6Q VDDQ 4,6,7,9,10,11 vincent.chen@to-top.com.hk All-bank REFRESH Average current: tCK = tCKmin; CKE is HIGH between valid commands; tRC = tREFI; CA bus inputs are switching; Data bus inputs are stable; ODT disabled Per-bank REFRESH Average current: tCK = tCKmin; CKE is HIGH between valid commands; tRC = tREFI/8; CA bus inputs are switching; Data bus inputs are stable; ODT disabled Power Down Self refresh current (-25C to +85C): CK_t=LOW, CK_c=HIGH; CKE is LOW; CA bus inputs are stable; Data bus inputs are stable; Maximum 1x Self-Refresh Rate; ODT disabled - 79 - 1,4,10,11 K4F6E3S4HM-MGCJ datasheet Rev. 1.0 LPDDR4 SDRAM NOTE ͫ 1) Published IDD values are the maximum of the distribution of the arithmetic mean. 2) ODT disabled: MR11[2:0] = 000B. 3) IDD current specifications are tested after the device is properly initialized. 4) Measured currents are the summation of VDDQ and VDD2. 5) Guaranteed by design with output load = 5pF and RON = 40 ohm. 6) The 1x Self-Refresh Rate is the rate at which the LPDDR4 device is refreshed internally during Self-Refresh, before going into the elevated Temperature range. 7) This is the general definition that applies to full array Self Refresh. 8) For all IDD measurements, VIHCKE = 0.8 x VDD2, VILCKE = 0.2 x VDD2. 9) IDD6 25C is guaranteed, IDD6 85C is typical of the distribution of the arithmetic mean. 10) These specification values are the summation of all the channel current and both channels are under the same condition at the same time. 11) Dual Channel devices are specified in dual channel operation (both channels operating together). SAMSUNG vincent.chen@to-top.com.hk - 80 - datasheet K4F6E3S4HM-MGCJ Rev. 1.0 LPDDR4 SDRAM 11.3 IDD Spec Table [Table 54] IDD Specification for 16Gb LPDDR4 Power Supply 16Gb (x16/Ch, 2-Chip) IDD01 VDD1 10 mA Symbol IDD0 IDD2P IDD2PS IDD2N IDD2NS IDD3P IDD3PS IDD3N IDD3NS IDD4R IDD4W IDD5 IDD5AB 3733Mbps Units IDD02 VDD2 65 mA IDD0Q VDDQ 0.5 mA IDD2P1 VDD1 2 mA IDD2P2 VDD2 6.25 mA IDD2PQ VDDQ 0.5 mA IDD2PS1 VDD1 2 mA IDD2PS2 VDD2 6.25 mA IDD2PSQ VDDQ 0.5 mA IDD2N1 VDD1 3 mA IDD2N2 VDD2 26.5 mA IDD2NQ VDDQ 0.5 mA IDD2NS1 VDD1 3 mA IDD2NS2 VDD2 20 mA IDD2NSQ VDDQ 0.5 mA IDD3P1 VDD1 2.8 mA SAMSUNG IDD3P2 VDD2 13.5 mA IDD3PQ VDDQ 0.5 mA IDD3PS1 VDD1 2.8 mA IDD3PS2 VDD2 13.5 mA IDD3PSQ VDDQ 0.5 mA IDD3N1 VDD1 3 mA IDD3N2 VDD2 32 mA IDD3NQ VDDQ 0.5 mA IDD3NS1 VDD1 3 mA vincent.chen@to-top.com.hk IDD3NS2 VDD2 28 mA IDD3NSQ VDDQ 0.5 mA IDD4R1 VDD1 8.5 mA IDD4R2 VDD2 420 mA IDD4RQ VDDQ 230 mA IDD4W1 VDD1 3 mA IDD4W2 VDD2 435 mA IDD4WQ VDDQ 0.5 mA IDD51 VDD1 75 mA IDD52 VDD2 315 mA IDD5Q VDDQ 0.5 mA IDD5AB1 VDD1 7 mA IDD5AB2 VDD2 41 mA IDD5ABQ VDDQ 0.5 mA - 81 - datasheet K4F6E3S4HM-MGCJ IDD61 IDD6 IDD62 IDD6Q LPDDR4 SDRAM Power Supply 16Gb (x16/Ch, 2-Chip) IDD5PB1 VDD1 7 mA IDD5PB2 VDD2 42 mA IDD5PBQ VDDQ 0.5 mA Symbol IDD5PB Rev. 1.0 25C VDD1 85C 25C VDD2 85C 25C VDDQ 85C 3733Mbps 1 5 2.7 22 0.4 0.5 SAMSUNG vincent.chen@to-top.com.hk - 82 - Units mA mA mA Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM 12.0 AC AND DC OUTPUT MEASUREMENT LEVELS 12.1 Single Ended AC and DC Output Levels Table 55 shows the output levels used for measurements of single ended signals. [Table 55] Single-ended AC and DC Output Levels Value Symbol Parameter Under LPDDR4TBD Un-term TBD to 3200 VSSQ term 3200 to 4266 VSSQ term Unit Notes 1 VOH (DC) AC, DC output high measurement level VDDQ-0.55 VDDQ/3 TBD V VOL (DC) AC, DC output low measurement level VSSQ VSSQ VSSQ V NOTE : 1) 60ohm ODT value is assumed. SAMSUNG vincent.chen@to-top.com.hk - 83 - Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM 12.2 Pull Up/Pull Down Driver Characteristics and Calibration [Table 56] Pull-down Driver Characteristics, with ZQ Calibration RONPD,NOM Resistor Min Nom Max Unit 40 Ohm RON40PD 0.9 1.0 1.1 RZQ/6 48 Ohm RON48PD 0.9 1.0 1.1 RZQ/5 60 Ohm RON60PD 0.9 1.0 1.1 RZQ/4 80 Ohm RON80PD 0.9 1.0 1.1 RZQ/3 120 Ohm RON120PD 0.9 1.0 1.1 RZQ/2 240 Ohm RON240PD 0.9 1.0 1.1 RZQ/1 NOTE : 1) All value are after ZQ Calibration. Without ZQ Calibration RONPD values are ± 30%. [Table 57] Pull-up Characteristics, with ZQ Calibration VOHPU, nom VOH,nom (mV) Min Nor Max Unit VDDQ/2.5 440 0.90 1.0 1.10 VOH,nom VDDQ/3 367 0.90 1.0 1.10 VOH,nom NOTE : 1) All values are after ZQ Calibration. Without ZQ Calibration VOH(nom) values are ± 30% 2) VOH,nom (mV) values are based on a nominal VDDQ = 1.1V. [Table 58] Valid Calibration Points ODT Value VOHPU, nom 240 120 80 60 48 40 VDDQ/2.5 VALID VALID VALID DNU DNU DNU VDDQ/3 VALID VALID VALID VALID VALID VALID SAMSUNG NOTE : 1) Once the output is calibrated for a given VOH(nom) calibration point, the ODT value may be changed without recalibration. 2) If the VOH(nom) calibration point is changed, then re-calibration is required. 3) DNU = Do Not Use. [Table 59] Pull-down Characteristics without ZQ Calibration RONPD,NOM Resistor Vout Min vincent.chen@to-top.com.hk Nom Max Unit Notes 40.0Ω RON40PD 0.5 × VOH 0.70 1.00 1.30 RZQ/6 1 48.0Ω RON48PD 0.5 × VOH 0.70 1.00 1.30 RZQ/5 1 NOTE: 1) Across entire operating temperature range, without calibration. [Table 60] Pull-up Characteristics without VOH Calibration (Die to Die variation) VOHPU, (nom) VOH(nom) (mV) Variation Min Nor Max Unit Notes VDDQ/2.5 440 0.70 1.0 1.30 VOH(nom) 1 VDDQ/3 367 0.70 1.0 1.30 VOH(nom) 1 NOTE : 1) ODT value of Memory controller should be informed with MRW before VOH calibration. [Table 61] VOUT level of un-terminated condition Parameter Output High voltage level when ODT of memory controller is turned off - 84 - Symbol Min Max Unit VOH_un-term VDDQ-0.55 VDDQ-0.15 V Note datasheet K4F6E3S4HM-MGCJ Rev. 1.0 LPDDR4 SDRAM 13.0 ELECTRICAL CHARACTERISTICS AND AC TIMING 13.1 Clock Specification The jitter specified is a random jitter meeting a Gaussian distribution. Input clocks violating the min/max values may result in malfunction of the LPDDR4 device. 13.1.1 Definition for tCK(avg) and nCK tCK(avg) is calculated as the average clock period across any consecutive 200 cycle window, where each clock period is calculated from rising edge to rising edge.  tCK  avg  =   where N  j=1  tC K j  N  N = 200 Unit ‘tCK(avg)’ represents the actual clock average tCK(avg) of the input clock under operation. Unit ‘nCK’ represents one clock cycle of the input clock, counting the actual clock edges. tCK(avg) may change by up to +/-1% within a 100 clock cycle window, provided that all jitter and timing specs are met. 13.1.2 Definition for tCK(abs) tCK(abs) is defined as the absolute clock period, as measured from one rising edge to the next consecutive rising edge. tCK(abs) is not subject to production test. 13.1.3 Definition for tCH(avg) and tCL(avg) SAMSUNG tCH(avg) is defined as the average high pulse width, as calculated across any consecutive 200 high pulses. N   tCH vincent.chen@to-top.com.hk avg  =  tC H j   N  tCK  avg      j=1 where N = 200 tCL(avg) is defined as the average low pulse width, as calculated across any consecutive 200 low pulses.  tCL  avg  =   N  j=1 where  tC L j   N  tCK  avg    N = 200 13.1.4 Definition for tCH(abs) and tCL(abs) tCH(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following falling edge. tCL(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following rising edge. Both tCH(abs) and tCL(abs) are not subject to production test. 13.1.5 Definition for tJIT(per) tJIT(per) is the single period jitter defined as the largest deviation of any signal tCK from tCK(avg). tJIT(per) = Min/max of {tCKi - tCK(avg) where i = 1 to 200}. tJIT(per),act is the actual clock jitter for a given system. tJIT(per),allowed is the specified allowed clock period jitter. tJIT(per) is not subject to production test. - 85 - datasheet K4F6E3S4HM-MGCJ Rev. 1.0 LPDDR4 SDRAM 13.1.6 Definition for tJIT(cc) tJIT(cc) is defined as the absolute difference in clock period between two consecutive clock cycles. tJIT(cc) = Max of |{tCK(i +1)- tCK(i)}|. tJIT(cc) defines the cycle to cycle jitter. tJIT(cc) is not subject to production test. 13.1.7 Definition for tERR(nper) tERR(nper) is defined as the cumulative error across n multiple consecutive cycles from tCK(avg). tERR(nper),act is the actual clock jitter over n cycles for a given system. tERR(nper),allowed is the specified allowed clock period jitter over n cycles. tERR(nper) is not subject to production test.  tERR  nper  =   i+n–1  j=i  tC K j – n  tCK  avg   tERR(nper),min can be calculated by the formula shown below: tERR  nper  min =  1 + 0.68LN  n    tJIT  per  min tERR(nper),max can be calculated by the formula shown below tERR  nper  max =  1 + 0.68LN  n    tJIT  per  max Using these equations, tERR(nper) tables can be generated for each tJIT(per),act value. SAMSUNG 13.1.8 Definition for duty cycle jitter tJIT(duty) tJIT(duty) is defined with absolute and average specification of tCH / tCL. tJIT  duty  min = MIN   tCH  abs  min – tCH  avg  min   tCL  abs  min – tCL  avg  min    tCK  avg  vincent.chen@to-top.com.hk tJIT  duty  max = MAX   tCH  abs  max – tCH  avg  max   tCL  abs  max – tCL  avg  max    tCK  avg  13.1.9 Definition for tCK(abs), tCH(abs) and tCL(abs) These parameters are specified per their average values, however it is understood that the following relationship between the average timing and the absolute instantaneous timing holds at all times. [Table 62] Definition for tCK(abs), tCH(abs), and tCL(abs) Parameter Symbol Min Unit Absolute Clock Period tCK(abs) tCK(avg),min + tJIT(per),min ps Absolute Clock HIGH Pulse Width tCH(abs) tCH(avg),min + tJIT(duty),min / tCK(avg)min tCK(avg) Absolute Clock LOW Pulse Width tCL(abs) tCL(avg),min + tJIT(duty),min / tCK(avg)min tCK(avg) NOTE : 1) tCK(avg),min is expressed is ps for this table. 2) tJIT(duty),min is a negative value. - 86 - datasheet K4F6E3S4HM-MGCJ Rev. 1.0 LPDDR4 SDRAM 13.2 Period Clock Jitter LPDDR4 devices can tolerate some clock period jitter without core timing parameter de-rating. This section describes device timing requirements in the presence of clock period jitter (tJIT(per)) in excess of the values found in Table 64, LPDDR4 AC Timing Table and how to determine cycle time de-rating and clock cycle de-rating. 13.2.1 Clock period jitter effects on core timing parameters (tRCD, tRP, tRTP, tWR, tWRA, tWTR, tRC, tRAS, tRRD, tFAW) Core timing parameters extend across multiple clock cycles. Period clock jitter will impact these parameters when measured in numbers of clock cycles. When the device is operated with clock jitter within the specification limits, the LPDDR4 device is characterized and verified to support tnPARAM = RU{tPARAM / tCK(avg)}. When the device is operated with clock jitter outside specification limits, the number of clocks or tCK(avg) may need to be increased based on the values for each core timing parameter. 13.2.1.1 Cycle time de-rating for core timing parameters For a given number of clocks (tnPARAM), for each core timing parameter, average clock period (tCK(avg)) and actual cumulative period error (tERR(tnPARAM),act) in excess of the allowed cumulative period error (tERR(tnPARAM),allowed), the equation below calculates the amount of cycle time de-rating (in ns) required if the equation results in a positive value for a core timing parameter.  tPARAM + tERR  tnPARAM  act – tERR  tnPARAM  allowed  CycleTimeDerating = MAX   -------------------------------------------------------------------------------------------------------------------------------------------------------------------- – tCK  avg   0    tnPARAM   A cycle time derating analysis should be conducted for each core timing parameter. The amount of cycle time derating required is the maximum of the cycle time de-ratings determined for each individual core timing parameter. 13.2.1.2 Clock Cycle de-rating for core timing parameters SAMSUNG For a given number of clocks (tnPARAM) for each core timing parameter, clock cycle de-rating should be specified with amount of period jitter (tJIT(per)). For a given number of clocks (tnPARAM), for each core timing parameter, average clock period (tCK(avg)) and actual cumulative period error (tERR(tnPARAM),act) in excess of the allowed cumulative period error (tERR(tnPARAM),allowed), the equation below calculates the clock cycle derating (in clocks) required if the equation results in a positive value for a core timing parameter. vincent.chen@to-top.com.hk  tPARAM + tERR  tnPARAM  act – tERR  tnPARAM  allowed  ClockCycleDerating = RU  --------------------------------------------------------------------------------------------------------------------------------------------------------------------  – tnPARAM tCK  avg    A clock cycle de-rating analysis should be conducted for each core timing parameter. 13.2.2 Clock jitter effects on Command/Address timing parameters Command/address timing parameters (tIS, tIH, tISb, tIHb) are measured from a command/address signal (CS or CA[5:0]) transition edge to its respective clock signal (CK_t/ CK_c) crossing. The specification values are not affected by the tJIT(per) applied, because the setup and hold times are relative to the clock signal crossing that latches the command/address. Regardless of clock jitter values, these values must be met. - 87 - K4F6E3S4HM-MGCJ datasheet Rev. 1.0 LPDDR4 SDRAM 13.2.3 Clock jitter effects on Read timing parameters 13.2.3.1 tRPRE When the device is operated with input clock jitter, tRPRE needs to be de-rated by the actual period jitter (tJIT(per),act,max) of the input clock in excess of the allowed period jitter (tJIT(per),allowed,max). Output de-ratings are relative to the input clock. tJIT  per  act ,max – tJIT  per  ,allowed ,max tRPRE  min derated  = 0.9 –  ---------------------------------------------------------------------------------------------------------------------   tCK  avg  For example, if the measured jitter into a LPDDR4 device has tCK(avg) = 625ps, tJIT(per),act,min = -xx, and tJIT(per),act,max = +xx ps, then tRPRE,min,derated = 0.9 - (tJIT(per),act,max - tJIT(per),allowed,max)/tCK(avg) = 0.9 - (xx - xx)/xx = yy tCK(avg). 13.2.3.2 tLZ(DQ), tHZ(DQ), tDQSCK, tLZ(DQS), tHZ(DQS) These parameters are measured from a specific clock edge to a data signal (DMn, DQm.: n=0,1,2,3. m=0 –31) transition and will be met with respect to that clock edge. Therefore, they are not affected by the amount of clock jitter applied (i.e. tJIT(per). 13.2.3.3 tQSH, tQSL These parameters are affected by duty cycle jitter which is represented by tCH(abs)min and tCL(abs)min. These parameters determine absolute Data-Valid window(DVW) at the LPDDR4 device pin. Absolute min DVW @LPDDR4 device pin = min { ( tQSH(abs)min – tDQSQmax), (tQSL(abs)min – tDQSQmax) } This minimum DVW shall be met at the target frequency regardless of clock jitter. 13.2.3.4 tRPST tRPST is affected by duty cycle jitter which is represented by tCL(abs). Therefore tRPST(abs)min can be specified by tCL(abs)min. tRPST(abs)min = tCL(abs)min – 0.05 = tQSL(abs)min SAMSUNG 13.2.4 Clock jitter effects on Write timing parameters 13.2.4.1 tDS, tDH vincent.chen@to-top.com.hk These parameters are measured from a data signal (DMn, DQm.: n=0,1,2,3. m=0 –31) transition edge to its respective data strobe signal (DQSn_t, DQSn_c : n=0,1,2,3) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), as the setup and hold are relative to the data strobe signal crossing that latches the data. Regardless of clock jitter values, these values shall be met. 13.2.4.2 tDSS, tDSH These parameters are measured from a data strobe signal (DQSx_t, DQSx_c) crossing to its respective clock signal (CK_t/CK_c) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per)), as the setup and hold of the data strobes are relative to the corresponding clock signal crossing. Regardless of clock jitter values, these values shall be met. - 88 - datasheet K4F6E3S4HM-MGCJ Rev. 1.0 LPDDR4 SDRAM 13.2.4.3 tDQSS This parameter is measured from a data strobe signal (DQSx_t, DQSx_c) crossing to the subsequent clock signal (CK_t/CK_c) crossing. When the device is operated with input clock jitter, this parameter needs to be de-rated by the actual period jitter tJIT(per),act of the input clock in excess of the allowed period jitter tJIT(per),allowed. tJIT  per  act ,min – tJIT  per  ,allowed ,min tDQSS  min derated  = 0.75 – ------------------------------------------------------------------------------------------------------------------tCK  avg  tJIT  per  act ,max – tJIT  per  ,allowed ,max tDQSS  max derated  = 1.25 – --------------------------------------------------------------------------------------------------------------------tCK  avg  For example, if the measured jitter into an LPDDR4 device has tCK(avg) = 625ps, tJIT(per),act,min = -xxps, and tJIT(per),act,max = +xx ps, then: tDQSS,(min,derated) = 0.75 - (-xx + yy)/625 = xxxx tCK(avg) tDQSS,(max,derated) = 1.25 - (xx . yy)/625 = xxxx tCK(avg) 13.3 LPDDR4 Refresh Requirement [Table 63] LPDDR4 Refresh Requirement Parameters per density for Dual Channel SDRAM devices Parameter Density per Channel Number of Banks per Channel Refresh Window Tcase  85C Refresh Window 1/2-Rate Refresh Refresh Window 1/4-Rate Refresh Symbol 16Gb 8Gb 8 Unit tREFW 32 ms tREFW 16 ms SAMSUNG vincent.chen@to-top.com.hk Required number of REFRESH commands in a tREFW window (min) Average Refresh Internal tREFW 8 ms R 8,192 - 3.904 us REFab tREFI REFpb 3) tREFIpb 488 ns Refresh Cycle time (All Banks) tRFCab 280 ns Refresh Cycle time (Per Bank) tRFCpb 140 ns 90 ns Per-bank Refresh to Per-bank Refresh different bank Time tpbR2pbR NOTE : 1) Refresh for each channel is independent of the other channel on the die, or other channels in a package. Power delivery in the user’s system should be verified to make sure the DC operating conditions are maintained when multiple channels are refreshed simultaneously. 2) Self refresh abort feature is available for higher density devices starting with 12Gb dual channel device and 6Gb single channel device and tXSR_abort(min) is defined as tRFCpb + 17.5ns. 3) tREFI values for all bank refresh is Tc = -25~85C, Tc means Operating Case Temperature. - 89 - Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM 13.4 AC Timing [Table 64] LPDDR4 AC Timing Table Parameter Symbol Maximum clock frequency LPDDR4 Min/ Max 3200Mbps 3733Mbps ~ 1600 1866 MIN 0.625 0.536 Unit MHz Clock Timing Average Clock Period tCK(avg) Average HIGH pulse width tCH(avg) Average LOW pulse width tCL(avg) Absolute clock period tCK(abs) Absolute HIGH clock pulse width tCH(abs) Absolute LOW clock pulse width tCL(abs) Clock period jitter tJIT(per) Maximum Clock Jitter between two consecutive cycles tJIT(cc) tJIT(duty), allowed Duty cycle jitter (with supported jitter) ns MAX 100 MIN 0.45 MAX 0.55 MIN 0.45 MAX 0.55 MIN tCK(avg) MIN + tJIT(per) MIN MIN 0.43 MAX 0.57 MIN 0.43 MAX 0.57 tCK(avg) tCK(avg) tCK(avg) tCK(avg) MIN -40 -36 MAX 40 36 MAX 80 72 MIN ps ps min((tCH(abs),min - tCH(avg),min), (tCL(abs),min - tCL(avg),min)) × tCK(avg) max((tCH(abs),max - tCH(avg),max), (tCL(abs),max - tCL(avg),max)) × tCK(avg) SAMSUNG MAX ns ps Core AC Parameters for x16 mode 17) READ latency (no DBI) WRITE latency (set A) RL MIN 28 vincent.chen@to-top.com.hk tCK(avg) 16 tCK(avg) WL MIN ACTIVATE-to-ACTIVATE command period (same bank) tRC MIN tRAS + tRPab (with all-bank precharge) tRAS+ tRPpb (with per-bank precharge) ns Minimum Self-Refresh Time (Entry to Exit) tSR MIN max(15ns, 3tCK) ns SELF REFRESH exit to next valid command delay tXSR MIN Max (tRFCab + 7.5ns, 2tCK) ns tXP MIN Max(7.5ns, 5tCK) ns MIN BL/2 tCK(avg) MIN 4 × tCCD tCK(avg) tRTP MIN Max(7.5ns, 8tCK) ns RAS-to-CAS delay tRCD MIN Max (18ns, 4tCK) ns Row Precharge Time (single bank) tRPpb MIN Max (18ns, 4tCK) ns Row Precharge Time (all banks) tRPab MIN Max(21ns, 4tCK) ns MIN Max(42ns, 3tCK) ns Exit power down to next valid command delay CAS-to-CAS delay CAS to CAS delay Masked Write Internal READ to PRECHARGE command delay tCCD tCCDMW 31) 14 32 Row active time tRAS WRITE recovery time tWR MIN Max(18ns, 6tCK) ns WRITE-to-READ delay tWTR MIN Max(10ns, 8tCK) ns Active bank-A to Active bank-B tRRD MIN Max(10ns, 4tCK) ns MIN 4 tCK tFAW MIN 40 ns tCKELPD MIN Max(7.5ns, 3tCK) ns Precharge to Precharge Delay Four-bank ACTIVATE Window CKE minimum pulse width during SELF REFRESH (low pulse width during SELF REFRESH) tPPD 33) READ AC Parameters 4) - 90 - MAX min (9 × tREFI × Refresh Rate19), 70.2) us datasheet K4F6E3S4HM-MGCJ Rev. 1.0 LPDDR4 SDRAM LPDDR4 Symbol Min/ Max Read preamble tRPRE 5), 8) MIN 2.0 tCK(avg) 0.5 tCK Read postamble tRPST 5), 9) MIN 0.5 tCK(avg) 1.5 tCK Read postamble tRPST MIN 1.5 tCK(avg) DQ low-impedance time from CK_t, CK_c tLZ(DQ) 5) MIN (RL × tCK) + tDQSCK(Min) - 200ps ps DQ high impedance time from CK_t, CK_c tHZ(DQ) 5) MAX (RL × tCK) + tDQSCK(Max) + tDQSQ(Max) + (BL/2 × tCK) - 100ps ps DQS_c low-impedance time from CK_t, CK_c tLZ(DQS) 5) MIN (RL × tCK) + tDQSCK(Min) - (tPRE(Max) × tCK) 200ps ps DQS_c high impedance time from CK_t, CK_c tHZ(DQS) 5) MAX (RL × tCK) + tDQSCK(Max) + (BL/2 × tCK) (RPST(Max) × tCK) - 100ps ps tDQSQ MAX 0.18 UI MIN 1500 MAX 3500 Parameter DQS-DQ skew 3200Mbps 3733Mbps Unit tDQSCK AC Parameters tDQSCK 14) DQS output access time from CK_t/CK_c ps DQS output access time from CK_t/CK_c temperature variation tDQSCK_temp 15) MAX 4 ps/C DQS output access time from CK_t/CK_c voltage variation tDQSCK_volt 16) MAX 7 ps/mV MAX 1.0 ns tESCKE 24) MIN Max(1.75ns, 3tCK) ns tSR24) MIN Max(15ns, 3tCK) ns MIN Max(tRFCab + 7.5ns, 2tCK) ns tDQSCK_rank2ran CK to DQS rank to rank variation k 22),23) Self Refresh Parameters Delay from SRE command to CKE Input low Minimum Self Refresh Time SAMSUNG tXSR24),25) Exit Self Refresh to Valid commands 4) WRITE AC Parameters Write command to 1st DQS latching vincent.chen@to-top.com.hk tDQSS MIN 0.75 MAX 1.25 tCK(avg) DQS input high-level width tDQSH MIN 0.4 tCK(avg) DQS input low-level width tDQSL MIN 0.4 tCK(avg) DQS falling edge to CK setup time tDSS MIN 0.2 tCK(avg) DQS falling edge hold time from CK tDSH MIN 0.2 tCK(avg) tWPRE MIN 2.0 tCK(avg) 0.5 tCK Write postamble tWPST 21) MIN 0.5 tCK(avg) 1.5 tCK Write postamble tWPST 21) MIN 1.5 tCK(avg) Write preamble ZQ Calibration Parameters ZQ Calibration tZQCAL MIN 1 us ZQ Calibration Values Latch Time tZQLAT MN Max (30ns, 8tCK) ns tZQRESET MIN Max (50ns, 3tCK) ns ZQ Calibration RESET time Power Down Parameters CKE minimum pulse width (HIGH and LOW pulse width) Delay from Valid command to CKE Input low Valid Clock Requirement after CKE Input Low tCKE MIN max(7.5ns, 4tCK) - tCMDCKE 26) MIN Max(1.75ns, 3tCK) ns tCKELCK 26) MIN Max(5ns, 5tCK) ns Valid CS Requirement before CKE Input Low tCSCKE MIN 1.75 ns Valid CS Requirement after CKE Input Low tCKELCS MIN Max(5ns,5tCK) ns tCKCKEH 26) MIN Max(1.75ns, 3tCK) -ns Valid Clock Requirement before CKE Input High - 91 - Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM LPDDR4 Symbol Min/ Max Exit power- down to next valid command delay tXP 26) MIN Max(7.5ns, 5tCK) ns Valid CS Requirement before CKE Input High tCSCKEH MIN 1.75 ns Valid CS Requirement after CKE Input High tCKEHCS MIN Max(7.5ns,5tCK) ns tMRWCKEL26) MIN Max(14ns,10tCK) ns tZQCKE 26) MIN Max(1.75ns,3tCK) ns Parameter Valid Clock and CS Requirement after CKE Input low after MRW Command Valid Clock and CS Requirement after CKE Input low after ZQ Calibration Start Command 3200Mbps 3733Mbps Unit Command Address Input Parameters 4) Rx Mask voltage - p-p Rx timing window CA AC input pulse amplitude pk-pk CA input pulse width Input Slew Rate over VcIVW VcIVW MAX 155 TcIVW MAX VIHL_AC MIN TcIPW MIN 0.6 MIN 1 MAX 7 SRIN_cIVW 150 mV 180 mV 0.3 190 UI* UI* V/ns Mode Register Read/Write AC Timing Additional time after tXP has expired until MRR command tMRRI MIN tRCD + 3nCK - MODE REGISTER READ command period tMRR MIN 8 nCK MODE REGISTER WRITE command period tMRW MIN Max(10ns, 10nCK) - Mode register set command delay tMRD MIN Max(14ns, 10tCK) - Boot Parameters (10 MHz - 55 MHz) Clock Cycle Time 11), 12), 13) SAMSUNG tCKb max 100 MIN 18 ns Address & Control Input Setup Time tISb MIN 1150 ps Address & Control Input Hold Time tIHb MIN 1150 ps MIN 2.0 MAX 10.0 MAX 1.2 ns vincent.chen@to-top.com.hk DQS Output Data Access Time from CK_t/CK_c tDQSCKb Data Strobe Edge to Output Data Edge tDQSQb ns Command Bus Training AC Parameters Valid Clock Requirement after CKE Input low tCKELCK MIN Max(5ns, 5nCK) tCK Data Setup for VREF Training Mode tDStrain MIN 2 ns Data Hold for VREF Training Mode tDHtrain MIN 2 ns tADR MAX 20 ns tCACD 29) MIN RU(tADR/tCK) tCK tDQSCKE 30) MIN 10 ns tCAENT MIN 250 ns VREF Step Time-multiple steps tVREFCA_LONG MAX 250 ns VREF Step Time-one step tVREFCA_SHORT MAX Asynchronous Data Read CA Bus Training command to CA Bus Training command delay Valid Strobe Requirement before CKE Low First CA Bus Training Command Following CKE LOW 80 ns Valid Clock Requirement before CS High tCKPRECS MIN 2tCK + tXP (tXP = max(7.5ns, 5nCK)) - Valid Clock Requirement after CS High tCKPSTCS MIN max(7.5ns, 5nCK) - Minimum delay from CS to DQS toggle in command bus training tCS_VREF MIN 2 tCK Minimum delay from CKE High to Strobe High Impedance tCKEHDQS - 10 ns tCKCKEH MIN Max(1.75ns, 3tCK) tMRZ MIN 1.5 ns ODT turn-on Latency from CKE tCKELODTon MIN 20 ns ODT turn-off Latency from CKE tCKELODToff MIN 20 ns Valid Clock Requirement before CKE Input High CA Bus Training CKE High to DQ Tri-state - 92 - Rev. 1.0 datasheet K4F6E3S4HM-MGCJ Parameter Exit Command Bus Training Mode to next valid command delay 32) LPDDR4 SDRAM LPDDR4 Symbol Min/ Max tXCBT_Short MIN Max(5nCK, 200ns) - tXCBT_Middle MIN Max(5nCK, 200ns) - tXCBT_Long MIN Max(5nCK, 250ns) - 3200Mbps 3733Mbps Unit Write Leveling Parameters DQS_t/DQS_c delay after write leveling mode is programmed tWLDQSEN MIN 20 tCK Write preamble for Write Leveling tWLWPRE MIN 20 tCK First DQS_t/DQS_c edge after write leveling mode is programmed tWLMRD MIN 40 tCK Write leveling output delay tWLO MAX 20 ns Mode register set command delay tMRD MIN Max(14ns, 10tCK) ns Valid Clock Requirement before DQS Toggle tCKPRDQS MIN Max(7.5ns, 4tCK) - Valid Clock Requirement after DQS Toggle tCKPSTDQS MIN Max(7.5ns, 4tCK) - Write leveling hold time tWLH 27) MIN 75 60 ps Write leveling setup time tWLS 27) MIN 75 60 ps MIN 120 100 ps tWLIVW Write leveling input valid window 28) Temperature De-Rating AC Timing 20) tDQSCK MAX 3600 ps RAS-to-CAS delay (derated) tRCD MIN tRCD + 1.875 ns ACTIVATE-to- ACTIVATE command period (derated) tRC MIN tRC + 3.75 ns Row active time (derated) tRAS MIN tRAS + 1.875 ns tRP MIN tRP + 1.875 ns MIN tRRD + 1.875 ns DQS output access time from CK_t/CK_c (derated) Row precharge time (derated) SAMSUNG tRRD Active bank A to active bank B (derated) NOTE : 1) Frequency values are for reference only. Clock cycle time (tCK) is used to determine device capabilities. 2) All AC timings assume an input slew rate of TBDV/ns. 3) Measured with 4 V/ns differential CK_t/CK_c slew rate and nominal VIX. 4) READ, WRITE, and Input setup and hold values are referenced to VREF. 5) For LOW-to-HIGH and HIGH-to-LOW transitions, the timing reference is at the point when the signal crosses the transition threshold (VTT). tHZ and tLZ transitions occur in the same access time (with respect to clock) as valid data transitions. These parameters are not referenced to a specific voltage level but to the time when the device output is no longer driving (for tRPST, tHZ(DQS) and tHZ(DQ)), or begins driving (for tRPRE, tLZ(DQS), tLZ(DQ)). Operating and Timing [Burst Read:RL=12, BL=8, tDQSCK 20 MHz and max voltage of 45 mV pk-pk from DC-20 MHz at a fixed temperature on the package. The voltage supply noise must comply to the component Min-Max DC Operating conditions. - 93 - K4F6E3S4HM-MGCJ datasheet Rev. 1.0 LPDDR4 SDRAM 15) tDQSCK_temp max delay variation as a function of Temperature. 16) tDQSCK_volt max delay variation as a function of DC voltage variation for VDDQ and VDD2. tDQSCK_volt should be used to calculate timing variation due to VDDQ and VDD2 noise < 20 MHz. Host controller do not need to account for any variation due to VDDQ and VDD2 noise > 20 MHz. The voltage supply noise must comply to the component Min-Max DC Operating conditions. The voltage variation is defined as the Max[abs{tDQSCKmin@V1-tDQSCKmax@V2}, abs{tDQSCKmax@V1-tDQSCKmin@V2}]/ abs{V1-V2}. For tester measurement VDDQ = VDD2 is assumed. 17) Precharge to precharge timing restriction does not apply to Auto-Precharge commands. 18) tXSR/tXP/tZQLAT are defined as “to the first rising clock edge next valid command”. 19) Refresh Rate is specified by MR4, OP[2:0]. 20) Timing derating applies for operation at 85°C to 105°C. 21) The length of Write Postamble depends on MR3 OP1 setting. 22) The same voltage and temperature are applied to tDQS2CK_rank2rank. 23) tDQSCK_rank2rank parameter is applied to multi-ranks per byte lane within a package consisting of the same design dies. 24) Delay time has to satisfy both analog time(ns) and clock count(tCK). It means that tESCKE will not expire until CK has toggled through at least 3 full cycles (3 *tCK) and 1.75ns has transpired. The case which 3tCK is applied to is shown below. Figure 23. tESCKE Timing 25) MRR-1, CAS-2, DES, MPC, MRW-1 and MRW-2 except PASR Bank/Segment setting are only allowed during this period. 26) Delay time has to satisfy both analog time(ns) and clock count(nCK). For example, tCMDCKE will not expire until CK has toggled through at least 3 full cycles (3 *tCK) and 1.75ns has transpired.The case which 3nCK is applied to is shown below. SAMSUNG vincent.chen@to-top.com.hk Figure 24. tCMDCKE Timing 27) In addition to the traditional setup and hold time specifications above, there is value in a input valid window based specification for write-leveling training. As the training is based on each device, worst case process skews for setup and hold do not make sense to close timing between CK and DQS. 28) tWLIVW is defined in a similar manner to tdIVW_Total, except that here it is a DQS input valid window with respect to CK. This would need to account for all VT (voltage and temperature) drift terms between CK and DQS within the DRAM that affect the write-leveling input valid window. The DQS input mask for timing with respect to CK is shown in Figure 25. The "total" mask (tWLIVW) defines the time the input signal must not encroach in order for the DQS input to be successfully captured by CK with a BER of lower than tbd. The mask is a receiver property and it is not the valid data-eye. Figure 25. DQS_t/DQS_c to CK_t/CK_c timings at the DRAM pins referenced from the internal latch 29) If tCACD is violated, the data for samples which violate tCACD will not be available, except for the last sample (where tCACD after this sample is met). Valid data for the last sample will be available after tADR. 30) DQS_t has to retain a low level during tDQSCKE period, as well as DQS_c has to retain a high level. 31) See Masked Write Operation for detail. 32) Exit Command Bus Training Mode to next valid command delay Time depends on value of VREF(CA) setting: MR12 OP[5:0] and VREF(CA) Range: MR12 OP[6] of FSP-OP 0 and 1. The details are shown in tFC value mapping table. Additionally exit Command Bus Training Mode to next valid command delay Time may affect VREF(DQ) setting. Settling time of VREF(DQ) level is same as VREF(CA) level. 33) Precharge to precharge timing restriction does not apply to Auto-Precharge commands. - 94 - datasheet K4F6E3S4HM-MGCJ Rev. 1.0 LPDDR4 SDRAM 13.5 CA Rx Voltage and Timing The command and address(CA) including CS input receiver compliance mask for voltage and timing is shown in the figure below. All CA, CS signals apply the same compliance mask and operate in single data rate mode. The CA input receiver mask for voltage and timing is shown in the figure below is applied across all CA pins. The receiver mask (Rx Mask) defines the area that the input signal must not encroach in order for the DRAM input receiver to be expected to be able to successfully capture a valid input signal; it is not the valid data-eye. Figure 26. CA Receiver (Rx) mask SAMSUNG vincent.chen@to-top.com.hk Figure 27. Across pin VREFCA voltage variation Vcent_CA(pin avg) is defined as the midpoint between the largest Vcent_CA voltage level and the smallest Vcent_CA voltage level across all CA and CS pins for a given DRAM component. Each CA Vcent level is defined by the center, i.e. widest opening, of the cumulative data input eye as depicted in Figure 27. This clarifies that any DRAM component level variation must be accounted for within the DRAM CA Rx mask. The component level Vref will be set by the system to account for Ron and ODT settings. - 95 - K4F6E3S4HM-MGCJ datasheet Rev. 1.0 LPDDR4 SDRAM Figure 28. CA Timings at the DRAM pins All of the timing terms in Figure 28. are measured from the CK_t/CK_c to the center(midpoint) of the TcIVW window taken at the VcIVW_total voltage levels centered around Vcent_CA(pin mid). SAMSUNG vincent.chen@to-top.com.hk Figure 29. CA TcIPW and SRIN_cIVW definition (for each input pulse) NOTE : 1) SRIN_cIVW=VcIVW_Total/(tr or tf), signal must be monotonic within tr and tf range. - 96 - Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM VIHL_AC(min)/2 Vcent CA Rx Mask Rx Mask Rx Mask VcIVW VIHL_AC(min)/2 Figure 30. CA VIHL_AC definition (for each input pulse) [Table 65] DRAM CMD/ADR, CS Symbol Parameter VcIVW TcIVW VIHL_AC DQ-1333 A) min max Rx Mask voltage - p-p - Rx timing window - CA AC input pulse amplitude pk-pk 210 TcIPW CA input pulse width SRIN_cIVW Input Slew Rate over VcIVW DQ-1600/1866 DQ-3733 DQ-3200 Unit NOTE 150 mV 1,2,3 0.3 UI* 1,2,3 - mV 4,7 - UI* 5 7 V/ns 6 min max min max min max 175 - 175 - 155 - 0.3 - 0.3 - 0.3 - - 210 - 190 - 180 0.55 - 0.55 - 0.6 - 0.6 1 7 1 7 1 7 1 * UI=tCK(avg)min NOTE : 1) CA Rx mask voltage and timing parameters at the pin including voltage and temperature drift. 2) Rx mask voltage VcIVW total(max) must be centered around Vcent_CA (pin_mid). 3) Vcent_CA must be within the adjustment range of the CA internal Vref. 4) CA only input pulse signal amplitude into the receiver must meet or exceed VIHL AC at any point over the total UI. No timing requirement above level. VIHL AC is the peak to peak voltage centered around Vcent_CA(pin mid) such that VIHL_AC/2 min must be met both above and below Vcent_CA. 5) CA only minimum input pulse width defined at the Vcent_CA (pin mid). 6) Input slew rate over VcIVW Mask centered at Vcent_CA (pin mid). 7) VIHL_AC does not have to be met when no transitions are occurring. SAMSUNG vincent.chen@to-top.com.hk A) The following Rx voltage and absolute timing requirements apply for DQ operating frequencies at or below 1333 for all speed bins. For example the TcIVW(ps) = 450ps at or below 1333 operating frequencies. - 97 - datasheet K4F6E3S4HM-MGCJ Rev. 1.0 LPDDR4 SDRAM 13.6 DRAM Data Timing Figure 31. Read data timing definitions tQH and tDQSQ across on DQ signals per DQS group SAMSUNG vincent.chen@to-top.com.hk - 98 - datasheet K4F6E3S4HM-MGCJ Rev. 1.0 LPDDR4 SDRAM DQS_c DQS_t DQx tQW tQW DQx SAMSUNG tQW DQz vincent.chen@to-top.com.hk Figure 32. Read data timing tQW valid window defined per DQ signal - 99 - Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM [Table 66] Read output timings Parameter Symbol LPDDR4-1600/ 1866 LPDDR4-2133/ 2400 LPDDR4-3200 LPDDR4-3733 Units Min Max Min Max Min Max Min Max - 0.18 - 0.18 - 0.18 - 0.18 UI - UI Notes Data Timing DQS_t, DQS_c to DQ Skew total, per group, per access (DBI-Disabled) DQ output hold time total from DQS_t, DQS_c (DBI-Disabled) tDQSQ tQH DQ output window time total, per pin (DBI-Disabled) min(tQS H,tQSL) - min(tQS H, tQSL) - min(tQS H, tQSL) - min(tQS H, tQSL) tQW_total 0.75 - 0.73 - 0.7 - 0.7 - UI 3 DQ output window time deterministic, per pin (DBI-Disabled) tQW_dj - TBD - TBD - TBD - TBD UI 2,3 DQS_t, DQS_c to DQ Skew total, per group, per access (DBI-Enabled) tDQSQ_DB - 0.18 - 0.18 - 0.18 - 0.18 UI min (tQSH_DBI, tQSL_DBI) - min (tQSH_DBI, tQSL_DBI) - min (tQSH_DBI, tQSL_DBI) - min (tQSH_DBI, tQSL_DBI) - UI 0.75 - 0.73 - 0.7 - 0.7 - UI 3 - tCK(avg) 3,4 - tCK(avg) 3,5 - tCK(avg) 4,6 - tCK(avg) 5,6 DQ output hold time total from DQS_t, DQS_c (DBI-Enabled) DQ output window time total, per pin (DBI-Enabled) I tQH_DBI tQW_total_ DBI Data Strobe Timing DQS_t, DQS_c differential output low time (DBI-Disabled) tQSL DQS_t, DQS_c differential output high time (DBI-Disabled) tQSH DQS_t, DQS_c differential output low time (DBI-Enabled) DQS_t, DQS_c differential output high time (DBI-Enabled) tCL(abs)0.05 tCH(abs)- - tCL(abs)0.05 tCH(abs)- - tCL(abs)0.05 tCH(abs)- - tCL(abs)0.05 tCH(abs)- SAMSUNG tQSL_DBI 0.05 tCL(abs)0.045 t tQSH_DBI CH(abs) 0.045 - - 0.05 tCL(abs)0.045 tCH(abs)- - - 0.05 tCL(abs)0.045 tCH(abs)- - - 0.05 tCL(abs)0.045 tCH(abs)- vincent.chen@to-top.com.hk 0.045 0.045 0.045 Unit UI = tCK(avg)min/2 NOTE : 1) The deterministic component of the total timing. Measurement method tbd. 2) This parameter will be characterized and guaranteed by design. 3) This parameter is function of input clock jitter. These values assume the min tCH(abs) and tCL(abs). When the input clock jitter min tCH(abs) and tCL(abs) is 0.44 or greater of tck(avg) the min value of tQSL will be tCL(abs)-0.04 and tQSH will be tCH(abs) -0.04. 4) tQSL describes the instantaneous differential output low pulse width on DQS_t - DQS_c, as it measured the next rising edge from an arbitrary falling edge. 5) tQSH describes the instantaneous differential output high pulse width on DQS_t - DQS_c, as it measured the next rising edge from an arbitrary falling edge. 6) This parameter is function of input clock jitter. These values assume the min tCH(abs) and tCL(abs). When the input clock jitter min tCH(abs) and tCL(abs) is 0.44 or greater of tck(avg) the min value of tQSL will be tCL(abs)-0.04 and tQSH will be tCH(abs) -0.04. - 100 datasheet K4F6E3S4HM-MGCJ Rev. 1.0 LPDDR4 SDRAM 13.7 DQ Rx Voltage And Timing The DQ input receiver mask for voltage and timing is shown Figure 33. is applied per pin. The “total” mask (VdIVW_total, TdiVW_total) defines the area the input signal must not encroach in order for the DQ input receiver to successfully capture an input signal with a BER of lower than tbd. The mask is a receiver property and it is not the valid data-eye. Figure 33. DQ Receiver (Rx) mask SAMSUNG vincent.chen@to-top.com.hk Figure 34. Across pin VREFDQ voltage variation Vcent_DQ(pin mid) is defined as the midpoint between the largest Vcent_DQ voltage level and the smallest Vcent_DQ voltage level across all DQ pins for a given DRAM component. Each DQ Vcent is defined by the center, i.e., widest opening, of the cumulative data input eye as depicted in Figure 34. This clarifies that any DRAM component level variation must be accounted for within the DRAM Rx mask. The component level Vref will be set by the system to account for Ron and ODT settings. - 101 Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM DQ, DQS Data-in at DRAM Latch DQ, DQS Data-in at DRAM Pin Internal Componsite Data- Eye Center aligned to DQS Non Minimum Data-Eye/ Maximum Rx Mask DQS_c DQS_c DQS_t DQS_t tDQS2DQx* VdIVW_total Rx Mask DRAM Pin DQx,y,z tDQS2DQy* VdIVW_total All DQ signals center aligned to the strobe at the DRAM internal latch Rx Mask DRAM Pin tDQS2DQz* VdIVW_total SAMSUNG Rx Mask DRAM Pin vincent.chen@to-top.com.hk tDQ2DQ Figure 35. DQ to DQS tDQS2DQ & tDQDQ Timings at the DRAM pins referenced from the internal latch NOTE : 1) tDQS2DQ is measured at the center(midpoint) of the TdiVW window. 2) DQz represents the max tDQS2DQ in this example. 3) DQy represents the min tDQS2DQ in this example. - 102 Rev. 1.0 datasheet K4F6E3S4HM-MGCJ tr LPDDR4 SDRAM tf Rx Mask VdIVW Total Vcent_DQ(pin mid) TdIPW Figure 36. DQ TdIPW and SRIN_dIVW definition (for each input pulse) NOTE : 1) SRIN_dIVW=VdIVW_Total/(tr or tf), signal must be monotonic within tr and tf range. VIHL_AC(min)/2 Vcent DQ Rx Mask Rx Mask Rx Mask VdIVW_total VIHL_AC(min)/2 SAMSUNG Figure 37. DQ VIHL_AC definition (for each input pulse) vincent.chen@to-top.com.hk - 103 Rev. 1.0 datasheet K4F6E3S4HM-MGCJ LPDDR4 SDRAM [Table 67] DRAM DQs In Receive Mode; Symbol 1600/1866 A) Parameter 2133/2400 3733 3200 min max min max min max min max Unit NOTE VdIVW_total Rx Mask voltage - p-p total - 140 - 140 - 140 - 130 mV 1,2,3,4 TdIVW_total Rx timing window total (At VdIVW voltage levels) - 0.22 - 0.22 - 0.25 - 0.25 UI* 1,2,4 TdIVW_1bit Rx timing window 1 bit toggle (At VdIVW voltage levels) - TBD - TBD - TBD - TBD UI* 1,2,4,12 DQ AC input pulse amplitude pkpk 180 - 180 - 180 - 180 - mV 5,13 TdIPW DQ Input pulse width (At Vcent_DQ) 0.45 - 0.45 - 0.45 - 0.45 - UI* 6 tDQS2DQ DQ to DQS offset 250 700 250 700 250 700 250 700 ps 7 tDQ2DQ DQ to DQ offset - 30 - 30 - 30 - 30 ps 8 tDQS2DQ_temp DQ to DQS offset temperature variation - 0.4 - 0.4 - 0.4 - 0.4 ps/C 9 tDQS2DQ_volt DQ to DQS offset voltage variation - 25 - 25 - 25 - 25 ps/50mV 10 SRIN_dIVW Input Slew Rate over VdIVW_total 1 7 1 7 1 7 1 7 V/ns 11 DQ to DQS offset rank to rank variation - 200 - 200 - 200 - 200 ps 14,15,16 VIHL_AC tDQS2DQ_rank2rank * UI=tck(avg)min/2 NOTE : 1) Data Rx mask voltage and timing parameters are applied per pin and includes the DRAM DQ to DQS voltage AC noise impact for frequencies >20MHz and max voltage of 45mv pk-pk from DC-20MHz at a fixed temperature on the package. The voltage supply noise must comply to the component Min-Max DC operating conditions. 2) The design specification is a BER 20MHz and max voltage of 45mv pk-pk from DC-20MHz at a fixed temperature on the package. For tester measurement VDDQ=VDD2 is assumed. 11) Input slew rate over VdIVW Mask centered at Vcent_DQ(pin mid). 12) Rx mask defined for a one pin toggling with other DQ signals in a steady state. 13) VIHL_AC does not have to be met when no transitions are occurring. 14) The same voltage and temperature are applied to tDQS2DQ_rank2rank. 15) tDQS2DQ_rank2rank parameter is applied to multi-ranks per byte lane within a package consisting of the same design dies. 16) tDQS2DQ_rabk2rank support was added to JESD209-4B, some older devices designed to support JESD209-4 and JESD209-4A may not support this parameter. Refer to vendor datasheet. SAMSUNG vincent.chen@to-top.com.hk A) The Rx voltage and absolute timing requirements apply for all DQ operating frequencies at or below 1600 for all speed bins. For example TdIVW_total(ps) = 137.5ps at or below 1600 operating frequencies. - 104