K6R1008V1D-UC10

K6R1004V1D Document Title 64Kx16 Bit High-Speed CMOS Static RAM(3.3V Operating) Operated at Commercial and Industrial Temperature Ranges. PRELIMINARY PRELIMINARY for AT&T CMOS SRAM Revision History Rev. No. Rev. 0.0 Rev. 0.1 Rev. 0.2 Rev. 1.0 History Initial document. Speed bin modify Current modify 1. Final datasheet release 2. Delete 12ns speed bin. 3. Change Icc for Industrial mode. Item Previous 8ns 100mA ICC(Industrial) 10ns 85mA 1. Delete UB,LB releated timing diagram. 1. Add the Lead Free Package type. Draft Data May. 11. 2001 June. 18. 2001 September. 9. 2001 December. 18. 2001 Current 90mA 75mA June. 19. 2002 July. 26, 2004 Final Final Remark Preliminary Preliminary Preliminary Final Rev. 2.0 Rev. 3.0 The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters. -1- Rev. 3.0 July 2004 K6R1004V1D 1Mb Async. Fast SRAM Ordering Information Org. 256K x4 Part Number K6R1004C1D-J(K)C(I) 10 K6R1004V1D-J(K)C(I) 08/10 K6R1008C1D-J(K,T,U)C(I) 10 128K x8 K6R1008V1D-J(K,T,U)C(I) 08/10 K6R1016C1D-J(K,T,U,E)C(I) 10 64K x16 K6R1016V1D-J(K,T,U,E)C(I) 08/10 3.3 5 3.3 8/10 10 8/10 VDD(V) 5 3.3 5 Speed ( ns ) 10 8/10 10 PKG J : 32-SOJ K: 32-SOJ(LF) J : 32-SOJ K : 32-SOJ(LF) T : 32-TSOP2 U : 32-TSOP2(LF) J : 44-SOJ K : 44-SOJ(LF) T : 44-TSOP2 U : 44-TSOP2(LF) E : 48-TBGA PRELIMINARY PRELIMINARY for AT&T CMOS SRAM Temp. & Power C : Commercial Temperature ,Normal Power Range I : Industrial Temperature ,Normal Power Range -2- Rev. 3.0 July 2004 K6R1004V1D FEATURES • Fast Access Time 8,10ns(Max.) • Low Power Dissipation Standby (TTL) : 20mA(Max.) (CMOS) : 5mA(Max.) Operating //K6R1004V1D-08: 80mA(Max.) K6R1004V1D-10: 65mA(Max.) • Single 3.3±0.3V Power Supply • TTL Compatible Inputs and Outputs • Fully Static Operation - No Clock or Refresh required • Three State Outputs • Center Power/Ground Pin Configuration • Standard Pin Configuration : K6R1004V1D-J : 32-SOJ-400 K6R1004V1D-K : 32-SOJ-400 (Lead-Free) • Operating in Commercial and Industrial Temperature range. PRELIMINARY PRELIMINARY for AT&T CMOS SRAM 256K x 4 Bit (with OE) High-Speed CMOS Static RAM(3.3V Operating) GENERAL DESCRIPTION The K6R1004V1D is a 1,048,576-bit high-speed Static Random Access Memory organized as 262,144 words by 4 bits. The K6R1004V1D uses 4 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. The device is fabricated using SAMSUNG′s advanced CMOS process and designed for high-speed circuit technology. It is particularly well suited for use in high-density high-speed system applications. The K6R1004V1D is packaged in a 400 mil 32-pin plastic SOJ. PIN CONFIGURATION(Top View) N.C 1 2 3 4 5 6 7 8 9 32 A17 31 A16 30 A15 29 A14 28 A13 27 OE 26 I/O4 FUNCTIONAL BLOCK DIAGRAM A0 A1 A2 Clk Gen. A0 A1 A2 A3 A4 A5 A6 A7 A8 Pre-Charge Circuit A3 CS I/O1 Vcc Row Select Vss SOJ 25 Vss 24 Vcc 23 I/O3 22 A12 21 A11 20 A10 19 18 A9 A8 Memory Array 512 Rows 512x4 Columns I/O2 10 WE A4 A5 A6 11 12 13 14 15 I/O1 ~ I/O4 Data Cont. CLK Gen. I/O Circuit & Column Select A7 N.C 16 17 N.C PIN FUNCTION A9 A10 A11 A12 A13 A14 A15 A16 A17 Pin Name A0 - A17 WE CS OE I/O1 ~ I/O4 VCC VSS N.C Pin Function Address Inputs Write Enable Chip Select Output Enable Data Inputs/Outputs Power(+3.3V) Ground No Connection CS WE OE -3- Rev. 3.0 July 2004 K6R1004V1D ABSOLUTE MAXIMUM RATINGS* Parameter Voltage on Any Pin Relative to VSS Voltage on VCC Supply Relative to VSS Power Dissipation Storage Temperature Operating Temperature Commercial Industrial Symbol VIN, VOUT VCC Pd TSTG TA TA Rating -0.5 to 4.6 -0.5 to 4.6 1 -65 to 150 0 to 70 -40 to 85 PRELIMINARY PRELIMINARY for AT&T CMOS SRAM Unit V V W °C °C °C * Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED DC OPERATING CONDITIONS(TA=0 to 70°C) Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min 3.0 0 2.0 -0.3* Typ 3.3 0 Max 3.6 0 VCC+0.3** 0.8 Unit V V V V * VIL(Min) = -2.0V a.c (Pulse Width ≤ 8ns) for I ≤ 20mA. ** VIH(Max) = VCC + 2.0V a.c (Pulse Width ≤ 8ns) for I ≤ 20mA. DC AND OPERATING CHARACTERISTICS*(TA=0 to 70°C, Vcc=3.3±0.3V, unless otherwise specified) Parameter Input Leakage Current Output Leakage Current Operating Current Symbol ILI ILO ICC VIN=VSS to VCC CS=VIH or OE=VIH or WE=VIL VOUT=VSS to VCC Min. Cycle, 100% Duty CS=VIL, VIN=VIH or VIL, IOUT=0mA Com. Ind. Standby Current ISB ISB1 Output Low Voltage Level Output High Voltage Level VOL VOH Min. Cycle, CS=VIH f=0MHz, CS≥VCC-0.2V, VIN≥VCC-0.2V or VIN≤0.2V IOL=8mA IOH=-4mA 8ns 10ns 8ns 10ns Test Conditions Min -2 -2 2.4 Max 2 2 80 65 90 75 20 5 0.4 V V mA Unit µA µA mA * The above parameters are also guaranteed at industrial temperature range. CAPACITANCE*(TA=25°C, f=1.0MHz) Item Input/Output Capacitance Input Capacitance * Capacitance is sampled and not 100% tested. Symbol CI/O CIN Test Conditions VI/O=0V VIN=0V TYP - Max 8 6 Unit pF pF -4- Rev. 3.0 July 2004 K6R1004V1D AC CHARACTERISTICS(TA=0 to 70°C, VCC=3.3±0.3V, unless otherwise noted.) TEST CONDITIONS Parameter Input Pulse Levels Input Rise and Fall Times Input and Output timing Reference Levels Output Loads PRELIMINARY PRELIMINARY for AT&T CMOS SRAM Value 0V to 3V 3ns 1.5V See below Output Loads(A) Output Loads(B) for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ RL = 50Ω +3.3V DOUT VL = 1.5V ZO = 50Ω 30pF* DOUT 319Ω 353Ω 5pF* * Capacitive Load consists of all components of the test environment. * Including Scope and Jig Capacitance READ CYCLE* Parameter Read Cycle Time Address Access Time Chip Select to Output Output Enable to Valid Output Chip Enable to Low-Z Output Output Enable to Low-Z Output Chip Disable to High-Z Output Output Disable to High-Z Output Output Hold from Address Change Chip Selection to Power Up Time Chip Selection to Power DownTime Symbol tRC tAA tCO tOE tLZ tOLZ tHZ tOHZ tOH tPU tPD K6R1004V1D-08 K6R1004V1D-10 Min 8 3 0 0 0 3 0 - Max 8 8 4 4 4 8 Min 10 3 0 0 0 3 0 - Max 10 10 5 5 5 10 Unit ns ns ns ns ns ns ns ns ns ns ns * The above parameters are also guaranteed at industrial temperature range. -5- Rev. 3.0 July 2004 K6R1004V1D WRITE CYCLE* Parameter Write Cycle Time Chip Select to End of Write Address Set-up Time Address Valid to End of Write Write Pulse Width(OE High) Write Pulse Width(OE Low) Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End of Write to Output Low-Z Symbol tWC tCW tAS tAW tWP tWP1 tWR tWHZ tDW tDH tOW K6R1004V1D-08 PRELIMINARY PRELIMINARY for AT&T CMOS SRAM K6R1004V1D-10 Min 8 6 0 6 6 8 0 0 4 0 3 Max 4 - Min 10 7 0 7 7 10 0 0 5 0 3 Max 5 - Unit ns ns ns ns ns ns ns ns ns ns ns * The above parameters are also guaranteed at industrial temperature range. TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH) tRC Address tOH Data Out Previous Valid Data tAA Valid Data TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) tRC Address tAA tCO tHZ(3,4,5) CS tOHZ OE tOLZ Data out ICC ISB High-Z tOE tDH Valid Data tPD 50% 50% tLZ(4,5) tPU VCC Current -6- Rev. 3.0 July 2004 K6R1004V1D NOTES(READ CYCLE) PRELIMINARY PRELIMINARY for AT&T CMOS SRAM 1. WE is high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL levels. 4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device. 5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested. 6. Device is continuously selected with CS=VIL. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. TIMING WAVEFORM OF WRITE CYCLE(1) (OE= Clock) tWC Address tAW OE tCW(3) CS tAS(4) WE tDW Data in High-Z tOHZ(6) Data out High-Z(8) Valid Data tDH tWP(2) tWR(5) TIMING WAVEFORM OF WRITE CYCLE(2) (OE=Low Fixed) tWC Address tAW CS tAS(4) WE tDW Data in High-Z tWHZ(6) Data out High-Z(8) Valid Data tOW (10) (9) tCW(3) tWP1(2) tWR(5) tDH -7- Rev. 3.0 July 2004 K6R1004V1D TIMING WAVEFORM OF WRITE CYCLE(3) (CS=Controlled) tWC Address tAW CS tAS(4) WE tDW Data in tCW(3) tWP(2) PRELIMINARY PRELIMINARY for AT&T CMOS SRAM tWR(5) tDH High-Z tLZ tWHZ(6) Valid Data High-Z Data out High-Z High-Z(8) NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ; A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of CS going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high. 6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state. 9. Dout is the read data of the new address. 10.When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied. FUNCTIONAL DESCRIPTION CS H L L L * X means Don′t Care. WE X H H L OE X* H L X Mode Not Select Output Disable Read Write I/O Pin High-Z High-Z DOUT DIN Supply Current ISB, ISB1 ICC ICC ICC -8- Rev. 3.0 July 2004 K6R1004V1D PACKAGE DIMENSIONS 32-SOJ-400 #32 #17 PRELIMINARY PRELIMINARY for AT&T CMOS SRAM Units:millimeters/Inches 10.16 0.400 11.18 ±0.12 0.440 ±0.005 9.40 ±0.25 0.370 ±0.010 0.20 #1 21.36 MAX 0.841 20.95 ±0.12 0.825 ±0.005 ( 1.30 ) 0.051 ( 1.30 ) 0.051 ( 0.95 ) 0.0375 +0.10 -0.05 +0.004 0.017 -0.002 +0.10 -0.05 #16 0.69 MIN 0.027 0.008 +0.004 -0.002 3.76 MAX 0.148 0.10 MAX 0.004 0.43 1.27 0.050 +0.10 -0.05 +0.004 0.028 -0.002 0.71 -9- Rev. 3.0 July 2004