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KC74125B

KC74125B

  • 厂商:

    SAMSUNG(三星)

  • 封装:

  • 描述:

    KC74125B - 1/4 INCH CCD IMAGE SENSOR FOR EIA CAMERA - Samsung semiconductor

  • 数据手册
  • 价格&库存
KC74125B 数据手册
KC74125B 1/4 INCH CCD IMAGE SENSOR FOR EIA CAMERA INTRODUCTION The KC74125B is an interline transfer CCD area image sensor developed for EIA 1/4 inch optical format video cameras, surveillance cameras, object detectors and image pattern recognizers. High sensitivity is achieved through onchip micro lenses and HAD (Hole Accumulated Diode) photosensors. This chip features a field integration read out system and an electronic shutter with variable charge storage time. 14Pin Cer DIP FEATURES • • • • • • • • • High Sensitivity Optical Size 1/4 inch Format No adjust Substrate Bias Variable Speed Electronic Shutter (1/60, 1/100 ~ 1/10,000sec) Low Dark Current Horizontal Register 3.3 to 5.0V Drive 14pin Ceramic DIP Package Field Integration Read Out System No DC Bias on Reset Gate ORDERING INFORMATION Device KC74125B Package 14Pin Cer DIP Operating -10 °C ~ +60 °C STRUCTURE • • • • • Number of Total Pixels: Number of Effective Pixels: Chip Size: Unit Pixel Size: Optical Blacks & Dummies: 537(H) × 505(V) 510(H) × 492(V) 4.83mm(H) × 4.04mm(V) 7.15µm(H) × 5.55µm(V) Refer to Figure Below Vertical 1 Line (Even Field Only) 16 2 510 25 1 Dummy Pixels Optical Black Pixels Effective Imaging Area OUTPUT V-CCD 492 12 Effective Pixels H-CCD 1 1/4 INCH CCD IMAGE SENSOR FOR EIA CAMERA KC74125B BLOCK DIAGRAM (Top View) 7 VOUT 6 GND 5 NC ΦV1 4 ΦV2 3 ΦV3 2 ΦV4 1 Vertical Shift Register CCD Vertical Shift Register CCD Vertical Shift Register CCD Horizontal Shift Register CCD Vertical Shift Register CCD 8 VDD 9 GND ΦSUB 10 11 VL ΦRG 12 ΦH1 13 ΦH2 14 Figure 1. Block Diagram PIN DESCRIPTION Table 1. Pin Description Pin 1 2 3 4 5 6 7 Symbol ΦV4 ΦV3 ΦV2 ΦV1 NC GND VOUT Description Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock No connection Ground Signal output Pin 8 9 10 11 12 13 14 Symbol VDD GND ΦSUB VL ΦRG ΦH1 ΦH2 Description Signal output GND Substrate clock Protection transistor bias Reset gate clock Horizontal register transfer clock Horizontal register transfer clock 2 KC74125B 1/4 INCH CCD IMAGE SENSOR FOR EIA CAMERA ABSOLUTE MAXIMUM RATINGS (NOTE) Table 2. Absolute Maximum Ratings Characteristics Substrate voltage SUB - GND VDD, VOUT - SUB Vertical clock input voltage ΦV1, ΦV3, - GND ΦV2, ΦV4 - GND ΦV1, ΦV3, - VL ΦV2, ΦV4 - VL ΦV1, ΦV2, ΦV3, ΦV4 - SUB Horizontal clock input voltage ΦH1, ΦH2 - VL ΦH1, ΦH2 - SUB Voltage difference between vertical and horizontal clock input pins ΦV1, ΦV2, ΦV3, ΦV4 ΦH1, ΦH2 ΦH1, ΦH2 - ΦV4 Output clock input voltage ΦRG - GND ΦRG - SUB Protection circuit bias voltage Operating temperature Storage temperature VL - SUB TOP TSTG -17 -0.3 -40 -40 -10 -30 Symbols Min. -0.3 -40 -0.3 -0.3 -0.3 -0.3 -40 -0.3 -30 Max. 40 10 30 17 30 17 10 7 7 15 16 16 16 16 10 60 80 Unit V V V V V V V V V V V V V V V °C °C NOTE: The device can be destroyed, if the applied voltage or temperature is higher than the absolute maximum rating voltage or temperature. 3 1/4 INCH CCD IMAGE SENSOR FOR EIA CAMERA KC74125B DC CHARACTERISTICS Table 3. DC Characteristics Item Output stage drain bias Protection circuit bias voltage Output stage drain current Symbol VDD VL IDD Min. 14.55 Typ. 15.0 Max. 15.45 Unit V The lowest vertical clock level 5 mA CLOCK VOLTAGE CONDITIONS Table 4. Clock Voltage Conditions Item Read-out clock voltage Vertical transfer clock voltage Symbol VVH1, VVH3 VVM1 ~ V VM4 VVL1 ~ V VL4 Horizontal transfer clock voltage VHH1, VHH2 VHL1, VHL2 Charge reset clock voltage VRGH VRGL Substrate clock voltage VΦSUB Min. 14.55 -0.2 -8.0 3.0 -0.05 4.75 -0.2 21.5 Typ. 15.0 0.0 -7.5 5.0 0.0 5.0 0.0 22.5 Max. 15.45 0.2 -7.0 5.25 0.05 5.25 0.2 23.5 Unit V V V V V V V V Remark High level Middle Low High Low High Low Shutter 4 KC74125B 1/4 INCH CCD IMAGE SENSOR FOR EIA CAMERA DRIVE CLOCK WAVEFORM CONDITIONS Read Out Clock Waveform 100% 90% VVH 1, VVH3 10% 0% tr twh tf 0V Vertical Transfer Clock Waveform ¥Õ V 1 VVH1 V VH VVHH VVHL ¥Õ V 3 VVHH V V HL V VH L VVHL V VH3 V VHH V VH H V VH V VL H V VL 1 V VL L V VL 3 V VL L V VL H V VL V VL ¥Õ V 2 V VH H V VHH V VH V VHL ¥Õ V 4 V VH V VH H V V HH V VH2 V VHL V VHL V VH 4 V VHL V VL 2 V VL H V VL H V VL L V VL V VH = ( V V H 1 + V V H 2)/ 2 V VL 4 V VL L V VL V VH H = V V H + 0. 3V V V L = (V V L 3 + V V L 4)/ 2 V ¥Õ V = V V H n - V V L n (n =1~4) V V H L = V V H - 0. 3 V V V L H = V V L + 0. 3V V VL L = V V L - 0. 3 V 5 1/4 INCH CCD IMAGE SENSOR FOR EIA CAMERA KC74125B Horizontal Transfer Clock Waveform Diagram tr twh tf 90% V¥ÕH 10% VH L twl Reset Gate Clock Waveform Diagram tr twh tf VR GH twl V¥ÕRG Point A RG waveform VRGLH VRGLL VRGL + 0.5V VRGL ¥ÕH1 waveform 10% VRGLH is the maximum value and VRGLL the minimum value of the coupling waveform in the period from Point A in the diagram about to RG rise VRGL = (VRGLH + VRGLL)/2, VFRG = VRGH - VRGL Substrate Clock Waveform 100% 90% V¥ÕSU B 10% VSU B 0% tr twh tf 6 KC74125B 1/4 INCH CCD IMAGE SENSOR FOR EIA CAMERA CLOCK EQUIVALENT CIRCUIT CONSTANT Table 5. Clock Equivalent Circuit Constant twh Item Read-out clock Vertical clock Symbol Min. ΦVH ΦV1, ΦV2 ΦV3, ΦV4 ΦH1 Horizontal clock Reset clock Substrate clock ΦH2 ΦRG ΦSUB 41 41 11 1.5 46 46 14 2.0 41 41 76 46 46 80 6.5 6.5 6.0 0.5 9.5 9.5 Typ. 2.5 Max. Min. Typ. Max. Min. Typ. 0.5 15 6.5 6.5 5.0 0.5 Max. Min. Typ. 0.5 250 9.5 9.5 Max. µs ns ns ns ns µs twl tr tf Unit 7 1/4 INCH CCD IMAGE SENSOR FOR EIA CAMERA KC74125B EQUIVALENT CIRCUIT PARAMETERS Table 6. Equivalent Circuit Parameters Item Capacitance between vertical transfer clock and GND Symbol C ΦV1, CΦV3 C ΦV2, CΦV4 Capacitance between vertical transfer clocks CΦV12, CΦV34 CΦV23, CΦV41 CΦV13 CΦV24 Capacitance between horizontal transfer clock and GND Capacitance between horizontal transfer clocks Capacitance between substrate clock and GND Vertical transfer clock serial resistor Vertical transfer clock ground resistor Horizontal transfer clock serial resistor Reset gate clock serial resistor CΦH1, CΦH2 CΦH12 CΦSUB RΦV1 ~ RΦV4 RΦVGND RΦH1, RΦH2 RΦRG Typ. 680 820 180 180 60 60 30 30 180 40 15 10 100 Unit pF pF pF pF pF pF pF pF pF Ω Ω Ω Ω Remark ¥ÕV1 R ¥ÕV1 C ¥ÕV1 ¥ÕV2 R ¥ÕV2 C ¥ÕV2 R ¥ÕH1 ¥ÕH1 C ¥ÕH12 R ¥ÕH2 ¥ÕH2 C ¥ÕH2 C ¥ÕV12 C ¥ÕV41 C ¥ÕV24 C ¥ÕV13 R ¥ÕVGND C ¥ÕV23 C ¥ÕH1 C ¥ÕV4 R ¥ÕV4 ¥ÕV4 C ¥ÕV34 C ¥ÕV3 R ¥ÕV3 ¥ÕV3 8 KC74125B 1/4 INCH CCD IMAGE SENSOR FOR EIA CAMERA OPERATING CHARACTERISTICS Device Temperature = 25 °C Table 7. Operating Characteristics Item Sensitivity Saturation signal Smear Blooming margin Uniformity Dark signal (NOTE) Dark shading (NOTE) Image lag Flicker Y NOTE: Test Temperature = 60 °C Symbol S YSAT SM BM U D ∆D YLAG FY Min. 85 800 Typ. 95 Max. Unit mV/lux mV Remark 1 2 3 4 5 6 7 8 9 0.007 1,000 0.01 % times 20 2 2 0.5 2 % mV mV % % TEST CONDITION 1. Use a light source with color temperature of 3,200K hallogen lamp and CM-500S for IR cut filter. The light source is adjusted in accordance with the average value of Y signals indicated in each item. 9 1/4 INCH CCD IMAGE SENSOR FOR EIA CAMERA KC74125B TEST METHODS 1. Measure the light intensities (L) when the averaged illuminance output value (Y) is the standard illuminance output value, 150mV (YA) and when half of 150mV (1/2 YA). 1 Y A – --- Y A 2 S = ------------------------------L YA – L 1 --- Y 2A 2. Adjust the light intensity to 15 times of the value with which Y is YA, then measure the averaged illuminance output value (Y = YSAT). 3. Adjust the light intensity to 500 times of the value with which Y is YA, then remove the read-out clock and drain the signal in photosensors by the electronic shutter operation in all the respective horizontal blanking times with the other clocks unchanged. Measure the maximum illuminance output value (YSM). Y SM 1- 1 SM = ----------- × ---------- × ------- × 100 ( % ) YA 500 10 4. Adjust the light intensity to 1,000 times of the value with which Y is YA, then inspect whether there is blooming phenomenon or not. 5. Measure the maximum and minimum illuminance output value (YMAX, YMIN) when the light intensity is adjusted to make Y to be YA. Y MAX – Y MIN U = ------------------------------------- × 100 ( % ) YA 6. Measure YD with the horizontal idling time transfer level as reference, when the device ambient temperature is 60 °C and all of the light sources are shielded. 7. Follow test method 6, measure the maximum (DMAX) and minimum illuminance output (DMIN). ∆ D = D MAX – D MIN 10 KC74125B 1/4 INCH CCD IMAGE SENSOR FOR EIA CAMERA 8. Adjust the light intensity of Y signal output value by strobe light to 150mV (YA), calculate by below formula with measuring the image lag signal which is qenerated by below timing diagram. Y LAG = ( Y lag ⁄ 150 ) × 100 ( % ) FLD SG1 Light Strobe Timing Y Signal Output 150mV YLag Output 9. Adjust the light intensity of Y signal average value to 150mV (YA), calculate by below formula with measuring the signal differences (∆Yf [mV]) between fields. F Y = ( ∆ Y f ⁄ YA ) × 100 ( % ) 11 1/4 INCH CCD IMAGE SENSOR FOR EIA CAMERA KC74125B SPECTRAL RESPONSE CHARACTERISTICS Excluding Light Source Characteristics 1 0.9 0.8 Spectral Response 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 400 425 450 475 500 525 550 575 600 625 650 675 700 Wave Length (nm) Figure 2. Spectral Response Characteristics 12 KC74125B 1/4 INCH CCD IMAGE SENSOR FOR EIA CAMERA APPLICATION CIRCUITS -7.5V CCD Out 1M 10µ /16V +- 100 3.9K 152 2SK1070 104 MA110 10µ/16V 7 VOUT 100K 1µ/35V VDD 8 GND 9 +- -+ 6 5 4 3 2 1 GND 103 KC74125B NC ΦV1 ΦV2 ΦV3 ΦV4 ΦSUB 10 VL 11 ΦRG 12 ΦH1 13 ΦH2 14 10 20 19 18 17 16 15 14 13 12 11 KS7221D 1 2 3 4 5 6 9 7 8 10 10µ /16V +- XSUB XV2 XV1 XSG1 XV3 XSG2 XV4 ΦH2 ΦH1 RG 15V Figure 3. Application Circuits 13 1/4 INCH CCD IMAGE SENSOR FOR EIA CAMERA KC74125B READ-OUT CLOCK TIMING CHART Unit: [µs] HD V1 Odd Field V2 2.5 V3 V4 38.1 1.2 1.5 2.5 2.0 0.3 V1 V2 Even Field V3 V4 Figure 4. Read-out Clock Timing Chart 14 KC74125B 1/4 INCH CCD IMAGE SENSOR FOR EIA CAMERA CLOCK TIMING CHART (VERTICAL SYNC.) FLD VD BLK HD 520 525 1 2 3 4 5 10 15 20 260 265 270 275 280 2468 1357 SG1 SG2 V1 V2 V3 V4 CCD OUT CLP1 492 491 246 135 246 135 492 491 246 135 Figure 5. Clock Timing Chart (Vertical Sync.) 15 1/4 INCH CCD IMAGE SENSOR FOR EIA CAMERA KC74125B CLOCK TIMING CHART (HORIZONTAL SYNC.) 10 5 3 2 1 2 1 16 15 10 5 3 2 1 25 20 15 10 5 3 2 1 510 505 500 XSHD XSHP CL P1 Figure 6. Clock Timing Chart (Horizontal Sync.) 16 SUB BL K HD RS H1 H2 V1 V2 V3 V4 KC74125B 1/4 INCH CCD IMAGE SENSOR FOR EIA CAMERA PACKAGE DIMENSIONS (Unit = mm) Glass 7583 Ceramicframe Al 2O 3 90%Min. (black) 0.38 Ceramic Base Al 2O 3 90%Min. (black) Lead Frame Alloy 42 ( Inner AI Outer Sn ) 4-R 0.50 (L/F CL) Y #14 #8 0.25 4-R 0.30 10.00¡¾0.12 5.40¡¾0.10 7.40¡¾0.10 X 2.50 X (L/F CL) 10.00¡¾0.12 R0.70 0.90¡¾0.08 1.00¡¾0.08 0.35¡¾0.08 4-R0.50 2.600 0.80¡¾0.15 9.46 ¡¾0.12 10.16¡¾0.30 #1 Y 6.00¡¾0.10 10.00¡¾0.12 #7 NOTES: 0.46¡¾0.10 Glass (7583) 1. Max. Leakage by Hellium Detector 2. Resistance Between Leads 3. Insulation Resistance :10-8atm. cc/sec at 10 -5 mmHg :Above 10 100HM at 25 ¡É, 60% R>H :Electrical leakage shall not exceed 5 nano AMP at 100V D.C 1.27¡¾0.25 4. Ceamic Material 5. Lead Frame - Coplanarity :Min. 90% al20 3 (black) :0.25 Max. (after L/F attach) :0.076/mm, -0.102/mm 4.13 - Planarity - Al clad 1.27 ¡¾0.05 0.30 ¡¾0.10 1.27 x 6 = 7.62¡¾0.10 9.60¡¾0.12 . Thickness . Thickness . Coverage - Sn thickness 6. Flatness - DIE attach pad - LID seal area 7. Other :5um to 10um (f or stamp) :2.5um to 12.7um (for etch) :Min. 0.762mm from lead tip :4um to 20um :Max. 0.051mm :Max. 0.051mm :In according to semi standards. Figure 7. Package Dimensions 17 1/4 INCH CCD IMAGE SENSOR FOR EIA CAMERA KC74125B HANDLING INSTRUCTIONS • Static Charge Prevention CCD image sensors can be easily damaged by static discharge. Before handling, be sure to take the following protective measures. — Use non chargeable gloves, clothes or material. Also use conductive shoes. — When handling directly, use an earth band. — Install a conductive mat on the floor or working table to prevent generation of static electricity. — Ionized air is recommended for discharging when handling CCD image sensor. — For the shipment of mounted substrates, use boxes treated for the prevention of static charges. • Soldering — Make sure the package temperature does not exceed 80 °C. — Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a grounded 30W soldering iron and solder each pin in less than 2 seconds. For repairs and and remount, cool sufficiently. — To dismount an imaging device, do not use a solder suction equipment. When using an electronic disoldering tool, use a thermal controller of the zero cross on/off type and connect to ground. • Dust and Dirt Protection — Operate in the clean environments (around class 1000 will be appropriate). — Do not either touch glass plates by hand or have object come in contact with glass surface. Should dirt stick to a glass surface blow it off with an air blow(for dirt stuck through static electricity ionized air is recommended). — Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be caerful not to scratch the glass. — Keep in case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. — When a protective tape is applied before shipping, just before use remove the tape applied electrostatic protection. Do not reuse the tape. • Do not expose to strong light (sun rays) for long period, color filter are discolored. • Exposure to high temperature or humidity will affect the characteristics. accordingly avoid storage or usage in such conditions. • CCD image sensors are precise optical equipment that should not be subject to mechanical shocks. 18
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