KFG5616U1A-PIB6

OneNAND256(KFG5616x1A-xxB6) FLASH MEMORY OneNANDTM Specification Density Part No. KFG5616Q1A-DEB6 KFG5616Q1A-PEB6 KFG5616D1A-DEB6 KFG5616D1A-PEB6 KFG5616U1A-DIB6 KFG5616U1A-PIB6 VCC(core & IO) 1.8V(1.7V~1.95V) 1.8V(1.7V~1.95V) 2.65V(2.4V~2.9V) 2.65V(2.4V~2.9V) 3.3V(2.7V~3.6V) 3.3V(2.7V~3.6V) Temperature Extended Extended Extended Extended Industrial Industrial PKG 67FBGA(LF) 48TSOP1 67FBGA(LF) 48TSOP1 67FBGA(LF) 48TSOP1 256Mb Version: Ver. 1.1 Date: Aug 12, 2005 1 OneNAND256(KFG5616x1A-xxB6) FLASH MEMORY 1.0 INTRODUCTION This specification contains information about the Samsung Electronics Company OneNAND™‚ Flash memory product family. Section 1.0 includes a general overview, revision history, and product ordering information. Section 2.0 describes the OneNAND device. Section 3.0 provides information about device operation. Electrical specifications and timing waveforms are in Sections 4.0 though 6.0. Section 7.0 provides additional application and technical notes pertaining to use of the OneNAND. Package dimensions are found in Section 8.0 INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. OneNAND™‚ is a trademark of Samsung Electronics Company, Ltd. Other names and brands may be claimed as the property of their rightful owners. Copyright © 2005, Samsung Electronics Company, Ltd 2 OneNAND256(KFG5616x1A-xxB6) FLASH MEMORY 1.1 OneNAND Revision History Document Title Revision History Revision No. History 0.0 1.0 1. Initial Issue 1. Corrected the errata 2. Added Data Protection flow chart. 3. Removed Cache Read Operation. 4. Added additional information on command register. 5. Revised Interrupt status register information. 6. Added INT pin schematic. 7. Changed tPGM1 to 205 from 320us, tPGM2 to 220 from 350us. 8. Revised AC/DC parameters 9. Revised ECC Bypass Description 10. Revised Reset Parameters and Timing Diagrams. Draft Date April 17, 2005 May 17, 2005 Remark Preliminary Final 1.1 1. Corrected the errata 2. Revised Invalid Block Table Creation Flow Chart. 3. Revised Multi Block Erase Description. 4. Revised Reset Mode Operation. Aug 12, 2005 Final 3 OneNAND256(KFG5616x1A-xxB6) FLASH MEMORY 1.2 Flash Product Type Selector Samsung offers a variety of Flash solutions including NAND Flash, OneNAND™ and NOR Flash. Samsung offers Flash products both component and a variety of card formats including RS-MMC, MMC, CompactFlash, and SmartMedia. To determine which Samsung Flash product solution is best for your application, refer the product selector chart. Application Requires Fast Random Read Fast Sequential Read Fast Write/Program Multi Block Erase Erase Suspend/Resume Copyback Lock/Unlock/Lock-Tight ECC Scalability Samsung Flash Products NAND • • OneNAND™ • • • (Max 64 Blocks) • • (EDC) External (Hardware/Software) • • (ECC) • Internal • • X • • NOR • 1.3 Ordering Information K F G 56 1 6 X 1 A - X X B 6 Speed 5 : 54MHz 6 : 66MHz Product Line desinator B : Include Bad Block D : Daisy Sample Operating Temperature Range E = Extended Temp. (-30 °C to 85 °C) I = Industrial Temp. (-40 °C to 85 °C) Package D : FBGA(Lead Free) P : TSOP(Lead Free) Version A : 2nd Generation Page Architecture 1 : 1KB Page Samsung OneNAND Memory Device Type G : Single Chip Density 56 : 256Mb Organization x16 Organization Operating Voltage Range Q : 1.8V(1.7 V to 1.95V) D : 2.65V(2.4V to 2.9V) U : 3.3V(2.7 V to 3.6V) 4 OneNAND256(KFG5616x1A-xxB6) FLASH MEMORY 1.4 Architectural Benefits OneNAND is a highly integrated non-volatile memory solution based around a NAND Flash memory array. The chip integrates system features including: • A BootRAM and bootloader • Two independent bi-directional 1KB DataRAM buffers • A High-Speed x16 Host Interface • On-chip Error Correction • On-chip NOR interface controller This on-chip integration enables system designers to reduce external system logic and use high-density NAND Flash in applications that would otherwise have to use more NOR components. OneNAND takes advantage of the higher performance NAND program time, low power, and high density and combines it with the synchronous read performance of NOR. The NOR Flash host interface makes OneNAND an ideal solution for applications like G3 Smart Phones, Camera Phones, and mobile applications that have large, advanced multimedia applications and operating systems, but lack a NAND controller. When integrated into a Samsung Multi-Chip-Package with Samsung Mobile DDR SDRAM, designers can complete a high-performance, small footprint solution. The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near you. 5 OneNAND256(KFG5616x1A-xxB6) FLASH MEMORY 1.5 Product Features 90nm 1.8V (1.7V ~ 1.95V), 2.65V (2.4 ~ 2.9V), 3.3V (2.7 ~3.6V) 16 bit 1KB BootRAM, 2KB DataRAM (1K+32)B Page Size, (64K+2K)B Block Size Device Architecture • Design Technology: • Supply Voltage: • Host Interface: • 3KB Internal BufferRAM: • SLC NAND Array: Device Performance • Host Interface Type: • • • • • Programmable Burst Read Latency Multiple Sector Read: Multiple Reset Modes: Multi Block Erase Low Power Dissipation: Synchronous Burst Read - Up to 66MHz clock frequency - Linear Burst 4-, 8-, 16, 32-words with wrap around - Continuous 512 word Sequential Burst Asynchronous Random Read - 76ns access time Asynchronous Random Write Latency 3(up to 40MHz), 4, 5, 6, and 7 Up to 2 sectors using Sector Count Register Cold/Warm/Hot/NAND Flash Core Resets up to 64 Blocks Typical Power, - Standby current : 10µA @1.8V Device 25µA @2.65V/3.3V Device - Synchronous Burst Read current(66MHz) : 15mA@1.8V Device 20mA@2.65V/3.3v Device - Load current : 30mA@1.8v Device, 30mA@2.65V/3.3V Device - Program current : 25mA@1.8V Device, 28mA@2.65V/3.3V Device - Erase current : 20mA@1.8V Device, 23mA@2.65V/3.3V Device - Multi Block Erase current : 20mA@1.8V Device, 23mA@2.65V/3.3V Device System Hardware • Voltage detector generating internal reset signal from Vcc - Write Protection for BootRAM • Hardware reset input (RP) - Write Protection for NAND Flash Array • Data Protection Modes - Write Protection during power-up - Write Protection during power-down • User-controlled One Time Programmable(OTP) area • Internal 2bit EDC / 1bit ECC • Internal Bootloader supports Booting Solution in system • Handshaking Feature • Detailed chip information - INT pin indicates Ready / Busy - Polling the interrupt register status bit - by ID register Packaging • 256Mb products 67ball, 7mm x 9mm x max 1.0mmt , 0.8mm ball pitch FBGA 48 TSOP 1, 12mm x 20mm, 0.5mm pitch 6 OneNAND256(KFG5616x1A-xxB6) FLASH MEMORY 1.6 General Overview OneNAND™‚ is a monolithic integrated circuit with a NAND Flash array using a NOR Flash interface. This device includes control logic, a NAND Flash array, and 3KB of internal BufferRAM. The BufferRAM reserves 1KB for boot code buffering (BootRAM) and 2KB for data buffering (DataRAM), split between 2 independent buffers. It has a x16 Host Interface and a random access time speed of ~76ns. The device operates up to a maximum host-driven clock frequency of 66MHz for synchronous reads at Vcc(or Vccq. Refer to chapter 4.2) with minimum 4-clock latency. Below 40MHz it is accessible with minimum 3-clock latency. Appropriate wait cycles are determined by programmable read latency. OneNAND provides for multiple sector read operations by assigning the number of sectors to be read in the sector counter register. The device includes one block-sized OTP (One Time Programmable) area that can be used to increase system security or to provide identification capabilities. 7 OneNAND256(KFG5616x1A-xxB6) FLASH MEMORY 2.0 2.1 DEVICE DESCRIPTION Detailed Product Description The OneNAND is an advanced generation, high-performance NAND-based Flash memory. It integrates on-chip a single-level-cell (SLC) NAND Flash Array memory with two independent data buffers, boot RAM buffer, a page buffer for the Flash array, and a one-time-programmable block. The combination of these memory areas enable high-speed pipelining of reads from host, BufferRAM, Page Buffer, and NAND Flash Array memory. Clock speeds up to 66MHz with a x16 wide I/O yields a 54MByte/second bandwidth. The OneNAND also includes a Boot RAM and boot loader. This enables the device to efficiently load boot code at device startup from the NAND Array without the need for off-chip boot device. One block of the NAND Array is set aside as an OTP memory area. This area, available to the user, can be configured and locked with secured user information. On-chip controller interfaces enable the device to operate in systems without NAND Host controllers. 8 OneNAND256(KFG5616x1A-xxB6) FLASH MEMORY 2.2 Definitions B (capital letter) W (capital letter) b (lower-case letter) ECC Calculated ECC Written ECC BufferRAM BootRAM DataRAM Sector Byte, 8bits Word, 16bits Bit Error Correction Code ECC that has been calculated during a load or program access ECC that has been stored as data in the NAND Flash array or in the BufferRAM On-chip internal buffer consisting of BootRAM and DataRAM A 1KB portion of the BufferRAM reserved for Boot Code buffering A 2KB portion of the BufferRAM reserved for Data buffering Part of a Page of which 512B is the main data area and 16B is the spare data area. It is also the minimum Load/Program/Copy-Back Program unit during a 1~2 sector operation is available. Possible data unit to be read from memory to BufferRAM or to be programmed to memory. - 528B of which 512B is in main area and 16B in spare area - 1056B of which 1024B is in main area and 32B in spare area Data unit 9 OneNAND256(KFG5616x1A-xxB6) FLASH MEMORY 2.3 2.3.1 Pin Configuration 48TSOP1 N.C A15 A14 A13 A12 A11 A10 A9 A8 WE VSS VCC INT AVD RP A7 A6 A5 A4 A3 A2 A1 A0 N.C VSS OE DQ15 DQ7 DQ14 DQ6 VCCQ DQ13 DQ5 DQ12 DQ4 DQ11 DQ3 DQ10 DQ2 VSS DQ9 DQ1 DQ8 DQ0 RDY CLK CE VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48-pin TSOP1 Standard Type 12mm x 20mm 0.5mm pitch 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 (TOP VIEW, Facing Down) TSOP1 OneNAND Chip 48pin, 12mm x 20mm, 0.5mm pitch TSOP1 10 OneNAND256(KFG5616x1A-xxB6) 2.3.2 67ball FBGA FLASH MEMORY NC NC NC NC NC NC WE RP DQ14 VSS VSS DQ13 NC NC DQ12 DQ8 DQ1 OE DQ9 VCC Core VCC IO NC DQ7 DQ4 DQ11 DQ10 DQ3 DQ15 A12 DQ0 A15 DQ5 DQ6 CLK CE DQ2 NC NC A9 A14 A13 AVD A7 A11 A8 NC INT A0 A1 NC A10 A6 NC NC RDY A4 A5 A2 A3 NC NC NC NC NC NC NC NC (TOP VIEW, Balls Facing Down) 67ball FBGA OneNAND Chip 67ball, 7mm x 9mm x max 1.0mmt , 0.8mm ball pitch FBGA 11 OneNAND256(KFG5616x1A-xxB6) FLASH MEMORY 2.4 Pin Name Host Interface A15~A0 Pin Description Type Nameand Description Address Inputs - Inputs for addresses during read and write operation, which are for addressing BufferRAM & Register. Data Inputs/Outputs - Inputs data during program and commands for all operations, outputs data during memory array/ register read cycles. Data pins float to high-impedance when the chip is deselected or outputs are disabled. Interrupt Notifying Host when a command has completed. It is open drain output with internal resister (~50k Ohm). After power up, it is at Hi-z state. And after IOBE is set to 1, it does not turn to hi-z condition when the chip is deselected or when outputs are disabled. Ready Indicates data valid in synchronous read modes and is activated while CE is low Clock CLK synchronizes the device to the system bus frequency in synchronous read mode. The first rising edge of CLK in conjunction with AVD low latches address input. Write Enable WE controls writes to the bufferRAM and registers. Datas are latched on the WE pulse’s rising edge Address Valid Detect Indicates valid address presence on address inputs. During asynchronous read operation, all addresses are latched on AVD’s rising edge, and during synchronous read operation, all addresses are latched on CLK’s rising edge while AVD is held low for one clock cycle. > Low : for asynchronous mode, indicates valid address ;for burst mode, causes starting address to be latched on rising edge on CLK > High : device ignores address inputs Reset Pin When low, RP resets internal operation of OneNAND. RP status is don’t care during power-up and bootloading. Chip Enable CE-low activates internal control logic, and CE-high deselects the device, places it in standby state, and places DQ in Hi-Z Output Enable OE-low enables the device’s output data buffers during a read cycle. Power for OneNAND Core This is the power supply for OneNAND Core. Power for OneNAND I/O This is the power supply for OneNAND I/O Vcc-IO / Vccq is internally separated from Vcc-Core / Vcc. Ground for OneNAND Do Not Use Leave it disconnected. These pins are used for testing. No Connection Lead is not internally connected. I DQ15~DQ0 I/O INT O RDY O CLK I WE I AVD I RP I CE I OE Power Supply VCC-Core / Vcc VCC-IO / Vccq VSS etc. DNU NC I NOTE: Do not leave power supply(Vcc-Core/Vcc-IO, VSS) disconnected. 12 OneNAND256(KFG5616x1A-xxB6) FLASH MEMORY 2.5 Block Diagram DQ15~DQ0 A15~A0 CLK CE Host Interface OE WE RP AVD Internal Registers INT RDY (Address/Command/Configuration /Status Registers) OTP (One Block) DataRAM0 DataRAM1 NAND Flash Array BufferRAM BootRAM StateMachine Bootloader Error Correction Logic 2.6 Memory Array Organization The OneNAND architecture integrates several memory areas on a single chip. 2.6.1 Internal (NAND Array) Memory Organization The on-chip internal memory is a single-level-cell (SLC) NAND array used for data storage and code. The internal memory is divided into a main area and a spare area. Main Area The main area is the primary memory array. This main area is divided into Blocks of 64 Pages. Within a Block, each Page is 1KB and is comprised of 2 Sectors. Within a Page, each Sector is 512B and is comprised of 256 Words. Spare Area The spare area is used for invalid block information and ECC storage. Spare area internal memory is associated with corresponding main area memory. Within a Block, each Page has two 16B Sectors of spare area. Each spare area Sector is 8 words. 13 OneNAND256(KFG5616x1A-xxB6) Internal Memory Array Information Area Main Spare Block 64KB 2KB Page 1KB 32B FLASH MEMORY Sector 512B 16B Internal Memory Array Organization Sector Main Area Spare Area 512B 16B Page Main Area Spare Area 512B Sector0 1KB 512B Sector1 16B Sector0 32B 16B Sector1 Block Main Area Spare Area 1KB Page0 32B Page0 Page 0 1KB Page63 64KB 32B Page63 2KB Page 63 14 OneNAND256(KFG5616x1A-xxB6) 2.6.2 External (BufferRAM) Memory Organization FLASH MEMORY The on-chip external memory is comprised of 3 buffers used for Boot Code storage and data buffering. The BootRAM is a 1KB buffer that receives Boot Code from the internal memory and makes it available to the host at start up. There are two independent 1KB bi-directional data buffers, DataRAM0 and DataRAM1. These dual buffers enable the host to execute simultaneous Read-While load, and Write-While-program operations after Boot Up. During Boot Up, the BootRam is used by the host to initialize the main memory, and deliver boot code from NAND Flash core to host. External (BufferRAM) Memory BootRAM (1KB) Internal (Nand Array) Memory Boot code (1KB) Host Nand Array DataRAM0 (1KB) DataRAM1 (1KB) OTP Block The external memory is divided into a main area and a spare area. Each buffer is the equivalent size of a Sector. The main area data is 512B. The spare area data is 16B. External Memory Array Information Area Total Size Number of Sectors Sector Main Spare BootRAM 1KB+32B 2 512B 16B DataRAM0 1KB+32B 2 512B 16B DataRAM1 1KB+32B 2 512B 16B 15 OneNAND256(KFG5616x1A-xxB6) External Memory Array Organization FLASH MEMORY Main area data (512B) Spare area data (16B) { BootRAM BootRAM 0 BootRAM 1 DataRAM0 DataRAM 0_0 DataRAM 0_1 DataRAM1 DataRAM 1_0 DataRAM 1_1 { Sector: (512 + 16) Byte 16 OneNAND256(KFG5616x1A-xxB6) FLASH MEMORY 2.7 Memory Map The following tables are the memory maps for the OneNAND. 2.7.1 Internal (NAND Array) Memory Organization The following tables show the Internal Memory address map in word order. Block Block0 Block1 Block2 Block3 Block4 Block5 Block6 Block7 Block8 Block9 Block10 Block11 Block12 Block13 Block14 Block15 Block16 Block17 Block18 Block19 Block20 Block21 Block22 Block23 Block24 Block25 Block26 Block27 Block28 Block29 Block30 Block31 Block Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh Page and Sector Address(1) 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh Size 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB Block Block32 Block33 Block34 Block35 Block36 Block37 Block38 Block39 Block40 Block41 Block42 Block43 Block44 Block45 Block46 Block47 Block48 Block49 Block50 Block51 Block52 Block53 Block54 Block55 Block56 Block57 Block58 Block59 Block60 Block61 Block62 Block63 Block Address 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh Page and Sector Address(1) 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh Size 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB NOTE 1) The 2nd bit of Page and Sector address register is Don’t care. So the address range is bigger than the real range. Even though 2nd bit is set to "1", this bit is always considered "0". Please refer to Start Address 8 register. 17 OneNAND256(KFG5616x1A-xxB6) Block Block64 Block65 Block66 Block67 Block68 Block69 Block70 Block71 Block72 Block73 Block74 Block75 Block76 Block77 Block78 Block79 Block80 Block81 Block82 Block83 Block84 Block85 Block86 Block87 Block88 Block89 Block90 Block91 Block92 Block93 Block94 Block95 Block Address 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005Ah 005Bh 005Ch 005Dh 005Eh 005Fh Page and Sector Address(1) 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh Size 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB Block Block96 Block97 Block98 Block99 Block100 Block101 Block102 Block103 Block104 Block105 Block106 Block107 Block108 Block109 Block110 Block111 Block112 Block113 Block114 Block115 Block116 Block117 Block118 Block119 Block120 Block121 Block122 Block123 Block124 Block125 Block126 Block127 Block Address 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006Ah 006Bh 006Ch 006Dh 006Eh 006Fh 0070h 0071h 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch 007Dh 007Eh 007Fh FLASH MEMORY Page and Sector Address(1) 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh Size 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB NOTE 1) 2nd bit of Page and Sector address is Don’t care. So the address range is bigger than the real range. Even though 2nd bit is set to "1", this bit is always considered "0". Please refer to Start Address 8 register. 18 OneNAND256(KFG5616x1A-xxB6) Block Block128 Block129 Block130 Block131 Block132 Block133 Block134 Block135 Block136 Block137 Block138 Block139 Block140 Block141 Block142 Block143 Block144 Block145 Block146 Block147 Block148 Block149 Block150 Block151 Block152 Block153 Block154 Block155 Block156 Block157 Block158 Block159 Block Address 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch 008Dh 008Eh 008Fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009Ah 009Bh 009Ch 009Dh 009Eh 009Fh Page and Sector Address(1) 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh Size 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB Block Block160 Block161 Block162 Block163 Block164 Block165 Block166 Block167 Block168 Block169 Block170 Block171 Block172 Block173 Block174 Block175 Block176 Block177 Block178 Block179 Block180 Block181 Block182 Block183 Block184 Block185 Block186 Block187 Block188 Block189 Block190 Block191 Block Address 00A0h 00A1h 00A2h 00A3h 00A4h 00A5h 00A6h 00A7h 00A8h 00A9h 00AAh 00ABh 00ACh 00ADh 00AEh 00AFh 00B0h 00B1h 00B2h 00B3h 00B4h 00B5h 00B6h 00B7h 00B8h 00B9h 00BAh 00BBh 00BCh 00BDh 00BEh 00BFh FLASH MEMORY Page and Sector Address(1) 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh Size 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB NOTE 1) 2nd bit of Page and Sector address is Don’t care. So the address range is bigger than the real range. Even though 2nd bit is set to "1", this bit is always considered "0". Please refer to Start Address 8 register. 19 OneNAND256(KFG5616x1A-xxB6) Block Block192 Block193 Block194 Block195 Block196 Block197 Block198 Block199 Block200 Block201 Block202 Block203 Block204 Block205 Block206 Block207 Block208 Block209 Block210 Block211 Block212 Block213 Block214 Block215 Block216 Block217 Block218 Block219 Block220 Block221 Block222 Block223 Block Address 00C0h 00C1h 00C2h 00C3h 00C4h 00C5h 00C6h 00C7h 00C8h 00C9h 00CAh 00CBh 00CCh 00CDh 00CEh 00CFh 00D0h 00D1h 00D2h 00D3h 00D4h 00D5h 00D6h 00D7h 00D8h 00D9h 00DAh 00DBh 00DCh 00DDh 00DEh 00DFh Page and Sector Address(1) 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh Size 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB Block Block224 Block225 Block226 Block227 Block228 Block229 Block230 Block231 Block232 Block233 Block234 Block235 Block236 Block237 Block238 Block239 Block240 Block241 Block242 Block243 Block244 Block245 Block246 Block247 Block248 Block249 Block250 Block251 Block252 Block253 Block254 Block255 Block Address 00E0h 00E1h 00E2h 00E3h 00E4h 00E5h 00E6h 00E7h 00E8h 00E9h 00EAh 00EBh 00ECh 00EDh 00EEh 00EFh 00F0h 00F1h 00F2h 00F3h 00F4h 00F5h 00F6h 00F7h 00F8h 00F9h 00FAh 00FBh 00FCh 00FDh 00FEh 00FFh FLASH MEMORY Page and Sector Address(1) 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh Size 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB NOTE 1) 2nd bit of Page and Sector address is Don’t care. So the address range is bigger than the real range. Even though 2nd bit is set to "1", this bit is always considered "0". Please refer to Start Address 8 register. 20 OneNAND256(KFG5616x1A-xxB6) Block Block256 Block257 Block258 Block259 Block260 Block261 Block262 Block263 Block264 Block265 Block266 Block267 Block268 Block269 Block270 Block271 Block272 Block273 Block274 Block275 Block276 Block277 Block278 Block279 Block280 Block281 Block282 Block283 Block284 Block285 Block286 Block287 Block Address 0100h 0101h 0102h 0103h 0104h 0105h 0106h 0107h 0108h 0109h 010Ah 010Bh 010Ch 010Dh 010Eh 010Fh 0110h 0111h 0112h 0113h 0114h 0115h 0116h 0117h 0118h 0119h 011Ah 011Bh 011Ch 011Dh 011Eh 011Fh Page and Sector Address(1) 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh Size 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB Block Block288 Block289 Block290 Block291 Block292 Block293 Block294 Block295 Block296 Block297 Block298 Block299 Block300 Block301 Block302 Block303 Block304 Block305 Block306 Block307 Block308 Block309 Block310 Block311 Block312 Block313 Block314 Block315 Block316 Block317 Block318 Block319 Block Address 0120h 0121h 0122h 0123h 0124h 0125h 0126h 0127h 0128h 0129h 012Ah 012Bh 012Ch 012Dh 012Eh 012Fh 0130h 0131h 0132h 0133h 0134h 0135h 0136h 0137h 0138h 0139h 013Ah 013Bh 013Ch 013Dh 013Eh 013Fh FLASH MEMORY Page and Sector Address(1) 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh Size 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB NOTE 1) 2nd bit of Page and Sector address is Don’t care. So the address range is bigger than the real range. Even though 2nd bit is set to "1", this bit is always considered "0". Please refer to Start Address 8 register. 21 OneNAND256(KFG5616x1A-xxB6) Block Block320 Block321 Block322 Block323 Block324 Block325 Block326 Block327 Block328 Block329 Block330 Block331 Block332 Block333 Block334 Block335 Block336 Block337 Block338 Block339 Block340 Block341 Block342 Block343 Block344 Block345 Block346 Block347 Block348 Block349 Block350 Block351 Block Address 0140h 0141h 0142h 0143h 0144h 0145h 0146h 0147h 0148h 0149h 014Ah 014Bh 014Ch 014Dh 014Eh 014Fh 0150h 0151h 0152h 0153h 0154h 0155h 0156h 0157h 0158h 0159h 015Ah 015Bh 015Ch 015Dh 015Eh 015Fh Page and Sector Address(1) 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh Size 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB Block Block352 Block353 Block354 Block355 Block356 Block357 Block358 Block359 Block360 Block361 Block362 Block363 Block364 Block365 Block366 Block367 Block368 Block369 Block370 Block371 Block372 Block373 Block374 Block375 Block376 Block377 Block378 Block379 Block380 Block381 Block382 Block383 Block Address 0160h 0161h 0162h 0163h 0164h 0165h 0166h 0167h 0168h 0169h 016Ah 016Bh 016Ch 016Dh 016Eh 016Fh 0170h 0171h 0172h 0173h 0174h 0175h 0176h 0177h 0178h 0179h 017Ah 017Bh 017Ch 017Dh 017Eh 017Fh FLASH MEMORY Page and Sector Address(1) 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh Size 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB NOTE 1) 2nd bit of Page and Sector address is Don’t care. So the address range is bigger than the real range. Even though 2nd bit is set to "1", this bit is always considered "0". Please refer to Start Address 8 register. 22 OneNAND256(KFG5616x1A-xxB6) Block Block384 Block385 Block386 Block387 Block388 Block389 Block390 Block391 Block392 Block393 Block394 Block395 Block396 Block397 Block398 Block399 Block400 Block401 Block402 Block403 Block404 Block405 Block406 Block407 Block408 Block409 Block410 Block411 Block412 Block413 Block414 Block415 Block Address 0180h 0181h 0182h 0183h 0184h 0185h 0186h 0187h 0188h 0189h 018Ah 018Bh 018Ch 018Dh 018Eh 018Fh 0190h 0191h 0192h 0193h 0194h 0195h 0196h 0197h 0198h 0199h 019Ah 019Bh 019Ch 019Dh 019Eh 019Fh Page and Sector Address(1) 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh Size 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB Block Block416 Block417 Block418 Block419 Block420 Block421 Block422 Block423 Block424 Block425 Block426 Block427 Block428 Block429 Block430 Block431 Block432 Block433 Block434 Block435 Block436 Block437 Block438 Block439 Block440 Block441 Block442 Block443 Block444 Block445 Block446 Block447 Block Address 01A0h 01A1h 01A2h 01A3h 01A4h 01A5h 01A6h 01A7h 01A8h 01A9h 01AAh 01ABh 01ACh 01ADh 01AEh 01AFh 01B0h 01B1h 01B2h 01B3h 01B4h 01B5h 01B6h 01B7h 01B8h 01B9h 01BAh 01BBh 01BCh 01BDh 01BEh 01BFh FLASH MEMORY Page and Sector Address(1) 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh Size 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB NOTE 1) 2nd bit of Page and Sector address is Don’t care. So the address range is bigger than the real range. Even though 2nd bit is set to "1", this bit is always considered "0". Please refer to Start Address 8 register. 23 OneNAND256(KFG5616x1A-xxB6) Block Block448 Block449 Block450 Block451 Block452 Block453 Block454 Block455 Block456 Block457 Block458 Block459 Block460 Block461 Block462 Block463 Block464 Block465 Block466 Block467 Block468 Block469 Block470 Block471 Block472 Block473 Block474 Block475 Block476 Block477 Block478 Block479 Block Address 01C0h 01C1h 01C2h 01C3h 01C4h 01C5h 01C6h 01C7h 01C8h 01C9h 01CAh 01CBh 01CCh 01CDh 01CEh 01CFh 01D0h 01D1h 01D2h 01D3h 01D4h 01D5h 01D6h 01D7h 01D8h 01D9h 01DAh 01DBh 01DCh 01DDh 01DEh 01DFh Page and Sector Address(1) 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh Size 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB Block Block480 Block481 Block482 Block483 Block484 Block485 Block486 Block487 Block488 Block489 Block490 Block491 Block492 Block493 Block494 Block495 Block496 Block497 Block498 Block499 Block500 Block501 Block502 Block503 Block504 Block505 Block506 Block507 Block508 Block509 Block510 Block511 Block Address 01E0h 01E1h 01E2h 01E3h 01E4h 01E5h 01E6h 01E7h 01E8h 01E9h 01EAh 01EBh 01ECh 01EDh 01EEh 01EFh 01F0h 01F1h 01F2h 01F3h 01F4h 01F5h 01F6h 01F7h 01F8h 01F9h 01FAh 01FBh 01FCh 01FDh 01FEh 01FFh FLASH MEMORY Page and Sector Address(1) 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh 0000h~00FDh Size 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB NOTE 1) 2nd bit of Page and Sector address is Don’t care. So the address range is bigger than the real range. Even though 2nd bit is set to "1", this bit is always considered "0". Please refer to Start Address 8 register. 24 OneNAND256(KFG5616x1A-xxB6) 2.7.2 Internal Memory Spare Area Assignment FLASH MEMORY The figure below shows the assignment of the spare area in the Internal Memory NAND Array. Main area 256W Main area 256W Spare area 8W Spare area 8W Note1 Note1 Note2 Note2 Note2 Note3 Note3 Note3 ECCm ECCm ECCm 1st 2nd 3rd LSB LSB MSB MSB LSB ECCs 1st ECCs 2nd (Note3) Note4 Note4 Spare Area Assignment in the Internal Memory NAND Array Information Word 1 2 3 4 Byte LSB MSB LSB MSB LSB MSB LSB MSB LSB 5 MSB LSB 6 MSB LSB MSB 8 LSB MSB 3 4 Dedicated to internal ECC logic. Read Only. ECCm 1st for main area data Dedicated to internal ECC logic. Read Only. ECCm 2nd for main area data Dedicated to internal ECC logic. Read Only. ECCm 3rd for main area data Dedicated to internal ECC logic. Read Only. ECCs 1st for 2nd word of spare area data Dedicated to internal ECC logic. Read Only. ECCs 2nd for 3rd word of spare area data Reserved for future use Available to the user 3 Reserved for future use 2 Managed by internal ECC logic for Logical Sector Number data Note 1 Description Invalid Block information in 1st and 2nd page of an invalid block { { { { { { { { 1st W 2nd W 3rd W 4th W 5th W 6th W 7th W 8th W 7 MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB 25 OneNAND256(KFG5616x1A-xxB6) 2.7.3 External Memory (BufferRAM) Address Map FLASH MEMORY The following table shows the External Memory address map in Word and Byte Order. Note that the data output is unknown while host reads a register bit of reserved area. Division Main area (64KB) Address (word order) 0000h~00FFh 0100h~01FFh 0200h~02FFh 0300h~03FFh 0400h~04FFh 0500h~05FFh 0600h~7FFFh Address (byte order) 00000h~001FEh 00200h~003FEh 00400h~005FEh 00600h~007FEh 00800h~009FEh 00A00h~00BFEh 00C00h~0FFFEh 10000h~1000Eh 10010h~1001Eh 10020h~1002Eh 10030h~1003Eh 10040h~1004Eh 10050h~1005Eh 1006Eh~11FFEh 12000h~17FFEh 18000h~19FFEh 1A000h~1DFFEh 1E000h~1FFFEh Size (total 128KB) 512B 512B 512B 512B 512B 512B 61KB 16B 16B 16B 16B 16B 16B 8096B 24KB 8KB 16KB 8KB 8096B 24KB 8KB 16KB 8KB 64B 61KB 32B 2KB 1KB Usage BootM 0 BootM 1 DataM 0_0 DataM 0_1 DataM 1_0 DataM 1_1 Reserved BootS 0 BootS 1 DataS 0_0 DataS 0_1 DataS 1_0 DataS 1_1 Reserved Reserved Reserved Reserved Registers Description BootRAM Main sector0 BootRAM Main sector1 DataRAM Main page0/sector0 DataRAM Main page0/sector1 DataRAM Main page1/sector0 DataRAM Main page1/sector1 Reserved BootRAM Spare sector0 BootRAM Spare sector1 DataRAM Spare page0/sector0 DataRAM Spare page0/sector1 DataRAM Spare page1/sector0 DataRAM Spare page1/sector1 Reserved Reserved Reserved Reserved Registers Spare area (8KB) 8000h~8007h 8008h~800Fh 8010h~8017h 8018h~801Fh 8020h~8027h 8028h~802Fh 8030h~8FFFh Reserved (24KB) Reserved (8KB) Reserved (16KB) Registers (8KB) 9000h~BFFFh C000h~CFFFh D000h~EFFFh F000h~FFFFh 26 OneNAND256(KFG5616x1A-xxB6) 2.7.4 External Memory Map Detail Information FLASH MEMORY The tables below show Word Order Address Map information for the BootRAM and DataRAM main and spare areas. • BootRAM(Main area) -0000h~01FFh: 2(sector) x 512byte(NAND main area) = 1KB 0000h~00FFh(512B) BootM 0 (sector 0 of page 0) • DataRAM(Main area) -0200h~05FFh: 4(sector) x 512byte(NAND main area) = 2KB 0200h~02FFh(512B) DataM 0_0 (sector 0 of page 0) • BootRAM(Spare area) -8000h~800Fh: 2(sector) x 16byte(NAND spare area) = 32B 8000h~8007h(16B) BootS 0 (sector 0 of page 0) • DataRAM(Spare area) -8010h~802Fh: 4(sector) x 16byte(NAND spare area) = 64B 8010h~8017h(16B) DataS 0_0 (sector 0 of page 0) 8018h~801Fh(16B) DataS 0_1 (sector 1 of page 0) 8020h~8027h(16B) DataS 1_0 (sector 0 of page 1) 8028h~802Fh(16B) DataS 1_1 (sector 1 of page 1) 8008h~800Fh(16B) BootS 1 (sector 1 of page 0) 0300h~03FFh(512B) DataM 0_1 (sector 1 of page 0) 0400h~04FFh(512B) DataM 1_0 (sector 0 of page 1) 0500h~05FFh(512B) DataM 1_1 (sector 1 of page 1) 0100h~01FFh(512B) BootM 1 (sector 1 of page 0) *NAND Flash array consists of 1KB page size and 64KB block size. 27 OneNAND256(KFG5616x1A-xxB6) 2.7.5 External Memory Spare Area Assignment Equivalent to 1word of NAND Flash FLASH MEMORY Buf. BootS 0 Word Address 8000h 8001h 8002h 8003h 8004h 8005h 8006h 8007h Byte Address 10000h 10002h 10004h 10006h 10008h 1000Ah 1000Ch 1000Eh 10010h 10012h 10014h 10016h 10018h 1001Ah 1001Ch 1001Eh 10020h 10022h 10024h 10026h 10028h 1002Ah 1002Ch 1002Eh 10030h 10032h 10034h 10036h 10038h 1003Ah 1003Ch 1003Eh F E D C B A 9 8 BI 7 6 5 4 3 2 1 0 Managed by Internal ECC logic Reserved for the future use ECC Code for Main area data (2nd) ECC Code for Spare area data (1st) FFh(Reserved for the future use) Free Usage BI Managed by Internal ECC logic Reserved for the future use ECC Code for Main area data (2nd) ECC Code for Spare area data (1st) FFh(Reserved for the future use) Free Usage BI Managed by Internal ECC logic Reserved for the future use ECC Code for Main area data (2nd) ECC Code for Spare area data (1 ) st Managed by Internal ECC logic ECC Code for Main area data (1st) ECC Code for Main area data (3rd) ECC Code for Spare area data (2nd) Reserved for the current and future use BootS 1 8008h 8009h 800Ah 800Bh 800Ch 800Dh 800Eh 800Fh Managed by Internal ECC logic ECC Code for Main area data (1st) ECC Code for Main area data (3rd) ECC Code for Spare area data (2nd) Reserved for the current and future use DataS 0_0 8010h 8011h 8012h 8013h 8014h 8015h 8016h 8017h Managed by Internal ECC logic ECC Code for Main area data (1st) ECC Code for Main area data (3rd) ECC Code for Spare area data (2nd) Free Usage BI Reserved for the current and future use FFh(Reserved for the future use) DataS 0_1 8018h 8019h 801Ah 801Bh 801Ch 801Dh 801Eh 801Fh Managed by Internal ECC logic Reserved for the future use ECC Code for Main area data (2nd) ECC Code for Spare area data (1 ) st Managed by Internal ECC logic ECC Code for Main area data (1st) ECC Code for Main area data (3rd) ECC Code for Spare area data (2nd) Free Usage Reserved for the current and future use FFh(Reserved for the future use) 28 OneNAND256(KFG5616x1A-xxB6) Equivalent to 1word of NAND Flash FLASH MEMORY Buf. DataS 1_0 Word Byte Address Address 8020h 8021h 8022h 8023h 8024h 8025h 8026h 8027h 10040h 10042h 10044h 10046h 10048h 1004Ah 1004Ch 1004Eh 10050h 10052h 10054h 10056h 10058h 1005Ah 1005Ch 1005Eh F E D C B A 9 8 BI 7 6 5 4 3 2 1 0 Managed by Internal ECC logic Reserved for the future use ECC Code for Main area data (2nd) ECC Code for Spare area data (1st) FFh(Reserved for the future use) Free Usage BI Managed by Internal ECC logic Reserved for the future use ECC Code for Main area data (2nd) ECC Code for Spare area data (1st) FFh(Reserved for the future use) Free Usage Managed by Internal ECC logic ECC Code for Main area data (1st) ECC Code for Main area data (3rd) ECC Code for Spare area data (2nd) Reserved for the current and future use Managed by Internal ECC logic ECC Code for Main area data (1st) ECC Code for Main area data (3rd) ECC Code for Spare area data (2nd) Reserved for the current and future use DataS 1_1 8028h 8029h 802Ah 802Bh 802Ch 802Dh 802Eh 802Fh NOTE: - BI: Invalid block Information >Host can use complete spare area except BI and ECC code area. For example, Host can write data to Spare area buffer except for the area controlled by ECC logic at program operation. >In case of ’with ECC’ mode, OneNAND automatically generates ECC code for both main and spare data of memory during program operation, but does not update ECC code to spare bufferRAM during load operation. >When loading/programming spare area, spare area BufferRAM address(BSA) and BufferRAM sector count(BSC) is chosen via Start buffer register as it is. 29 OneNAND256(KFG5616x1A-xxB6) FLASH MEMORY 2.8 Registers Section 2.8 of this specification provides information about the OneNAND registers. 2.8.1 Register Address Map This map describes the register addresses, register name, register description, and host accessibility. Address (word order) F000h F001h F002h F003h F004h F005h F006h F007h~F0FFh F100h F101h F102h F103h F104h F105h F106h F107h F108h~F1FFh Address (byte order) 1E000h 1E002h 1E004h 1E006h 1E008h 1E00Ah 1E00Ch 1E00Eh~1E1FEh 1E200h 1E202h 1E204h 1E206h 1E208h 1E20Ah 1E20Ch 1E20Eh 1E210h~1E3FEh Host Access R R R R R R R R/W R/W R/W R/W R/W Device identification N/A Data buffer size Boot buffer size Amount of data/boot buffers Info about technology Reserved for user NAND Flash Block address N/A Destination Block address for Copy back program Destination Page & Sector address for Copy back program N/A N/A N/A NAND Flash Page & Sector address Reserved for user Buffer Number for the page data transfer to/from the memory and the start Buffer Address The meaning is with which buffer to start and how many buffers to use for the data transfer Reserved for user Reserved for vendor specific purposes Host control and memory operation commands Memory and Host Interface Configuration N/A Reserved for user Reserved for vendor specific purposes Controller Status and result of memory operation Memory Command Completion Interrupt Status Reserved for user Start memory block address in Write Protection mode Name Manufacturer ID Device ID Version ID Data Buffer size Boot Buffer size Amount of buffers Technology Reserved Start address 1 Start address 2 Start address 3 Start address 4 Start address 5 Start address 6 Start address 7 Start address 8 Reserved Description Manufacturer identification F200h 1E400h Start Buffer R/W F201h~F207h F208h~F21Fh F220h F221h F222h F223h~F22Fh F230h~F23Fh F240h F241h F242h~F24Bh F24Ch 1E402h~1E40Eh 1E410h~1E43Eh 1E440h 1E442h 1E444h 1E446h~1E45Eh 1E460h~1E47Eh 1E480h 1E482h 1E484h~1E496h 1E498h Reserved Reserved Command System Configuration 1 System Configuration 2 Reserved Reserved Controller Status Interrupt Reserved Start Block Address R/W R, R/W R R/W R/W 30 OneNAND256(KFG5616x1A-xxB6) Address (word order) F24Dh F24Eh F24Fh~FEFFh FF00h FF01h FF02h FF03h FF04h FF05h~FFFFh Address (byte order) 1E49Ah 1E49Ch 1E49Eh~1FDFEh 1FE00h 1FE02h 1FE04h 1FE06h 1FE08h 1FE0Ah~1FFFEh Host Access R/W R R R R R R Reserved for user FLASH MEMORY Name Reserved Write Protection Status Reserved ECC Status Register ECC Result of main area data ECC Result of spare area data ECC Result of main area data ECC Result of spare area data Reserved Description Current memory Write Protection status (unlocked/locked/tight-locked) Reserved for user ECC status of sector ECC error position of Main area data error for first selected Sector ECC error position of Spare area data error for first selected Sector ECC error position of Main area data error for second selected Sector ECC error position of Spare area data error for second selected Sector Reserved for vendor specific purposes 2.8.2 Manufacturer ID Register F000h (R) This Read register describes the manufacturer's identification. Samsung Electronics Company manufacturer's ID is 00ECh. F000h, default = 00ECh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ManufID 31 OneNAND256(KFG5616x1A-xxB6) 2.8.3 Device ID Register F001h (R) FLASH MEMORY This Read register describes the device. F001h, see table for default. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DeviceID Device Identification Device Identification DeviceID [1:0] Vcc DeviceID [2] Muxed/Demuxed DeviceID [3] Single/DPP DeviceID [7:4] Density DeviceID [8] Top/Bottom Boot Device ID Default Description 00 = 1.8V, 01 = 2.65V/3.3V, 10/11 = reserved 0 = Muxed, 1 = Demuxed 0 = Single, 1 = DDP 0000 = 128Mb, 0001 = 256Mb, 0010 = 512Mb, 0011 = 1Gb, 0100 = 2Gb, 0101=4Gb 0 = Bottom Boot, 1 = Top Boot Device KFG5616Q1A KFG5616D1A KFG5616U1A DeviceID[15:0] 0014h 0015h 0015h 32 OneNAND256(KFG5616x1A-xxB6) 2.8.4 Version ID Register F002h FLASH MEMORY This register is reserved for manufacturer 2.8.5 Data Buffer Size Register F003h (R) This Read register describes the size of the Data Buffer. F003h, default = 0400h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DataBufSize Data Buffer Size Information Version Identification DataBufSize Description Total data buffer size in Words equal to 2 buffers of 512 Words each (2 x 512 = 210) in the memory interface 2.8.6 Boot Buffer Size Register F004h (R) This Read register describes the size of the Boot Buffer. F004h, default = 0200h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BootBufSize Register Information BootBufSize Description Total boot buffer size in Words equal to 1 buffer of 512 Words (1 x 512 = 29) in the memory interface 33 OneNAND256(KFG5616x1A-xxB6) 2.8.7 Number of Buffers Register F005h (R) FLASH MEMORY This Read register describes the number of each Buffer. F005h, default = 0201h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DataBufAmount BootBufAmount Number of Buffers Information Register Information DataBufAmount BootBufAmount Description The number of data buffers = 2 (2N, N=1) The number of boot buffers = 1 (2N, N=0) 2.8.8 Technology Register F006h (R) This Read register describes the internal NAND array technology. F006h, default = 0000h 15 14 13 12 11 10 9 8 Tech 7 6 5 4 3 2 1 0 Technology Information Technology NAND SLC NAND MLC Reserved Register Setting 0000h 0001h 0002h ~ FFFFh 34 OneNAND256(KFG5616x1A-xxB6) 2.8.9 Start Address1 Register F100h (R/W) FLASH MEMORY This Read/Write register describes the NAND Flash block address which will be loaded, programmed, or erased. F100h, default = 0000h 15 14 13 12 11 10 9 8 7 6 5 4 FBA 3 2 1 0 Reserved(0000000) Device 256Mb Number of Block 512 FBA FBA[8:0] Start Address1 Information Register Information FBA Description NAND Flash Block Address 2.8.10 Start Address2 Register F101h (R/W) This register is reserved for future use. 35 OneNAND256(KFG5616x1A-xxB6) 2.8.11 Start Address3 Register F102h (R/W) FLASH MEMORY This Read/Write register describes the NAND Flash destination block address which will be copy back programmed. F102h, default = 0000h 15 14 13 12 11 10 9 8 7 6 5 4 FCBA 3 2 1 0 Reserved(0000000) Device 256Mb Start Address3 Information Register Information FCBA Number of Block 512 FBA FCBA[8:0] Description NAND Flash Copy Back Block Address 2.8.12 Start Address4 Register F103h (R/W) This Read/Write register describes the NAND Flash destination page address in a block and the NAND Flash destination sector address in a page for copy back programming. F103h, default = 0000h 15 14 13 12 11 10 9 8 7 6 5 FCPA 4 3 2 1 0 Reserved(00000000) Reserved FCSA Start Address4 Information Item FCPA FCSA Description NAND Flash Copy Back Page Address NAND Flash Copy Back Sector Address Default Value 000000 0 Range 000000 ~ 111111, 6 bits for 64 pages 0 ~ 1, 1 bit for 2 sectors 36 OneNAND256(KFG5616x1A-xxB6) 2.8.13 Start Address5 Register F104h This register is reserved for future use. FLASH MEMORY 2.8.14 Start Address6 Register F105h This register is reserved for future use. 2.8.15 Start Address7 Register F106h This register is reserved for future use. 2.8.16 Start Address8 Register F107h (R/W) This Read/Write register describes the NAND Flash start page address in a block for a page load, copy back program, or program operation and the NAND Flash start sector address in a page for a load, copy back program, or program operation. F107h, default = 0000h 15 14 13 12 11 10 9 8 7 6 5 FPA 4 3 2 1 Reserved 0 FSA Reserved (00000000) Start Address8 Information Item FPA FSA Description NAND Flash Page Address NAND Flash Sector Address Default Value 000000 0 Range 000000 ~ 111111, 6 bits for 64 pages 0 ~ 1, 1 bit for 2 sectors 37 OneNAND256(KFG5616x1A-xxB6) 2.8.17 Start Buffer Register F200h (R/W) FLASH MEMORY This Read/Write register describes the BufferRAM Sector Count (BSC) and BufferRAM Sector Address (BSA). The BufferRAM Sector Count (BSC) field specifies the number of sectors to be loaded, programmed, or copy back programmed. At 0 value (the default value), the number of sector is "2". For example, if BSA = 1000, BSC = 0, then the selected BufferRAM will count up from '1000 → 1001'. The BufferRAM Sector Address (BSA) is the sector 0~1 address in the internal BootRAM and DataRAM where data is placed. F200h, default = 0000h 15 14 13 12 11 10 BSA 9 8 7 6 5 4 3 2 1 0 BSC Reserved(0000) Reserved(0000000) Start Buffer Register Information Item BSA[3] BSA[2] BSA[0] Description Selection bit between BootRAM and DataRAM Selection bit between DataRAM0 and DataRAM1 Selection bit between Sector0 and Sector1 in the internal BootRAM Selection bit between Sector0 and Sector1 in the internal DataRAM Main area data (512B) Spare area data (16B) BSA Sector: (512 + 16) Byte { BootRAM BootRAM 0 BootRAM 1 DataRAM0 DataRAM 0_0 DataRAM 0_1 DataRAM1 DataRAM 1_0 DataRAM 1_1 { 38 0000 0001 1000 1001 BSC 1 0 1100 1101 Number of Sectors 1 sector 2 sectors OneNAND256(KFG5616x1A-xxB6) 2.8.18 Command Register F220h (R/W) FLASH MEMORY This Read/Write register describes the operation of the OneNAND interface. Note that all command should be issued when INT is turned to busy from ready state, by writing 0 to INT register. After any command is issued, INT goes back to ready state as the corresponding operation is completed. (00F0h and 00F3h may be issued during busy at certain cases. Refer to command register table below) F220h, default = 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Command CMD 0000h 0013h 0080h 001Ah 001Bh 0023h 002Ah 002Ch 0071h 0094h 0095h 00B0h 0030h 00F0h 00F3h 0065h Operation Load single/multiple sector data unit into buffer Load single/multiple spare sector into buffer Program single/multiple sector data unit from buffer1) Program single/multiple spare data unit from buffer Copy back Program operation Unlock NAND array a block Lock NAND array a block Lock-tight NAND array a block Erase Verify Read Block Erase Multi-Block Erase Erase Suspend Erase Resume Reset NAND Flash Core Reset OneNAND OTP Access 2) Acceptable command during busy 00F0h, 00F3h 00F0h, 00F3h 00F0h, 00F3h 00F0h, 00F3h 00F0h, 00F3h 00F0h, 00F3h 00F0h, 00F3h 00F0h, 00F3h 00F0h, 00F3h 00F0h, 00F3h NOTE: 1) 0080h programs both main and spare area, while 001Ah programs only spare area. Refer to chapter 5.8 for NOP limits in issuing these commands. When using 0080h and 001Ah command, Read-only part in spare area must be masked by FF. (Refer to chapter 2.7.2) 2)’Reset OneNAND’(=Hot reset) command makes the registers and NAND Flash core into default state as the warm reset(=reset by RP pin). 39 OneNAND256(KFG5616x1A-xxB6) FLASH MEMORY 2.8.19 System Configuration 1 Register F221h (R, R/W) This Read/Write register describes the system configuration. F221h, default = 40C0h 15 R/W RM 14 13 R/W BRL 12 11 10 R/W BL 9 8 R/W ECC 7 R/W RDY pol 6 R/W INT pol 5 R/W IOBE 4 R/W RDY Conf 3 2 R Reserved(000) 1 0 R BWPS Read Mode (RM) RM 0 1 Read Mode Information[15] Item RM Burst Read Latency (BRL) BRL 000 001 010 011 100 101 110 111 Latency Cycles 8(N/A) 9(N/A) 10(N/A) 3(up to 40MHz) 4(default, min.) 5 6 7 Definition Read Mode Description Selects between asynchronous read mode and synchronous read mode Read Mode Asynchronous read(default) Synchronous read Burst Read Latency (BRL) Information[14:12] Item BRL Definition Burst Read Latency Description Specifies the access latency in the burst read transfer for the initial access 40 OneNAND256(KFG5616x1A-xxB6) Burst Length (BL) BL 000 001 010 011 100 101~111 Burst Length (BL) Information[11:9] Item BL Definition Burst Length 32 words Reserved Burst Length(Main) FLASH MEMORY Burst Length(Spare) Continuous(default) 4 words 8 words 16 words N/A Description Specifies the size of the burst length during a synchronous read, wrap around and linear burst read Error Correction Code (ECC) Information[8] Item ECC Definition Error Correction Code Operation Description 0 = with correction (default) 1 = without correction (bypassed) RDY Polarity (RDYpol) Information[7] Item RDYpol Definition RDY signal polarity Description 1 = high for ready (default) 0 = low for ready INT Polarity (INTpol) Information[6] INTpol 0 1 (default) INT bit of Interrupt Status Register 0 (busy) 1 (ready) 0 (busy) 1 (ready) INT Pin output High Low Low High 41 OneNAND256(KFG5616x1A-xxB6) I/O Buffer Enable (IOBE) FLASH MEMORY IOBE is the I/O Buffer Enable for the INT and RDY signals. At startup, INT and RDY outputs are High-Z. Bits 6 and 7 become valid after IOBE is set to "1". IOBE can be reset by a Cold Reset or by writing "0" to bit 5 of System Configuration1 Register. I/O Buffer Enable Information[5] Item IOBE Definition I/O Buffer Enable for INT and RDY signals Description 0 = disable (default) 1 = enable RDY Configuration (RDY conf) RDY Configuration Information[4] Item RDY conf Definition RDY configuration Description 0=active one clock before valid data(default) 1=active with valid data active Boot Buffer Write Protect Status (BWPS) Boot Buffer Write Protect Status Information[0] Item BWPS Definition Boot Buffer Write Protect Status Description 0 = locked (fixed) 42 OneNAND256(KFG5616x1A-xxB6) 2.8.20 System Configuration 2 Register F222h This register is reserved for future use. FLASH MEMORY 2.8.21 Controller Status Register F240h (R) This Read register shows the overall internal status of the OneNAND and the controller. F240h, default = 0000h 15 OnGo 14 Lock 13 Load 12 Prog 11 Erase 10 Error 9 Sus 8 7 6 OTPL 5 4 3 2 1 0 TO (0) Reserv RSTB ed(0) Reserved(000000) OnGo This bit shows the overall internal status of the OneNAND device. OnGo Information[15] Item OnGo Definition Internal Device Status Description 0 = ready 1 = busy Lock This bit shows whether the host is loading data from the NAND Flash array into the locked BootRAM or whether the host is performing a program/erase of a locked block of the NAND Flash array. Lock Information[14] Lock 0 1 Locked/Unlocked Check Result Unlocked Locked Load This bit shows the Load Operation status. Load Information[13] Item Load Definition Load Operation status Description 0 = ready (default) 1 = busy or error (see controller status output modes) 43 OneNAND256(KFG5616x1A-xxB6) Program This bit shows the Program Operation status. Program Information[12] Item Prog Definition Program Operation status FLASH MEMORY Description 0 = ready (default) 1 = busy or error (see controller status output modes) Erase This bit shows the Erase Operation status. Erase Information[11] Item Erase Definition Erase Operation status Description 0 = ready (default) 1 = busy or error (see controller status output modes) Error This bit shows the overall Error status, including Load Reset, Program Reset, and Erase Reset status. Error Information[10] Current Sector/Page Load/Program/CopyBack. Program/ Erase Result and Invalid Command Input Pass Fail Error 0 1 Erase Suspend (Sus) This bit shows the Erase Suspend status. Sus Information[9] Sus 0 1 Erase Suspend Status Erase Resume(Default) Erase Suspend, Program Ongoing(Susp.), Load Ongoing(Susp.), Program Fail(Susp.), Load Fail(Susp.), Invalid Command(Susp.) 44 OneNAND256(KFG5616x1A-xxB6) Reset / Busy (RSTB) This bit shows the Reset Operation status. RSTB Information[7] Item RSTB Definition Reset Operation Status FLASH MEMORY Description 0 = ready (default) 1 = busy (see controller status output modes) OTP Lock Status (OTPL) This bit shows whether the OTP block is locked or unlocked. Locking the OTP has the effect of a 'write-protect' to guard against accidental re-programming of data stored in the OTP block. The OTPL status bit is automatically updated at power-on. OTP Lock Information[6] OTPL 0 1 OTP Locked/Unlocked Status OTP Block Unlock Status(Default) OTP Block Lock Status(Disable OTP Program/Erase) Time Out (TO) This bit determines if there is a time out for load, program, copy back program, and erase operations. It is fixed at 'no time out'. TO Information[0] Item TO Definition Time Out Description 0 = no time out 45 OneNAND256(KFG5616x1A-xxB6) Controller Status Register Output Modes FLASH MEMORY Controller Status Register [15:0] Mode Load Ongoing Program Ongoing Erase Ongoing Reset Ongoing Multi-Block Erase Ongoing Erase Verify Read Ongoing Load OK Program OK Erase OK Erase Verify Read OK3) Load Fail1) Program Fail Erase Fail Erase Verify Read Fail3) Load Reset2) Program Reset Erase Reset Erase Suspend Program Lock Erase Lock Load Lock(Buffer Lock) OTP Program Fail(Lock) OTP Program Fail OTP Erase Fail Program Ongoing(Susp.) Load Ongoing(Susp.) Program Fail(Susp.) Load Fail(Susp.) Invalid Command Invalid Command(Susp.) [15] OnGo 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 [14] Lock 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 0 0 0 0 0 0 [13] Load 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 [12] Prog 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 1 1 0 1 0 1 0 0 0 [11] 0 0 1 0 1 0 0 0 0 0 0 0 1 1 0 0 1 1 0 1 0 0 0 1 1 1 1 1 0 1 [10] 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 0 1 1 1 1 [9] Sus 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1 1 0 1 [8] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 [7] 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 [6] 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 1 0 0/1 0/1 0/1 0/1 0/1 0/1 0/1 [5:1] 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 [0] TO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Erase Error Reserved(0) RSTB OTPL Reserved(0) NOTE: 1. ERm and/or ERs bits in ECC status register at Load Fail case is 10. (2bits error - uncorrectable) 2. ERm and ERs bits in ECC status register at Load Reset case are 00. (No error) 3. Multi Block Erase status should be checked by Erase Verify Read operation. 46 OneNAND256(KFG5616x1A-xxB6) 2.8.22 Interrupt Status Register F241h (R/W) This Read/Write register shows status of the OneNAND interrupts. F241h, defaults = 8080h after Cold Reset; 8010h after Warm/Hot Reset 15 INT 14 13 12 11 10 9 8 7 RI 6 WI 5 EI 4 FLASH MEMORY 3 2 1 0 Reserved(0000000) RSTI Reserved(0000) Interrupt (INT) This is the master interrupt bit. The INT bit is wired directly to the INT pin on the chip. Upon writing '0' to the INT bit, the INT pin goes low if INTpol is high and goes high if INTpol is low. INT Interrupt [15] Status Conditions Default State Cold 1 sets itself to ’1’ One or more of RI, WI, RSTI and EI is set to ’1’, or 0065h, 0023h, 0071h, 002A and 002C commands are completed ’0’ is written to this bit, or Cold/Warm/Hot reset is being performed Warm/hot 1 Valid State 0 0→ 1 1→ 0 interrupt Function off Pending clears to ’0’ off Read Interrupt (RI) This is the Read interrupt bit. RI Interrupt [7] Status Conditions Default State Cold 1 sets itself to ’1’ At the completion of an Load Operation (0000h, 0013h, Load Data into Buffer, or boot is done) ’0’ is written to this bit, or Cold/Warm/Hot reset is being performed Warm/hot 0 Valid State 0 0→ 1 1→ 0 Interrupt Function off Pending clears to ’0’ off Write Interrupt (WI) This is the Write interrupt bit. WI Interrupt [6] Status Conditions Default State Cold 0 sets itself to ’1’ clears to ’0’ At the completion of an Program Operation (0080h, 001Ah, 001Bh) ’0’ is written to this bit, or Cold/Warm/Hot reset is being performed Warm/hot 0 Valid State 0 0→ 1 1→ 0 interrupt Function off Pending off 47 OneNAND256(KFG5616x1A-xxB6) Erase Interrupt (EI) This is the Erase interrupt bit. EI Interrupt [5] Status Conditions Default State Cold 0 sets itself to ’1’ clears to ’0’ At the completion of an Erase Operation (0094h, 0095h, 0030h) ’0’ is written to this bit, or Cold/Warm/Hot reset is being performed Warm/hot 0 FLASH MEMORY Valid State 0 0→ 1 1→ 0 Interrupt Function off Pending off Reset Interrupt (RSTI) This is the Reset interrupt bit. RSTI Interrupt [4] Status Conditions Default State Cold 0 sets itself to ’1’ clears to ’0’ At the completion of an Reset Operation (00B0h, 00F0h, 00F3h or warm reset is released) ’0’ is written to this bit Warm/hot 1 Valid State 0 0→ 1 1→ 0 interrupt Function off Pending off 2.8.23 Start Block Address Register F24Ch (R/W) This Read/Write register shows the NAND Flash block address in the Write Protection mode. Setting this register precedes a 'Lock Block' command, 'Unlock Block' command, or ’Lock-Tight' Command. F24Ch, default = 0000h 15 14 13 12 11 10 9 8 7 6 5 4 SBA 3 2 1 0 Reserved(00000000) Device 256Mb SBA Information[9:0] Item SBA Definition Start Block Address Number of Block 512 SBA [8:0] Description Precedes Lock Block, Unlock Block, or Lock-Tight commands 48 OneNAND256(KFG5616x1A-xxB6) 2.8.24 End Block Address Register F24Dh This register is reserved for future use. FLASH MEMORY 2.8.25 NAND Flash Write Protection Status Register F24Eh (R) This Read register shows the Write Protection Status of the NAND Flash memory array. To read the write protection status, FBA has to be set before reading the register. F24Eh, default = 0002h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 US 1 LS 0 LTS Reserved(0000000000000) Write Protection Status Information[2:0] Item US LS LTS Bit 2 1 0 Definition Unlocked Status Locked Status Locked-Tight Status Description 1 = current NAND Flash block is unlocked 1 = current NAND Flash block is locked 1 = current NAND Flash block is locked-tight 2.8.26 ECC Status Register FF00h (R) This Read register shows the Error Correction Status. The OneNAND can detect 1- or 2-bit errors and correct 1-bit errors. 3-bit or more error detection and correction is not supported. ECC can be performed on the NAND Flash main and spare memory areas. The ECC status register can also show the number of errors in a sector as a result of an ECC check in during a load operation. ECC status bits are also updated during a boot loading operation. FF00h, default = 0000h 15 14 13 12 11 10 9 8 7 ERm1 6 5 ERs1 4 3 ERm0 2 1 ERs0 0 Reserved(00000000) Error Status ERm, ERs 00 01 10 11 ECC Status No Error 1-bit error(correctable) 2 bits error (uncorrectable) Reserved 49 OneNAND256(KFG5616x1A-xxB6) ECC Information[7:0] FLASH MEMORY Item ERm0 Definition 1st selected sector of the main BufferRAM 2nd selected sector of the main BufferRAM 1st selected sector of the spare BufferRAM 2nd selected sector of the spare BufferRAM Description Status of errors in the 1st selected sector of the main BufferRAM as a result of an ECC check during a load operation. Also updated during a Bootload operation. Status of errors in the 2nd selected sector of the main BufferRAM as a result of an ECC check during a load operation. Also updated during a Bootload operation. Status of errors in the 1st selected sector of the spare BufferRAM as a result of an ECC check during a load operation. Also updated during a Bootload operation. Status of errors in the 2nd selected sector of the spare BufferRAM as a result of an ECC check during a load operation. Also updated during a Bootload operation. ERm1 ERs0 ERs1 2.8.27 ECC Result of 1st Selected Sector, Main Area Data Register FF01h (R) This Read register shows the Error Correction result for the 1st selected sector of the main area data. ECCposWord0 is the error position address in the Main Area data of 256 words. ECCposIO0 is the error position address which selects 1 of 16 DQs. ECCposWord0 and ECCposIO0 are also updated at boot loading. FF01h, default = 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved(0000) ECCposWord0 ECCposIO0 2.8.28 ECC Result of 1st Selected Sector, Spare Area Data Register FF02h (R) This Read register shows the Error Correction result for the 1st selected sector of the spare area data. ECClogSector0 is the error position address for 1.5 words of 2nd and 3rd words in the spare area. ECCposIO0 is the error position address which selects 1 of 16 DQs. ECClogSector0 and ECCposIO0 are also updated at boot loading. FF02h, default = 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved(0000000000) ECClogSector0 ECCposIO0 50 OneNAND256(KFG5616x1A-xxB6) FLASH MEMORY 2.8.29 ECC Result of 2nd Selected Sector, Main Area Data Register FF03h (R) This Read register shows the Error Correction result for the 2nd selected sector of the main area data. ECCposWord1 is the error position address in the Main Area data of 256 words. ECCposIO1 is the error position address which selects 1 of 16 DQs. ECCposWord1 and ECCposIO1 are also updated at boot loading. FF03h, default = 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved(0000) ECCposWord1 ECCposIO1 2.8.30 ECC Result of 2nd Selected Sector, Spare Area Data Register FF04h (R) This Read register shows the Error Correction result for the 2nd selected sector of the spare area data. ECClogSector1 is the error position address for 1.5 words of 2nd and 3rd words in the spare area. ECCposIO1 is the error position address which selects 1 of 16 DQs. ECClogSector1 and ECCposIO1 are also updated at boot loading. FF04h, default = 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved(0000000000) ECClogSector1 ECCposIO1 ECC Log Sector ECClogSector0~ECClogSector1 indicates the error position in the 2nd word and LSB of 3rd word in the spare area. Refer to note 2 in chapter 2.7.2 ECClogSector Information [5:4] ECClogSector 00 01 10, 11 Error Position 2nd word 3rd word Reserved 51 OneNAND256(KFG5616x1A-xxB6) FLASH MEMORY 3.0 DEVICE OPERATION This section of the datasheet discusses the operation of the OneNAND device. It is followed by AC/DC Characteristics and Timing Diagrams which may be consulted for further information. The OneNAND supports a limited command-based interface in addition to a register-based interface for performing operations on the device. 3.1 Command Based Operation The command-based interface is active in the boot partition. Commands can only be written with a boot area address. Boot area data is only returned if no command has been issued prior to the read. The entire address range, except for the boot area, can be used for the data buffer. All commands are written to the boot partition. Writes outside the boot partition are treated as normal writes to the buffers or registers. The command consists of one or more cycles depending on the command. After completion of the command the device starts its execution. Writing incorrect information including address and data to the boot partition or writing an improper command will terminate the previous command sequence and make the device enter the ready status. The defined valid command sequences are stated in Command Sequences Table. Command Sequences Command Definition Read Data from Buffer Write Data to Buffer Reset OneNAND Load Data into Buffer3) Read Identification Data 6) Add Data Add Data Add Data Add Data Add Data Cycles 1 1 1 2 2 1st cycle DP1) Data DP Data BP2) 00F0h BP 00E0h BP 0090h BP 0000h4) XXXXh5) Data 2nd cycle NOTE: 1) DP(Data Partition) : DataRAM Area 2) BP(Boot Partition) : BootRAM Area [0000h ~ 01FFh, 8000h ~ 800Fh]. 3) Load Data into Buffer operation is available within a block(64KB) 4) Load 1KB unit into DataRAM0. Current Start address(FPA) is automatically incremented by 1KB unit after the load. 5) 0000h -> Data is Manufacturer ID 0001h -> Data is Device ID 0002h -> Current Block Write Protection Status 6) WE toggling can terminate ’Read Identification Data’ operation. 52 OneNAND256(KFG5616x1A-xxB6) 3.1.1 Reading Data From Buffer FLASH MEMORY The buffer memory can be read by addressing a Read to the desired buffer area. 3.1.2 Writing Data to Buffer The buffer memory can be written to by addressing a Write to a desired buffer area. 3.1.3 Reset OneNAND Command The Reset command is given by writing 00F0h to the boot partition address. Reset will return all default values into the device. 3.1.4 Load Data Into Buffer Command Load Data into Buffer command is a two-cycle command. Two sequential designated command activates this operation. Sequentially writing 00E0h and 0000h to the boot partition [0000h~01FFh, 8000h~800Fh] will load one page to DataRAM0. This operation refers to FBA and FPA. FSA, BSA, and BSC are not considered. At the end of this operation, FPA will be automatically increased by 1. So continuous issue of this command will sequentially load data in next page to DataRAM0. This page address increment is restricted within a block. The default value of FBA and FPA is 0. Therefore, initial issue of this command after power on will load the first page of memory, which is usually boot code. 3.1.5 Read Identification Data Command The Read Identification Data command consists of two cycles. It gives out the devices identification data according to the given address. The first cycle is 0090h to the boot partition address and second cycle is read from the addresses specified in Identification Data Description Table. Identification Data Description Address 0000h 0001h 0002h Data Out Manufacturer ID : 00ECh Device ID : refer to chapter 2.8.3 Current Block Write Protection Status 1) Note 1) To read the write protection status, FBA has to be set before issuing this command. 53 OneNAND256(KFG5616x1A-xxB6) FLASH MEMORY 3.2 Device Bus Operation Operation Standby Warm Reset Asynchronous Write Asynchronous Read Load Initial Burst Read CE H X L L L OE X X H L H WE X X L H H ADQ0~15 High-Z High-Z Add. In / Data In Add. In / Data Out Add. In Burst Data Out High-Z High-Z RP H L H H H CLK X X L L AVD X X The device bus operations are shown in the table below. Burst Read Terminate Burst Read Cycle Terminate Burst Read Cycle via RP Terminate Current Burst Read Cycle and Start New Burst Read Cycle L L H H H H X X X H X H L X X X X H H Add In H Note : L=VIL (Low), H=VIH (High), X=Don’t Care. 54 OneNAND256(KFG5616x1A-xxB6) FLASH MEMORY 3.3 Reset Mode Operation The One NAND has 4 reset modes: Cold/Warm/Hot Reset, and NAND Flash Core Reset. Section 3.3 discusses the operation of these reset modes. The Register Reset Table shows the which registers are affected by the various types or Reset operations. Internal Register Reset Table Internal Registers F000h F001h F002h F003h F004h F005h F006h F100h F101h F102h F103h F107h F200h F220h F221h F240h F241h F24Ch F24Dh F24Eh FF00h FF01h FF02h FF03h FF04h Manufacturer ID Register (R) Device ID Register (R): OneNAND Version ID Register (R): N/A Data Buffer size Register (R) Boot Buffer size Register (R) Amount of Buffers Register (R) Technology Register (R) Start Address1 Register (R/W): FBA Start Address2 Register (R/W): Reserved Start Address3 Register (R/W): FCBA Start Address4 Register (R/W): FCPA, FCSA Start Address8 Register (R/W): FPA, FSA Start Buffer Register (R/W): BSA, BSC Command Register (R/W) System Configuration 1 Register (R/W) Controller Status Register (R) Interrupt Status Register (R/W) Start Block Address (R/W) End Block Address: N/A NAND Flash Write Protection Status (R) ECC Status Register (R) (Note2) ECC Result of Sector 0 Main area data Register(R) ECC Result of Sector 0 Spare area data Register (R) ECC Result of Sector 1 Main area data Register(R) ECC Result of Sector 1 Spare area data Register (R) Default Cold Reset 00ECh (Note 3) N/A 0400h 0200h 0201h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 40C0h 0000h 0000h N/A 0002h 0000h 0000h 0000h 0000h 0000h N/A N/A N/A N/A N/A N/A N/A 0000h 0000h 0000h 0000h 0000h 0000h 0000h 40C0h 0000h 8080h 0000h N/A 0002h 0000h 0000h 0000h 0000h 0000h Warm Reset (RP) N/A N/A N/A N/A N/A N/A N/A 0000h 0000h 0000h 0000h 0000h 0000h 0000h (Note1) Hot Hot NAND Flash Reset Reset Core Reset (00F3h) (BP-F0) (00F0h) N/A N/A N/A N/A N/A N/A N/A 0000h 0000h 0000h 0000h 0000h 0000h 0000h (Note1) N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 0000h 0000h 0000h 0000h 0000h 0000h 8010h 0000h N/A 0002h 0000h 0000h 0000h 0000h 0000h 0000h 8010h N/A N/A N/A 0000h 0000h 0000h 0000h 0000h NOTE: 1) RDYpol, INTpol, IOBE are reset by Cold reset. The other bits except OTPL are reset by cold/warm/hot reset. OTPL is updated by cold reset, referring to the specified OTP area. 2) ECC Status Register & ECC Result Registers are reset when any command is issued. 3) Refer to Device ID Register F001h. 55 OneNAND256(KFG5616x1A-xxB6) 3.3.1 Cold Reset Mode Operation See Timing Diagram 6.9 FLASH MEMORY At system power-up, the voltage detector in the device detects the rising edge of Vcc and releases an internal power-up reset signal. This triggers bootcode loading. Bootcode loading means that the boot loader in the device copies designated sized data (1KB) from the beginning of memory into the BootRAM. This sequence is the Cold Reset of OneNAND. The POR(Power On Reset) triggering level is typically 1.5V. Boot code copy operation activates 400us after POR. Therefore, the system power should reach 1.7V within 400us from the POR triggering level for bootcode data to be valid. For 2.65V and 3.3V device, POR level is typically 1.8V and system power should reach 2.2V within 400us. It takes approximately 70us to copy 1KB of bootcode. Upon completion of loading into the BootRAM, it is available to be read by the host. The INT pin is not available until after IOBE = 1 and IOBE bit can be changed by host. 3.3.2 Warm Reset Mode Operation See Timing Diagrams 6.10 A Warm Reset means that the host resets the device by using the RP pin. When the a RP low is issued, the device logic stops all current operations and executes internal reset operation and resets current NAND Flash core operation synchronized with the falling edge of RP. During an Internal Reset Operation, the device initializes internal registers and makes output signals go to default status. The BufferRAM data is kept unchanged after Warm/Hot reset operations. The device guarantees the logic reset operation in case RP pulse is longer than tRP min. (200ns). The device may reset if tRP < tRP min(200ns), but this is not guaranteed. Warm reset will abort the current NAND Flash core operation. During a warm reset, the content of memory cells being altered is no longer valid as the data will be partially programmed or erased. Warm reset has no effect on contents of BootRAM and DataRAM. 3.3.3 Hot Reset Mode Operation See Timing Diagram 6.11 A Hot Reset means that the host resets the device by Reset command. The reset command can be either Command based or Register Based. Upon receiving the Reset command, the device logic stops all current operation and executes an internal reset operation and resets the current NAND Flash core operation. During an Internal Reset Operation, the device initializes internal registers and makes output signals go to default status. The BufferRAM data is kept unchanged after Warm/Hot reset operations. Hot reset will abort the current NAND Flash core operation. During a Hot reset, the content of memory cells being altered is no longer valid as the data will be partially programmed or erased. Hot reset has no effect on contents of BootRAM and DataRAM. 3.3.4 NAND Flash Core Reset Mode Operation See Timing Diagram 6.12 The Host can reset the NAND Flash Core operation by issuing a NAND Flash Core reset command. NAND Flash core reset will abort the current NAND Flash core operation. During a NAND Flash core reset, the content of memory cells being altered is no longer valid as the data will be partially programmed or erased. Hot reset has no effect on contents of BootRAM and DataRAM, as well as register values. 56 OneNAND256(KFG5616x1A-xxB6) FLASH MEMORY 3.4 Write Protection Operation The OneNAND can be write-protected to prevent re-programming or erasure of data. The areas of write-protection are the BootRAM, and the NAND Flash Array. 3.4.1 BootRAM Write Protection Operation At system power-up, voltage detector in the device detects the rising edge of Vcc and releases the internal power-up reset signal which triggers bootcode loading. And the designated size data(1KB) is copied from the first page of the first block in the NAND flash array to the BootRAM. After the bootcode loading is completed, the BootRAM is always locked to protect the boot code from the accidental write. 3.4.2 NAND Flash Array Write Protection Operation The device has both hardware and software write protection of the NAND Flash array. Hardware Write Protection Operation The hardware write protection operation is implemented by executing a Cold or Warm Reset. On power up, the NAND Flash Array is in its default, locked state. The entire NAND Flash array goes to a locked state after a Cold or Warm Reset. Software Write Protection Operation The software write protection operation is implemented by writing a Lock command (002Ah) or a Lock-tight command (002Ch) to command register (F220h). Lock (002Ah) and Lock-tight (002Ch) commands write protects the block defined in the Start Block Address Register F24Ch. 3.4.3 NAND Array Write Protection States There are three lock states in the NAND Array: unlocked, locked, and locked-tight. OneNAND supports lock/unlock/lock-tight by one block, so each block should be locked/unlocked/locked-tight individually. Write Protection Status The current block Write Protection status can be read in NAND Flash Write Protection Status Register(F24Eh). There are three bits US, LS, LTS -, which are not cleared by hot reset. These Write Protection status registers are updated when FBA is set, and when Write Protection command is entered. The followings summarize locking status. example) In default, [2:0] values are 010. -> If host executes unlock block operation, then [2:0] values turn to 100. -> If host executes lock-tight block operation, then [2:0] values turn to 001. 57 OneNAND256(KFG5616x1A-xxB6) 3.4.3.1 Unlocked NAND Array Write Protection State FLASH MEMORY An Unlocked block can be programmed or erased. The status of an unlocked block can be changed to locked or locked-tight using the appropriate software command. (locked-tight state can be achieved via lock-tight command which follows lock command) Only one block can be released from lock state to unlock state with Unlock command and addresses. The unlocked block can be changed with new lock command. Therefore, each block has its own lock/unlock/lock-tight state. Unlocked Unlock Command Sequence: Start block address+Unlock block command (0023h) 3.4.3.2 Locked NAND Array Write Protection State A Locked block cannot be programmed or erased. All blocks default to a locked state following a Cold or Warm Reset. Unlocked blocks can be changed to locked using the Lock block command. The status of a locked block can be changed to unlocked or locked-tight using the appropriate software command. Locked Lock Command Sequence: Start block address+Lock block command (002Ah) 58 OneNAND256(KFG5616x1A-xxB6) 3.4.3.3 Locked-tight NAND Array Write Protection State FLASH MEMORY A block that is in a locked-tight state can only be changed to lock state after a Cold or Warm Reset. Unlock and Lock command sequences will not affect its state. This is an added level of write protection security. A block must first be set to a locked state before it can be changed to locked-tight using the Lock-tight command. locked-tight blocks will revert to a locked state following a Cold or Warm Reset. Locked-tight Lock-Tight Command Sequence: Start block address+Lock-tight block command (002Ch) 3.4.4 NAND Flash Array Write Protection State Diagram Lock RP pin: High & Start block address Lock block Command or Cold reset or Warm reset unlock Lock RP pin: High & Start block address +Unlock block Command Lock Power On RP pin: High & Start block address +Lock-tight block Command Lock Lock-tight Lock Cold reset or Warm reset 59 OneNAND256(KFG5616x1A-xxB6) Data Protection Operation Flow Diagram FLASH MEMORY Start Write ’SBA’ of Flash Add: F24Ch DQ=SBA Write 0 to interrupt register Add: F241h DQ=0000h Write ’lock/unlock/lock-tight’ Command Add: F220h DQ=002Ah/0023h/002Ch Wait for INT register low to high transition Add: F241h DQ[15]=INT Lock/Unlock/Lock-Tight completed Note) Samsung strongly recommend to follow the above flow chart 60 OneNAND256(KFG5616x1A-xxB6) FLASH MEMORY 3.5 Data Protection During Power Down Operation See Timing Diagram 6.13 The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below POR level, about 1.3V. It is recommended that the RP pin, which provides hardware protection, should be kept at VIL before power-down. 3.6 Load Operation The Load operation is initiated by setting up the start address from which the data is to be loaded. The Load command is issued in order to initiate the load. During a Load operation, the device: -Transfers the data from NAND Flash array into the BufferRAM -ECC is checked and any detected and corrected error is reported in the status response as well as any unrecoverable error. Once the BufferRAM has been filled, an interrupt is issued to the host so that the contents of the BufferRAM can be read. The read from the BufferRAM can be an asynchronous read mode or synchronous read mode. The status information related to load operation can be checked by the host if required. The device has a dual data buffer memory architecture (DataRAM0, DataRAM1), each 1KB in size. Each DataRAM buffer has 2 Sectors. The device is capable of independent and simultaneous data-read operation from one data buffer and data-load operation to the other data buffer. Refer to the information for more details in section 3.12.1, "Read-While-Load Operation". Load Operation Flow Chart Diagram Start Write ’Load’ Command Add: F220h DQ=0000h or 0013h Write ’FBA’ of Flash Add: F100h DQ=FBA Write ’FPA, FSA’ of Flash Add: F107h DQ=FPA, FSA Wait for INT register low to high transition Add: F241h DQ[15]=INT Write ’BSA, BSC’ of DataRAM Add: F200h DQ=BSA, BSC Read Controller Status Register Add: F240h DQ[10]=Error Write 0 to interrupt register Add: F241h DQ=0000h DQ[10]=0? YES Host reads data from DataRAM NO Map Out Read completed 61 OneNAND256(KFG5616x1A-xxB6) FLASH MEMORY 3.7 Read Operation See Timing Diagrams 6.1, 6.2, 6.3 and 6.4 The device has two read modes; Asynchronous Read and Synchronous Burst Read. The initial state machine automatically sets the device into the Asynchronous Read Mode (RM=0) to prevent the spurious altering of memory content upon device power up or after a Hardware reset. No commands are required to retrieve data in Asynchronous Read Mode. The Synchronous Read Mode is enabled by setting RM bit of System Configuration1 Register (F221h) to Synchronous Read Mode (RM=1). See Section 2.8.19 for more information about System Configuration1 Register. 3.7.1 Asynchronous Read Mode Operation (RM=0) See Timing Diagrams 6.3 and 6.4 In an Asynchronous Read Mode, data is output with respect to a logic input, AVD. Output data will appear on DQ15-DQ0 in when a valid address is asserted on A15-A0 while driving AVD and CE to VIL. / WE is held at VIH. The function of the AVD signal is to latch the valid address. Address access time from AVD low (tAA) is equal to the delay from valid addresses to valid output data. The Chip Enable access time (tCE) is equal to the delay from the falling edge of CE to valid data at the outputs. The Output Enable access time (tOE) is the delay from the falling edge of OE to valid data at the output. 3.7.2 Synchronous Read Mode Operation (RM=1) See Timing Diagrams 6.1 and 6.2 In a Synchronous Read Mode, data is output with respect to a clock input. The device is capable of a continuous linear burst operation and a fixed-length linear burst operation of a preset length. Burst address sequences for continuous and fixed-length burst operations are shown in the table below. Burst Address Sequences Start Addr. 0 Wrap around 1 2 . . Burst Address Sequence(Decimal) Continuous Burst 0-1-2-3-4-5-6... 1-2-3-4-5-6-7... 2-3-4-5-6-7-8... . . 4-word Burst 0-1-2-3-0... 1-2-3-0-1... 2-3-0-1-2... . . 8-word Burst 0-1-2-3-4-5-6-7-0... 1-2-3-4-5-6-7-0-1... 2-3-4-5-6-7-0-1-2... . . 16-word Burst 0-1-2-3-4-....-13-14-15-0... 1-2-3-4-5-....-14-15-0-1... 2-3-4-5-6-....-15-0-1-2... . . 32-word Burst 0-1-2-3-4-....-29-30-31-0... 1-2-3-4-5-....-30-31-0-1... 2-3-4-5-6-....-31-0-1-2... . . In the burst mode, the initial word will be output asynchronously, regardless of BRL. While the following words will be determined by BRL value. The latency is determined by the host based on the BRL bit setting in the System Configuration 1 Register. The default BRL is 4 latency cycles. At clock frequencies of 40MHz or lower, latency cycles can be reduced to 3. BRL can be set up to 7 latency cycles. 62 OneNAND256(KFG5616x1A-xxB6) 3.7.2.1 Continuous Linear Burst Read Operation See Timing Diagram 6.2 FLASH MEMORY First Clock Cycle The initial word is output at tIAA after the rising edge of the first CLK cycle. The RDY output indicates the initial word is ready to the system by pulsing high. If the device is accessed synchronously while it is set to Asynchronous Read Mode, the first data can still be read out. Subsequent Clock Cycles Subsequent words are output (Burst Access Time from Valid Clock to Output) tBA after the rising edge of each successive clock cycle, which automatically increments the internal address counter. Terminating Burst Read The device will continue to output sequential burst data until the system asserts CE high, or RP low, wrapping around until it reaches the designated address (see Section 2.7.3 for address map information). Alternately, a Cold/Warm/Hot Reset, asserting CE high, or a WE low pulse will terminate the burst read operation. Synchronous Read Boundary Division BootRAM Main(0.5Kw) BufferRAM0 Main(0.5Kw) BufferRAM1 Main(0.5Kw) Reserved Main BootRAM Spare(16w) BufferRAM0 Spare(16w) BufferRAM1 Spare(16w) Reserved Spare Reserved Register Register(4Kw) Add.map(word order) 0000h~01FFh 0200h~03FFh 0400h~05FFh 0600h~7FFFh 8000h~800Fh 8010h~801Fh 8020h~802Fh 8030h~8FFFh 9000h~EFFFh F000h~FFFFh Not Support Not Support Not Support Not Support Not Support * Reserved area is not available on Synchronous read 3.7.2.2 4-, 8-, 16-, 32-Word Linear Burst Read Operation See Timing Diagram 6.1 An alternate Burst Read Mode enables a fixed number of words to be read from consecutive address. The device supports a burst read from consecutive addresses of 4-, 8-, 16-, and 32-words with a linear-wrap around. When the last word in the burst has been reached, assert CE and OE high to terminate the operation. In this mode, the start address for the burst read can be any address of the address map with one exception. The device does not support a 32-word linear burst read on the spare area of the BufferRAM. 63 OneNAND256(KFG5616x1A-xxB6) 3.7.2.3 Programmable Burst Read Latency Operation See Timing Diagrams 6.1 and 6.2 FLASH MEMORY Upon power up, the number of initial clock cycles from Valid Address (AVD) to initial data defaults to four clocks. The number of clock cycles (n) which are inserted after the clock which is latching the address. The host can read the first data with the (n+1)th rising edge. The number of total initial access cycles is programmable from three to seven cycles. After the number of programmed burst clock cycles is reached, the rising edge of the next clock cycle triggers the next burst data. Four Clock Burst Read Latency (default condition) Rising edge of the clock cycle following last read latency triggers next burst data CE ≈ CLK ≈ -1 AVD 0 1 2 3 4 ≈ tBA A0: A15 DQ0: DQ15 tIAA OE Hi-Z tRDYS Valid Address ≈ D6 D7 D0 D1 D2 D3 D7 D0 ≈ Hi-Z ≈ RDY tRDYA 3.7.3 Handshaking Operation The handshaking feature allows the host system to simply monitor the RDY signal from the device to determine when the initial word of burst data is ready to be read. To set the number of initial cycles for optimal burst mode, the host should use the programmable burst read latency configuration (see Section 2.8.19, "System Configuration1 Register"). The rising edge of RDY which is derived at the same cycle of data fetch clock indicates the initial word of valid burst data. 64 OneNAND256(KFG5616x1A-xxB6) 3.7.4 Output Disable Mode Operation FLASH MEMORY When the CE or OE input is at VIH, output from the device is disabled. The outputs are placed in the high impedance state. 3.8 Program Operation The Program operation is used to program data from the on-chip BufferRAMs into the NAND FLASH memory array. The device has two 1KB data buffers, each 1 Page (1KB + 32B) in size. Each page has 2 sectors of 512B each main area and 16B spare area. The device can be programmed in units of 1~2 sectors. The architecture of the DataRAMs permits a simultaneous data-write operation from the Host to one of data buffers and a program operation from the other data buffer to the NAND Flash Array memory. Refer to Section 3.12.2, "Write While Program Operation", for more information. Addressing for program operation Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of the block to MSB (most significant bit) pages of the block. Random page address programming is prohibited. Page 63 (64) : Page 63 (64) : Page 31 (32) : Page 31 (1) : Page 2 Page 1 Page 0 (3) (2) (1) Page 2 Page 1 Page 0 (3) (32) (2) Data register From the LSB page to MSB page DATA IN: Data (1) Data (64) Data register Ex.) Random page program (Prohibition) DATA IN: Data (1) Data (64) 65 OneNAND256(KFG5616x1A-xxB6) Program Operation Flow Diagram FLASH MEMORY Start Write 0 to interrupt register Add: F241h DQ=0000h Write ’Program’ Command Add: F220h DQ=0080h or 001Ah Write Data into DataRAM2) ADD: DP DQ=Data-in Data Input Completed? YES Write ’FBA’ of Flash Add: F100h DQ=FBA NO Wait for INT register low to high transition Add: F241h DQ[15]=INT Read Controller Status Register Write ’FPA, FSA’ of Flash Add: F107h DQ=FPA, FSA Add: F240h DQ[10]=Error Write ’BSA, BSC’ of DataRAM Add: F200h DQ=BSA, BSC DQ[10]=0? YES Program completed NO Program Error * : If program operation results in an error, map out the block including the page in error and copy the target data to another block. Note 1) This must happen before data input 2) Data input could be done anywhere between "Start" and "Write Program Command". During the execution of the Internal Program Routine, the host is not required to provide any further controls or timings. Furthermore, all commands, except a Reset command, will be ignored. A reset during a program operation will cause data corruption at the corresponding location. If a program error is detected at the completion of the Internal Program Routine, map out the block, including the page in error, and copy the target data to another block. An error is signaled if DQ10 = "1" of Controller Status Register(F240h) . Data input from the Host to the DataRAM can be done at any time during the Internal Program Routine after "Start" but before the "Write Program Command" is written. 66 OneNAND256(KFG5616x1A-xxB6) FLASH MEMORY 3.9 Copy-Back Program Operation The Copy-Back program is configured to quickly rewrite data stored in one page without utilizing memory other than OneNAND. Since the time-consuming cycles of serial access and re-loading cycles are removed, the system performance is improved. The benefit is especially obvious when a portion of block is updated and the rest of the block also need to be copied to the newly assigned free block. Data from the source page is saved in one of the on-chip DataRAM buffers and then programmed directly into the destination page. The DataRAM overwrites the previous data using the Buffer Sector Address (BSA) and Buffer Sector Count (BSC). The Copy-Back Program Operation does this by performing sequential page-reads without a serial access and executing a copy-program using the address of the destination page. Copy-Back Program Operation Flow Chart Start Write ’Copy-back Program’ command Add: F220h DQ=001Bh Write ’FBA’ of Flash Add: F100h DQ=FBA Write ’FPA, FSA’ of Flash Add: F107h DQ=FPA, FSA Wait for INT register low to high transition Add: F241h DQ[15]=INT Write ’FCBA’ of Flash Add: F102h DQ=FCBA Read Controller Status Register Add: F240h DQ[10]=Error Write ’FCPA, FCSA’ of Flash Add: F103h DQ=FCPA, FCSA DQ[10]=0? YES Copy back completed NO Copy back Error Write ’BSA, BSC’ of DataRAM Add: F200h DQ=BSA, BSC 1) Write 0 to interrupt register Add: F241h DQ=0000h * : If program operation results in an error, map out the block including the page in error and copy the target data to another block. Note 1) Selected DataRAM by BSA & BSC is used for Copy back operation, so previous data is overwritten. 2) FBA, FPA and FSA should be input prior to FCBA, FCPA and FCSA. 67 OneNAND256(KFG5616x1A-xxB6) The Copy-Back steps shown in the flow chart are: FLASH MEMORY • Data is read from the NAND Array using Flash Block Address (FBA), Flash Page Address (FPA) and Flash Sector Address (FSA). FBA, FPA, and FSA identify the source address to read data from NAND Flash array. • The BufferRAM Sector Count (BSC) and BufferRAM Sector Address (BSA) identifies how many sectors and the location of the sectors in DataRAM that are used. • The destination address in the NAND Array is written using the Flash Copy-Back Block Address (FCBA), Flash Copy-Back Page Address (FCPA), and Flash Copy-Back Sector Address (FCSA). • The Copy-Back Program command is issued to start programming. • Upon completion of copy-back programming to the destination page address, the Host checks the status to see if the operation was successfully completed. If there was an error, map out the block including the page in error and copy the target data to another block. 68 OneNAND256(KFG5616x1A-xxB6) 3.9.1 FLASH MEMORY Copy-Back Program Operation with Random Data Input See Timing Diagram 6.7 The Copy-Back Program Operation with Random Data Input in OneNAND consists of 2 phase, Load data into DataRAM, Modify data and program into designated page. Data from the source page is saved in one of the on-chip DataRAM buffers and modified by the host, then programmed into the destination page. As shown in the flow chart, data modification is possible upon completion of load operation. ECC is also available at the end of load operation. Therefore, using hardware ECC of OneNAND, accumulation of 1 bit error can be avoided. Copy-Back Program Operation with Random Data Input will be effectively utilized at modifying certain bit, byte, word, or sector of source page to destination page while it is being copied. Copy-Back Program Operation with Random Data Input Flow Chart Start DQ[10]=0? YES Random Data Input Add: Random Address in Selected DataRAM DQ=Data NO Map Out Write ’FBA’ of Flash Add: F100h DQ=FBA Write ’FPA, FSA’ of Flash Add: F107h DQ=FPA, FSA Write ’BSA, BSC’ of DataRAM Add: F200h DQ=BSA, BSC Write ’FBA’ of Flash Add: F100h DQ=FBA Write 0 to interrupt register Add: F241h DQ=0000h Write ’FPA, FSA’ of Flash Add: F107h DQ=FPA, FSA Write ’Load’ Command Add: F220h DQ=0000h or 0013h Write 0 to interrupt register Add: F241h DQ=0000h Write ’Program’ Command Wait for INT register low to high transition Add: F241h DQ[15]=INT Read Controller Status Register Add: F240h DQ[10]=Error Add: F220h DQ=0080h or 001Ah Wait for INT register low to high transition Add: F241h DQ[15]=INT Read Controller Status Register Add: F240h DQ[10]=Error DQ[10]=0? YES Copy back completed NO Copy back Error 69 OneNAND256(KFG5616x1A-xxB6) FLASH MEMORY 3.10 Erase Operation There are multiple methods for erasing data in the device including Block Erase and Multi-Block Erase. 3.10.1 Block Erase Operation See Timing Diagram 6.8 The device can be erased one block at a time. To erase a block is to write all 1's into the desired memory block by executing the Internal Erase Routine. All previous data is lost. Block Erase Operation Flow Chart Start Write ’FBA’ of Flash Add: F100h DQ=FBA Write 0 to interrupt register Add: F241h DQ=0000h Write ’Erase’ Command Add: F220h DQ=0094h Wait for INT register low to high transition Add: F241h DQ=[15]=INT Read Controller Status Register Add: F240h DQ[10]=Error DQ[10]=0? YES Erase completed NO Erase Error * : If erase operation results in an error, map out the failing block and replace it with another block. 70 OneNAND256(KFG5616x1A-xxB6) In order to perform the Internal Erase Routine, the following command sequence is necessary. • The Host sets the block address of the memory location. FLASH MEMORY • The Erase Command initiates the Internal Erase Routine. During the execution of the Routine, the host is not required to provide further controls or timings. During the Internal erase routine, all commands, except the Reset command and Erase Suspend Command, written to the device will be ignored. A reset during an erase operation will cause data corruption at the corresponding location. 3.10.2 Multi-Block Erase Operation See Timing Diagram 6.8 Using Multi-Block Erase, the device can erase up to 64 multiple blocks simultaneously. Multiple blocks can be erased by issuing a Multi-Block Erase command and writing the block address of the memory location to be erased. The final Flash Block Address (FBA) and Block Erase command initiate the internal multi block erase routine. During a Multi-Block Erase, the OnGo bit of the Controller Status Register is set to '1'(busy) from the time first block address to be latched is written until the actual erase has finished. During block address latch sequence, issuing of other commands except Block Erase and Multi Block Erase at INT=High will abort the current operation. So to speak, It will cancel the previously latched addresses of Multi Block Erase Operation. On the other hand, Other command issue at INT=low will be ignored. A reset during an erase operation will cause data corruption at the address location being operated on during the reset. Despite a failed block during Multi-Block Erase operation, the device will continue the erase operation until all other specified blocks are erased. Erase Suspend Command issue during Multi Block Erase Address latch sequence is prohibited. Locked Blocks If there are locked blocks in the specified range, the Multi-Block Erase operation works as the follows. Case 1: All specified blocks except BA(2) will be erased. [BA(1)+0095h] + [BA((2), locked)+0095h] + ... + [BA(N-1)+0095h] + [BA(N)+0094h] Case 2: Multi-Block Erase Operation is suspended and fails to start if the last Block Erase command is put together with the locked block address until right command and address input are issued. [BA(1)+0095h] + [BA(2)+0095h] + ... + [BA(N-1)+0095h] + [BA((N), locked)+0094h] Case 3: All specified blocks except BA(N) are erased. [BA(1)+0095h] + [BA(2)+0095h] + ... + [BA(N-1)+0095h] + [BA((N), locked)+0094h] + [BA(N+1)+0094h] 71 OneNAND256(KFG5616x1A-xxB6) 3.10.3 Multi-Block Erase Verify Read Operation FLASH MEMORY After a Multi-Block Erase Operation, verify Erase Operation result of each block with Multi-Block Erase Verify Command combined with address of each block. If a failed address is identified, it must be managed in firmware. Multi Block Erase/ Multi Block Erase Verify Read Flow Chart Start Write ’FBA’ of Flash Add: F100h DQ=FBA Read Controller Status Register Add: F240h DQ[10]=Error Write ’FBA’ of Flash Add: F100h DQ=FBA Write 0 to interrupt register Add: F241h DQ=0000h DQ[10]=0? NO YES Erase completed Write 0 to interrupt register Add: F241h DQ=0000h Write ’Block Erase Command’ Add: F220h DQ=0094h Write ’Multi Block Erase’ Command Add: F220h DQ=0095h Wait for INT register low to high transition Add: F241h DQ=[15]=INT Wait for INT register low to high transition Add: F241h DQ=[15]=INT Write ’FBA’ of Flash Add: F100h DQ=FBA NO NO Erase Error Final Multi Block Erase Address? YES Multi Block Erase completed Final Multi Block Erase? YES Write 0 to interrupt register Add: F241h DQ=0000h Multi Block Erase Verify Read Write ’Multi Block Erase Verify Read Command’ Add: F220h DQ=0071h Wait for INT register low to high transition Add: F241h DQ=[15]=INT 72 OneNAND256(KFG5616x1A-xxB6) 3.10.4 Erase Suspend / Erase Resume Operation FLASH MEMORY The Erase Suspend/Erase Resume Commands interrupt and restart a Block Erase or Multi-Block Erase operation so that user may perform another urgent operation on the block that is not being designated by Erase/Multi-Block Erase Operation. Erase Suspend During a Block Erase Operation When Erase Suspend command is written during a Block Erase or Multi-Block Erase operation, the device requires a maximum of 500us to suspend erase operation. Erase Suspend Command issue during Block Address latch sequence is prohibited. After the erase operation has been suspended, the device is ready for the next operation including a load, program, copy-back program, Lock, Unlock, Lock-tight, Hot Reset, NAND Flash Core Reset, Command Based Reset, Multi-Block Erase Read Verify, or OTP Access. The subsequent operation can be to any block that was NOT being erased. A special case arises pertaining Erase Suspend to the OTP. A Reset command is used to exit from the OTP Access mode. If the Reset-triggered exit from the OTP Access Mode happens during an Erase Suspend Operation, the erase routine could fail. Therefore to exit from the OTP Access Mode without suspending the erase operation stop, a 'NAND Flash Core Reset' command should be issued. For the duration of the Erase Suspend period the following commands are not accepted: • Block Erase/Multi-Block Erase/Erase Suspend Erase Suspend and Erase Resume Operation Flow Chart Start Write 0 to interrupt register Add: F241h DQ=0000h Write 0 to interrupt register Add: F241h DQ=0000h Write ’Erase Resume Command’ Add: F220h DQ=0030h Write ’Erase Suspend Command’1) Add: F220h DQ=00B0h Wait for INT register low to high transition Add: F241h DQ=[15]=INT Wait for INT register low to high transition for 500us Add: F241h DQ=[15]=INT Check Controller Status Register in case of Block Erase Do Multi Block Erase Verify Read in case of Multi Block Erase Another Operation * * Another Operation ; Load, Program Copy-back Program, OTP Access2), Hot Reset, Flash Reset, CMD Reset, Multi Block Erase Verify, Lock, Lock-tight, Unlock Note 1) Erase Suspend command input is prohibited during Multi Block Erase address latch period. 2) If OTP access mode exit happens with Reset operation during Erase Suspend mode, Reset operation could hurt the erase operation. So if a user wants to exit from OTP access mode without the erase operation stop, Reset NAND Flash Core command should be used. 73 OneNAND256(KFG5616x1A-xxB6) FLASH MEMORY Erase Resume When the Erase Resume command is executed, the Block Erase will restart. The Erase Resume operation does not actually resume the erase, but starts it again from the beginning. When an Erase Suspend or Erase Resume command is executed, the addresses are in Don't Care state. For Multi Block Erase, Erase suspend/Resume can be operated after final Erase command (0094h) is issued. Therefore, Erase Resume operation does not actually resume from the erased block. But resumes the multi block erase from the begging. 3.11 OTP Operation On Block of the NAND Flash Array memory is reserved as a One-Time Programmable Block memory area. The OTP block can be read, programmed and locked using the same operations as any other NAND Flash Array memory block. OTP block cannot be erased. OTP block is fully-guaranteed to be a valid block. Entering the OTP Block The OTP block is separately accessible from the rest of the NAND Flash Array by using the OTP Access command instead of the Flash Block Address (FBA). Exiting the OTP Block To exit the OTP Access Mode, a Cold-, Warm-, Hot-, or NAND Flash Core Reset operation is performed. Exiting the OTP Block during an Erase Operation If the Reset-triggered exit from the OTP Access Mode happens during an Erase Suspend Operation, the erase routine could fail. Therefore to exit from the OTP Access Mode without suspending the erase operation stop, a 'NAND Flash Core Reset' command should be issued. The OTP Block Page Assignments OTP area is one block size ((64K+2K)B, 64 Pages) and is divided into two areas. The 20-page User Area is available as an OTP storage area. The 44-page Manufacturer Area is programmed by the manufacturer prior to shipping the device to the user. OTP Block Page Allocation Information Area User Manufacturer Page 0 ~ 19 (20 pages) 20 ~ 63 (44 pages) Use Designated as user area Used by the device manufacturer 74 OneNAND256(KFG5616x1A-xxB6) OTP Area Structure FLASH MEMORY Page:1KB+32B Sector(main area):512B One Block: 64pages 64KB+2KB Sector(spare area):16B Manufacturer Area : 44pages page 20~ page 63 User Area : 20pages page 0~ page 19 75 OneNAND256(KFG5616x1A-xxB6) 3.11.1 OTP Load Operation FLASH MEMORY An OTP Load Operation accesses the OTP area and transfers identified content from the OTP to the DataRAM on-chip buffer, thus making the OTP contents available to the Host. The OTP area is a separate part of the NAND Flash Array memory. It is accessed by issuing OTP Access command(65h) instead of a Flash Block Address (FBA) command. After being accessed with the OTP Access Command, the contents of OTP memory area are loaded using the same operations as a normal load operation to the NAND Flash Array memory (see section 3.6 for more information). To exit the OTP access mode following an OTP Load Operation, a Cold-, Warm-, Hot-, or NAND Flash Core Reset operation is performed. OTP Read Operation Flow Chart Start Write ’FBA’ of Flash1) Add: F100h DQ=FBA Write 0 to interrupt register Add: F241h DQ=0000h Write ’Load’ Command Add: F220h DQ=0000h or 0013h Write ’OTP Access’ Command Add: F220h DQ=0065h Wait for INT register low to high transition Add: F241h DQ[15]=INT Wait for INT register low to high transition Add: F241h DQ[15]=INT Write ’FPA, FSA’ of Flash1) Add: F107h DQ=FPA, FSA Host reads data from DataRAM OTP Reading completed Write ’BSA, BSC’ of DataRAM Add: F200h DQ=BSA, BSC Do Cold/Warm/Hot /NAND Flash Core Reset Write 0 to interrupt register Add: F241h DQ=0000h OTP Exit Note 1) FBA(NAND Flash Block Address) could be omitted or could be any address. 76 OneNAND256(KFG5616x1A-xxB6) 3.11.2 OTP Program Operation FLASH MEMORY An OTP Program Operation accesses the OTP area and programs content from the DataRAM on-chip buffer to the designated page(s) of the OTP. A memory location in the OTP area can be programmed only one time (no erase operation permitted). The OTP area is programmed using the same sequence as normal program operation after being accessed by the command (see section 3.8 for more information). Programming the OTP Area • Issue the OTP Access Command • Write data into the DataRAM (data can be input at anytime between the "Start" and "Write Program" commands) • Issue a Flash Block Address (FBA) which is unlocked area address of NAND Flash Array address map. • Issue a Write Program command to program the data from the DataRAM into the OTP • When the OTP programming is complete, do a Cold-, Warm-, Hot-, NAND Flash Core Reset to exit the OTP Access mode. 77 OneNAND256(KFG5616x1A-xxB6) OTP Program Operation Flow Chart FLASH MEMORY Start Write ’FBA’ of Flash1) Add: F100h DQ=FBA Write ’FBA’ of Flash Add: F100h DQ=FBA3) Write ’FPA, FSA’ of Flash Add: F107h DQ=FPA, FSA Write 0 to interrupt register Add: F241h DQ=0000h Write ’BSA, BSC’ of DataRAM Add: F200h DQ=BSA, BSC Write ’OTP Access’ Command Add: F220h DQ=0065h Wait for INT register low to high transition Add: F241h DQ[15]=INT Write 0 to interrupt register Add: F241h DQ=0000h Write Program command Add: F220h DQ=0080h or 001Ah Automatically checked OTPL=0? YES NO Automatically updated Write Data into DataRAM2) Add: DP DQ=Data-in Data Input Completed? NO Wait for INT register low to high transition Add: F241h DQ[15]=INT Update Controller Status Register Add: F240h DQ[14]=1(Lock), DQ[10]=1(Error) Wait for INT register low to high transition Add: F241h DQ[15]=INT Read Controller Status Register Add: F240h DQ[10]=0(Pass) OTP Programming completed Read Controller Status Register Add: F240h DQ[10]=1(Error) Do Cold/Warm/Hot /NAND Flash Core reset Do Cold/Warm/Hot /NAND Flash Core reset OTP Exit OTP Exit Note 1) FBA(NAND Flash Block Address) could be omitted or any address. 2) Data input could be done anywhere between "Start" and "Write Program Command". 3) FBA should point the unlocked area address among NAND Flash Array address map. 78 OneNAND256(KFG5616x1A-xxB6) 3.11.3 OTP Lock Operation FLASH MEMORY Even though the OTP area can only be programmed once without erase capability, it can be locked when the device starts up to prevent any changes from being made. Unlike the main area of the NAND Flash Array memory, once the OTP block is locked, it cannot be unlocked. Locking the OTP Programming to the OTP area can be prevented by locking the OTP area. Locking the OTP area is accomplished by programming XXXCh to 8th word of sector0 of page0 of the spare0 memory area. At device power-up, this word location is checked and if XXXCh is found, the OTPL bit of the Controller Status Register is set to "1", indicating the OTP is locked. When the Program Operation finds that the status of the OTP is locked, the device updates the Error Bit of the Controller Status Register as "1" (fail). OTP Lock Operation Steps • • • • • • • Issue the OTP Access Command Fill data to be programmed into DataRAM (data can be input at anytime between the "Start" and "Write Program" commands) Write 'XXXCH' data into the 8th word of sector0 of page0 of the spare0 memory area of the DataRAM. Issue a Flash Block Address (FBA) to unlocked address in the NAND Flash Array address map. Issue a Program command to program the data from the DataRAM into the OTP When the OTP lock is complete, do a Cold Reset to exit the OTP Access mode and update OTP lock bit[6]. OTP lock bit[6] of the Controller Status Register will be set to "1" and the OTP will be locked. 79 OneNAND256(KFG5616x1A-xxB6) OTP Lock Operation Flow Chart FLASH MEMORY Start Write ’FBA’ of Flash Add: F100h DQ=FBA3) Write ’FBA’ of Flash1) Add: F100h DQ=FBA Write 0 to interrupt register Add: F241h DQ=0000h Write ’FPA, FSA’ of Flash Add: F107h DQ=0000h Write ’BSA, BSC’ of DataRAM Add: F200h DQ=0001h Write ’OTP Access’ Command Add: F220h DQ=0065h Wait for INT register low to high transition Add: F241h DQ[15]=INT Write 0 to interrupt register Add: F241h DQ=0000h Write Program command Add: F220h DQ=0080h or 001Ah Write Data into DataRAM2) Add: 8th Word in spare0/sector0/page0 DQ=XXXCh Wait for INT register low to high transition Add: F241h DQ[15]=INT Do Cold reset Automatically updated Update Controller Status Register Add: F240h DQ[6]=1(OTPL) OTP lock completed Note 1) FBA(NAND Flash Block Address) could be omitted or any address. 2) Data input could be done anywhere between "Start" and "Write Program Command". 3) FBA should point the unlocked area address among NAND Flash Array address map. 80 OneNAND256(KFG5616x1A-xxB6) FLASH MEMORY 3.12 Dual Operations The device has independent dual data buffers on-chip (except during the Boot Load period) that enables higher performance read and program operation. 3.12.1 Read-While-Load Operation This operation accelerates the read performance of the device by enabling data to be read out by the host from one DataRAM buffer while the other DataRAM buffer is being loaded with data from the NAND Flash Array memory. 1) Data Load Page A 3) Data Load Page B Data Buffer0 Data Buffer1 2) Data Read 2) Data Load 3) Data Read The dual data buffer architecture provides the capability of executing a data-read operation from one of DataRAM buffers during a simultaneous data-load operation from Flash to the other buffer. Simultaneous load and read operation to same data buffer is prohibited. See sections 3.6 and 3.7 for more information on Load and Read Operations. If host sets FBA, FSA, or FPA while loading into designated page, it will fail the internal load operation. Address registers should not be updated until internal operation is completed. 3.12.2 Write-While-Program Operation This operation accelerates the programming performance of the device by enabling data to be written by the host into one DataRAM buffer while the NAND Flash Array memory is being programmed with data from the other DataRAM buffer. Page A 2) Program 1) Data Write Data Buffer0 Data Buffer1 3) Data Write Page B 3) Program 2) Data Write The dual data buffer architecture provides the capability of executing a data-write operation to one of DataRAM buffers during simultaneous data-program operation to Flash from the other buffer. Simultaneous program and write operation to same data buffer is prohibited. See sections 3.8 for more information on Program Operation. If host sets FBA, FSA, or FPA while programming into designated page, it will fail the internal program operation. Address registers should not be updated until internal operation is completed. 81 Read While Load Diagram ADD Add_ reg DB0 _add 0000h 0000h Flash _add LD_ CMD Read Status DB1 _add LD_ CMD Int_ reg CMD_ reg CS_ reg Add_ reg Int_ reg CMD_ reg 0~15 Page A Add_ reg Page B Add_ reg Data Load 2) _DB1 DQ 0~15 Flash _add 1) Data Load _DB0 1) Data Load _DB0 DB0_radd* Data Load 2) _DB1 Data Read _DB0 * WE OE INT * DBS should be set before accessing DataRAM for DDP OneNAND256(KFG5616x1A-xxB6) 82 Int_reg : Interrupt Register Address Add_reg : Address Register Address Flash_add : Flash Address to be loaded DBn_add : DataRAM Address to be loaded CMD_reg : Command Register Address LD_CMD : Load Command Data Load_DBn : Load Data from NAND Flash Array to DataRAMn CS_reg : Controller Status Register Address Data Read_DBn : Read Data from DBn DBn_radd : DataRAM Address to be read FLASH MEMORY Write While Program Diagram Page A Add_ reg Add_ reg Add_ reg DB1_wadd* 2) DB0 _add 0000h Read Status Flash _add 0000h DB1 _add PD_ CMD Data PGM _PageA Data Write _DB1 * PD_ CMD Int_ reg CMD_ reg Data PGM _PageA CS_ reg CMD_ reg Int_ reg Page B ADD 0~15 DB0_wadd* 1) Add_ reg Data PGM _PageB DB0_wadd* DQ 0~15 Data Write _DB0 * Flash _add Data PGM _PageB Data Write _DB0 * WE OE OneNAND256(KFG5616x1A-xxB6) INT 83 Add_reg : Address Register Address DBn_add : DataRAM Address to be programmed DBn_wadd : DataRAM Address to be written Data Write_DBn : Write Data to DataRAMn Flash_add : Flash Address to be programmed Int_reg : Interrupt Register Address CMD_reg : Command Register Address PD_CMD : Program Command Data PGM_PageA : Program Data from DataRAM to PageA CS_reg : Controller Status Register Address * DBS should be set before accessing DataRAM for DDP FLASH MEMORY OneNAND256(KFG5616x1A-xxB6) FLASH MEMORY 3.13 ECC Operation The OneNAND device has on-chip ECC with the capability of detecting 2 bit errors and correcting 1-bit errors in the NAND Flash Array memory main and spare areas. As the device transfers data from a BufferRAM to the NAND Flash Array memory Page Buffer for Program Operation, the device initiates a background operation which generates an Error Correction Code (ECC) of 24bits for each sector main area data and 10bits for 2nd and 3rd word data of each sector spare area. During a Load operation from the NAND Flash Array memory Page, the on-chip ECC engine generates a new ECC. The 'Load ECC result' is compared to the originally 'Program ECC' thus detecting the number and position of errors. Single-bit error is corrected. ECC is updated by the device automatically. After a Load Operation, the Host can determine whether there was error by reading the 'ECC Status Register' (refer to section 2.8.26). Error types are divided into 'no error', '1bit correctable error', and '2bit error uncorrectable error'. OneNAND supports 2bit EDC even though 2bit error seldom or never occurs. Hence, it is not recommeded for Host to read 'ECC Status Register' for checking ECC error because the built-in Error Correction Logic of OneNAND automatically corrects ECC error. When the device reads the NAND Flash Array memory main and spare area data with an ECC operation, the device doesn't place the newly generated ECC for main and spare area into the buffer. Instead it places the ECC which was generated and written during the program operation into the buffer. An ECC operation is also done during the Boot Loading operation. 3.13.1 ECC Bypass Operation In an ECC bypass operation, the device does not generate ECC as a background operation. The result does not indicate error position (refer to the ECC Result Table). In a Program Operation the ECC code to NAND Flash Array memory spare area is not updated. During a Load operation, the on-chip ECC engine does not generate a new ECC internally. Also the ECC Status & Result to Registers are invalid. The error is not corrected and detected by itself, so that ECC bypass operation is not recommended for host. ECC bypass operation is set by the 9bit of System Configuration 1 Register (see section 2.8.19) ECC Code and ECC Result by ECC Operation Program operation Operation ECC operation ECC bypass Load operation ECC Status & Result Update to Registers Update Invalid 1bit Error Correct Not correct ECC Code Update to NAND ECC Code at BufferRAM Spare Flash Array Spare Area Area Update Not update Pre-written ECC code(1) loaded Pre-written code(1) loaded NOTE: 1. Pre-written ECC code : ECC code which is previously written to NAND Flash Spare Area in program operation. 84 OneNAND256(KFG5616x1A-xxB6) FLASH MEMORY 3.14 Invalid Block Operation Invalid blocks are defined as blocks in the device's NAND Flash Array memory that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The information regarding the invalid block(s) is called the Invalid Block Information. Devices with invalid block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An invalid block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design must be able to mask out the invalid block(s) via address mapping. The 1st block, which is placed on 00h block address, is always fully guaranteed to be a valid block. Due to invalid marking, during load operation for identifying invalid block, a load error may occur. 3.14.1 Invalid Block Identification Table Operation A system must be able to recognize invalid block(s) based on the original invalid block information and create an invalid block table. Invalid blocks are identified by erasing all address locations in the NAND Flash Array memory except locations where the invalid block(s) information is written prior to shipping. An invalid block(s) status is defined by the 1st word in the spare area. Samsung makes sure that either the 1st or 2nd page of every invalid block has non-FFFFh data at the 1st word of sector0. Since the invalid block information is also erasable in most cases, it is impossible to recover the information once it has been erased. Any intentional erase of the original invalid block information is prohibited. The following suggested flow chart can be used to create an Invalid Block Table. 85 OneNAND256(KFG5616x1A-xxB6) Invalid Block Table Creation Flow Chart FLASH MEMORY Start Set Block Address = 0 Increment Block Address Create (or update) Invalid Block(s) Table No * Check "FFFFh" ? Yes Check "FFFFh" at the 1st word of sector 0 of spare area in 1st and 2nd page No Last Block ? Yes End 3.14.2 Invalid Block Replacement Operation Within its life time, additional invalid blocks may develop with NAND Flash Array memory. Refer to the device's qualification report for the actual data. The following possible failure modes should be considered to implement a highly reliable system. In the case of a status read failure after erase or program, a block replacement should be done. Because program status failure during a page program does not affect the data of the other pages in the same block, a block replacement can be executed with a page-sized buffer by finding an erased empty block and reprogramming the current target data and copying the rest of the replaced block. Block Failure Modes and Countermeasures Failure Mode Erase Failure Program Failure Single Bit Failure in Load Operation Detection and Countermeasure sequence Status Read after Erase --> Block Replacement Status Read after Program --> Block Replacement Error Correction by ECC mode of the device 86 OneNAND256(KFG5616x1A-xxB6) FLASH MEMORY Referring to the diagram for further illustration, when an error happens in the nth page of block 'A' during program operation, copy the data in the 1st ~ (n-1)th page to the same location of block 'B' via data buffer0. Then copy the nth page data of block 'A' in the data buffer1 to the nth page of block 'B' or any free block. Do not further erase or program block 'A' but instead complete the operation by creating an 'Invalid Block Table' or other appropriate scheme. Block Replacement Operation Sequence 1st (n-1)th nth (page) { { Block A 1 an error occurs. 1 Block B 2 Data Buffer0 of the device Data Buffer1 of the device (assuming the nth page data is maintained) 1st (n-1)th nth (page) ∼ ∼ 87 OneNAND256(KFG5616x1A-xxB6) FLASH MEMORY 4.0 4.1 DC CHARACTERISTICS Absolute Maximum Ratings Parameter Vcc Symbol Vcc (for 1.8V) Vcc (for 2.65V/3.3V) VIN (for 1.8V) VIN (for 2.65V/3.3V) Tbias Tstg IOS TA (Extended Temp.) TA (Industrial Temp.) Rating -0.5 to + 2.45 -0.5 to + 4.6 -0.5 to + 2.45 -0.5 to + 4.6 -30 to +125 -40 to +125 -65 to +150 5 -30 to +85 -40 to +85 °C °C mA °C V Unit Voltage on any pin relative to VSS All Pins Temperature Under Bias Storage Temperature Short Circuit Output Current Recommended Operating Temperature Extended Industrial NOTES: 1. Minimum DC voltage is -0.5V on Input/ Output pins. During transitions, this level should not fall to POR level(typ. 1.5V@1.8V device, 1.8V@2.65V/ 3.3V device). Maximum DC voltage is Vcc+0.6V on input / output pins which, during transitions, may overshoot to Vcc+2.0V for periods