KM23V8105D

KM23V8105D(G) 8M-Bit (1Mx8 /512Kx16) CMOS MASK ROM FEATURES • Switchable organization 1,048,576 x 8(byte mode) 524,288 x 16(word mode) • Random access time/Page Access Time 3.3V Operation : 100/30ns(Max.) 3.0V Operation : 120/50ns(Max.) • 4 Words / 8 bytes page access • Supply voltage : single +3.0V/ single +3.3V • Current consumption Operating : 40mA(Max.) Standby : 30µA(Max.) • Fully static operation • All inputs and outputs TTL compatible • Three state outputs • Package -. KM23V8105D : 42-DIP-600 -. KM23V8105DG : 44-SOP-600 CMOS MASK ROM GENERAL DESCRIPTION The KM23V8105D(G) is a fully static mask programmable ROM fabricated using silicon gate CMOS process technology, and is organized either as 1,048,576 x 8 bit(byte mode) or as 524,288 x 16 bit(word mode) depending on BHE voltage level.(See mode selection table) This device includes PAGE read mode function, page read mode allows 4 words(or 8 bytes) of data to read fast in the same page, CE and A2 ~ A18 should not be changed. This device operates with 3.0V or 3.3V power supply, and all inputs and outputs are TTL compatible. Because of its asynchronous operation, it requires no external clock assuring extremely easy operation. It is suitable for use in program memory of microprocessor, and data memory, character generator. The KM23V8105D is packaged in a 42-DIP and the KM23V8105DG in a 44-SOP. FUNCTIONAL BLOCK DIAGRAM A18 . . . . . . . . A2 A0~A1 A-1 X BUFFERS AND DECODER MEMORY CELL MATRIX (524,288x16/ 1,048,576x8) PIN CONFIGURATION A18 A17 A7 1 2 3 4 5 6 7 8 9 42 N.C 41 A8 40 A9 39 A10 38 A11 37 A12 36 A13 35 A14 34 A15 33 A16 32 BHE 31 VSS 30 Q15/A-1 29 Q7 28 Q14 27 Q6 26 Q13 25 Q5 24 Q12 23 Q4 22 VCC N.C 1 A18 A17 A7 A6 A5 A4 A3 A2 2 3 4 5 6 7 8 9 44 N.C 43 N.C 42 A8 41 A9 40 A10 39 A11 38 A12 37 A13 36 A14 35 A15 34 A16 33 BHE 32 VSS 31 Q15/A-1 30 Q7 29 Q14 28 Q6 27 Q13 26 Q5 25 Q12 24 Q4 23 VCC Y BUFFERS AND DECODER SENSE AMP. DATA OUT BUFFERS ... A6 A5 A4 A3 A2 A1 A0 10 CE 11 VSS 12 A1 10 A0 11 CE 12 VSS 13 OE 14 Q0 15 Q8 16 Q1 17 Q9 18 Q2 19 Q10 20 Q3 21 Q11 22 CE OE BHE Pin Name A0 - A1 A2 - A18 Q0 - Q14 Q15 /A-1 BHE CE OE VCC VSS N.C Pin Function Page Address Inputs Address Inputs Data Outputs Output 15(Word mode)/ LSB Address(Byte mode) Word/Byte selection Chip Enable Output Enable Power Ground No Connection CONTROL LOGIC Q0/Q8 Q7/Q15 DIP SOP OE 13 Q0 14 Q8 15 Q1 16 Q9 17 Q2 18 Q10 19 Q3 20 Q11 21 KM23V8105D KM23V8105DG KM23V8105D(G) ABSOLUTE MAXIMUM RATINGS Item Voltage on Any Pin Relative to VSS Temperature Under Bias Storage Temperature Symbol VIN TBIAS TSTG Rating CMOS MASK ROM Unit V °C °C -0.3 to +4.5 -10 to +85 -55 to +150 NOTE : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to th e conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extendd periods may e affect device reliability. RECOMMENDED OPERATING CONDITIONS (Voltage reference to VSS, TA=0 to 70°C) Item Supply Voltage Supply Voltage Symbol VCC VSS Min 2.7/3.0 0 Typ 3.0/3.3 0 Max 3.3/3.6 0 Unit V V DC CHARACTERISTICS Parameter Operating Current Standby Current(TTL) Standby Current(CMOS) Input Leakage Current Output Leakage Current Input High Voltage, All Inputs Input Low Voltage, All Inputs Output High Voltage Level Output Low Voltage Level Symbol ICC ISB1 ISB2 ILI ILO VIH VIL VOH VOL IOH=-400µA IOL=2.1mA Test Conditions CE=OE=VIL, all outputs open CE=VIH, all outputs open CE=VCC, all outputs open VIN=0 to VCC VOUT=0 to VCC Min 2.0 -0.3 2.4 Max 40 500 30 10 10 VCC+0.3 0.6 0.4 Unit mA µA µA µA µA V V V V NOTE : Minimum DC Voltage(VIL) is -0.3V an input pins. During transitions, this level may undershoot to -2.0V for periods