KM416C4000C

KM416C4000C, KM416C4100C CMOS DRAM 4M x 16bit CMOS Dynamic RAM with Fast Page Mode DESCRIPTION This is a family of 4,194,304 x 16 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time ( -5 or -6) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. This 4Mx16 Fast Page Mode DRAM family is fabricated using Samsung′s advanced CMOS process to realize high band-width, low power consumption and high reliability. FEATURES • Part Identification - KM416C4000C(5.0V, 8K Ref.) - KM416C4100C(5.0V, 4K Ref.) • Active Power Dissipation Unit : mW Speed -5 -6 8K 495 440 4K 660 605 • Fast Page Mode operation • 2CAS Byte/Word Read/Write operation • CAS-before-RAS refresh capability • RAS-only and Hidden refresh capability • Fast parallel test mode capability • TTL(5.0V) compatible inputs and outputs • Early Write or output enable controlled write • JEDEC Standard pinout • Available in Plastic TSOP(II) package • +5.0V±10% power supply • Refresh Cycles Part NO. KM416C4000C* KM416C4100C Refresh cycle 8K 4K Refresh time Normal 64ms RAS UCAS LCAS W Control Clocks Vcc Vss Lower Data in Buffer Sense Amps & I/O Lower Data out Buffer Upper Data in Buffer Upper Data out Buffer FUNCTIONAL BLOCK DIAGRAM VBB Generator * Access mode & RAS only refresh mode : 8K cycle/64ms CAS-before-RAS & Hidden refresh mode : 4K cycle/64ms Refresh Timer Refresh Control Row Decoder DQ0 to DQ7 • Performance Range Speed -5 -6 Refresh Counter Memory Array 4,194,304 x 16 Cells OE DQ8 to DQ15 tRAC 50ns 60ns tCAC 13ns 15ns tRC 90ns 110ns tPC 35ns 40ns A0~A12 (A0~A11)*1 A0~A8 (A0~A9)*1 Row Address Buffer Col. Address Buffer Column Decoder Note) *1 : 4K Refresh SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. KM416C4000C, KM416C4100C CMOS DRAM PIN CONFIGURATION (Top Views) • KM416C40(1)00CS VCC DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 N.C VCC W RAS N.C N.C N.C N.C A0 A1 A2 A3 A4 A5 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 VSS DQ15 DQ14 DQ13 DQ12 VSS DQ11 DQ10 DQ9 DQ8 N.C VSS LCAS UCAS OE N.C N.C A12(N.C)* A11 A10 A9 A8 A7 A6 VSS (400mil TSOP(II)) *(N.C) : N.C for 4K Refresh Product Pin Name A0 - A12 A0 - A11 DQ0 - 15 VSS RAS UCAS LCAS W OE VCC N.C Pin function Address Inputs(8K Product) Address Inputs(4K Product) Data In/Out Ground Row Address Strobe Upper Column Address Strobe Lower Column Address Strobe Read/Write Input Data Output Enable Power(+5.0V) No Connection KM416C4000C, KM416C4100C ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to VSS Voltage on VCC supply relative to VSS Storage Temperature Power Dissipation Short Circuit Output Current Symbol VIN,VOUT VCC Tstg PD IOS Address Rating -1.0 to +7.0 -1.0 to +7.0 -55 to +150 1 50 CMOS DRAM Units V V °C W mA * Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA= 0 to 70°C) Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min 4.5 0 2.6 -1.0 *2 Typ 5.0 0 Max 5.5 0 VCC+1.0 0.7 *1 Units V V V V *1 : VCC+2.0V at pulse width≤20ns which is measured at VCC *2 : -2.0 at pulse width≤20ns which is measured at VSS DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.) Parameter Input Leakage Current (Any input 0≤VIN≤VCC+0.5V, all other pins not under test=0 Volt) Output Leakage Current (Data out is disabled, 0V≤VOUT≤VCC) Output High Voltage Level(IOH=-5mA) Output Low Voltage Level(IOL=4.2mA) Symbol II(L) IO(L) VOH VOL Min -5 -5 2.4 Max 5 5 0.4 Units uA uA V V KM416C4000C, KM416C4100C DC AND OPERATING CHARACTERISTICS (Continued) Max Symbol Power Don′t care Normal Don′t care Don′t care Normal Don′t care Speed KM416C4000C ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 -5 -6 Don′t care -5 -6 -5 -6 Don′t care -5 -6 90 80 2 90 80 60 50 1 120 110 KM416C4100C 120 110 2 120 110 70 60 1 120 110 CMOS DRAM Units mA mA mA mA mA mA mA mA mA mA ICC1* : Operating Current (RAS and UCAS, LCAS, Address cycling @tRC=min.) ICC2 : Standby Current (RAS=UCAS=LCAS=W=VIH) ICC3* : RAS-only Refresh Current (UCAS=LCAS=VIH, RAS, Address cycling @tRC=min.) ICC4* : Fast Page Mode Current (RAS=VIL, UCAS or LCAS, Address cycling @tPC=min.) ICC5 : Standby Current (RAS=UCAS=LCAS=W=VCC-0.2V) ICC6* : CAS-Before-RAS Refresh Current (RAS and UCAS or LCAS cycling @tRC=min) *Note : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1, ICC3 and ICC6, address can be changed maximum once while RAS=VIL. In ICC4, address can be changed maximum once within one fast page mode cycle time, tPC. KM416C4000C, KM416C4100C CAPACITANCE (TA=25°C, VCC=5.0V, f=1MHz) Parameter Input capacitance [A0 ~ A12] Input capacitance [RAS, UCAS, LCAS, W, OE] Output capacitance [DQ0 - DQ15] Symbol CIN1 CIN2 CDQ Min - CMOS DRAM Max 5 7 7 Units pF pF pF AC CHARACTERISTICS (0°C≤TA≤70°C, See note 1,2) Test condition : VCC=5.0V±10%, Vih/Vil=2.6/0.7V, Voh/Vol=2.4/0.6V Parameter Random read or write cycle time Read-modify-write cycle time Access time from RAS Access time from CAS Access time from column address CAS to output in Low-Z Output buffer turn-off delay Transition time (rise and fall) RAS precharge time RAS pulse width RAS hold time CAS hold time CAS pulse width RAS to CAS delay time RAS to column address delay time CAS to RAS precharge time Row address set-up time Row address hold time Column address set-up time Column address hold time Column address to RAS lead time Read command set-up time Read command hold time referenced to CAS Read command hold time referenced to RAS Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data set-up time Data hold time Symbol Min -5 Max Min 110 153 50 13 25 0 0 1 30 50 13 50 13 20 15 5 0 10 0 10 25 0 0 0 10 10 15 13 0 10 10K 37 25 10K 13 50 0 0 1 40 60 15 60 15 20 15 5 0 10 0 10 30 0 0 0 10 10 15 15 0 10 10K 45 30 10K 13 50 60 15 30 -6 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 16 9,19 9,19 8 8 13 13 4 10 3,4,10 3,4,5 3,10 3 6 2 Units Note tRC tRWC tRAC tCAC tAA tCLZ tOFF tT tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCH tWP tRWL tCWL tDS tDH 90 133 KM416C4000C, KM416C4100C AC CHARACTERISTICS (Continued) Parameter Refresh period (4K, Normal) Refresh period (8K, Normal) Write command set-up time CAS to W delay time RAS to W delay time Column address to W delay time CAS precharge W delay time CAS set-up time (CAS -before-RAS refresh) CAS hold time (CAS -before-RAS refresh) RAS to CAS precharge time Access time from CAS precharge Fast Page mode cycle time Fast Page mode read-modify-write cycle time CAS precharge time (Fast Page cycle) RAS pulse width (Fast Page cycle) RAS hold time from CAS precharge OE access time OE to data delay Output buffer turn off delay time from OE OE command hold time Write command set-up time (Test mode in) Write command hold time (Test mode in) W to RAS precharge time (C-B-R refresh) W to RAS hold time (C-B-R refresh) RAS pulse width (C-B-R self refresh) RAS precharge time (C-B-R self refresh) CAS hold time (C-B-R self refresh) Symbol Min -5 Max 64 64 0 36 73 48 53 5 10 5 30 35 76 10 50 30 13 13 0 13 10 15 10 10 100 90 -50 13 13 0 15 10 15 10 10 100 110 -50 200K 40 85 10 60 35 0 38 83 53 60 5 10 5 Min -6 CMOS DRAM Units Max 64 64 ms ms ns ns ns ns ns ns ns ns 35 ns ns ns ns 200K ns ns 15 ns ns 13 ns ns ns ns ns ns us ns ns Note tREF tREF tWCS tCWD tRWD tAWD tCPWD tCSR tCHR tRPC tCPA tPC tPRWC tCP tRASP tRHCP tOEA tOED tOEZ tOEH tWTS tWTH tWRP tWRH tRASS tRPS tCHS 7 7,15 7 7 17 18 3 14 6 11 11 20,21,22 20,21,22 20,21,22 KM416C4000C, KM416C4100C TEST MODE CYCLE Parameter Random read or write cycle time Read-modify-write cycle time Access time from RAS Access time from CAS Access time from column address RAS pulse width CAS pulse width RAS hold time CAS hold time Column Address to RAS lead time CAS to W delay time RAS to W delay time Column Address to W delay time Fast Page mode cycle time Fast Page mode read-modify-write cycle time RAS pulse width (Fast Page cycle) Access time from CAS precharge OE access time OE to data delay OE command hold time Symbol Min -5 Max Min 115 160 55 18 30 55 18 18 55 30 41 78 53 40 81 55 200K 35 18 18 18 18 20 10K 10K 65 20 20 65 35 43 88 58 45 90 65 200K 40 20 65 20 35 10K 10K -6 Max CMOS DRAM ( Note 11 ) Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 3 7 7 7 3,4,10,12 3,4,5,12 3,10,12 Note tRC tRWC tRAC tCAC tAA tRAS tCAS tRSH tCSH tRAL tCWD tRWD tAWD tPC tPRWC tRASP tCPA tOEA tOED tOEH 95 138 KM416C4000C, KM416C4100C NOTES CMOS DRAM 1. An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles before proper device operation is achieved. 2. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and VIL(max) and are assumed to be 5ns for all inputs. 3. Measured with a load equivalent to 2 TTL load and 100pF. 4. Operation within the tRCD(max) limit insures that tRAC(max) can be met, tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. 5. Assumes that tRCD≥tRCD(max). 6. tOFF(min)and tOEZ(max) define the time at which the output achieves the open circuit condition and are not referenced Voh or Vol. 7. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS≥tWCS(min), the cycle is an early write cycle and the data output will remain high impedance for the duration of the cycle. If tCWD≥tCWD(min), tRWD≥tRWD(min) and tAWD≥tAWD(min), then the cycle is a read-modify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the condition of the data out is indeterminate. 8. Either tRCH or tRRH must be satisfied for a read cycle. 9. These parameters are referenced to CAS falling edge in early write cycles and to W falling edge in read-modify-write cycles. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only. 10. If tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA. These specifications are applied in the test mode. 11. In test mode read cycle, the value of tRAC, tAA, tCAC is delayed by 2ns to 5ns for the specified values. These parameters 12. should be specified in test mode cycles by adding the above value to the specified value in this data sheet. KM416C40(1)00C Truth Table RAS H L L L L L L L L LCAS X H L H L L H L L UCAS X H H L L H L L L W X X H H H L L L H OE X X L L L H H H H DQ0 - DQ7 Hi-Z Hi-Z DQ-OUT Hi-Z DQ-OUT DQ-IN DQ-IN Hi-Z DQ8-DQ15 Hi-Z Hi-Z Hi-Z DQ-OUT DQ-OUT DQ-IN DQ-IN Hi-Z STATE Standby Refresh Byte Read Byte Read Word Read Byte Write Byte Write Word Write - KM416C4000C, KM416C4100C 13. tASC, tCAH are referenced to the earlier CAS falling edge. CMOS DRAM 14. tCP is specified from the later CAS rising edge in the previous cycle to the earlier CAS falling edge in the next cycle. 15. tCWD is referenced to the later CAS falling edge at word read-modify-write cycle. 16. tCWL is specified from W falling edge to the earlier CAS rising edge. 17. tCSR is referenced to the earlier CAS falling edge before RAS transition low. 18. tCHR is referenced to the later CAS rising edge after RAS transition low. RAS LCAS UCAS tCSR tCHR 19. tDS is specified for the earlier CAS falling edge and tDH is specified by the later CAS falling edge. LCAS UCAS tDS DQ0 ~ DQ15 Din tDH 20. If tRASS≥100us, then RAS precharge time must use tRPS instead of tRP. 21. For RAS-only refresh and burst CAS-before-RAS refresh mode, 4096(4K/8K) cycles of burst refresh must be executed within 64ms before and after self refresh, in order to meet refresh specification. 22. For distributed CAS-before-RAS with 15.6us interval CAS-before-RAS refresh should be executed with in 15.6us immediately before and after self refresh in order to meet refresh specification. KM416C4000C, KM416C4100C WORD READ CYCLE CMOS DRAM tRC tRAS RAS VIH VIL - tRP tCRP UCAS VIH VIL - tCSH tRCD tRSH tCAS tCRP tCRP LCAS VIH VIL - tCSH tRCD tRSH tCAS tRAL tCAH COLUMN ADDRESS tCRP tRAD tASR A VIH VIL - tRAH tASC ROW ADDRESS tRCS W VIH VIL - tRCH tRRH tAA OE VIH VIL - tOEA tCAC tCLZ tOFF tOEZ DATA-OUT DQ0 ~ DQ7 VOH VOL DQ8 ~ DQ15 VOH VOL - tRAC OPEN tCAC tRAC OPEN tCLZ tOEZ DATA-OUT tOFF Don′t care Undefined KM416C4000C, KM416C4100C LOWER BYTE READ CYCLE NOTE : DIN = OPEN CMOS DRAM tRC tRAS RAS VIH VIL - tRP tCRP UCAS VIH VIL - tRPC tCRP LCAS VIH VIL - tCSH tRCD tRAD tRSH tCAS tRAL tCAH COLUMN ADDRESS tASR A VIH VIL - tRAH tASC ROW ADDRESS tRCS W VIH VIL - tRCH tRRH tOFF tAA tOEZ tOEA tCAC tCLZ DATA-OUT OE VIH VIL - DQ0 ~ DQ7 VOH VOL DQ8 ~ DQ15 VOH VOL - tRAC OPEN OPEN Don′t care Undefined KM416C4000C, KM416C4100C UPPER BYTE READ CYCLE NOTE : DIN = OPEN CMOS DRAM tRC tRAS RAS VIH VIL - tRP tCRP UCAS VIH VIL - tCSH tRCD tRSH tCAS tRPC tCRP tCRP LCAS VIH VIL - tRAD tRAL tASR tRAH tASC tCAH COLUMN ADDRESS A VIH VIL - ROW ADDRESS tRCS W VIH VIL - tRCH tRRH tOFF tAA tOEZ tOEA OE VIH VIL - DQ0 ~ DQ7 VOH VOL DQ8 ~ DQ15 VOH VOL - OPEN tCAC tRAC OPEN tCLZ DATA-OUT Don′t care Undefined KM416C4000C, KM416C4100C WORD WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN CMOS DRAM tRAS RAS VIH VIL - tRC tRP tCRP UCAS VIH VIL - tCSH tRCD tRSH tCAS tCRP tCRP LCAS VIH VIL - tCSH tRCD tRSH tCAS tRAD tCRP tASR A VIH VIL - tRAH tASC tRAL tCAH COLUMN ADDRESS ROW ADDRESS tWCS W VIH VIL - tWCH tWP OE VIH VIL - DQ0 ~ DQ7 VIH VIL - tDS tDH DATA-IN DQ8 ~ DQ15 VIH VIL - tDS tDH DATA-IN Don′t care Undefined KM416C4000C, KM416C4100C LOWER BYTE WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN CMOS DRAM tRC tRAS RAS VIH VIL - tRP tCRP UCAS VIH VIL - tRPC tCRP LCAS VIH VIL - tCSH tRCD tRSH tCAS tRAD tCRP tASR A VIH VIL - tRAH tASC tRAL tCAH COLUMN ADDRESS ROW ADDRESS tWCS W VIH VIL - tWCH tWP OE VIH VIL - DQ0 ~ DQ7 VIH VIL - tDS tDH DATA-IN DQ8 ~ DQ15 VIH VIL - Don′t care Undefined KM416C4000C, KM416C4100C UPPER BYTE WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN CMOS DRAM tRAS RAS VIH VIL - tRC tRP tCRP UCAS VIH VIL - tCSH tRCD tRSH tCAS tCRP tCRP LCAS VIH VIL - tRPC tRAD tASR A VIH VIL - tRAH tASC tRAL tCAH COLUMN ADDRESS ROW ADDRESS tWCS W VIH VIL - tWCH tWP OE VIH VIL - DQ0 ~ DQ7 VIH VIL - DQ8 ~ DQ15 VIH VIL - tDS tDH DATA-IN Don′t care Undefined KM416C4000C, KM416C4100C WORD WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : DOUT = OPEN CMOS DRAM tRAS RAS VIH VIL - tRC tRP tCRP UCAS VIH VIL - tCSH tRCD tRSH tCAS tCRP tCRP LCAS VIH VIL - tCSH tRCD tRSH tCAS tRAD tCRP tASR A VIH VIL - tRAH tASC tRAL tCAH COLUMN ADDRESS ROW ADDRESS tCWL tRWL W VIH VIL - tWP OE VIH VIL - tOED tDS tOEH tDH DATA-IN DQ0 ~ DQ7 VIH VIL - DQ8 ~ DQ15 VIH VIL - tDS tDH DATA-IN Don′t care Undefined KM416C4000C, KM416C4100C LOWER BYTE WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : DOUT = OPEN CMOS DRAM tRAS RAS VIH VIL - tRC tRP tCRP UCAS VIH VIL - tRPC tCRP LCAS VIH VIL - tCSH tRCD tRSH tCAS tRAD tCRP tASR A VIH VIL - tRAH tASC tRAL tCAH COLUMN ADDRESS ROW ADDRESS tCWL tRWL W VIH VIL - tWP OE VIH VIL - tOED tDS tOEH tDH DATA-IN DQ0 ~ DQ7 VIH VIL - DQ8 ~ DQ15 VIH VIL - Don′t care Undefined KM416C4000C, KM416C4100C UPPER BYTE WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : DOUT = OPEN CMOS DRAM tRC tRAS RAS VIH VIL - tRP tCRP UCAS VIH VIL - tCSH tRCD tRSH tCAS tCRP tCRP LCAS VIH VIL - tRPC tRAD tASR A VIH VIL - tRAH tASC tRAL tCAH COLUMN ADDRESS ROW ADDRESS tCWL W VIH VIL - tRWL tWP OE VIH VIL - tOED tOEH DQ0 ~ DQ7 VIH VIL - DQ8 ~ DQ15 VIH VIL - tDS tDH DATA-IN Don′t care Undefined KM416C4000C, KM416C4100C WORD READ - MODIFY - WRITE CYCLE CMOS DRAM tRWC tRAS RAS VIH VIL - tRP tCRP UCAS VIH VIL - tRCD tRSH tCAS tCRP LCAS VIH VIL - tRCD tRAD tRSH tCAS tCSH tASR A VIH VIL - tRAH tASC tCAH ROW ADDR COLUMN ADDRESS tAWD tCWD W VIH VIL VIH VIL - tRWL tCWL tWP tRWD tOEA tCLZ tCAC tAA tOED tOEZ VALID DATA-OUT OE DQ0 ~ DQ7 VI/OH VI/OL - tRAC tCLZ tCAC tAA tRAC tDS tDH VALID DATA-IN DQ8 ~ DQ15 VI/OH VI/OL - tOED tOEZ VALID DATA-OUT tDS tDH VALID DATA-IN Don′t care Undefined KM416C4000C, KM416C4100C LOWER-BYTE READ - MODIFY - WRITE CYCLE CMOS DRAM tRWC tRAS RAS VIH VIL - tRP tCRP UCAS VIH VIL - tRPC tCRP LCAS VIH VIL - tRCD tRAD tRSH tCAS tCSH tASR A VIH VIL - tRAH tASC tCAH ROW ADDR COLUMN ADDRESS tAWD tCWD W VIH VIL VIH VIL - tRWL tCWL tWP tRWD tOEA tCLZ tCAC tAA tOED tOEZ VALID DATA-OUT OE DQ0 ~ DQ7 VI/OH VI/OL DQ8 ~ DQ15 VI/OH VI/OL - tRAC tDS tDH VALID DATA-IN OPEN Don′t care Undefined KM416C4000C, KM416C4100C UPPER-BYTE READ - MODIFY - WRITE CYCLE CMOS DRAM tRWC tRAS RAS VIH VIL - tRP tCRP UCAS VIH VIL - tRCD tRSH tCAS tCRP LCAS VIH VIL - tRPC tRAD tASR tRAH tASC tCAH tCSH A VIH VIL - ROW ADDR COLUMN ADDRESS tAWD tCWD W VIH VIL VIH VIL - tRWL tCWL tWP tRWD tOEA OE DQ0 ~ DQ7 VI/OH VI/OL - OPEN tCLZ tCAC tAA tRAC tOED tOEZ VALID DATA-OUT DQ8 ~ DQ15 VI/OH VI/OL - tDS tDH VALID DATA-IN Don′t care Undefined KM416C4000C, KM416C4100C FAST PAGE MODE WORD READ CYCLE CMOS DRAM tRASP RAS VIH VIL ¡ó tRP tCSH tCRP UCAS VIH VIL - tRHCP tPC tCP tPC tCAS tCP tPC tCAS tCP tCAS tRAL tRPC tRCD tCAS tCRP LCAS VIH VIL - tRCD tRAD tRAH tASC tCP tCAS tCAS tCP tCAS tCP tCAS tRPC tASR A VIH VIL - tCAH tASC tCAH tASC tCAH COLUMN ADDR tASC tCAH ROW ADDR COLUMN ADDRESS COLUMN ADDRESS COLUMN ADDRESS tRCS W VIH VIL - tRCH tRCS tRCH tRCS tRCH tRCS tRCH tRRH tCAC tAA tAA tOEA tCPA tOEA tAA tCPA tOEA tCAC tAA tCPA tOEA tCAC OE VIH VIL - tCAC DQ0 ~ DQ7 VOH VOL - tOFF tOEZ VALID DATA-OUT VALID DATA-OUT tOFF tOEZ VALID DATA-OUT tOFF tOEZ VALID DATA-OUT tOFF tOEZ tRAC tCLZ tCAC DQ8 ~ DQ15 VOH VOL - tRAC VALID DATA-OUT tOFF tOEZ VALID DATA-OUT tOFF tOEZ VALID DATA-OUT tOFF tOEZ VALID DATA-OUT tOFF tOEZ tCLZ Don′t care Undefined KM416C4000C, KM416C4100C FAST PAGE MODE LOWER BYTE READ CYCLE CMOS DRAM tRASP RAS VIH VIL ¡ó tRP tRHCP tCRP UCAS VIH VIL - tRPC tCSH tRAL tPC tRCD tCAS tRAD tRAH tASC tCAH COLUMN ADDRESS tCRP LCAS VIH VIL - tCP tPC tCAS tCP tPC tCAS tCP tCAS tRPC tASR A VIH VIL - tASC tCAH COLUMN ADDRESS tASC tCAH COLUMN ADDR tASC tCAH ROW ADDR COLUMN ADDRESS tRCS W VIH VIL - tRCS tRCH tRCH tRCS tRCH tRCS tRCH tRRH tCAC tAA VIH VIL - tCAC tAA tCPA tOEA tAA tCPA tOEA tCAC tAA tOEA tCPA tOEA OE DQ0 ~ DQ7 VOH VOL - tCAC tRAC VALID DATA-OUT tOFF tOEZ VALID DATA-OUT tOFF tOEZ VALID DATA-OUT tOFF tOEZ VALID DATA-OUT tOFF tOEZ tCLZ DQ8 ~ DQ15 VOH VOL - OPEN Don′t care Undefined KM416C4000C, KM416C4100C FAST PAGE MODE UPPER BYTE READ CYCLE CMOS DRAM tRASP RAS VIH VIL ¡ó tRP tCSH tCRP UCAS VIH VIL - tRHCP tPC tCP tPC tCAS tCP tPC tCAS tCP tCAS tRPC tCAS tRCD tCRP LCAS VIH VIL - tRPC tRAL tRAD tASR A VIH VIL - tRAH tASC tCAH tASC tCAH tASC tCAH COLUMN ADDR tASC tCAH ROW ADDR COLUMN ADDRESS COLUMN ADDRESS COLUMN ADDRESS tRCS W VIH VIL - tRCS tRCH tRCH tRCS tRCH tRCS tRCH tRRH tCAC tAA tAA tOEA tCPA tOEA tAA tCPA tOEA tCAC tAA tCPA tOEA tCAC OE VIH VIL - DQ0 ~ DQ7 VOH VOL - OPEN DQ8 ~ DQ15 VOH VOL - tCAC tRAC VALID DATA-OUT tOFF tOEZ VALID DATA-OUT tOFF tOEZ VALID DATA-OUT tOFF tOEZ VALID DATA-OUT tOFF tOEZ tCLZ Don′t care Undefined KM416C4000C, KM416C4100C FAST PAGE MODE WORD WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN CMOS DRAM tRASP RAS VIH VIL ¡ó tRP tRHCP tCRP UCAS VIH VIL - tPC tRCD tCAS tPC tRCD tCAS tRAD tCSH tCP tCAS ¡ó tPC tCP tCAS ¡ó tRSH tCP tCAS tCRP tCRP LCAS VIH VIL - tPC tCP tRSH tCAS tRAL tASR A VIH VIL - tRAH tASC tCAH tASC tCAH ¡ó ¡ó tASC tCAH ROW ADDR COLUMN ADDRESS COLUMN ADDRESS COLUMN ADDRESS tWCS W VIH VIL - tWCH tWCS tWCH tWP ¡ó tWCS tWCH tWP tWP OE VIH VIL - ¡ó ¡ó DQ0 ~ DQ7 VIH VIL - tDS tDH VALID DATA-IN tDS tDH ¡ó VALID DATA-IN tDS tDH ¡ó VALID DATA-IN DQ8 ~ DQ15 VIH VIL - tDS tDH VALID DATA-IN tDS tDH ¡ó VALID DATA-IN tDS tDH ¡ó VALID DATA-IN Don′t care Undefined KM416C4000C, KM416C4100C FAST PAGE MODE LOWER BYTE WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN CMOS DRAM tRASP RAS VIH VIL ¡ó tRP tRHCP tCRP UCAS VIH VIL ¡ó tRPC tCRP LCAS VIH VIL - tPC tRCD tCAS tRAD tCSH tCP tCAS ¡ó tPC tCP tRSH tCAS tRAL tASR A VIH VIL - tRAH tASC tCAH tASC tCAH ¡ó ¡ó tASC tCAH ROW ADDR COLUMN ADDRESS COLUMN ADDRESS COLUMN ADDRESS tWCS W VIH VIL - tWCH tWCS tWCH tWP ¡ó tWCS tWCH tWP tWP OE VIH VIL - ¡ó ¡ó DQ0 ~ DQ7 VIH VIL - tDS tDH VALID DATA-IN tDS tDH ¡ó VALID DATA-IN tDS tDH VALID DATA-IN ¡ó DQ8 ~ DQ15 VIH VIL - Don′t care Undefined KM416C4000C, KM416C4100C FAST PAGE MODE UPPER BYTE WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN CMOS DRAM tRASP RAS VIH VIL ¡ó tRP tRHCP tCRP UCAS VIH VIL - tPC tRCD tCAS tCP tCAS ¡ó tPC tCP tRSH tCAS tRPC tCRP LCAS VIH VIL - tRAD tCSH tASR A VIH VIL - tRAL tCAH tASC tCAH ¡ó ¡ó tRAH tASC tASC tCAH ROW ADDR. COLUMN ADDRESS COLUMN ADDRESS COLUMN ADDRESS tWCS W VIH VIL - tWCH tWCS tWCH tWP ¡ó tWCS tWCH tWP tWP OE VIH VIL - ¡ó ¡ó DQ0 ~ DQ7 VIH VIL - ¡ó ¡ó DQ8 ~ DQ15 VIH VIL - tDS tDH VALID DATA-IN tDS tDH ¡ó VALID DATA-IN tDS tDH ¡ó VALID DATA-IN Don′t care Undefined KM416C4000C, KM416C4100C FAST PAGE MODE WORD READ-MODIFY-WRITE CYCLE CMOS DRAM tRASP RAS VIH VIL - tRP tCSH tCRP tPRWC tRCD tCAS tCRP tRCD tCAS tRAD tRAH tASR tCAH tASC COL. ADDR tRSH tCP tCAS tCP tCAS tRAL tCAH tASC COL. ADDR tCRP UCAS VIH VIL - tCRP LCAS VIH VIL - A VIH VIL - ROW ADDR tRCS tCWL W VIH VIL - tRCS tWP tCWD tAWD tCPWD tOEA tRWL tCWL tWP tCWD tAWD tRWD tOEA tOED tCAC tAA tOEZ tDH tDS OE VIH VIL - tCAC tAA tOED tDH tDS tOEZ DQ0 ~ DQ7 VI/OH VI/OL - tRAC tCLZ tCLZ VALID DATA-OUT VALID DATA-IN VALID DATA-OUT VALID DATA-IN tOED tCAC tAA DQ8 ~ DQ15 VI/OH VI/OL - tCAC tDH tDS tAA tOED tDH tDS tOEZ tOEZ tRAC tCLZ tCLZ VALID DATA-OUT VALID DATA-IN VALID DATA-OUT VALID DATA-IN Don′t care Undefined KM416C4000C, KM416C4100C FAST PAGE MODE LOWER BYTE READ - MODIFY - WRITE CYCLE CMOS DRAM tRASP RAS VIH VIL - tRP tCSH tCRP tRPC UCAS VIH VIL - tCRP LCAS VIH VIL - tRCD tPRWC tCAS tCP tRSH tCAS tCRP tRAD tRAH tASR A VIH VIL ROW ADDR tCAH tASC COL. ADDR tRAL tASC COL. ADDR tCAH tRCS W VIH VIL - tCWL tWP tCWD tAWD tRWD tOEA tOED tCAC tAA tOEZ tDH tDS tRCS tCWD tAWD tCPWD tOEA tCAC tAA tOED tRWL tCWL tWP OE VIH VIL - tDH tDS tOEZ DQ0 ~ DQ7 VI/OH VI/OL - tRAC tCLZ tCLZ VALID DATA-OUT VALID DATA-IN VALID DATA-OUT VALID DATA-IN DQ8 ~ DQ15 VI/OH VI/OL - OPEN Don′t care Undefined KM416C4000C, KM416C4100C FAST PAGE MODE UPPER BYTE READ - MODIFY - WRITE CYCLE CMOS DRAM tRASP RAS VIH VIL - tRP tCSH tCRP tPRWC tCAS tCRP tRSH tCAS tRPC tRCD tCP tCRP UCAS VIH VIL VIH VIL - LCAS tRAD tRAH tASR A VIH VIL ROW ADDR tCAH tASC COL. ADDR tRAL tASC COL. ADDR tCAH tRCS W VIH VIL - tCWL tWP tCWD tAWD tRWD tOEA tRCS tCWD tAWD tCPWD tOEA tRWL tCWL tWP OE VIH VIL - DQ0 ~ DQ7 VI/OH VI/OL - OPEN tOED tCAC tAA tDH tOEZ tDS tCAC tAA tDH tOEZ tDS tOED DQ8 ~ DQ15 VI/OH VI/OL - tRAC tCLZ tCLZ VALID DATA-OUT VALID DATA-IN VALID DATA-OUT VALID DATA-IN Don′t care Undefined KM416C4000C, KM416C4100C RAS - ONLY REFRESH CYCLE NOTE : W, OE , DIN = Don′t care DOUT = OPEN tRC RAS VIH VIL - CMOS DRAM tRP tRPC tRAS tCRP UCAS VIH VIL - tCRP LCAS VIH VIL - tASR A VIH VIL - tRAH ROW ADDR CAS - BEFORE - RAS REFRESH CYCLE NOTE : OE , A = Don′t care tRP RAS VIH VIL - tRC tRAS tRPC tCSR tCHR tRP tCRP tCP UCAS VIH VIL - tCP LCAS VIH VIL - tCSR tCHR DQ0 ~ DQ7 VOH VOL DQ8 ~ DQ15 VOH VOL W VIH VIL - tOFF OPEN OPEN tWRP tWRH Don′t care Undefined KM416C4000C, KM416C4100C HIDDEN REFRESH CYCLE ( READ ) CMOS DRAM tRC RAS VIH VIL - tRP tRC tRAS tRP tRAS tCRP UCAS VIH VIL - tRCD tRSH tCHR tCRP LCAS VIH VIL - tRCD tRAD tRSH tCHR tRAL tASC tCAH COLUMN ADDRESS tASR A VIH VIL - tRAH ROW ADDRESS tRCS W VIH VIL - tWRH tAA OE VIH VIL - tOEA tOFF tCAC tCLZ DQ0 ~ DQ7 VOH VOL - tRAC OPEN tOEZ DATA-OUT DQ8 ~ DQ15 VOH VOL - OPEN DATA-IN DATA-OUT Don′t care Undefined KM416C4000C, KM416C4100C HIDDEN REFRESH CYCLE ( WRITE ) NOTE : DOUT = OPEN CMOS DRAM tRC RAS VIH VIL - tRP tRC tRAS tRP tRAS tCRP UCAS VIH VIL - tRCD tRSH tCHR tCRP LCAS VIH VIL - tRCD tRSH tCHR tRAD tASR A VIH VIL - tRAH tASC tRAL tCAH COLUMN ADDRESS ROW ADDRESS tWRH W VIH VIL - tWCS tWP tWRP tWCH OE VIH VIL - DQ0 ~ DQ7 VIH VIL DQ8 ~ DQ15 VIH VIL - tDS tDH DATA-IN tDS tDH DATA-IN Don′t care Undefined KM416C4000C, KM416C4100C CAS - BEFORE - RAS SELF REFRESH CYCLE NOTE : OE , A = Don′t care tRP RAS VIH VIL - CMOS DRAM tRASS tRPS tRPC tCP tCSR tCHS tRPC UCAS VIH VIL - tCP LCAS VIH VIL - tCSR tCHS DQ0 ~ DQ7 VOH VOL DQ8 ~ DQ15 VOH VOL W VIH VIL - tOFF OPEN OPEN tWRP tWRH TEST MODE IN CYCLE NOTE : OE , A = Don′t care tRP RAS VIH VIL - tRC tRAS tRP tCRP tCP UCAS VIH VIL - tRPC tCSR tCHR tCP LCAS VIH VIL - tCSR tCHR W VIH VIL - tWTS tOFF tWTH DQ0 ~ DQ15 VOH VOL - OPEN Don′t care Undefined KM416C4000C, KM416C4100C PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(II) 50 TSOP(II) 400mil CMOS DRAM Units : Inches (millimeters) 0.455 (11.56) 0.471 (11.96) 0.400 (10.16) 0.004 (0.10) 0.010 (0.25) 0.841 (21.35) MAX 0.821 (20.85) 0.829 (21.05) 0.047 (1.20) MAX 0.010 (0.25) TYP 0.018 (0.45) 0.030 (0.75) 0~8 O 0.034 (0.875) 0.0315 (0.80) 0.002 (0.05) MIN 0.010 (0.25) 0.018 (0.45)