KM416V254D

KM416C254D, KM416V254D CMOS DRAM 256K x 16Bit CMOS Dynamic RAM with Extended Data Out DESCRIPTION This is a family of 262,144 x 16 bit Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random access of memory cells within the same row. Power supply voltage(+5.0V or +3.3V), Access time (-5,-6 or -7), power consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS-before-RAS refresh, RASonly refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 256Kx16 EDO Mode DRAM family is fabricated using Samsung′s advanced CMOS process to realize high band-width, low power consumption and high reliability. It may be used as graphic memory unit for microcomputer, personal computer and portable machines. • Extended Data Out Mode operation FEATURES • Part Identification - KM416C254D/DL (5V, 512 Ref.) - KM416V254D/DL (3.3V, 512 Ref.) • 2 CAS Byte/Wrod Read/Write operation • CAS-before-RAS refresh capability • RAS-only and Hidden refresh capability • Self-refresh capability (L-ver only) • TTL(5V)/LVTTL(3.3V) compatible inputs and outputs • Early Write or output enable controlled write • JEDEC Standard pinout • Available in 40-pin SOJ 400mil and 44(40)-pin packages • Triple +5V±10% power supply (5V product) • Triple +3.3V±0.3V power supply (3.3V product) • Active Power Dissipation Speed -5 -6 -7 • Refresh Cycles Part NO. C254D V254D VCC 5V 3.3V Refresh cycle 512 3.3V(512 Ref.) 255 235 Unit : mW 5V(512 Ref.) 605 495 440 FUNCTIONAL BLOCK DIAGRAM Refresh period Normal 8ms L-ver 128ms RAS UCAS LCAS W Control Clocks VBB Generator Vcc Vss Lower Data in Buffer Sense Amps & I/O Lower Data out Buffer Upper Data in Buffer Upper Data out Buffer Refresh Timer Row Decoder • Performance Range Refresh Control DQ0 to DQ7 Speed -5 -6 -7 tRAC 50ns 60ns 70ns tCAC 15ns 15ns 20ns tRC 84ns 104ns 124ns tHPC 20ns 25ns 30ns Remark 5V only 5V/3.3V 5V/3.3V A0~A8 Col. Address Buffer Refresh Counter Row Address Buffer Memory Array 262,144 x16 Cells OE Column Decoder DQ8 to DQ15 SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. KM416C254D, KM416V254D CMOS DRAM PIN CONFIGURATION (Top Views) •KM416C/V254DJ •KM416C/V254DT VCC DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 N.C N.C W RAS N.C A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VSS DQ15 DQ14 DQ13 DQ12 VSS DQ11 DQ10 DQ9 DQ8 N.C LCAS UCAS OE A8 A7 A6 A5 A4 VSS VCC DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 N.C N.C W RAS N.C A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VSS DQ15 DQ14 DQ13 DQ12 VSS DQ11 DQ10 DQ9 DQ8 N.C LCAS UCAS OE A8 A7 A6 A5 A4 VSS (SOJ) (TSOP-II) Pin Name A0 - A8 DQ0 - 15 VSS RAS UCAS LCAS W OE VCC N.C Pin Function Address Inputs Data In/Out Ground Row Address Strobe Upper Column Address Strobe Lower Column Address Strobe Read/Write Input Data Output Enable Power(+5V) Power(+3.3V) No Connection KM416C254D, KM416V254D ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to VSS Voltage on VCC supply relative to VSS Storage Temperature Power Dissipation Short Circuit Output Current Symbol 3.3V VIN,VOUT VCC Tstg PD IOS -0.5 to +4.6 -0.5 to +4.6 -55 to +150 1 50 Rating CMOS DRAM Units 5V -1.0 to +7.0 -1.0 to +7.0 -55 to +150 1 50 V V °C W mA * Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA= 0 to 70°C) Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Symbol Min VCC VSS VIH VIL 3.0 0 2.0 -0.3*2 3.3V Typ 3.3 0 Max 3.6 0 VCC+0.3*1 0.8 Min 4.5 0 2.4 -1.0*2 5V Typ 5.0 0 Max 5.5 0 VCC+1.0*1 0.8 V V V V Units *1 : VCC+1.3V/15ns(3.3V), VCC+2.0V/20ns(5V), Pulse width is measured at VCC *2 : -1.3V/15ns(3.3V), -2.0V/20ns(5V), Pulse width is measured at VSS DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.) Max Parameter Input Leakage Current (Any input 0≤VIN≤VIN+0.3V, all other input pins not under test=0 Volt) 3.3V Output Leakage Current (Data out is disabled, 0V≤VOUT ≤VCC) Output High Voltage Level(IOH=-2mA) Output Low Voltage Level(IOL=2mA) Input Leakage Current (Any input 0≤VIN≤VIN+0.5V, all other input pins not under test=0 Volt) 5V Output Leakage Current (Data out is disabled, 0V≤VOUT ≤VCC) Output High Voltage Level(IOH=-5mA) Output Low Voltage Level(IOL=4.2mA) Symbol II(L) IO(L) VOH VOL II(L) IO(L) VOH VOL Min -5 -5 2.4 -5 -5 2.4 Max 5 5 0.4 5 5 0.4 Units uA uA V V uA uA V V KM416C254D, KM416V254D DC AND OPERATING CHARACTERISTICS (Continued) Symbol Power Speed KM416V254D ICC1 ICC2 ICC3 Don′t care Don′t care Don′t care -5 -6 -7 Don′t care -5 -6 -7 -5 -6 -7 Don′t care -5 -6 -7 Don′t care Don′t care 70 65 1 70 65 60 55 0.5 100 70 65 200 100 Max KM416C254D 110 90 80 2 110 90 80 90 80 70 1 150 110 90 80 300 200 CMOS DRAM Units mA mA mA mA mA mA mA mA mA mA mA uA mA mA mA uA uA ICC4 Don′t care Normal L Don′t care L L ICC5 ICC6 ICC7 ICCS ICC1 * : Operating Current (RAS and UCAS, LCAS, Address cycling @tRC=min.) ICC2 : Standby Current (RAS=UCAS=LCAS=W=VIH) ICC3 * : RAS-only Refresh Current (UCAS=LCAS=VIH, RAS, Address cycling @tRC=min.) ICC4 * : Extended Data Out Mode Current (RAS=VIL, UCAS or LCAS, Address cycling @tHPC =min.) ICC5 : Standby Current (RAS=UCAS=LCAS=W=VCC-0.2V) ICC6 * : CAS-Before-RAS Refresh Current (RAS and UCAS or LCAS cycling @tRC=min.) ICC7 : Battery back-up current, Average power supply current, Battery back-up mode Input high voltage(VIH)=VCC-0.2V, Input low voltage(VIL)=0.2V, UCAS, LCAS=0.2V, DQ=Don′t care, TRC=125us, TRAS =TRAS min~300ns ICCS : Self Refresh Current RAS=UCAS=LCAS=VIL, W=OE=A0 ~ A8=VCC-0.2V or 0.2V, DQ0 ~ DQ15=VCC-0.2V, 0.2V or Open *Note : ICC1 , ICC3 , ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1 , ICC3 , ICC6 and ICC7, address can be changed maximum once while RAS=VIL. In ICC4 , address can be changed maximum once within one Hyper page mode cycle time, tHPC . KM416C254D, KM416V254D CAPACITANCE (TA=25°C, VCC=5V or 3.3V, f=1MHz) Parameter Input capacitance [A0 ~ A8] Input capacitance [RAS, UCAS, LCAS, W, OE] Output capacitance [DQ0 - DQ15] Symbol CIN1 CIN2 CDQ Min - CMOS DRAM Max 5 7 7 Units pF pF pF AC CHARACTERISTICS (0°C≤TA≤70°C, See note 1,2) Test condition (5V device) : VCC=5.0V±10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.0/0.8V Test condition (3.3V device) : VCC=3.3V±0.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V Parameter Random read or write cycle time Read-modify-write cycle time Access time from RAS Access time from CAS Access time from column address CAS to output in Low-Z Output buffer turn-off delay from CAS Transition time (rise and fall) RAS precharge time RAS pulse width RAS hold time CAS hold time CAS pulse width RAS to CAS delay time RAS to column address delay time CAS to RAS precharge time Row address set-up time Row address hold time Column address set-up time Column address hold time Column address to RAS lead time Read command set-up time Read command hold time referenced to CAS Read command hold time referenced to RAS Write command set-up time Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Note) *1 : 5V only Symbol Min -5*1 Max Min 104 138 50 15 25 3 3 2 30 50 15 40 8 20 15 5 0 10 0 8 25 0 0 0 0 10 10 13 8 10K 35 25 10K 13 50 3 3 2 40 60 15 50 10 20 15 5 0 10 0 10 30 0 0 0 0 10 10 15 10 10K 45 30 10K 13 50 60 15 30 3 3 2 50 70 20 60 15 20 15 5 0 10 0 15 35 0 0 0 0 10 10 15 15 10K 50 35 10K 18 50 -6 Max Min 124 163 70 20 35 -7 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 16 8 8 7 13 13 4 10 3,4,10 3,4,5 3,10 3 6,12 2 Units Notes tRC tRWC tRAC tCAC tAA tCLZ tCEZ tT tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCS tWCH tWP tRWL tCWL 84 116 KM416C254D, KM416V254D AC CHARACTERISTICS (Continued) Parameter Data set-up time Data hold time Refresh period (Normal) Refresh period (L-ver) CAS to W delay time RAS to W delay time Column address to W delay time CAS precharge to W delay time CAS set-up time (CAS -before-RAS refresh) CAS hold time (CAS -before-RAS refresh) RAS to CAS precharge time CAS precharge time (C-B-R counter test cycle) Access time from CAS precharge Hyper Page mode cycle time Hyper Page read-modify-write cycle time CAS precharge time (Hyper Page cycle) RAS pulse width (Hyper Page cycle) RAS hold time from CAS precharge OE access time OE to data delay Output buffer turn off delay time from OE OE command hold time Output data hold time Output buffer turn off delay from RAS Output buffer turn off delay from W W to data delay OE to CAS hold time CAS hold time to OE OE precharge time W pulse width (Hyper Page Cycle) RAS pulse width (C-B-R self refresh) RAS precharge time (C-B-R self refresh) CAS hold time (C-B-R self refresh) Note) *1 : 5V only Symbol Min -5*1 Max Min 0 10 8 128 32 67 42 45 5 10 5 20 28 20 57 8 50 30 15 13 3 15 5 3 3 13 5 5 5 5 100 90 -50 15 13 13 13 3 15 5 3 3 13 5 5 5 5 100 110 -50 15 13 13 100K 25 66 10 60 35 15 18 3 20 5 3 3 18 5 5 5 5 100 130 -50 100K 32 77 47 52 5 10 5 20 35 30 81 10 70 40 8 128 42 92 57 62 5 10 5 25 0 8 -6 Max Min 0 15 -7 CMOS DRAM Units Max ns ns 8 128 ms ms ns ns ns ns ns ns ns ns 40 ns ns ns ns 100K ns ns 20 ns ns 18 ns ns ns 20 18 ns ns ns ns ns ns ns us ns ns Notes 9,19 9,19 tDS tDH tREF tREF tCWD tRWD tAWD tCPWD tCSR tCHR tRPC tCPT tCPA tHPC tHPRWC tCP tRASP tRHCP tOEA tOED tOEZ tOEH tDOH tREZ tWEZ tWED tOCH tCHO tOEP tWPE tRASS tRPS tCHS 7,15 7 7 7 17 18 3 11 11 14 3 6 6,12 6 20,21,22 20,21,22 20,21,22 KM416C254D, KM416V254D NOTES CMOS DRAM 1. An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles before proper device operation is achieved. 2. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and VIL(max) and are assumed to be 2ns for all inputs. 3. Measured with a load equivalent to 2 TTL(5V)/1 TTL(3.3V) loads and 50pF. 4. Operation within the tRCD (max) limit insures that tRAC (max) can be met. tRCD (max) is specified as a reference point only. If tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 5. Assumes that tRCD ≥tRCD (max). 6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to Voh or Vol. 7. tWCS , tRWD , tCWD , tAWD and tCPWD are non restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥tWCS (min), the cycle is an early write cycle and the data output will remain high impedance for the duration of the cycle. If tCWD ≥tCWD (min), tRWD ≥tRWD (min), tAWD ≥tAWD (min) and tCPWD ≥tCPWD (min) then the cycle is a read-modify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the condition of the data out is indeterminate. 8. Either tRCH or tRRH must be satisfied for a read cycle. 9. These parameters are referenced to the first CAS falling edge in early write cycles and to W falling edge in OE controlled write cycle and read-modify-write cycles. 10. Operation within the tRAD (max) limit insures that tRAC (max) can be met. tRAD (max) is specified as a reference point only. If tRAD is greater than the specified tRAD (max) limit, then access time is controlled by tAA. 11. tASC ≥6ns, Assume tT = 2.0ns 12. If RAS goes high before CAS high going, the open circuit condition of the output is achieved by CAS high going. If CAS goes high before RAS high going, the open circuit condition of the output is achieved by RAS going. KM416C/V254D/DL Truth Table RAS H L L L L L L L L LCAS H H L H L L H L L UCAS H H H L L H L L L W H H H H H L L L H OE H H L L L H H H H DQ0 - DQ7 Hi-Z Hi-Z DQ-OUT Hi-Z DQ-OUT DQ-IN DQ-IN Hi-Z DQ8-DQ15 Hi-Z Hi-Z Hi-Z DQ-OUT DQ-OUT DQ-IN DQ-IN Hi-Z STATE Standby Refresh Byte Read Byte Read Word Read Byte Write Byte Write Word Write - KM416C254D, KM416V254D 13. tASC , tCAH are referenced to the earlier CAS rising edge. CMOS DRAM 14. tCP is specified from the last CAS rising edge in the previous cycle to the first CAS falling edge in the next cycle. 15. tCWD is referenced to the later CAS falling edge at word red-modify-write cycle. 16. tCWL is specified from W falling edge to the earlier CAS rising edge. 17. tCSR is referenced to earlier CAS falling low before RAS transition low. 18. tCHR is referenced to the later CAS rising high after RAS transition low. RAS LCAS UCAS tCSR tCHR 19. tDS, tDH are specified for the earlier CAS falling low. LCAS UCAS tDS DQ0 ~ DQ15 Din tDH W 20. f tRASS ≥100us, then RAS precharge time must use tRPS instead of tRP. 21. For RAS-only refresh and burst CAS-before-RAS refresh mode, 512(512K) cycle of burst refresh must be executed within 8ms before and after self refresh, in order to meet refresh specification. 22. For distributed CAS-before-RAS with 15.6us interval, CAS-before-RAS refresh should be executed with in 15.6us immediately before and after self refresh in order to meet refresh specification. KM416C254D, KM416V254D WORD READ CYCLE CMOS DRAM tRAS RAS VIH VIL - tRC tRP tCRP UCAS VIH VIL - tCSH tRCD tRSH tCAS tCRP tCRP LCAS VIH VIL - tCSH tRCD tRSH tCAS tCRP tRAD tASR A VIH VIL - tRAH tASC tRAL tCAH COLUMN ADDRESS ROW ADDRESS tRCS W VIH VIL - tRCH tRRH tAA tOLZ OE VIH VIL - tOEA tCAC tCLZ tCEZ tOEZ DATA-OUT DQ0 ~ DQ7 VOH VOL DQ8 ~ DQ15 VOH VOL - tRAC OPEN tCAC tRAC OPEN tCLZ tOEZ DATA-OUT tCEZ Don′t care Undefined KM416C254D, KM416V254D LOWER BYTE READ CYCLE NOTE : DIN = OPEN CMOS DRAM tRC tRAS RAS VIH VIL - tRP tCRP UCAS VIH VIL - tRPC tCRP LCAS VIH VIL - tCSH tRCD tRAD tRSH tCAS tRAL tCAH COLUMN ADDRESS tASR A VIH VIL - tRAH tASC ROW ADDRESS tRCS W VIH VIL - tRCH tRRH tCEZ tAA tOEZ tOEA tCAC tCLZ DATA-OUT OE VIH VIL - DQ0 ~ DQ7 VOH VOL DQ8 ~ DQ15 VOH VOL - tRAC OPEN tOLZ OPEN Don′t care Undefined KM416C254D, KM416V254D UPPER BYTE READ CYCLE NOTE : DIN = OPEN CMOS DRAM tRC tRAS RAS VIH VIL - tRP tCRP UCAS VIH VIL - tCSH tRCD tRSH tCAS tCRP tCRP LCAS VIH VIL - tRPC tRAD tRAL tASR A VIH VIL - tRAH tASC tCAH COLUMN ADDRESS ROW ADDRESS tRCS W VIH VIL - tRCH tRRH tCEZ tAA tOEZ tOEA tOLZ OE VIH VIL - DQ0 ~ DQ7 VOH VOL DQ8 ~ DQ15 VOH VOL - OPEN tCAC tRAC OPEN tCLZ DATA-OUT Don′t care Undefined KM416C254D, KM416V254D WORD WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN CMOS DRAM tRC tRAS RAS VIH VIL - tRP tCRP UCAS VIH VIL - tCSH tRCD tRSH tCAS tCRP tCRP LCAS VIH VIL - tCSH tRCD tRSH tCAS tRAD tCRP tASR A VIH VIL - tRAH tASC tRAL tCAH COLUMN ADDRESS ROW ADDRESS tWCS W VIH VIL - tWCH tWP OE VIH VIL - DQ0 ~ DQ7 VIH VIL - tDS tDH DATA-IN DQ8 ~ DQ15 VIH VIL - tDS tDH DATA-IN Don′t care Undefined KM416C254D, KM416V254D LOWER BYTE WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN CMOS DRAM tRC tRAS RAS VIH VIL - tRP tCRP UCAS VIH VIL - tCRP LCAS VIH VIL - tCSH tRCD tRSH tCAS tRAD tCRP tASR A VIH VIL - tRAH tASC tRAL tCAH COLUMN ADDRESS ROW ADDRESS tWCS W VIH VIL - tWCH tWP OE VIH VIL - DQ0 ~ DQ7 VIH VIL - tDS tDH DATA-IN DQ8 ~ DQ15 VIH VIL - Don′t care Undefined KM416C254D, KM416V254D UPPER BYTE WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN CMOS DRAM tRC tRAS RAS VIH VIL - tRP tCRP UCAS VIH VIL - tCSH tRCD tRSH tCAS tCRP tCRP LCAS VIH VIL - tRAD tASR tRAH tASC tRAL tCAH COLUMN ADDRESS A VIH VIL - ROW ADDRESS tWCS W VIH VIL - tWCH tWP OE VIH VIL - DQ0 ~ DQ7 VIH VIL - DQ8 ~ DQ15 VIH VIL - tDS tDH DATA-IN Don′t care Undefined KM416C254D, KM416V254D WORD WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : DOUT = OPEN CMOS DRAM tRC tRAS RAS VIH VIL - tRP tCRP UCAS VIH VIL - tCSH tRCD tRSH tCAS tCRP tCRP LCAS VIH VIL - tCSH tRCD tRSH tCAS tRAD tCRP tASR A VIH VIL - tRAH tASC tRAL tCAH COLUMN ADDRESS ROW ADDRESS tCWL tRWL W VIH VIL - tWP OE VIH VIL - tOED tDS tOEH tDH DATA-IN DQ0 ~ DQ7 VIH VIL - DQ8 ~ DQ15 VIH VIL - tDS tDH DATA-IN Don′t care Undefined KM416C254D, KM416V254D LOWER BYTE WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : DOUT = OPEN CMOS DRAM tRC tRAS RAS VIH VIL - tRP tCRP UCAS VIH VIL - tRPC tCRP LCAS VIH VIL - tCSH tRCD tRSH tCAS tRAD tCRP tASR A VIH VIL - tRAH tASC tRAL tCAH COLUMN ADDRESS ROW ADDRESS tCWL tRWL W VIH VIL - tWP OE VIH VIL - tOED tDS tOEH tDH DATA-IN DQ0 ~ DQ7 VIH VIL - DQ8 ~ DQ15 VIH VIL - Don′t care Undefined KM416C254D, KM416V254D UPPER BYTE WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : DOUT = OPEN CMOS DRAM tRC tRAS RAS VIH VIL - tRP tCRP UCAS VIH VIL - tCSH tRCD tRSH tCAS tCRP tCRP tCRP LCAS VIH VIL - tRAD tASR tRAH tASC tRAL tCAH COLUMN ADDRESS A VIH VIL - ROW ADDRESS W VIH VIL - tCWL tRWL tWP OE VIH VIL - tOED tOEH DQ0 ~ DQ7 VIH VIL - DQ8 ~ DQ15 VIH VIL - tDS tDH DATA-IN Don′t care Undefined KM416C254D, KM416V254D WORD READ - MODIFY - WRITE CYCLE CMOS DRAM tRWC tRAS RAS VIH VIL - tRP tCRP UCAS VIH VIL - tRCD tRSH tCAS tCRP LCAS VIH VIL - tRCD tRAD tRSH tCAS tCSH tASR A VIH VIL - tRAH tASC tCAH ROW ADDR. COLUMN ADDRESS tAWD tCWD W VIH VIL VIH VIL - tRWL tCWL tWP tRWD tOEA tOLZ tCLZ tCAC tAA tOED tOEZ VALID DATA-OUT OE DQ0 ~ DQ7 VI/OH VI/OL - tRAC tDS tDH VALID DATA-IN tOLZ tCLZ tCAC tAA DQ8 ~ DQ15 VI/OH VI/OL - tRAC tOED tOEZ VALID DATA-OUT tDS tDH VALID DATA-IN Don′t care Undefined KM416C254D, KM416V254D LOWER-BYTE READ - MODIFY - WRITE CYCLE CMOS DRAM tRWC tRAS RAS VIH VIL - tRP tCRP UCAS VIH VIL - tRPC tCRP LCAS VIH VIL - tRCD tRSH tCAS tRAD tCSH tASR tRAH tASC tCAH A VIH VIL - ROW ADDR. COLUMN ADDRESS tAWD tCWD W VIH VIL VIH VIL - tRWL tCWL tWP tRWD tOEA OE tOLZ tCLZ tCAC tAA DQ0 ~ DQ7 VI/OH VI/OL DQ8 ~ DQ15 VOH VOL - tOED tOEZ VALID DATA-OUT tRAC tDS tDH VALID DATA-IN OPEN Don′t care Undefined KM416C254D, KM416V254D UPPER-BYTE READ - MODIFY - WRITE CYCLE CMOS DRAM tRWC tRAS RAS VIH VIL - tRP tCRP UCAS VIH VIL - tRCD tRSH tCAS tCRP LCAS VIH VIL - tRPC tRAD tCSH tASR tRAH tASC tCAH A VIH VIL - ROW ADDR COLUMN ADDRESS tAWD tCWD W VIH VIL VIH VIL - tRWL tCWL tWP tRWD tOEA OE DQ0 ~ DQ7 VOH VOL - OPEN tOLZ tCLZ tCAC tAA tOED tOEZ VALID DATA-OUT DQ8 ~ DQ15 VI/OH VI/OL - tRAC tDS tDH VALID DATA-IN Don′t care Undefined KM416C254D, KM416V254D HYPER PAGE MODE WORD READ CYCLE CMOS DRAM tRASP RAS VIH VIL - tRP tCSH tCRP UCAS VIH VIL - tRHCP tHPC tCP tHPC tCAS tCP tHPC tCAS tCP tCAS tRCD tCAS tCRP LCAS VIH VIL - tRCD tRAD tRAH tASC tCP tCAS tCAS tCP tCAS tCP tCAS tREZ tASR A VIH VIL - tCAH tASC tCAH tASC tCAH COLUMN ADDR tASC tCAH ROW ADDR COLUMN ADDRESS COLUMN ADDRESS COLUMN ADDRESS tRAL tRCS W VIH VIL - tRRH tRCH tAA tCPA tCAC tOCH tCAC tAA tCPA tCPA tCAC tAA tCHO tOEP OE VIH VIL - tOEA tOEA tCAC tOEP tDOH VALID DATA-OUT DQ0 ~ DQ7 VOH VOL - tRAC tOEZ VALID DATA-OUT VALID DATA-OUT tOEZ VALID DATA-OUT VALID DATA-OUT tOEZ tOLZ tCLZ tCAC DQ8 ~ DQ15 VOH VOL - tOEP tDOH VALID DATA-OUT tRAC tOEZ VALID DATA-OUT VALID DATA-OUT tOEZ VALID DATA-OUT VALID DATA-OUT tOLZ tCLZ Don′t care Undefined KM416C254D, KM416V254D HYPER PAGE MODE LOWER BYTE READ CYCLE CMOS DRAM tRASP RAS VIH VIL ¡ó tRP tCRP UCAS VIH VIL - tRPC tCSH tHPC tRCD tCP tCAS tCAS tCP tCAS tHPC tCP tCAS tRHCP tHPC tREZ LCAS VIH VIL - tASR A VIH VIL - tRAD tRAH tASC tCAH tASC tCAH tASC tCAH tASC COLUMN ADDR tCAH COLUMN ADDRESS ROW ADDR COLUMN ADDRESS COLUMN ADDRESS tRAL tRCS W VIH VIL - tRRH tRCH tAA tCPA tAA tCAC tOCH tOEA tCAC tOEP tDOH VALID DATA-OUT tCAC tAA tCPA tCHO tOEP tCPA tCAC tAA OE VIH VIL - tOEA DQ0 ~ DQ7 VOH VOL - tRAC tOEZ VALID DATA-OUT VALID DATA-OUT tOEZ VALID DATA-OUT VALID DATA-OUT tOEZ DQ8 ~ DQ15 VOH VOL - tOLZ tCLZ OPEN Don′t care Undefined KM416C254D, KM416V254D HYPER PAGE MODE UPPER BYTE READ CYCLE CMOS DRAM tRASP RAS VIH VIL ¡ó tRP tCSH tCRP UCAS VIH VIL - tRHCP tHPC tCP tHPC tCAS tCP tHPC tCAS tCP tCAS tRPC tRCD tCAS tCRP LCAS VIH VIL - tRPC tASR A VIH VIL - tRAD tRAH tASC tCAH tASC tCAH tASC tCAH COLUMN ADDR. tASC tCAH tREZ ROW ADDR. COLUMN ADDRESS COLUMN ADDRESS COLUMN ADDRESS tRAL tRCS W VIH VIL - tRRH tRCH tAA tCPA tCAC tOCH tCAC tAA tCPA tCHO tOEP tCPA tCAC tAA OE VIH VIL - tOEA tOEA DQ0 ~ DQ7 VOH VOL - OPEN tCAC tOEP tDOH VALID DATA-OUT DQ8 ~ DQ15 VOH VOL - tRAC tOEZ VALID DATA-OUT VALID DATA-OUT tOEZ VALID DATA-OUT VALID DATA-OUT tOEZ tOLZ tCLZ Don′t care Undefined KM416C254D, KM416V254D HYPER PAGE MODE WORD WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN CMOS DRAM tRASP RAS VIH VIL ¡ó tRP tRHCP tCRP UCAS VIH VIL - tHPC tRCD tCAS tHPC tRCD tCAS tRAD tCSH tCP tCAS ¡ó tHPC tCP tCAS ¡ó tRSH tCP tCAS tCRP tCRP LCAS VIH VIL - tHPC tCP tRSH tCAS tRAL tASR A VIH VIL - tRAH tASC tCAH tASC tCAH ¡ó tASC tCAH ROW ADDR COLUMN ADDRESS COLUMN ADDRESS ¡ó COLUMN ADDRESS tWCS W VIH VIL - tWCH tWCS tWCH tWP ¡ó tWCS tWCH tWP tWP OE VIH VIL - ¡ó ¡ó DQ0 ~ DQ7 VIH VIL - tDS tDH VALID DATA-IN tDS tDH ¡ó VALID DATA-IN tDS tDH ¡ó VALID DATA-IN DQ8 ~ DQ15 VIH VIL - tDS tDH VALID DATA-IN tDS tDH ¡ó VALID DATA-IN tDS tDH ¡ó VALID DATA-IN Don′t care Undefined KM416C254D, KM416V254D HYPER PAGE MODE LOWER BYTE WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN CMOS DRAM tRASP RAS VIH VIL ¡ó tRP tRHCP tRPC tCRP UCAS VIH VIL - tCRP LCAS VIH VIL - tHPC tRCD tCAS tRAD tCSH tCP tCAS ¡ó tHPC tCP tRSH tCAS tRAL tASR A VIH VIL - tRAH tASC tCAH tASC tCAH ¡ó tASC tCAH ROW ADDR COLUMN ADDRESS COLUMN ADDRESS ¡ó COLUMN ADDRESS tWCS W VIH VIL - tWCH tWCS tWCH tWP ¡ó tWCS tWCH tWP tWP OE VIH VIL - ¡ó ¡ó DQ0 ~ DQ7 VIH VIL - tDS tDH VALID DATA-IN tDS tDH ¡ó VALID DATA-IN tDS tDH ¡ó VALID DATA-IN DQ8 ~ DQ15 VIH VIL - Don′t care Undefined KM416C254D, KM416V254D HYPER PAGE MODE UPPER BYTE WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN CMOS DRAM tRASP RAS VIH VIL ¡ó tRP tRHCP tCRP UCAS VIH VIL - tHPC tRCD tCAS tCP tCAS ¡ó tHPC tCP tRSH tCAS tRPC tCRP LCAS VIH VIL - tRAD tCSH tASR A VIH VIL - tRAL tCAH tASC tCAH ¡ó tRAH tASC tASC tCAH ROW ADDR COLUMN ADDRESS COLUMN ADDRESS ¡ó COLUMN ADDRESS tWCS W VIH VIL - tWCH tWCS tWCH tWP ¡ó tWCS tWCH tWP tWP OE VIH VIL - ¡ó ¡ó DQ0 ~ DQ7 VIH VIL - ¡ó ¡ó DQ8 ~ DQ15 VIH VIL - tDS tDH VALID DATA-IN tDS tDH ¡ó VALID DATA-IN tDS tDH ¡ó VALID DATA-IN Don′t care Undefined KM416C254D, KM416V254D HYPER PAGE MODE WORD READ - MODIFY - WRITE CYCLE CMOS DRAM tRASP RAS VIH VIL - tRP tHPRWC tRSH tCSH tCRP tRCD tCAS tCP tCAS tCP tCAS tCAS tCRP UCAS VIH VIL - tCRP LCAS VIH VIL - tRCD tCRP tRAD tRAH tASR A VIH VIL ROW ADDR tASC COL. ADDR tCAH tASC COL. ADDR tRAL tCAH tRCS W VIH VIL - tCWL tWP tCWD tAWD tRWD tRCS tCWD tAWD tCPWD tOEA tRWL tCWL tWP OE VIH VIL - tOEA tOED tCAC tAA tOEZ tDS tDH tCAC tOED tAA tDH tOEZ tDS DQ0 ~ DQ7 VI/OH VI/OL - tRAC tCLZ VALID DATA-OUT tCLZ VALID DATA-IN VALID DATA-OUT VALID DATA-IN tOED tCAC tAA DQ8 ~ DQ15 VI/OH VI/OL - tDH tOEZ tDS tCAC tAA tOEZ tOED tDH tDS tRAC tCLZ VALID DATA-OUT tCLZ VALID DATA-IN VALID DATA-OUT VALID DATA-IN Don′t care Undefined KM416C254D, KM416V254D HYPER PAGE MODE LOWER BYTE READ - MODIFY - WRITE CYCLE CMOS DRAM tRASP RAS VIH VIL - tRP tHPRWC tRPC tCSH tCRP UCAS VIH VIL - tCRP LCAS VIH VIL - tRCD tCAS tRAD tRAH tCP tRSH tCAS tCRP tASR A VIH VIL ROW ADDR tASC COL. ADDR tCAH tASC COL. ADDR tCAH tRAL tRCS W VIH VIL - tCWL tWP tCWD tRCS tRWL tCWL tWP tCWD tAWD tRWD OE VIH VIL - tAWD tCPWD tOEA tOED tCAC tDH tDS tAA tOEZ tOED tDH tDS tOEA tCAC tAA tOEZ DQ0 ~ DQ7 VI/OH VI/OL - tRAC tCLZ tOLZ VALID DATA-OUT tCLZ VALID DATA-IN tOLZ VALID DATA-OUT VALID DATA-IN DQ8 ~ DQ15 VI/OH VI/OL - OPEN Don′t care Undefined KM416C254D, KM416V254D HYPER PAGE MODE UPPER BYTE READ - MODIFY - WRITE CYCLE CMOS DRAM tRASP RAS VIH VIL - tRP tHPRWC tRSH tCAS tRPC tCSH tCRP tRCD tCAS tCP tCRP UCAS VIH VIL - tCRP LCAS VIH VIL - tRAD tRAH tASR A VIH VIL ROW ADDR tASC COL. ADDR tCAH tASC COL. ADDR tCAH tRAL tRCS W VIH VIL - tCWL tWP tCWD tRCS tRWL tCWL tWP tCPWD tCWD tAWD tAWD tRWD OE VIH VIL - tOEA tOEA DQ0 ~ DQ7 VI/OH VI/OL - OPEN tOLZ tOED tCAC tAA tOEZ tDH tDS tCAC tAA tOEZ tCLZ VALID DATA-OUT VALID DATA-IN VALID DATA-OUT VALID DATA-IN tOLZ tOED tDH tDS DQ8 ~ DQ15 VI/OH VI/OL - tRAC tCLZ Don′t care Undefined KM416C254D, KM416V254D HYPER PAGE READ AND WRITE MIXED CYCLE CMOS DRAM tRASP RAS VIH VIL READ(tCAC ) READ(tCPA ) WRITE READ(tAA ) tRP tHPC tCP VIH UCAS VIL - tHPC tCP tCP tCAS tHPC tCP tCAS tCAH tCP tRHCP tHPC tCAS tHPC tCAS tRCD tCAS tCP tCAS tHPC LCAS VIH VIL - tRAD tASR tRAH tASC tCAS tCAS tCAH tASC COLUMN ADDRESS tCAH tASC tASC tCAH COL. ADDR A VIH VIL - ROW ADDR COLUMN ADDRESS COL. ADDR tRAL tRCS W VIH VIL - tRCH tRCS tRCH tWCS tWCH tRCH tWPE tCLZ tCPA OE VIH VIL - tWED DQ0 ~ DQ7 VI/OH VI/OL - tOEA tCAC tAA tRAC tWEZ tWEZ VALID DATA-OUT tDH tDS VALID DATA-IN tAA VALID DATA-OUT tREZ VALID DATA-OUT DQ8 ~ DQ15 VI/OH VI/OL - tOEA tCAC tAA tRAC tWEZ tWEZ VALID DATA-OUT tDH tDS VALID DATA-IN tAA VALID DATA-OUT tREZ VALID DATA-OUT Don′t care Undefined KM416C254D, KM416V254D RAS - ONLY REFRESH CYCLE NOTE : W, OE , DIN = Don′t care DOUT = OPEN tRC RAS VIH VIL - CMOS DRAM tRP tRAS tCRP tRPC UCAS VIH VIL - tCRP LCAS VIH VIL - tASR A VIH VIL - tRAH ROW ADDR CAS - BEFORE - RAS REFRESH CYCLE NOTE : OE, A = Don′t care tRC tRAS tRPC tCSR tCHR tRP RAS VIH VIL - tRP tRPC tCP UCAS VIH VIL - tCP LCAS VIH VIL - tCSR tCHR DQ0 ~ DQ7 VOH VOL DQ8 ~ DQ15 VOH VOL - tCEZ OPEN OPEN Don′t care Undefined KM416C254D, KM416V254D HIDDEN REFRESH CYCLE ( READ ) CMOS DRAM tRC RAS VIH VIL - tRP tRC tRAS tRP tRAS tCRP UCAS VIH VIL - tRCD tRSH tCHR tCRP LCAS VIH VIL - tRCD tRAD tRSH tCHR tASR A VIH VIL - tRAH tASC tCAH COLUMN ADDRESS ROW ADDRESS tRCS W VIH VIL - tWRH tRAL tAA OE VIH VIL - tOEA tCEZ tREZ tWEZ tOLZ tOEZ DATA-OUT tCAC tCLZ DQ0 ~ DQ7 VOH VOL - tRAC OPEN DQ8 ~ DQ15 VOH VOL - OPEN DATA-IN DATA-OUT Don′t care Undefined KM416C254D, KM416V254D HIDDEN REFRESH CYCLE ( WRITE ) NOTE : DOUT = OPEN CMOS DRAM tRC RAS VIH VIL - tRP tRC tRAS tRP tRAS tCRP UCAS VIH VIL - tRCD tRSH tCHR tCRP LCAS VIH VIL - tRCD tRSH tCHR tRAD tASR tRAH tASC tCAH COLUMN ADDRESS A VIH VIL - ROW ADDRESS tWRH tWCS W VIH VIL - tWRP tWCH tWP OE VIH VIL - tDS DQ0 ~ DQ7 VIH VIL - tDH DATA-IN tDS DQ8 ~ DQ15 VIH VIL - tDH DATA-IN Don′t care Undefined KM416C254D, KM416V254D CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE RAS VIH VIL VIH VIL VIH VIL - CMOS DRAM tRP tRAS tCSR tCPT tCHR tCPT tCHR tRSH tCAS tRSH tCAS tRAL tASC tCAH UCAS tCSR LCAS A VIH VIL - COLUMN ADDRESS READ CYCLE W VIH VIL VIH VIL - tWRP tWRH tAA tRCS tCAC tRRH tRCH OE DQ0 ~ DQ15 VOH VOL - tCLZ tOEA tOEZ DATA-OUT tREZ WRITE CYCLE W VIH VIL VIH VIL - tCEZ tWRP tWRH tWCS tRWL tCWL tWCH tWP tWEZ OE tDS DQ0 ~ DQ15 VIH VIL - tDH DATA-IN READ-MODIFY-WRITE tWRP W VIH VIL - tWRH tRCS tAWD tCWD tCAC tWP tCWL tRWL tAA tOEA OE VIH VIL - tOED tCLZ tOEZ tDS tDH DQ0 ~ DQ15 VI/OH VI/OL VALID DATA-OUT VALID DATA-IN Don′t care Undefined KM416C254D, KM416V254D CAS - BEFORE - RAS SELF REFRESH CYCLE NOTE : OE , A = Don′t care tRP RAS VIH VIL - CMOS DRAM tRASS tRPS tRPC tCP UCAS VIH VIL - tRPC tCSR tCHS tCP LCAS VIH VIL - tCSR tCHS DQ0 ~ DQ7 VOH VOL DQ8 ~ DQ15 VOH VOL - tCEZ OPEN OPEN Don′t care Undefined KM416C254D, KM416V254D PACKAGE DIMENSION 40 SOJ 400mil CMOS DRAM Units : Inches (millimeters) #40 0.435 (11.06) 0.445 (11.30) 0.400 (10.16) 0.360 (9.15) 0.380 (9.65) 0.010 (0.25) TYP 0.018 (0.45) 0.030 (0.75) 0~8 O 0.006 (0.15) 0.012 (0.30) #1 0.027 (0.69) MIN 1.041 (26.44) MAX 1.020 (25.92) 1.030 (26.16) 0.148 (3.76) MAX 0.026 (0.66) 0.032 (0.81) 0.015 (0.38) 0.021 (0.53) 0.0375 (0.95) 0.050 (1.27) 44(40) TSOP(II) 400mil Units : Inches (millimeters) 0.455 (11.56) 0.471 (11.96) 0.400 (10.16) 0.004 (0.10) 0.010 (0.25) 0.741 (18.81) MAX 0.721 (18.31) 0.729 (18.51) 0.047 (1.20) MAX 0.032 (0.805) 0.0315 (0.80) 0.002 (0.05) MIN 0.010 (0.25) 0.018 (0.45)