KM44C4005C

KM44C4005C, KM44C4105C CMOS DRAM 4M x 4Bit CMOS Quad CAS DRAM with Extended Data Out DESCRIPTION This is a family of 4,194,304 x 4 bit Quad CAS with Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random access of memory cells within the same row, so called Hyper Page Mode. Refresh cycle (2K Ref. or 4K Ref.), access time (-5 or -6), power consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. Four separate CAS pins provide for seperate I/O operation allowing this device to operate in parity mode. This 4Mx4 Extended Data Out Quad CAS DRAM family is fabricated using Samsung′s advanced CMOS process to realize high bandwidth, low power consumption and high reliability. FEATURES • Part Identification - KM44C4005C/C-L (5V, 4K Ref.) - KM44C4105C/C-L (5V, 2K Ref.) • Extended Data Out mode operation (Fast Page Mode with Extended Data Out) • Four separate CAS pins provide for separate I/O operation • CAS-before-RAS refresh capability • RAS-only and Hidden refresh capability • Self-refresh capability (L-ver only) • Fast parallel test mode capability Unit : mW • TTL compatible inputs and outputs • Early Write or output enable controlled write 2K 605 550 • JEDEC Standard pinout • Available in Plastic SOJ and TSOP(II) packages • Single +5V±10% power supply • Active Power Dissipation Refresh Cycle 4K -5 -6 495 440 Speed FUNCTIONAL BLOCK DIAGRAM • Refresh Cycles Part NO. C4005C C4105C Refresh cycle 4K 2K Refresh period Normal 64ms 32ms L-ver 128ms Refresh Timer Refresh Control Row Decoder Sense Amps & I/O RAS CAS 0 - 3 W Control Clocks Vcc Vss VBB Generator Data in Buffer • Performance Range Speed -5 -6 Refresh Counter Memory Array 4,194,304 x 4 Cells DQ0 to DQ3 tRAC 50ns 60ns tCAC 13ns 15ns tRC 84ns 104ns tHPC 20ns 25ns A0-A11 (A0 - A10) *1 A0 - A9 (A0 - A10) *1 Row Address Buffer Col. Address Buffer Column Decoder Data out Buffer OE Note) *1 : 2K Refresh SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. KM44C4005C, KM44C4105C CMOS DRAM PIN CONFIGURATION (Top Views) •KM44C40(1)05CK •KM44C40(1)05CS VCC DQ0 DQ1 W RAS *A11(N.C) CAS0 CAS1 A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VSS DQ3 DQ2 CAS3 OE A9 CAS2 N.C A8 A7 A6 A5 A4 VSS VCC DQ0 DQ1 W RAS *A11(N.C) CAS0 CAS1 A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VSS DQ3 DQ2 CAS3 OE A9 CAS2 N.C A8 A7 A6 A5 A4 VSS *A11 is N.C for KM44C4105C(5V, 2K Ref. product) K : 300mil 28 SOJ S : 300mil 28 TSOP II Pin Name A0 - A11 A0 - A10 DQ0 - 3 VSS RAS CAS0~CAS3 W OE VCC N.C Pin Function Address Inputs (4K Product) Address Inputs (2K Product) Data In/Out Ground Row Address Strobe Column Address Strobe Read/Write Input Data Output Enable Power(+5.0V) No Connection KM44C4005C, KM44C4105C ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to VSS Voltage on VCC supply relative to VSS Storage Temperature Power Dissipation Short Circuit Output Current Symbol VIN, VOUT VCC Tstg PD IOS Rating -1.0 to +7.0 -1.0 to +7.0 -55 to +150 1 50 CMOS DRAM Units V V °C W mA * Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA= 0 to 70°C) Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min 4.5 0 2.4 -1.0*2 Typ 5.0 0 Max 5.5 0 VCC+1.0*1 0.8 Units V V V V *1 : VCC+2.0V/20ns, Pulse width is measured at VCC *2 : -2.0/20ns, Pulse width is measured at VSS DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.) Parameter Input Leakage Current (Any input 0≤VIN≤VIN+0.5V, all other input pins not under test=0 Volt) Output Leakage Current (Data out is disabled, 0V≤VOUT ≤VCC) Output High Voltage Level(IOH=-5mA) Output Low Voltage Level(IOL=4.2mA) Symbol II(L) IO(L) VOH VOL Min -5 -5 2.4 Max 5 5 0.4 Units uA uA V V KM44C4005C, KM44C4105C DC AND OPERATING CHARACTERISTICS (Continued) Symbol Power Don′t care Normal L Don′t care Speed -5 -6 Don′t care -5 -6 -5 -6 Don′t care -5 -6 Don′t care Don′t care Max KM44C4005C 90 80 2 1 90 80 80 70 1 250 90 80 300 250 KM44C4105C 110 100 2 1 110 100 90 80 1 250 110 100 300 250 CMOS DRAM Units mA mA mA mA mA mA mA mA mA mA mA mA uA mA mA mA uA uA ICC1 ICC2 ICC3 ICC4 Don′t care Normal L Don′t care L L ICC5 ICC6 ICC7 ICCS ICC1 * : Operating Current (RAS and CAS cycling @tRC=min.) ICC2 : Standby Current (RAS=CAS=W=VIH) ICC3 * : RAS-only Refresh Current (CAS=VIH, RAS cycling @tRC=min.) ICC4 * : Hyper Page Mode Current (RAS=VIL, CAS, Address cycling @tHPC =min.) ICC5 : Standby Current (RAS=CAS=W=VCC-0.2V) ICC6 * : CAS-Before-RAS Refresh Current (RAS and CAS cycling @tRC=min.) ICC7 : Battery back-up current, Average power supply current, Battery back-up mode Input high voltage(VIH)=VCC-0.2V, Input low voltage(VIL)=0.2V, CAS=0.2V, DQ=Don′t care, TRC=31.25us(4K/L-ver), 62.5us(2K/L-ver), TRAS =TRAS min~300ns ICCS : Self Refresh Current RAS=CAS=0.2V, W=OE=A0 ~ A11=VCC-0.2V or 0.2V, DQ0 ~ DQ3=VCC-0.2V, 0.2V or Open *Note : ICC1 , ICC3 , ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1 , ICC3 and ICC6 address can be changed maximum once while RAS=VIL. In ICC4 , address can be changed maximum once within one Hyper page mode cycle time, tHPC . KM44C4005C, KM44C4105C CAPACITANCE (TA=25°C, VCC=5V, f=1MHz) Parameter Input capacitance [A0 ~ A11] Input capacitance [RAS, CASx, W, OE] Output capacitance [DQ0 - DQ3] Symbol CIN1 CIN2 CDQ Min - CMOS DRAM Max 5 7 7 Units pF pF pF AC CHARACTERISTICS (0°C≤TA≤70°C, See note 1,2) Test condition : VCC=5.0V±10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.0/0.8V Parameter Random read or write cycle time Read-modify-write cycle time Access time from RAS Access time from CAS Access time from column address CAS to output in Low-Z Output buffer turn-off delay from CAS OE to output in Low-Z Transition time (rise and fall) RAS precharge time RAS pulse width RAS hold time CAS hold time CAS pulse width RAS to CAS delay time RAS to column address delay time CAS to RAS precharge time Row address set-up time Row address hold time Column address set-up time Column address hold time Column address to RAS lead time Read command set-up time Read command hold time referenced to CAS Read command hold time referenced to RAS Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Symbol Min -5 Max Min 104 140 50 13 25 3 3 3 2 30 50 13 38 8 20 15 5 0 10 0 8 25 0 0 0 10 10 13 8 10K 37 25 10K 50 13 3 3 3 2 40 60 15 45 10 20 15 5 0 10 0 10 30 0 0 0 10 10 15 10 10K 45 30 10K 50 15 60 15 30 -6 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 19 8,17 8 16 18 18 16 19 25 4,18 10 17 3,4,10 3,4,5,20 3,10 3,20 6,13 3 2 Units Notes tRC tRWC tRAC tCAC tAA tCLZ tCEZ tOLZ tT tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCH tWP tRWL tCWL 84 106 KM44C4005C, KM44C4105C AC CHARACTERISTICS (Continued) Parameter Data set-up time Data hold time Refresh period (2K, Normal) Refresh period (4K, Normal) Refresh period (L-ver) Write command set-up time CAS to W delay time RAS to W delay time Column address to W delay time CAS precharge to W delay time CAS set-up time (CAS -before-RAS refresh) CAS hold time (CAS -before-RAS refresh) RAS to CAS precharge time Access time from CAS precharge Hyper Page mode cycle time Hyper Page read-modify-write cycle time CAS precharge time (Hyper Page cycle) RAS pulse width (Hyper Page cycle) RAS hold time from CAS precharge OE access time OE to data delay Output buffer turn off delay time from OE OE command hold time Write command set-up time (Test mode in) Write command hold time (Test mode in) W to RAS precharge time(C-B-R refresh) W to RAS hold time(C-B-R refresh) Output data hold time Output buffer turn off delay from RAS Output buffer turn off delay from W W to data delay OE to CAS hold time CAS hold time to OE OE precharge time W pulse width (Hyper Page Cycle) RAS pulse width (C-B-R self refresh) RAS precharge time (C-B-R self refresh) CAS hold time (C-B-R self refresh) Hold time CAS low to CAS high Symbol Min -5 Max Min 0 10 32 64 128 0 30 67 42 47 5 10 5 28 20 62 8 50 30 13 13 3 13 10 10 10 10 5 3 3 15 5 5 5 5 100 90 -50 5 13 13 13 15 3 15 10 10 10 10 5 3 3 15 5 5 5 5 100 110 -50 5 15 15 15 200K 24 71 10 60 35 15 0 34 79 49 54 5 10 5 35 32 64 -6 CMOS DRAM Units Max ns ns ms ms ms ns ns ns ns ns ns ns ns ns ns ns ns 200K ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns us ns ns ns Notes 9 9 tDS tDH tREF tREF tREF tWCS tCWD tRWD tAWD tCPWD tCSR tCHR tRPC tCPA tHPC tHPRWC tCP tRASP tRHCP tOEA tOED tOEZ tOEH tWTS tWTH tWRP tWRH tDOH tREZ tWEZ tWED tOCH tCHO tOEP tWPE tRASS tRPS tCHS tCLCH 0 8 128 7,18 7,16 7 7 7 18 17 18 3,17 14,21 14,21 22 23 24 6 11 11 6,13 6 27,28,29 27,28,29 27,28,29 15,26 KM44C4005C, KM44C4105C TEST MODE CYCLE Parameter Random read or write cycle time Read-modify-write cycle time Access time from RAS Access time from CAS Access time from column address RAS pulse width CAS pulse width RAS hold time CAS hold time Column address to RAS lead time CAS to W delay time RAS to W delay time Column address to W delay time CAS precharge to W delay time Hyper Page mode cycle time Hyper Page read-modify-write cycle time RAS pulse width (Hyper Page cycle) Access time from CAS precharge OE access time OE to data delay OE command hold time Symbol Min -5 Max Min 109 145 55 18 30 55 13 18 43 30 35 72 47 52 25 52 55 200K 33 18 18 18 20 20 10K 10K 65 15 20 50 35 39 84 54 59 30 61 65 65 20 35 10K 10K -6 Max CMOS DRAM ( Note 11 ) Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 200K 40 20 ns ns ns ns ns 3 7 7 7 7 14 14 3,4,10,12 3,4,5,12 3,10,12 Notes tRC tRWC tRAC tCAC tAA tRAS tCAS tRSH tCSH tRAL tCWD tRWD tAWD tCPWD tHPC tHPRWC tRASP tCPA tOEA tOED tOEH 89 121 KM44C4005C, KM44C4105C NOTES CMOS DRAM 1. An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles before proper device operation is achieved. 2. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and VIL(max) and are assumed to be 2ns for all inputs. 3. Measured with a load equivalent to 2 TTL loads and 100pF. 4. Operation within the tRCD (max) limit insures that tRAC (max) can be met. tRCD (max) is specified as a reference point only. If tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 5. Assumes the tRCD ≥tRCD (max). 6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to Voh or Vol. 7. tWCS , tRWD , tCWD , tAWD and tCPWD are non restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥tWCS (min), the cycle is an early write cycle and the data output will remain high impedance for the duration of the cycle. If tCWD ≥tCWD (min), tRWD ≥tRWD (min), tAWD ≥tAWD (min) and tCPWD ≥tCPWD (min), then the cycle is a readmodify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the condition of the data out is indeterminate. 8. tRCH and tRRH must be satisfied for a read cycle. 9. These parameters are referenced to the first CAS falling edge in early write cycles and to W falling edge in OE controlled write cycle and read-modify-write cycles. 10. Operation within the tRAD (max) limit insures that tRAC (max) can be met. tRAD (max) is specified as a reference point only. If tRAD is greater than the specified tRAD (max) limit, then access time is controlled by tAA. 11. These specifications are applied in the test mode. 12. In test mode read cycle, the values of tRAC, tAA and tCAC are delayed by 2ns to 5ns for the specified values. These parameters should be specified in test mode cycles by adding 5ns to the specified value in this data sheet. 13. If RAS goes high before CAS high going, the open circuit condition of the output is achieved by CAS high going. If CAS goes high before RAS high going, the open circuit condition of the output is achieved by RAS high going. 14. tASC ≥6ns, Assume tT = 2.0ns. 15. In order to hold the address latched by the first CAS going low, the parameter tCLCH must be met. 16. The last CASx edge to go low. 17. The last CASx edge to go high. 18. The first CASx edge to go low. 19. The first CASx edge to go high. 20. Output parameter is refrenced to corresponding CASx input. 21. The last rising CASx edge to next cycle′s last rising CASx edge. 22. The last rising CASx edge to first falling CASx edge. 23. The first DQx controlled by the first CASx to go low. 24. The last DQx controlled by the last CASx to go high. 25. Each CASx must meet minimum pulse width. 26. The last falling CASx edge to the first rising CASx edge. 27. If tRASS ≥100us, then RAS precharge time must use tRPS instead of tRP. 28. For RAS-only refresh and burst CAS-before-RAS refresh mode, 4096(4K)/2048(2K) cycles of burst refresh must be executed within 64ms/32ms before and after self refresh, in order to meet refresh specification. 29. For distributed CAS-before-RAS with 15.6us interval, CAS-before-RAS refresh should be executed with in 15.6us immediately before and after self refresh in order to meet refresh specification. KM44C4005C, KM44C4105C READ CYCLE CMOS DRAM tRC tRAS RAS VIH VIL - tRP tCSH tCRP CAS0 VIH VIL - tCRP tRSH tCAS tRCD tCRP CAS1 VIH VIL - tCRP CAS2 VIH VIL - tCRP CAS3 VIH VIL - tCLCH tRAD tASR A VIH VIL - tRAH tASC tRAL tCAH COLUMN ADDRESS ROW ADDRESS tRCS W VIH VIL - tRCH tRRH tROH tAA tOEZ tOEA tCAC tCLZ tREZ tCEZ DATA-OUT OE VIH VIL - DQ0 ~ DQ3 VIH VIL - tRAC OPEN tOLZ tWEZ Don′t care Undefined KM44C4005C, KM44C4105C WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN CMOS DRAM tRC tRAS RAS VIH VIL - tRP tCSH tCRP CAS0 VIH VIL - tCRP tRSH tCAS tRCD tCRP CAS1 VIH VIL - tCRP CAS2 VIH VIL - tCRP CAS3 VIH VIL - tCLCH tCSH tASC tRAL tCAH COLUMN ADDRESS tRAD tASR A VIH VIL - tRAH ROW ADDRESS tWCS W VIH VIL - tWCH tWP OE VIH VIL - DQ0 ~ DQ3 VIH VIL - tDS tDH DATA-IN Don′t care Undefined KM44C4005C, KM44C4105C WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : DOUT = OPEN CMOS DRAM tRC tRAS RAS VIH VIL - tRP tCSH tCRP CAS0 VIH VIL - tCRP tRSH tCAS tRCD tCRP CAS1 VIH VIL - tCRP CAS2 VIH VIL - tCRP CAS3 VIH VIL - tCLCH tRAD tASR tRAH tASC tRAL tCAH COLUMN ADDRESS A VIH VIL - ROW ADDRESS tCWL tRWL W VIH VIL - tWP OE VIH VIL - tOED tDS tOEH tDH DATA-IN DQ0 ~ DQ3 VIH VIL - Don′t care Undefined KM44C4005C, KM44C4105C READ - MODIFY - WRTIE CYCLE CMOS DRAM tRC tRAS RAS VIH VIL - tRP tCSH tCRP CAS0 VIH VIL - tCRP tRSH tCAS tRCD tCRP CAS1 VIH VIL - tCRP CAS2 VIH VIL - tCRP CAS3 VIH VIL - tCLCH tRAD tASR tRAH tASC tRAL tCAH COLUMN ADDRESS A VIH VIL - ROW ADDRESS tAWD tCWD W VIH VIL - tRWL tCWL tWP OE VIH VIL - tRWD tOEA tCLZ tCAC tAA tRAC VALID DATA-OUT tOED tOEZ tDS DQ0 ~ DQ3 VIH VIL - tDH VALID DATA-IN tOLZ Don′t care Undefined KM44C4005C, KM44C4105C HYPER PAGE MODE READ CYCLE CMOS DRAM tRASP RAS VIH VIL - tRP tRHCP tCRP CAS0 VIH VIL VIH CAS1 VIL VIH CAS2 VIL VIH CAS3 VIL - tHPC tRCD tCAS tASC tCLCH tCP ¡ó tHPC tCP tRSH tCAS tCLCH tCAS ¡ó ¡ó tRAL tRAD tASR tRAH tCSH tASC tCAH COLUMN ADDRESS ¡ó tASC tCAH ¡ó ¡ó tASC tCAH COLUMN ADDRESS A VIH VIL - ROW ADDR COLUMN ADDRESS tRCS W VIH VIL - tRCH tAA tOEA tRCS tAA tCPA tRCH ¡ó tRCS tAA tCPA tRRH tRCH OE VIH VIL - ¡ó ¡ó tCAC tRAC tCLZ tOEZ VALID DATA-OUT tCLZ ¡ó tOEZ VALID DATA-OUT tOEZ VALID DATA-OUT DQ0 VIH VIL VIH VIL - tCLZ VALID DATA-OUT DQ1 ¡ó VALID DATA-OUT tRAC DQ2 VIH VIL VIH VIL VALID DATA-OUT ¡ó VALID DATA-OUT tOLZ tCLZ ¡ó VALID DATA-OUT DQ3 Don't care Undefined KM44C4005C, KM44C4105C HYPER PAGE MODE WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN CMOS DRAM tRASP RAS VIH VIL - tRP tRHCP tCRP CAS0 VIH VIL VIH VIL VIH VIL VIH VIL - tHPC tRCD tCAS tCP ¡ó tHPC tCP tRSH tCAS tCAS ¡ó CAS1 tCAS ¡ó tCAS CAS2 tCAS tCAS ¡ó CAS3 tRAD tASC tASR tRAH tCAS ¡ó tCSH tCAH COLUMN ADDRESS tASC tCAH ¡ó ¡ó tASC tCAH A VIH VIL - ROW ADDR COLUMN ADDRESS COLUMN ADDRESS tWCS W VIH VIL - tWCH tWP tWCS tWP tWCH ¡ó tWCS tWCH tWP OE VIH VIL - ¡ó ¡ó tDS DQ0 VIH VIL VIH VIL VIH VIL VIH VIL - tDH tDS tDH ¡ó tDS tDH VALID DATA-IN VALID DATA-IN ¡ó ¡ó VALID DATA-IN tDS DQ1 tDH ¡ó tDS tDH VALID DATA-IN VALID DATA-IN tDS DQ2 tDH tDS tDH ¡ó VALID DATA-IN VALID DATA-IN ¡ó ¡ó tDS DQ3 tDH VALID DATA-IN ¡ó Don′t care Undefined KM44C4005C, KM44C4105C HYPER PAGE READ - MODIFY - WRITE CYCLE CMOS DRAM tRASP RAS VIH VIL - tRP tPRWC tRSH tCRP tRCD CAS0 VIH VIL VIH VIL VIH VIL VIH VIL - tCP tCAS tCAS CAS1 tCLCH tCAS CAS2 tCAS tCAS CAS3 tCAS tRAD tRAH tASC COL. ADDR tCLCH tCSH tCAH tRAL tASC COL. ADDR tASR A VIH VIL ROW ADDR tCAH tRCS W VIH VIL - tCWL tWP tCWD tAWD tRWD tOEA tOED tCAC tAA tOEZ tDH tDS tCWD tAWD tOEA tCAC tAA tOEZ tCLZ VALID DATA-OUT VALID DATA-IN VALID DATA-OUT tRWL tCWL tWP OE VIH VIL - tOED tDH tDS DQ0 ~ DQ3 VIH VIL - tRAC tCLZ VALID DATA-IN Don′t care Undefined KM44C4005C, KM44C4105C RAS - ONLY REFRESH CYCLE* NOTE : W, OE, DIN = Don′t care DOUT = OPEN tRC tRP CMOS DRAM tRAS RAS VIH VIL - tCRP CASX VIH VIL - tRPC tCRP tASR A VIH VIL ROW ADDR tRAH CAS - BEFORE - RAS REFRESH CYCLE NOTE : OE, A = Don′t care tRC tRP RAS VIH VIL - tRAS tRP tRPC tCP tRPC tCSR tWRP tWRH tCHR CASX VIH VIL - W VIH VIL - DQ0 ~ DQ3 VIH VIL - tCEZ OPEN Don′t care Undefined KM44C4005C, KM44C4105C HIDDEN REFRESH CYCLE ( READ ) CMOS DRAM tRC tRAS RAS VIH VIL - tRC tRP tRAS tRP tCRP CASX VIH VIL - tRCD tRSH tCHR tRAD tASR A VIH VIL - tRAH tASC tCAH COLUMN ADDRESS ROW ADDRESS tWRH tRCS W VIH VIL - tAA OE VIH VIL - tOEA tCAC tRAC tCLZ tOEZ DATA-OUT tCEZ DQX VIH VIL - OPEN Don′t care Undefined KM44C4005C, KM44C4105C HIDDEN REFRESH CYCLE ( WRITE ) NOTE : DOUT = OPEN CMOS DRAM tRC RAS VIH VIL - tRC tRP tRAS tRP tRAS tCRP CASX VIH VIL - tRCD tRAD tRSH tCHR tASR A VIH VIL - tRAH tASC tCAH COLUMN ADDRESS ROW ADDRESS tWRH tWCS W VIH VIL - tWRP tWCH tWP OE VIH VIL - tDS DQX VIH VIL DATA-IN tDH Don′t care Undefined KM44C4005C, KM44C4105C CAS - BEFORE - RAS SELF REFRESH CYCLE NOTE : OE, A = Don′t care, WE=Vcc-0.2V CMOS DRAM tRP RAS VIH VIL - tRASS tRPS tRPC tCHS tRPC tCP CASX VIH VIL - tCSR DQ0 ~ DQ3 VOH VOL - tCEZ OPEN TEST MODE IN CYCLE NOTE : OE, A = Don′t care tRC tRP RAS VIH VIL - tRAS tRP tCRP tCP tRPC tCSR tWTS tWTH tCHR CASX VIH VIL - W VIH VIL - DQ0 ~ DQ3 VIH VIL - tCEZ OPEN Don′t care Undefined KM44C4005C, KM44C4105C PACKAGE DIMENSION 28 SOJ 300mil CMOS DRAM Units : Inches (millimeters) #28 0.330 (8.39) 0.340 (8.63) 0.300 (7.62) 0.260 (6.61) 0.280 (7.11) 0.006 (0.15) 0.012 (0.30) #1 0.027 (0.69) MIN 0.741 (18.82) MAX 0.720 (18.30) 0.730 (18.54) 0.148 (3.76) MAX 0.026 (0.66) 0.032 (0.81) 0.015 (0.38) 0.021 (0.53) 0.0375 (0.95) 0.050 (1.27) 28 TSOP(II) 300mil Units : Inches (millimeters) 0.355 (9.02) 0.371 (9.42) 0.300 (7.62) 0.004 (0.10) 0.010 (0.25) 0.741 (18.81) MAX 0.721 (18.31) 0.729 (18.51) 0.047 (1.20) MAX 0.010 (0.25) TYP 0.018 (0.45) 0.030 (0.75) 0~8 O 0.037 (0.95) 0.050 (1.27) 0.002 (0.05) MIN 0.012 (0.30) 0.020 (0.50)