KM44V1000D

KM44C1000D, KM44V1000D CMOS DRAM 1M x 4Bit CMOS Dynamic RAM with Fast Page Mode DESCRIPTION This is a family of 1,048,576 x 4bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells within the same row. Power supply voltage (+5V or +3.3V), access time (-5, -6 or -7), power consumption(Normal or Low power), and package type (SOJ or TSOP-II) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, self-refresh operation is available in 3.3V Low power version. This 1Mx4 Fast Page Mode DRAM family is fabricated using Samsung′s advanced CMOS process to realize high band-width, low power consumption and high reliability. It may be used as main memory for main frames and mini computers, personal computer and high performance microprocessor systems. FEATURES • Part Identification - KM44C1000D/D-L(5V, 1K Ref.) - KM44V1000D/D-L(3.3V, 1K Ref.) • Fast Page Mode operation • CAS-before-RAS refresh capability • RAS-only and Hidden refresh capability • Self-refresh capability (3.3V, L-ver only) • Fast parallel test mode capability • TTL(5V)/LVTTL(3.3V) compatible inputs and outputs • Early write or output enable controlled write • Active Power Dissipation Unit : mW Speed -5 -6 -7 3.3V 220 200 5V 470 415 360 • JEDEC Standard pinout • Available in 26(20)-pin SOJ 300mil and TSOP(II) 300mil packages • Single +5V±10% power supply(5V product) • Single +3.3V±0.3V power supply(3.3V product) FUNCTIONAL BLOCK DIAGRAM • Refresh Cycles Part NO. KM44C1000D KM44V1000D Refresh cycle 1K Refresh Period Normal 16ms L-ver 128ms Refresh Timer Refresh Control Row Decoder Sense Amps & I/O Data in Buffer RAS CAS W Control Clocks VBB Generator Vcc Vss • Performance Range Speed -5 -6 -7 Refresh Counter tRAC 50ns 60ns 70ns tCAC 15ns 15ns 20ns tRC 90ns 110n 130n tPC 35ns 40ns 45ns Remark 5V only 5V/3.3V 5V/3.3V A0~A9 Col. Address Buffer Row Address Buffer Memory Array 1,048,576 x4 Cells DQ0 to DQ3 Data out Buffer Column Decoder OE SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. KM44C1000D, KM44V1000D CMOS DRAM PIN CONFIGURATION (Top Views) •KM44C/V1000DJ •KM44C/V1000DT DQ0 DQ1 W RAS A9 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VSS DQ3 DQ2 CAS OE A8 A7 A6 A5 A4 DQ0 DQ1 W RAS A9 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VSS DQ3 DQ2 CAS OE A8 A7 A6 A5 A4 ( SOJ ) ( TSOP-II ) Pin Name A0 - A9 DQ0 - 3 VSS RAS CAS W OE VCC Pin function Address Inputs Data In/out Ground Row Address Strobe Column Address Strobe Read/Write Input Data Output Enable Power(+5V) Power(+3.3V) KM44C1000D, KM44V1000D ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to VSS Voltage on VCC supply relative to VSS Storage Temperature Power Dissipation Short Circuit Output Current Symbol 3.3V VIN, VOUT VCC Tstg PD IOS -0.5 to +4.6 -0.5 to +4.6 -55 to +150 600 50 Rating 5V CMOS DRAM Units -1 to +7.0 -1 to +7.0 -55 to +150 600 50 V V °C mW mA * Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA= 0 to 70°C) Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Symbol Min VCC VSS VIH VIL 3.0 0 2.0 -0.3*2 3.3V Typ 3.3 0 Max 3.6 0 VCC+0.3*1 0.8 Min 4.5 0 2.4 -0.1*2 5V Typ 5.0 0 Max 5.5 0 VCC+1.0*1 0.8 V V V V Units *1 : VCC +1.3V/15ns(3.3V), VCC +2.0V/20ns(5V), Pulse width is measured at VCC *2 : - 1.3V/15ns(3.3V), - 2.0V/20ns(5V), Pulse width is measured at VSS DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.) Parameter Input Leakage Current (Any input 0≤VIN≤VCC+0.3V, all other input pins not under test=0 Volt) 3.3V Output Leakage Current (Data out is disabled, 0V≤VOUT ≤VCC) Output High Voltage Level(IOH=-2mA) Output Low Voltage Level(IOL=2mA) Input Leakage Current (Any input 0≤VIN≤VCC+0.5V, all other input pins not under test=0 Volt) 5V Output Leakage Current (Data out is disabled, 0V≤VOUT ≤VCC) Output High Voltage Level(IOH=-5mA) Output Low Voltage Level(IOL=4.2mA) Symbol II(L) IO(L) VOH VOL II(L) IO(L) VOH VOL Min -5 -5 2.4 -5 -5 2.4 Max 5 5 0.4 5 5 0.4 Units uA uA V V uA uA V V KM44C1000D, KM44V1000D Max KM44V1000D ICC1 ICC2 ICC3 Don′t Care Don′t Care Don′t Care -5 -6 -7 Don′t Care -5 -6 -7 -5 -6 -7 Don′t Care -5 -6 -7 Don′t Care Don′t Care 60 55 1 60 55 45 40 0.5 100 60 55 200 150 CMOS DRAM DC AND OPERATING CHARACTERISTICS (Recommend operating conditions unless otherwise noted.) Symbol Power Speed Units KM44C1000D 85 75 65 2 85 75 65 65 55 45 1 200 85 75 65 300 mA mA mA mA mA mA mA mA mA mA mA uA mA mA mA uA uA ICC4 Don′t Care Normal L Don′t Care L L ICC5 ICC6 ICC7 ICCS ICC1 * : Operating Current (RAS and CAS cycling @tRC=min.) ICC2 : Standby Current (RAS=CAS=W=VIH) ICC3 * : RAS-only Refresh Current (CAS=VIH, RAS, Address cycling @tRC=min.) ICC4 * : Fast Page Mode Current (RAS=VIL, CAS, Address cycling @tPC=min.) ICC5 : Standby Current (RAS=CAS=W=VCC-0.2V) ICC6 * : CAS-Before-RAS Refresh Current (RAS and CAS cycling @tRC=min) ICC7 : Battery back-up current, Average power supply current, Battery back-up mode Input high voltage(VIH)=VCC-0.2V, Input low voltage(VIL)=0.2V, CAS=0.2V, DQ=Don′t Care, TRC=125us(L-ver.), TRAS =TRAS min~300ns ICCS : Self refresh current RAS=CAS=VIL, W=OE =A0 ~ A9=VCC- 0.2V or 0.2V DQ0 ~ DQ3=VCC- 0.2V, 0.2V or OPEN *Note : ICC1 , ICC3 , ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1 , ICC3 ICC6 and ICC7, address can be changed maximum once while RAS=VIL. In ICC4 , address can be changed maximum once within one fast page mode cycle time, tPC. KM44C1000D, KM44V1000D CAPACITANCE (TA=25°C, VCC=5V or 3.3V, f=1MHz) Parameter Input capacitance [A0 ~ A9] Input capacitance [RAS, CAS, W, OE] Output capacitance [DQ0 - DQ3] Symbol CIN1 CIN2 CDQ Min - CMOS DRAM Max 5 7 7 Units pF pF pF AC CHARACTERISTICS (0°C≤T≤70°C, See note 1,2) Test condition (5V device) : VCC=5.0V±10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.4/0.4V Test condition (3.3V device) : VCC=3.3V±0.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V Parameter Random read or write cycle time Read-modify-write cycle time Access time from RAS Access time from CAS Access time from column address CAS to output in Low-Z Output buffer turn-off delay Transition time (rise and fall) RAS precharge time RAS pulse width RAS hold time CAS hold time CAS pulse width RAS to CAS delay time RAS to column address delay time CAS to RAS precharge time Row address set-up time Row address hold time Column address set-up time Column address hold time Column address to RAS lead time Read command set-up time Read command hold time referenced to CAS Read command hold time referenced to RAS Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Note) *1 : 5V only Symbol Min -5*1 Max Min 110 152 50 15 25 0 0 3 30 50 15 50 15 20 15 5 0 10 0 10 25 0 0 0 10 10 15 13 10K 35 25 10K 12 50 0 0 3 40 60 15 60 15 20 15 5 0 10 0 10 30 0 0 0 10 10 15 15 10K 45 30 10K 12 50 60 15 30 0 0 3 50 70 20 70 20 20 15 5 0 10 0 15 35 0 0 0 15 15 15 15 10K 50 35 10K 17 50 -6 Max Min 130 177 70 20 35 7 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 8 4 10 3,4,10 3,4,5 3,10 3 6 2 Units Notes tRC tRWC tRAC tCAC tAA tCLZ tOFF tT tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCH tWP tRWL tCWL 90 132 KM44C1000D, KM44V1000D AC CHARACTERISTICS (0°C≤TA≤70°C, See note 2) Parameter Data set-up time Data hold time Refresh period (Normal) Refresh period (L-ver) Write command set-up time CAS to W delay time RAS to W delay time Column address to W delay time CAS precharge to W delay time CAS set-up time (CAS-before-RAS refresh) CAS hold time (CAS-before-RAS refresh) RAS to CAS precharge time CAS precharge time (C-B-R counter test cycle) Access time from CAS precharge Fast Page mode cycle time Fast Page read-modify-write cycle time CAS precharge time (Fast Page cycle) RAS pulse width (Fast Page cycle) RAS hold time from CAS precharge OE access time OE to data delay Out put buffer turn off delay time from OE OE command hold time Write command set-up time (Test mode in) Write command hold time (Test mode in) W to RAS precharge time (C-B-R refresh) W to RAS hold time (C-B-R refresh) RAS pulse width (C-B-R self refresh) RAS precharge time (C-B-R self refresh) CAS Hold time (C-B-R self refresh) Note) *1 : 5V only Symbol Min -5*1 Max Min 0 10 16 128 0 37 72 47 52 10 10 5 20 30 35 77 10 50 30 15 12 0 15 10 10 10 10 100 90 -50 12 12 0 15 10 10 10 10 100 110 -50 12 200K 40 82 10 60 35 15 17 0 20 10 10 10 10 100 130 -50 200K 0 37 82 52 57 10 10 5 20 35 45 97 10 70 40 16 128 0 47 97 62 67 10 15 5 25 0 10 -6 Max Min 0 15 -7 CMOS DRAM Units Max ns ns 16 128 ms ms ns ns ns ns ns ns ns ns ns 40 ns ns ns ns 200K ns ns 20 ns ns 17 ns ns ns ns ns ns us ns ns Notes 9 9 tDS tDH tREF tREF tWCS tCWD tRWD tAWD tCPWD tCSR tCHR tRPC tCPT tCPA tPC tPRWC tCP tRASP tRHCP tOEA tOED tOEZ tOEH tWTS tWTH tWRP tWRH tRASS tRPS tCHS 7 7 7 7 7 3 6 14,15,16 14,15,16 14,15,16 KM44C1000D, KM44V1000D TEST MODE CYCLE Parameter Random read or write cycle time Read-modify-write cycle time Access time from RAS Access time from CAS Access time from column address RAS pulse width CAS pulse width RAS hold time CAS hold time Column Address to RAS lead time CAS to W delay time RAS to W delay time Column Address to W delay time Fast Page mode cycle time Fast Page mode read-modify-write cycle RAS pulse width (Fast Page cycle) Access time from CAS precharge OE access time OE to data delay OE command hold time Note) *1 : 5V only Symbol Min -5*1 Max Min 115 160 55 18 30 55 18 18 55 30 41 78 53 40 81 55 200K 35 20 18 18 20 20 10K 10K 65 20 20 65 35 45 90 60 45 90 65 200K 40 20 25 25 65 20 35 10K 10K 75 25 25 75 40 55 105 70 50 105 75 -6 Max Min 135 190 -7 CMOS DRAM ( Note 11 ) Units Max ns ns 75 25 40 10K 10K ns ns ns ns ns ns ns ns ns ns ns ns ns 200K 45 25 ns ns ns ns ns 3 7 7 7 3,4,10 3,4,5 3,10 Notes tRC tRWC tRAC tCAC tAA tRAS tCAS tRSH tCSH tRAL tCWD tRWD tAWD tPC tPRWC tRASP tCPA tOEA tOED tOEH 95 138 KM44C1000D, KM44V1000D NOTES CMOS DRAM 1. An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles before proper device operation is achieved. 2. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and VIL(max) and are assumed to be 5ns for all inputs. 3. Measured with a load equivalent to 2 TTL(5V)/1 TTL(3.3V) loads and 100pF. 4. Operation within the tRCD (max) limit insures that tRAC (max) can be met. tRCD (max) is specified as a reference point only. If tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 5. Assumes that tRCD ≥tRCD (max). 6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to Voh or Vol. 7. tWCS , tRWD , tCWD , tAWD and tCPWD are non restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥tWCS (min), the cycle is an early write cycle and the data output will remain high impedance for the duration of the cycle. If tCWD ≥tCWD (min), tRWD ≥tRWD (min), tAWD ≥tAWD (min) and tCPWD ≥tCPWD (min) then the cycle is a read-modify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the condition of the data out is indeterminate. 8. Either tRCH or tRRH must be satisfied for a read cycle. 9. These parameters are referenced to CAS falling edge in early write cycles and to W falling edge in read-modify-write cycles. 10. Operation within the tRAD (max) limit insures that tRAC (max) can be met. tRAD (max) is specified as a reference point only. If tRAD is greater than the specified tRAD (max) limit, then access time is controlled by tAA. 11. These specifiecations are applied in the test mode. 12. In test mode read cycle, the value of tRAC , tAA, tCAC is delayed by 2ns to 5ns for the specified values. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. 13. tOFF(MAX) defines the time at which the output achieves the open circuit condition and are not referenced to output voltage level. 14. If tRASS ≥100us, then RAS precharge time must use tRPS instead of tRP. 15. For RAS-only refresh and burst CAS-before-RAS refresh mode, 1024(1K) cycle of burst refresh must be executed within 16ms before and after self refresh, in order to meet refresh specification. 16. For distributed CAS-before-RAS with 15.6us interval, CAS-before-RAS refresh should be executed with in 15.6us immediately before and after self refresh in order to meet refresh specification. KM44C1000D, KM44V1000D READ CYCLE CMOS DRAM tRC tRAS RAS VIH VIL - tRP tCSH tCRP CAS VIH VIL - tRCD tRSH tCAS tRAL tCAH COLUMN ADDRESS tCRP tRAD tASR A VIH VIL - tRAH tASC ROW ADDRESS tRCS W VIH VIL - tRCH tRRH tOFF tAA tOEZ tOEA tCAC OE VIH VIL - DQ0 ~ DQ3(7) VOH VOL - tRAC OPEN tCLZ DATA-OUT Don′t care Undefined KM44C1000D, KM44V1000D WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN CMOS DRAM tRAS RAS VIH VIL - tRC tRP tCSH tCRP CAS VIH VIL - tRCD tRSH tCAS tRAL tCAH COLUMN ADDRESS tCRP tRAD tASR A VIH VIL - tRAH tASC ROW ADDRESS tCWL tRWL tWCS W VIH VIL - tWCH tWP OE VIH VIL - DQ0 ~ DQ3(7) VIH VIL - tDS tDH DATA-IN Don′t care Undefined KM44C1000D, KM44V1000D WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : DOUT = OPEN CMOS DRAM tRC tRAS RAS VIH VIL - tRP tCSH tCRP CAS VIH VIL - tRCD tRSH tCAS tRAL tCAH COLUMN ADDRESS tCRP tRAD tASR tRAH tASC A VIH VIL - ROW ADDRESS tCWL tRWL W VIH VIL - tWP OE VIH VIL - tOED tDS tOEH tDH DATA-IN DQ0 ~ DQ3(7) VIH VIL - Don′t care Undefined KM44C1000D, KM44V1000D READ - MODIFY - WRTIE CYCLE CMOS DRAM tRWC tRAS RAS VIH VIL - tRP tCRP CAS VIH VIL - tRCD tRAD tRAH tRSH tCAS tCAH tCSH tASR VIH VIL - tASC COLUMN ADDRESS A ROW ADDR tAWD tCWD W VIH VIL - tRWL tCWL tWP OE VIH VIL - tRWD tOEA tCLZ tCAC tAA tRAC VALID DATA-OUT tOED tOEZ DQ0 ~ DQ3(7) VI/OH VI/OL - tDS tDH VALID DATA-IN Don′t care Undefined KM44C1000D, KM44V1000D FAST PAGE READ CYCLE CMOS DRAM tRASP RAS VIH VIL ¡ó tRP tRHCP tCRP CAS VIH VIL - tPC tRCD tCAS tRAD tASC tCSH tCAH COLUMN ADDRESS tCP tCAS ¡ó tCP tRSH tCAS tASR A VIH VIL ROW ADDR tRAH tASC tCAH ¡ó ¡ó tASC tCAH COLUMN ADDRESS COLUMN ADDRESS tRCS W VIH VIL - tRCH tRCS ¡ó tRAL tRCS tRRH tRCH tCAC tOEA OE VIH VIL - tCAC tOEA ¡ó ¡ó tCAC tOEA tAA DQ0 ~ DQ3(7) VOH VOL - tRAC tCLZ tOEZ VALID DATA-OUT tAA tOFF tCLZ tOEZ VALID DATA-OUT tAA tOFF tCLZ VALID DATA-OUT tOFF tOEZ Don′t care Undefined KM44C1000D, KM44V1000D FAST PAGE WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN CMOS DRAM tRASP RAS VIH VIL ¡ó tRP tRHCP tCRP CAS VIH VIL - tPC tRCD tCAS tRAD tASC tCP tCAS ¡ó tPC tCP tRSH tCAS tRAL tASR A VIH VIL - tRAH tCSH tCAH COLUMN ADDRESS tASC tCAH ¡ó ¡ó tASC tCAH ROW ADDR COLUMN ADDRESS COLUMN ADDRESS tWCS W VIH VIL - tWCH tWP tCWL tWCS tWP tWCH ¡ó tWCS tWCH tWP tCWL tRWL tCWL ¡ó ¡ó OE VIH VIL - DQ0 ~ DQ3(7) VIH VIL - tDS tDH tDS tDH ¡ó tDS tDH VALID DATA-IN VALID DATA-IN ¡ó VALID DATA-IN Don′t care Undefined KM44C1000D, KM44V1000D FAST PAGE READ - MODIFY - WRITE CYCLE CMOS DRAM tRASP RAS VIH VIL - tRP tCSH tRCD tRSH tCP tCAS tRAD tRAH tASR tASC COL. ADDR tCRP tCAS tPRWC CAS VIH VIL - tCAH tRAL tASC COL. ADDR tCAH A VIH VIL - ROW ADDR tRCS W VIH VIL - tRWL tCWL tWP tCWD tAWD tRWD tOEA tOED tCAC tAA tOEZ tDH tDS tCWD tAWD tCPWD tOEA tCAC tAA tOEZ tOED tDH tDS tCWL tWP OE VIH VIL - DQ0 ~ DQ3(7) VI/OH VI/OL - tRAC tCLZ tCLZ VALID DATA-OUT VALID DATA-IN VALID DATA-OUT VALID DATA-IN Don′t care Undefined KM44C1000D, KM44V1000D RAS - ONLY REFRESH CYCLE NOTE : W, OE, DIN = Don′t care DOUT = OPEN tRC tRP CMOS DRAM tRAS RAS VIH VIL - tCRP CAS VIH VIL - tRPC tCRP tASR A VIH VIL ROW ADDR tRAH CAS - BEFORE - RAS REFRESH CYCLE NOTE : OE, A = Don′t care tRC tRP RAS VIH VIL - tRAS tRP tRPC tCP tRPC tCSR tWRP tWRH tCHR CAS VIH VIL - W VIH VIL - DQ0 ~ DQ3(7) VOH VOL - tOFF OPEN Don′t care Undefined KM44C1000D, KM44V1000D HIDDEN REFRESH CYCLE ( READ ) CMOS DRAM tRC tRAS RAS VIH VIL - tRC tRP tRAS tRP tCRP CAS VIH VIL - tRCD tRSH tCHR tRAD tASR A VIH VIL - tRAH tASC tCAH COLUMN ADDRESS ROW ADDRESS tRAL tRCS W VIH VIL - tWRH tAA OE VIH VIL - tOEA tCAC tOFF tOEZ DATA-OUT DQ0 ~ DQ3(7) VOH VOL - tRAC OPEN tCLZ Don′t care Undefined KM44C1000D, KM44V1000D HIDDEN REFRESH CYCLE ( WRITE ) NOTE : DOUT = OPEN CMOS DRAM tRC RAS VIH VIL - tRC tRP tRAS tRP tRAS tCRP CAS VIH VIL - tRCD tRAD tRSH tCHR tASR A VIH VIL - tRAH tASC tCAH COLUMN ADDRESS ROW ADDRESS tRAL VIH VIL - tWRH tWRP tWCS tWP tWCH W OE VIH VIL - tDS DQ0 ~ DQ3(7) VIH VIL - tDH DATA-IN Don′t care Undefined KM44C1000D, KM44V1000D CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE CMOS DRAM tRP RAS VIH VIL VIH VIL - tRAS tCPT tCHR tRSH tCAS tRAL tASC tCAH tCSR CAS A VIH VIL - COLUMN ADDRESS READ CYCLE W VIH VIL VIH VIL - tWRP tWRH tRCS tAA tCAC tRRH tRCH OE DQ0 ~ DQ3(7) VOH VOL - tCLZ tOEA tOEZ DATA-OUT WRITE CYCLE W VIH VIL VIH VIL - tOFF tWRP tWRH tWCS tRWL tCWL tWCH tWP OE tDS DQ0 ~ DQ3(7) VIH VIL - tDH DATA-IN READ-MODIFY-WRITE tWRP W VIH VIL - tWRH tRCS tAWD tCWD tCAC tWP tCWL tRWL tAA tOEA OE VIH VIL - tOED tCLZ tOEZ tDS tDH DQ0 ~ DQ3(7) VI/OH VI/OL VALID DATA-OUT VALID DATA-IN Don′t care Undefined KM44C1000D, KM44V1000D CAS - BEFORE - RAS SELF REFRESH CYCLE NOTE : OE, A = Don′t care CMOS DRAM tRP RAS VIH VIL - tRASS tRPS tRPC tCHS tRPC tCP CAS VIH VIL - tCSR DQ0 ~ DQ3(7) VOH VOL - tOFF OPEN tWRP tWRH W VIH VIL - TEST MODE IN CYCLE NOTE : OE, A = Don′t care tRC tRP RAS VIH VIL - tRAS tRP tRPC tCP tRPC tCSR tWTS tWTH tCHR CAS VIH VIL - W VIH VIL - DQ0 ~ DQ3(7) VOH VOL - tOFF OPEN Don′t care Undefined KM44C1000D, KM44V1000D PACKAGE DIMENSION 26(20) SOJ 300mil CMOS DRAM Units : Inches (millimeters) #26(20) 0.300 (7.62) 0.260 (6.61) 0.330 (8.39) 0.340 (8.63) 0.280 (7.11) 0.006 (0.15) 0.012 (0.30) 0.027 (0.69) MIN 0.691 (17.55) MAX 0.670 (17.03) 0.680 (17.27) 0.148 (3.76) MAX 0.026 (0.66) 0.032 (0.81) 0.015 (0.38) 0.021 (0.53) 0.0375 (0.95) 0.050 (1.27) 26(20) TSOP(II) 300mil Units : Inches (millimeters) 0.355 (9.02) 0.371 (9.42) 0.300 (7.62) 0.004 (0.10) 0.010 (0.25) 0.691 (17.54) MAX 0.671 (17.04) 0.679 (17.24) 0.047 (1.20) MAX 0.010 (0.25) TYP 0.018 (0.45) 0.030 (0.75) 0~8 O 0.037 (0.95) 0.050 (1.27) 0.002 (0.05) MIN 0.012 (0.30) 0.020 (0.50)