KM48S8030C

KM48S8030C Revision History Revision 0.0 (Oct., 1998) • PC133 first published. Preliminary PC133 CMOS SDRAM REV. 0 Oct. '98 KM48S8030C 2M x 8Bit x 4 Banks Synchronous DRAM FEATURES • • • • JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs -. CAS latency 3 only -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Burst read single-bit write operation DQM for masking Auto & self refresh 64ms refresh period (4K Cycle) Preliminary PC133 CMOS SDRAM GENERAL DESCRIPTION The KM48S8030C is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 8 bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. • • • • • ORDERING INFORMATION Part No. KM48S8030CT-G/FA Max Freq. 133MHz (CL 3) Interface Package LVTTL 54 TSOP(II) FUNCTIONAL BLOCK DIAGRAM I/O Control LWE LDQM Data Input Register Bank Select 2M x 8 Sense AMP 2M x 8 2M x 8 2M x 8 Refresh Counter Output Buffer Row Decoder Row Buffer DQi Address Register CLK ADD Column Decoder Col. Buffer Latency & Burst Length LRAS LCBR LCKE LRAS LCBR LWE LCAS Timing Register Programming Register LWCBR LDQM CLK CKE CS RAS CAS WE DQM * Samsung Electronics reserves the right to change products or specification without notice. REV. 0 Oct. '98 KM48S8030C PIN CONFIGURATION (Top view) VDD DQ0 VDDQ N.C DQ1 VSSQ N.C DQ2 VDDQ N.C DQ3 VSSQ N.C VDD N.C WE CAS RAS CS BA0 BA1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS DQ7 VSSQ N.C DQ6 VDDQ N.C DQ5 VSSQ N.C DQ4 VDDQ N.C VSS N.C/RFU DQM CLK CKE N.C A11 A9 A8 A7 A6 A5 A4 VSS Preliminary PC133 CMOS SDRAM 54Pin TSOP (II) (400mil x 875mil) (0.8 mm Pin pitch) PIN FUNCTION DESCRIPTION Pin CLK CS Name System clock Chip select Input Function Active on the positive going edge to sample all inputs. Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA11, Column address : CA0 ~ CA8 Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. Data inputs/outputs are multiplexed on the same pins. Power and ground for the input buffers and the core logic. Isolated power supply and ground for the output buffers to provide improved noise immunity. This pin is recommended to be left No Connection on the device. CKE Clock enable A0 ~ A11 BA0 ~ BA1 RAS CAS WE DQM DQ0 ~ 7 VDD/VSS VDDQ/VSSQ N.C/RFU Address Bank select address Row address strobe Column address strobe Write enable Data input/output mask Data input/output Power supply/ground Data output power/ground No connection /reserved for future use REV. 0 Oct. '98 KM48S8030C ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD, VDDQ TSTG PD IOS Preliminary PC133 CMOS SDRAM Value -1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ +150 1 50 Unit V V °C W mA Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS Parameter Supply voltage Input logic high voltage Input logic low voltage Output logic high voltage Output logic low voltage Input leakage current (Inputs) Input leakage current (I/O pins) Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C) Symbol VDD, VDDQ VIH VIL VOH VOL IIL IIL Min 3.0 2.0 -0.3 2.4 -1 -1.5 Typ 3.3 3.0 0 Max 3.6 VDDQ+0.3 0.8 0.4 1 1.5 Unit V V V V V uA uA 1 2 IOH = -2mA IOL = 2mA 3 3,4 Note Notes : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns. 3. Any input 0V ≤ VIN ≤ VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. 4. Dout is disabled, 0V ≤ VOUT ≤ VDDQ. CAPACITANCE Clock (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV) Pin Symbol CCLK CIN CADD COUT Min 2.5 2.5 2.5 4.0 Max 4.0 5.0 5.0 6.5 Unit pF pF pF pF RAS, CAS, WE, CS, CKE, DQM Address DQ0 ~ DQ7 REV. 0 Oct. '98 KM48S8030C DC CHARACTERISTICS Parameter (Recommended operating condition unless otherwise noted, TA = 0 to 70°C) Symbol Test Condition Burst length = 1 tRC ≥ tRC(min) IOL = 0 mA CKE ≤ VIL(max), tCC = 15ns CAS Latency Preliminary PC133 CMOS SDRAM Version -A 75 1 1 12 Unit Note Operating current (One bank active) Precharge standby current in power-down mode ICC1 ICC2P mA 1 ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞ ICC2N CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 15ns Input signals are changed one time during 30ns mA Precharge standby current in non power-down mode CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ ICC2NS Input signals are stable ICC3P CKE ≤ VIL(max), tCC = 15ns mA 6 2 2 20 10 3 110 mA 125 1 450 mA mA uA 2 3 4 1 mA mA Active standby current in power-down mode Active standby current in non power-down mode (One bank active) ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞ ICC3N ICC3NS CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 15ns Input signals are changed one time during 30ns CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable IOL = 0 mA Page burst 2Banks activated tCCD = 2CLKs tRC ≥ tRC(min) CKE ≤ 0.2V mA Operating current (Burst mode) Refresh current Self refresh current ICC4 ICC5 ICC6 Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. KM48S8030CT-G** 4. KM48S8030CT-F** REV. 0 Oct. '98 KM48S8030C AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C) Parameter Input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition 3.3V Preliminary PC133 CMOS SDRAM Value 2.4/0.4 1.4 tr/tf = 1/1 1.4 See Fig. 2 Vtt = 1.4V Unit V V ns V 1200Ω Output 870Ω 50pF VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA Output Z0 = 50Ω 50Ω 50pF (Fig. 1) DC output load circuit (Fig. 2) AC output load circuit OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) Parameter Row active to row active delay RAS to CAS delay Row precharge time Row active time Row cycle time Last data in to row precharge Last data in to new col. address Delay Last data in to burst stop Col. address to col. address delay Number of valid output data Symbol tRRD(min) tRCD(min) tRP(min) tRAS(min) tRAS(max) tRC(min) tRDL(min) tCDL(min) tBDL(min) tCCD(min) CAS latency=3 Version -A 2 3 3 6 100 9 2 1 1 1 2 CLK CLK CLK CLK us CLK CLK CLK CLK CLK ea 1 2 2 2 3 4 1 1 1 1 Unit Note Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. REV. 0 Oct. '98 KM48S8030C AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Parameter CAS latency=3 CLK to valid output delay Output data hold time CAS latency=3 tSAC CAS latency=3 tOH tCH tCL tSS tSH tSLZ tSHZ 2.5 2.5 1.5 0.8 1 2.7 Symbol Min CLK cycle time tCC 7.5 -A Preliminary PC133 CMOS SDRAM Unit Max 1000 5.4 ns ns ns ns ns ns ns 5.4 ns ns Note 1 1,2 2 3 3 3 3 2 CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-Z CLK to output in Hi-Z CAS latency=3 Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. REV. 0 Oct. '98 KM48S8030C SIMPLIFIED TRUTH TABLE Command Register Mode register set Auto refresh Refresh Entry Self refresh Exit L H H CKEn-1 CKEn CS RAS CAS WE Preliminary PC133 CMOS SDRAM DQM BA0,1 A10/AP A11, A9 ~ A0 Note H H X H L H X X L L L H L L H X L H L L H X H L L H H X H H X X OP code X 1,2 3 3 X X X V V X Row address L H Column address (A0 ~ A8) Column address (A0 ~ A8) 3 3 Bank active & row addr. Read & column address Write & Column Address Burst stop Precharge Bank selection All banks Clock suspend or active power down Entry Exit Entry Precharge power down mode Exit DQM No operation command Auto precharge disable Auto precharge enable Auto precharge disable Auto precharge enable L L 4 4,5 4 4,5 6 H H H X X X L L L H L H H L X V X X H X V X L H H X V X X H X V L L L X V X X H X V X X X V L H X V X L H X H L H L H L X X X X X X V X X 7 X H L L H H H H L X H L X H X H X H X (V=Valid, X=Don′t care, H=Logic high, L=Logic low) Notes : 1. OP Code : Operand code A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2) REV. 0 Oct. '98