KM684000ALGI-7L

K6T1008C2E Family Document Title 128Kx8 bit Low Power CMOS Static RAM CMOS SRAM Revision History Revision No. 0.0 1.0 History Design target Finalize - Improve tWP form 55ns to 50ns for 70ns product. - Remove 55ns speed bin from industrial product. Errata correction Revise Revise - Add 55ns parts to industrial products. Draft Data October 12, 1998 August 30, 1999 Remark Preliminary Final 1.01 2.0 3.0 December 1, 1999 February 14, 2000 March 3, 2000 Final Final The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserves the right to change the specifications and products. SAMSUNG Electronics will answer to your questions. If you have any questions, please contact the SAMSUNG branch offices. 1 Revision 3.0 March 2000 K6T1008C2E Family 128Kx8 bit Low Power CMOS Static RAM FEATURES • Process Technology: TFT • Organization: 128Kx8 • Power Supply Voltage: 4.5~5.5V • Low Data Retention Voltage: 2V(Min) • Three state output and TTL Compatible • Package Type: 32-DIP-600, 32-SOP-525, 32-TSOP1-0820F/R CMOS SRAM GENERAL DESCRIPTION The K6T1008C2E families are fabricated by SAMSUNG′s advanced CMOS process technology. The families support various operating temperature ranges and have various package types for user flexibility of system design. The families also support low data retention voltage for battery back-up operation with low data retention current. PRODUCT FAMILY Power Dissipation Product Family K6T1008C2E-L K6T1008C2E-B K6T1008C2E-P K6T1008C2E-F 1. The parameters are tested with 50pF test load Operating Temperature Vcc Range Speed Standby (ISB1, Max) 50µA 10µA 50µA 15µA Operating (ICC2, Max) PKG Type Commercial(0~70°C) 4.5~5.5V Industrial(-40~85°C) 551)/70ns 32-DIP-600, 32-SOP-525 32-TSOP1-0820F/R 50mA 32-SOP -525 32-TSOP1-0820F/R PIN DESCRIPTION A11 A9 A8 A13 WE VCC CS2 A15 A15 VCC CS2 NC WE A16 A14 A13 A12 A7 A8 A6 A5 A9 A4 A11 OE A4 A5 CS 1 A6 A7 I/O8 A12 A14 I/O7 A16 I/O6 NC VCC I/O5 A15 CS2 I/O4 WE A13 A8 A9 A11 A10 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 A3 A2 A1 A0 I/O1 I/O2 I/O3 VSS I/O4 I/O5 I/O6 I/O7 I/O8 CS 1 A10 OE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CS 1 I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2 A3 FUNCTIONAL BLOCK DIAGRAM Clk gen. Precharge circuit. N.C A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 32-TSOP Type1-Forward Raw Address 32-SOP 32-DIP 27 26 25 24 23 22 21 20 19 18 17 Row select Memory array 1024 rows 128 ×8 columns I/O1 I/O8 32-TSOP Type1-Reverse Data cont I/O Circuit Column select Data cont Column Address Name CS 1, CS2 OE WE I/O1~I/O8 A0~A16 Vcc Vss N.C. Function Chip Select Input Output Enable Input Write Enable Input Data Inputs/Outputs Address Inputs Power Ground No Connection CS 1 CS 2 WE OE Control logic SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. 2 Revision 3.0 March 2000 K6T1008C2E Family PRODUCT LIST Commercial Temperature Products(0~70°C) Part Name K6T1008C2E-DL55 K6T1008C2E-DL70 K6T1008C2E-DB55 K6T1008C2E-DB70 K6T1008C2E-GL55 K6T1008C2E-GL70 K6T1008C2E-GB55 K6T1008C2E-GB70 K6T1008C2E-TB55 K6T1008C2E-TB70 K6T1008C2E-RB55 K6T1008C2E-RB70 Function 32-DIP, 55ns, Low Power 32-DIP, 70ns, Low Power 32-DIP, 55ns, Low Low Power 32-DIP, 70ns, Low Low Power 32-SOP, 55ns, Low Power 32-SOP, 70ns, Low Power 32-SOP, 55ns, Low Low Power 32-SOP, 70ns, Low Low Power 32-TSOP F, 55ns, Low Low Power 32-TSOP F, 70ns, Low Low Power 32-TSOP R, 55ns, Low Low Power 32-TSOP R, 70ns, Low Low Power CMOS SRAM Industrial Temperature Products(-40~85°C) Part Name K6T1008C2E-GP55 K6T1008C2E-GP70 K6T1008C2E-GF55 K6T1008C2E-GF70 K6T1008C2E-TF55 K6T1008C2E-TF70 K6T1008C2E-RF55 K6T1008C2E-RF70 Function 32-SOP, 55ns, Low Power 32-SOP, 70ns, Low Power 32-SOP, 55ns, Low Low Power 32-SOP, 70ns, Low Low Power 32-TSOP F, 55ns, Low Low Power 32-TSOP F, 70ns, Low Low Power 32-TSOP R, 55ns, Low Low Power 32-TSOP R, 70ns, Low Low Power FUNCTIONAL DESCRIPTION CS1 H X1) L L L CS2 X 1) OE X 1) WE X 1) I/O High-Z High-Z High-Z Dout Din Mode Deselected Deselected Output Disabled Read Write Power Standby Standby Active Active Active L H H H X1) H L X 1) X1) H H L 1. X means don′t care (Must be in high or low states) ABSOLUTE MAXIMUM RATINGS1) Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage temperature Operating Temperature Symbol VIN,VOUT VCC PD TSTG TA Ratings -0.5 to 7.0 -0.5 to 7.0 1.0 -65 to 150 0 to 70 -40 to 85 Unit V V W °C °C °C Remark K6T1008C2E-L/-B K6T1008C2E-P/-F 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 3 Revision 3.0 March 2000 K6T1008C2E Family RECOMMENDED DC OPERATING CONDITIONS1) Item Supply voltage Ground Input high voltage Input low voltage Symbol Vcc Vss VIH VIL Product K6T1008C2E Family All Family K6T1008C2E Family K6T1008C2E Family Min 4.5 0 2.2 -0.5 3) CMOS SRAM Typ 5.0 0 - Max 5.5 0 Vcc+0.5 0.8 2) Unit V V V V Note: 1. Commercial Product: TA=0 to 70°C Industrial Product: TA=-40 to 85°C, otherwise specified. 2. Overshoot: Vcc+3.0V in case of pulse width≤30ns. 3. Undershoot: -3.0V in case of pulse width≤30ns. 4. Overshoot and undershoot are sampled, not 100% tested. CAPACITANCE1) (f=1MHz, TA=25°C) Item Input capacitance Input/Output capacitance 1. Capacitance is sampled, not 100% tested Symbol CIN CIO Test Condition VIN=0V VIO=0V Min - Max 6 8 Unit pF pF DC AND OPERATING CHARACTERISTICS Item Input leakage current Output leakage current Operating power supply current Average operating current Symbol ILI ILO ICC ICC1 ICC2 Output low voltage Output high voltage Standby Current(TTL) Standby Current(CMOS) VOL VOH ISB ISB1 VIN=Vss to Vcc CS1=VIH or CS2=VIL or OE =VIH or WE=VIL, VIO=Vss to Vcc IIO=0mA, CS1=VIL, CS 2=VIH, VIN=VIH or VIL, Read Cycle time=1µs, 100%duty, I IO=0mA, CS1 ≤0.2V, CS2 ≥Vcc-0.2V, V IN≤0.2V or VIN≥VCC-0.2V Cycle time=Min, 100% duty, IIO=0mA, CS1 =VIL, CS2=VIH, VIN=VIH or VIL Test Conditions Min Typ Max Unit -1 -1 2.4 1 1 10 7 50 0.4 3 50 1) µA µA mA mA mA V V mA µA IOL=2.1mA IOH=-1.0mA CS1=VIH, CS2=VIL, Other inputs=VIH or VIL CS1≥Vcc-0.2V, CS2≥Vcc-0.2V or CS2≤0.2V, Other inputs=0~Vcc 1. 50µA for Low power product, in case of Low Low power products are comercial=10µA, industrial=15µA. 4 Revision 3.0 March 2000 K6T1008C2E Family AC OPERATING CONDITIONS TEST CONDITIONS( Test Load and Input/Output Reference) Input pulse level: 0.8 to 2.4V Input rising and falling time: 5ns Input and output reference voltage:1.5V Output load(see right): CL=100pF+1TTL CL=50pF+1TTL CL1) CMOS SRAM 1. Including scope and jig capacitance AC CHARACTERISTICS (VCC=4.5~5.5V, Commercial Product: TA=0 to 70°C, Industrial Product: TA=-40 to 85°C) Speed Bins Parameter List Symbol Min Read Cycle Time Address Access Time Chip Select to Output Output Enable to Valid Output Read Chip Select to Low-Z Output Output Enable to Low-Z Output Chip Disable to High-Z Output Output Disable to High-Z Output Output Hold from Address Change Write Cycle Time Chip Select to End of Write Address Set-up Time Address Valid to End of Write Write Write Pulse Width Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End Write to Output Low-Z tRC tAA tCO tOE tLZ tOLZ tHZ tOHZ tOH tWC tCW tAS tAW tWP tWR tWHZ tDW tDH tOW 55 10 5 0 0 10 55 45 0 45 40 0 0 20 0 5 55ns Max 55 55 25 20 20 20 Min 70 10 5 0 0 10 70 60 0 60 50 0 0 25 0 5 70ns Max 70 70 35 25 25 25 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Units DATA RETENTION CHARACTERISTICS Item Vcc for data retention Symbol VDR CS1≥Vcc-0.2V1) K6T1008C2E-L Data retention current IDR Vcc=3.0V, CS1≥Vcc-0.2V1) K6T1008C2E-B K6T1008C2E-P K6T1008C2F-F Data retention set-up time Recovery time tSDR tRDR See data retention waveform Test Condition Min 2.0 0 5 Typ Max 5.5 20 10 25 10 ms µA Unit V 1. CS1 ≥Vcc-0.2V, CS2≥Vcc-0.2V(CS1 controlled) or CS2≤0.2V(CS2 controlled) 5 Revision 3.0 March 2000 K6T1008C2E Family TIMMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, CS2=WE=VIH) tRC Address tOH Data Out Previous Data Valid tAA CMOS SRAM Data Valid TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) tRC Address tAA tCO1 CS1 tHZ(1,2) CS2 tCO2 tOE tOH OE tOLZ tLZ Data Valid tOHZ Data out NOTES (READ CYCLE) High-Z 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ (Min.) both for a given device and from device to device interconnection. 6 Revision 3.0 March 2000 K6T1008C2E Family TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled) tWC Address tCW(2) CS 1 tAW CS 2 tCW(2) tWP(1) WE tAS(3) Data in tWHZ Data out Data Undefined tDW Data Valid tOW tDH tWR(4) CMOS SRAM TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled) tWC Address tAS(3) CS 1 tAW CS 2 tWP(1) WE tDW Data in Data Valid tDH tCW(2) tWR(4) Data out High-Z High-Z 7 Revision 3.0 March 2000 K6T1008C2E Family TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled) tWC Address tAS(3) CS1 tAW CS2 tCW(2) tWP(1) tDW Data in Data Valid tDH tCW(2) tWR(4) CMOS SRAM WE Data out NOTES (WRITE CYCLE) High-Z High-Z 1. A write occurs during the overlap of a low CS1 , a high CS2 and a low WE. A write begins at the latest transition among CS1 goes low, CS2 going high and WE going low: A write end at the earliest transition among CS1 going high, CS2 going low and WE going high, tWP is measured from the begining of write to the end of write. 2. tCW is measured from the CS1 going low or CS2 going high to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. t WR1 applied in case a write ends as CS1 or WE going high tWR2 applied in case a write ends as CS2 going to low. DATA RETENTION WAVE FORM CS1 controlled VCC 4.5V tSDR Data Retention Mode tRDR 2.2V VDR CS≥VCC - 0.2V CS1 GND CS2 controlled VCC 4.5V CS 2 tSDR Data Retention Mode tRDR VDR 0.4V GND CS2≤0.2V 8 Revision 3.0 March 2000 K6T1008C2E Family PACKAGE DIMENSIONS 32 DUAL INLINE PACKAGE (600mil) CMOS SRAM Units: millimeters(inches) 0.25 +0.10 -0.05 +0.004 0.010-0.002 #32 #17 13.60±0.20 0.535±0.008 #1 42.31 1.666 MAX 41.91±0.20 1.650±0.008 #16 3.81 ±0.20 0.150±0.008 5.08 0.200 MAX 1 5.24 0 .600 0~15° ( 1.91 ) 0.075 0.46 ±0.10 0.018±0.004 1.52 ±0.10 0.060±0.004 3.30±0.30 0.130±0.012 2.54 0.100 0.38 MIN 0.015 32 PLASTIC SMALL OUTLINE PACKAGE (525mil) 0~8° #32 #17 14.12±0.30 0.556±0.012 11.43±0.20 0.450±0.008 13 .34 0. 525 #1 20.87 MAX 0.822 20.47±0.20 0.806±0.008 #16 2.74±0.20 0.108 ±0.008 3.00 0.118 MAX 0.10 0.20 +0.05 0.004 0.008+0.002 - 0.80±0.20 0.031 ±0.008 0.10 MAX 0.004 MAX +0.100 -0.050 +0.004 0.016 -0.002 ( 0.71 ) 0.028 0.41 1.27 0.050 0.05 MIN 0.002 9 Revision 3.0 March 2000 K6T1008C2E Family PACKAGE DIMENSIONS 32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0820F) +0.10 -0.05 +0.004 0.008-0.002 CMOS SRAM Units: millimeters(inches) 0.20 20.00±0.20 0.787±0.008 #32 ( 8.40 0.331 MAX 8.00 0 .315 0.25 ) 0.010 #1 0.50 0.0197 #16 #17 1.00 ±0.10 0.039±0.004 1.20 0.047 MAX 0.15 +0.10 -0.05 0.004 0.006+0.002 - 0.05 0.002 MIN 0.25 0.010 TYP 18.40±0.10 0.724±0.004 0~8 ° 0.45 ~0.75 0.018 ~0.030 ( 0.50 ) 0.020 32 THIN SMALL OUTLINE PACKAGE TYPE I (0820R) 0.20 +0.10 -0.05 0.004 0.008+0.002 - 20.00±0.20 0.787±0.008 #17 ( 8.4 0 0.3 31 MAX 8.00 0 .315 0.25 ) 0.010 #16 0.50 0.0197 #1 #32 1.00±0.10 0.039±0.004 1.20 0.047 MAX 0.05 0.002 MIN 0.25 0.010 TYP 18.40 ±0.10 0.724±0.004 0~8° 0.45 ~0.75 0.018 ~0.030 ( 0.50 ) 0.020 10 0.10 MAX 0.004 MAX +0.10 -0.05 +0.004 0.006 -0.002 0.15 Revision 3.0 March 2000 0 .10 MAX 0 .004 MAX