KM68512ALG-5

KM68512A Family Document Title 64Kx8 bit Low Power CMOS Static RAM CMOS SRAM Revision History Revision No. 0.0 0.1 1.0 2.0 History Initial draft Revision Finalize Revision - Add 45ns part with 30pf test load. Revision - Change Data Sheet format : One data sheets for industrial and commercial product Revision - Change Data Sheet format - Remove 45ns part from commercial product and 100ns part from industrial product - Remove low power part form TSOP package Draft Data Novemer 28, 1993 May 13, 1994 December 1, 1994 August 12, 1995 Remark Design target Preliminary Final Final 3.0 April 15, 1996 Final 4.0 January 9, 1998 Final The attached data, sheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices. 1 Revision 4.0 January 1997 KM68512A Family 64Kx8 bit Low Power CMOS Static RAM FEATURES • Process Technology: Poly Load • Organization: 64Kx8 • Power Supply Voltage: 4.5~5.5V • Low Data Retention Voltage: 2V(Min) • Three state output and TTL Compatible • Package Type: 32-SOP-525, 32-TSOP1-0820F CMOS SRAM GENERAL DESCRIPTION The KM68512A families are fabricated by SAMSUNG′s advanced CMOS process technology. The families support various operating temperature ranges and have various package types for user flexibility of system design. The families also support low data retention voltage for battery back-up operation with low data retention current. PRODUCT FAMILY Power Dissipation Product Family KM68512AL KM68512AL-L KM68512ALI KM68512ALI-L Industrial (-40~85°C) Operating Temperature VCC Range Speed Standby (ISB1, Max) 100µA 20µA 100µA 50µA 70mA 32-SOP 32-TSOP1-F Operating (ICC2, Max) PKG Type Commercial (0~70°C) 4.5 to 5.5V 55/70ns 70ns PIN DESCRIPTION N.C N.C A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 VCC A15 CS2 WE A13 A8 A9 A11 OE A10 CS 1 I/O8 I/O7 I/O6 I/O5 I/O4 A11 A9 A8 A13 WE CS2 A15 VCC NC NC A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CS 1 I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2 A3 FUNCTIONAL BLOCK DIAGRAM Clk gen. Precharge circuit. A3 A4 A5 A6 A7 A12 A13 A14 A15 32-SOP 25 24 23 22 21 20 19 18 17 Row select 32-TSOP Type1 - Forward Memory array 512 rows 128×8 columns I/O1 I/O8 Data cont I/O Circuit Column select Data cont Name CS1, CS 2 OE WE A0~A15 I/O1~I/O8 Vcc Vss N.C Function Chip Select Inputs Output Enable Input Write Enable Input Address Inputs Data Inputs/Outputs Power Ground No Connection CS 1 CS2 WE OE A0 A1 A2 A8 A9 A10 A11 Control Logic SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. 2 Revision 4.0 January 1997 KM68512A Family PRODUCT LIST Commercial Temperature Products(0~70°C) Part Name KM68512ALG-5 KM68512ALG-5L KM68512ALG-7 KM68512ALG-7L KM68512ALT-5L KM68512ALT-7L Function 32-SOP, 55ns, L-pwr 32-SOP, 55ns, LL-pwr 32-SOP, 70ns, L-pwr 32-SOP, 70ns, LL-pwr 32-TSOP1-F, 55ns, LL-pwr 32-TSOP1-F, 70ns, LL-pwr KM68512ALTI-7L CMOS SRAM Industrial Temperature Products(-40~85°C) Part Name KM68512ALGI-7 KM68512ALGI-7L Function 32-SOP, 70ns, L-pwr 32-SOP, 70ns, LL-pwr 32-TSOP1-F, 70ns, LL-pwr FUNCTIONAL DESCRIPTION CS1 H X1) L L L CS2 X1) L H H H OE X1) X1) H L X1) WE X1) X1) H H L I/O Pin High-Z High-Z High-Z Dout Din Mode Deselected Deselected Output Disabled Read Write Power Standby Standby Active Active Active 1. X means don′t care.(Must be low or high state) ABSOLUTE MAXIMUM RATINGS1) Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage temperature Operating Temperature Soldering temperature and time Symbol VIN,VOUT VCC PD TSTG TA TSOLDER Ratings -0.5 to 7.0 -0.5 to 7.0 1.0 -65 to 150 0 to 70 -40 to 85 260°C, 10sec(Lead Only) Unit V V W °C °C °C Remark KM68512A KM68512AI - 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 3 Revision 4.0 January 1997 KM68512A Family RECOMMENDED DC OPERATING CONDITIONS1) Item Supply voltage Ground Input high voltage Input low voltage Symbol Vcc Vss VIH VIL Min 4.5 0 2.2 -0.53) Typ 5.0 0 - CMOS SRAM Max 5.5 0 Vcc+0.5V 0.8 2) Unit V V V V Note 1. Commercial Product : TA=0 to 70°C, unless otherwise specified Industrial Product : TA=-40 to 85°C, unless otherwise specified 2. Overshoot : V CC+3.0V in case of pulse width ≤30ns 3. Undershoot : -3.0V in case of pulse width ≤30ns 4. Overshoot and undershoot are sampled, not 100% tested CAPACITANCE1)(f=1MHz, TA=25°C) Item Input capacitance Input/Output capacitance 1. Capacitance is sampled, not 100% tested Symbol CIN CIO Test Condition VIN=0V VIO=0V Min - Max 6 8 Unit pF pF DC AND OPERATING CHARACTERISTICS Item Input leakage current Output leakage current Operating power supply current Symbol ILI ILO ICC ICC1 Average operating current ICC2 Output low voltage Output high voltage Standby Current(TTL) Standby Current (CMOS) KM68512AL/L-L ISB1 KM68512ALI/LI-L VOL VOH ISB VIN=Vss to Vcc CS 1=VIH or CS 2=VIL or OE=VIH or WE=VIL, VIO=Vss to Vcc IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIH or VIL Cycle time=1µs, 100% duty, IIO=0mA CS 1≤0.2V, CS2≥VCC-0.2V, VIN≤0.2V or VIN≥Vcc -0.2V Cycle time=Min, 100% duty, IIO=0mA, CS1=VIL, CS 2=VIH, VIN=VIH or VIL Test Conditions Min -1 -1 2.4 - Typ Max Unit 7 2 1 2 1 1 1 15 10 70 0.4 3 100 20 100 50 µA µA mA mA mA V V mA µA µA IOL=2.1mA IOH=-1.0mA CS 1=VIH, CS2=VIL, Other inputs =VIH or VIL Low Power CS 1≥Vcc-0.2V, CS2≥Vcc-0.2V or CS2≤0.2V Low Low Power Other inputs =0 ~ Vcc Low Power Low Low Power 4 Revision 4.0 January 1997 KM68512A Family AC OPERATING CONDITIONS TEST CONDITIONS( Test Load and Input/Output Reference) Input pulse level : 0.8 to 2.4V Input rising and falling time : 5ns Input and output reference voltage :1.5V Output load(see right) : CL=100pF+1TTL CMOS SRAM CL1) 1. Including scope and jig capacitance AC CHARACTERISTICS (Vcc=4.5~5.5V, KM68512A Family:TA=0 to 70°C, Parameter List Symbol KM68512AI Family:TA=-40 to 85°C) Speed Bins 55ns 70ns Max 55 55 25 20 20 20 Min 70 10 5 0 0 10 70 60 0 60 50 0 0 30 0 5 Max 70 70 35 25 25 25 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Units Min Read cycle time Address access time Chip select to output Output enable to valid output Read Chip select to low-Z output Output enable to low-Z output Chip disable to high-Z output Output disable to high-Z output Output hold from address change Write cycle time Chip select to end of write Address set-up time Address valid to end of write Write Write pulse width Write recovery time Write to output high-Z Data to write time overlap Data hold from write time End write to output low-Z tRC tAA tCO1, tCO2 tOE tLZ tOLZ tHZ tOHZ tOH tWC tCW tAS tAW tWP tWR tWHZ tDW tDH tOW 55 10 5 0 0 10 55 45 0 45 40 0 0 25 0 5 DATA RETENTION CHARACTERISTICS Item Vcc for data retention VDR KM68512AL/L-L Data retention current IDR KM68512ALI/LI-L Data retention set-up time Recovery time tSDR tRDR Symbol 11) Test Condition CS ≥Vcc-0.2V Vcc=3.0V CS1≥Vcc-0.2V CS2≥Vcc-0.2V or CS2≤0.2V L-Ver LL-Ver L-Ver LL-Ver Min 2.0 0 5 Typ 1 0.5 - Max 5.5 50 10 50 25 - Unit V µA See data retention waveform ms 1. CS1≥Vcc-0.2V, CS2 ≥Vcc-0.2V( CS1 controlled) or CS2≤0.2V(CS2 controlled). 5 Revision 4.0 January 1997 KM68512A Family TIMMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, WE=VIH) tRC Address tOH Data Out Previous Data Valid tAA CMOS SRAM Data Valid TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) tRC Address tAA tCO1 CS 1 tHZ(1,2) CS 2 tCO2 tOE tOH OE tOLZ tLZ Data Valid tOHZ Data out NOTES (READ CYCLE) High-Z 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 6 Revision 4.0 January 1997 KM68512A Family TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled) tWC Address tCW(2) CS1 tAW CS2 tCW(2) tWP(1) WE tAS(3) Data in tWHZ Data out Data Undefined tDW Data Valid tOW tDH tWR(4) CMOS SRAM TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled) tWC Address tAS(3) CS1 tAW CS2 tWP(1) WE tDW Data in Data Valid tDH tCW(2) tWR(4) Data out High-Z High-Z 7 Revision 4.0 January 1997 KM68512A Family TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled) CMOS SRAM tWC Address tAS(3) CS 1 tAW CS 2 tCW(2) tWP(1) tDW Data in Data Valid tDH tCW(2) tWR(4) WE Data out NOTES (WRITE CYCLE) High-Z High-Z 1. A write occurs during the overlap of a low CS1, a high CS 2 and a low WE. A write begins at the latest transition among CS1 goes low, CS2 going high and WE going low : A write end at the earliest transition among CS1 going high, CS2 going low and WE going high, tWP is measured from the begining of write to the end of write. 2. t CW is measured from the CS1 going low or CS2 going high to the end of write. 3. t AS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR(1) applied in case a write ends as CS1 or WE going high tWR(2) applied in case a write ends as CS2 going to low. DATA RETENTION WAVE FORM CS1 controlled VCC 4.5V tSDR Data Retention Mode tRDR 2.2V VDR CS1≥VCC - 0.2V CS1 GND CS2 controlled VCC 4.5V CS2 tSDR Data Retention Mode tRDR VDR 0.4V GND CS2≤0.2V 8 Revision 4.0 January 1997 KM68512A Family PACKAGE DIMENSIONS 32 PIN SMALL OUTLINE PACKAGE (525mil) CMOS SRAM Units: millimeter(Inch) #32 #17 0~8 ° 11.43 ±0.20 0.450±0.008 #1 20.87 MAX 0.822 20.47±0.20 0.806±0.008 #16 2.74±0.20 0.108±0.008 3.00 0.118 MAX 13 .34 0.5 25 14.12±0.30 0.556±0.012 0.10 0.20 +0.05 0.004 0.008+0.002 - 0.80±0.20 0.031 ±0.008 0.10 MAX 0.004 MAX +0.100 -0.050 +0.004 0.016 -0.002 ( 0.71 ) 0.028 0.41 1.27 0.050 0.05 MIN 0.002 32-THIN SMALL OUTLINE PACKAGE TYPE I (0820F) 0.20 +0.10 -0.05 0.004 0.008+0.002 - 20.00±0.20 0.787 ±0.008 #32 ( 8.00 0.315 0.25 ) 0.010 #1 MAX 8.40 0.331 0.50 0.0197 #16 #17 1.00±0.10 0.039±0.004 1.20 0.047 MAX 0.05 0.002 MIN 0.25 0.010 TYP 18.40±0.10 0.724±0.004 0~8° 0.45 ~0.75 0.018 ~0.030 ( 0.50 ) 0.020 9 Revision 4.0 January 1997 0.10 MAX 0 .004 MAX +0.10 -0.05 0.004 0.006+0.002 - 0.15