KS0655

KS0655 120 / 128 CHANNEL TFT-LCD GATE DRIVER November. 1999. Ver. 0.1 Prepared by: Jae il Byeon kerigma@samsung.co.kr Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of LCD Driver IC Team. KS0655 120 / 128 CHANNEL TFT-LCD GATE DRIVER KS0655 Specification Revision History Version 0.0 0.1 Original The contents of page 9, 10, 13 and 14 have been modified Content Date Aug.1999 Nov.1999 2 120 / 128 CHANNEL TFT-LCD GATE DRIVER KS0655 CONTENTS INTRODUCTION .................................................................................................... 4 FEATURES ............................................................................................................ 4 BLOCK DIAGRAM................................................................................................. 5 PIN ASSIGNMENTS ............................................................................................. 6 PIN DESCRIPTIONS.............................................................................................. 7 ABSOLUTE MAXIMUM RATINGS ........................................................................ 8 RECOMMENDED OPERATION RATINGS........................................................... 8 DC CHARACTERISTICS ....................................................................................... 9 AC CHARACTERISTICS ..................................................................................... 10 AC TIMING DIAGRAM......................................................................................... 11 OPERATION DESCRIPTION............................................................................... 12 OPERATION METHOD ........................................................................................................ 12 OUTPUT PIN ........................................................................................................................ 13 VOLTAGE BIASING ............................................................................................................. 14 RECOMMENDED TIMING.................................................................................................... 15 3 KS0655 120 / 128 CHANNEL TFT-LCD GATE DRIVER INTRODUCTION The KS0655 is a TFT-LCD gate driver having 120 / 128 outputs. It can drive TFT panel gate ON voltage up to 40 V. It can operate within the logic voltage 3.0 to 5.5 V. FEATURES • • • • • 120 / 128 outputs Maximum TFT panel gate ON voltage = 40 V Bi-directional shift register Logic supply voltage = 3.0 to 5.5 V TCP 4 120 / 128 CHANNEL TFT-LCD GATE DRIVER KS0655 BLOCK DIAGRAM VDD VLO VSS 120/128 U/D CPV DI/O S/R 001 S/R 002 128 Shift Register S/R 127 S/R 128 DO/I OE1 OE2 OE3 Level Shifter VGG VOFF 128 Ouput Buffer G001 G002 G127 G128 Figure 1. Block Diagram 5 KS0655 120 / 128 CHANNEL TFT-LCD GATE DRIVER PIN ASSIGNMENTS G001 G002 G003 G004 VOFF VSS DI/O VLO 120/128 VDD U/D CPV OE3 OE2 OE1 DO/I VGG G125 G126 G127 G128 Figure 2. Pin Assignments 6 KS0655 (Top View) 120 / 128 CHANNEL TFT-LCD GATE DRIVER KS0655 PIN DESCRIPTIONS Symbol Pin Name I/O Description DI/O DO/I Start pulse input/output When these inputs operate as the input, the start pulse data is read at the rising edge of shift clock, CPV. When these inputs operate as the output, the start pulse output is the next chip’s start pulse input. The output pulse is generated I/O at the falling edge of the 128th shift clock, CPV. When U/D = H, the shift register does right shifting operation. (Input = DI/O and output = DO/I) When U/D = L, the shift register does left shifting operation. (Input = DO/I and output = DI/O) I I When U/D = H, DI/O → G001 →……→ G128 → DO/I When U/D = L, DO/I → G128 →……→ G001 → DI/O The shift register operates in synchronization with the rising edge of this input This input selects the number of available outputs When SEL = L, 128 output mode When SEL = H, 120 output mode(G61 - G68 are disabled) This input controls the state of the driver outputs. When OE = H, the driver output is fixed to VOFF. When OE = L, the driver output is VGG or VOFF corresponding to the data. The output signals change in synchronization with the rising edge of shift clock input, CPV. The amplitude of the driver output is VGG - VOFF. This input is TFT-LCD gate off voltage. This input operates as the reference to the level conversion of the other input. The other logic input range: VDD - VLO This input is logic and driver ground. Always, has negative potential. The TFT gate ON voltage is VGG - VOFF. This is the voltage source for internal logic operation. U/D CPV 120/128 Shift direction control input Shift clock input Output selection input I OE1 OE2 OE3 G001 to G128 VOFF VLO Output enable input I Driver output Gate off voltage Logic input low voltage O I I VSS VGG VDD Negative power supply Driver positive power supply Logic positive power supply I I I 7 KS0655 120 / 128 CHANNEL TFT-LCD GATE DRIVER ABSOLUTE MAXIMUM RATINGS (VSS = VOFF = 0 V) Table 1. Absolute Maximum Ratings Parameter Logic positive power supply Driver positive power supply Logic input low voltage Input voltage Operation temperature Storage temperature Symbol VDD VGG VLO VIN Top Tstg Ratings - 0.3 to 22.0 - 0.3 to 45.0 - 0.3 to VDD + 0.3 - 0.3 to VDD + 0.3 - 20 to 75 - 55 to 150 Unit V V V V °C °C CAUTIONS If the absolute maximum rating is exceeded momentarily, the quality of this product may be degraded. It is desirable to use this product within the range of the absolute maximum ratings. The power supplying order is as follows. ON: VLO → VDD → VSS, VOFF → Control Input → VGG OFF: VGG → Control Input → VSS, VOFF → VDD → VLO RECOMMENDED OPERATION RATINGS (VLO = 0 V ≥ VSS = VOFF) Table 2. Recommended Operation Ratings Parameter Logic positive power supply Driver positive power supply Logic negative power supply Driver negative power supply Power supply voltage Operation frequency Output load Symbol VDD VGG VSS VOFF VGG - VOFF fCPV CL Min. 3.0 6 - 15 - 15 21 Typ. Max. 5.5 40 0 0 40 100 500 Unit V V V V V kHz pF 8 120 / 128 CHANNEL TFT-LCD GATE DRIVER KS0655 DC CHARACTERISTICS (VLO = 0 V ≥ VSS = VOFF) Table 3. DC Characteristics (Ta = - 20 to 75 ° C, VGG - VOFF = 21 to 40 V, VLO - VSS = 15 to 0 V, VDD - VLO = 3.0 to 5.5 V) Parameter Symbol Condition Min. Max. Unit High input voltage Low input voltage High output voltage Low output voltage VIH VIL VOH VOL ROH LCD driver output ON resistance ROL High output current Low output current Input leak current IGG IDD ILK VX = VDD - VLO IOH = - 40 µA IOL = 40 µA VOUT = VGG - 0.5 V, VGG = 40 V, VSS = VOFF = 0 V VOUT = 0.5 V, VGG = 40 V, VSS = VOFF = 0 V Without output load VDD - VSS = 3.3 V VDD - VSS = 19 V VLO + 0.9VX VSS VDD - 0.4 VSS VDD VLO + 0.1VX VDD VSS + 0.4 500 V (1) Pin used V V V Ω G001 to G128 G001 to G128 VGG (1) (3) (1) (2) -5 500 400 400 1000 5 Ω µA µA µA µA NOTES: 1. DI/O, DO/I, CPV, OE1, OE2, OE3, U/D, 120/128 used. 2. When U/D = H, DO/I used, and when U/D = L, DI/O used. 3. Input swing voltage = VDD to VDD - 3.3 V 9 KS0655 120 / 128 CHANNEL TFT-LCD GATE DRIVER AC CHARACTERISTICS (VLO = 0 V ≥ VSS = VOFF) Table 4. AC Characteristics (Ta = - 20 to 75 ° C, VGG - VOFF = 21 to 40 V, VLO - VSS = 15 to 0 V, VDD - VLO = 3.0 to 5.5 V) Parameter Symbol Condition Min. Max. Clock period Clock pulse width Output enable input width Data setup time Data hold time Output delay time (1) Output delay time (2) Output delay time (3) tCPV tCPVH, tCPVL twOE tsDI thDI tpdDO tpdG tpdOE Duty = 50 % CL = 30 pF CL = 300 pF 10 4 1 700 700 800 800 800 ns µs Unit 10 tCPVH tCPV 50 % tCPVL tsDI 50 % tpdG 50 % thDI 50 % 50 % 50 % 50 % AC TIMING DIAGRAM CPV 120 / 128 CHANNEL TFT-LCD GATE DRIVER DI/O (U/D=H) DO/I (U/D=L) G1 (U/D=H) G128 (U/D=L) 50 % tpdOE twOE 50 % 50 % 50 % OE1~3 tpdOE 50 % Figure 3. AC Timing Diagram tpdDO 50 % G2 to G127 G128 (U/D=H) G1 (U/D=L) tpdDO DO/I (U/D=H) DI/O (U/D=L) 50 % KS0655 11 KS0655 120 / 128 CHANNEL TFT-LCD GATE DRIVER OPERATION DESCRIPTION OPERATION METHOD The start pulse input, DI/O (when U/D is “H”) or DO/I (when U/D = “L”), is synchronized with the rising edge of CPV and stored in the first shift register. While stored pulse is transferred to the next register at the next rising edge of CPV, a new pulse is stored simultaneously. Output pin (G1 to G128) supplies VGG voltage or VOFF voltage to the TFT-LCD panel depending on the pulse of the shift register. The start pulse output, DO/I (when U/D is “H”) or DI/O (when U/D = “L”), is synchronized with the falling edge of CPV and the pulse of the last register (G1 or G128) is transferred to the next IC. The voltage level of the start pulse output is VDD with “H” data, VSS with “L” data The relationship between U/D and shift data input / out pin is as follows: Table 5. The Relationship between U/D and the Start Pulse Input / Output Mode 128 output 120 output U/D state “H” “L” “H” “L” Shift data Input DI/O DO/I DI/O DO/I Output DO/I DI/O DO/I DI/O Data transfer direction G1 → G2 → G3 → G4 → G5 →……→ G128 G128 → G127 → G126 → G125 →……→ G1 G1 → G2 →……→ G60 → G69 →……→ G127 → G128 G128 → G127 →……→ G69 → G60 → ……→ G2 → G1 12 120 / 128 CHANNEL TFT-LCD GATE DRIVER KS0655 OUTPUT PIN (G1 TO G128) If the data of the shift register to an output drive pin is “H”, the voltage level of the output is VGG and if the data is “L”, the level of the output is VOFF. But, when OE is “H”, the voltage level of the output is VOFF irrespective of the data of the shift register. Table 6. The Relationship between OE and the Output Level Condition Pin OE1 OE2 OE3 OE1 OE2 OE3 OE1 OE2 OE3 OE1 OE2 OE3 “L” “H” 128 Output “L” “H” 120 Output State Mode 120/128 Output pin control Control relationship G1, G4, G7,……, G55, G58, G69, G72,……, G123, G126 G2, G5, G8,……, G56, G59, G70, G73,……, G124, G127 G3, G6, G9,……, G57, G60, G71, G74,……, G125, G128 G1, G4, G7,……, G55, G58, G69, G72,……, G123, G126 G2, G5, G8,……, G56, G59, G70, G73,……, G124, G127 G3, G6, G9,……, G57, G60, G71, G74,……, G125, G128 G1, G4, G7,………………………………………, G124, G127 G2, G5, G8,………………………………………, G125, G128 G3, G6, G9,………………………………………, G126 G1, G4, G7,………………………………………, G124, G127 G2, G5, G8,………………………………………, G125, G128 G3, G6, G9,………………………………………, G126 Normal output (VGG / VOFF) VOFF Normal output (VGG / VOFF) VOFF Output level 13 KS0655 120 / 128 CHANNEL TFT-LCD GATE DRIVER VOLTAGE BIASING The driver negative power supply, VSS, can be any value between VLO and VLO - 15V. G1 to G128 VGG (40 V) G1 to G128 VGG (33 V) Input signal VDD (3.3 V) Logic Output VDD (3.3 V) Input signal Logic Output VLO (0 V) VLO (0 V) = VOFF = VSS VSS (-7 V) = VOFF Figure 4. Example of Voltage Biasing 14 120 / 128 CHANNEL TFT-LCD GATE DRIVER KS0655 RECOMMENDED TIMING - 128 output mode When U/D = "H" Input DI/O CPV OE1 OE2 OE3 G1 G2 G3 G4 G128 Output DO/I When U/D = "L" Input DO/I CPV OE2 OE1 OE3 G128 G127 G126 G125 G1 Output DI/O VGG VDD VOFF VSS VGG VDD VOFF VSS Figure 5. Recommended Timing 15 KS0655 120 / 128 CHANNEL TFT-LCD GATE DRIVER - 120 output mode When U/D = "H" Input DI/O CPV OE1 OE2 OE3 G1 G2 G3 G61 to G68 G128 Output DO/I When U/D = "L" Input DO/I CPV OE3 OE2 OE1 G128 G127 G126 G68 to G61 G1 Output DI/O VGG VDD VOFF VOFF VSS VGG VDD VOFF VOFF VSS Figure 5. Recommended Timing (Continued) 16 120 / 128 CHANNEL TFT-LCD GATE DRIVER KS0655 NOTES 17