KS0794
160 COM / 160 SEG DRIVER FOR STN LCD
August.1999. Ver. 1.1
Prepared by:
Gyeong-Nam, Kim kgn@samsung.co.kr
Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of LCD Driver IC Team.
160 COM / SEG DRIVER FOR STN LCD
PRELIMINARY SPEC. VER. 1.1
KS0794
KS0794 Specification Revision History
Version 0.0 1.0 1.1 l l l Original Including application note. p6, p16 revision. Content Date Apr.1999 Jul.1999 Aug.1999
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KS0794
PRELIMINARY SPEC. VER. 1.1
160 COM / SEG DRIVER FOR STN LCD
CONTENTS
INTRODUCTION ..................................................................................................................................................4 FEATURES ..........................................................................................................................................................4 BLOCK DIAGRAM ...............................................................................................................................................5 PAD CONFIGURATION .......................................................................................................................................6 PAD CENTER COORDINATES............................................................................................................................7 PIN DESCRIPTION ..............................................................................................................................................9 FUNCTIONAL DESCRIPTION............................................................................................................................10 BLOCK FUNCTION .....................................................................................................................................10 PIN FUNCTION ...........................................................................................................................................11 FUNCTIONAL OPERATIONS......................................................................................................................15 SPECIFICATIONS..............................................................................................................................................18 ABSOLUTE MAXIMUM RATINGS ...............................................................................................................18 RECOMMENDED OPERATING CONDITIONS ...........................................................................................18 DC CHARACTERISTICS .............................................................................................................................19 AC CHARACTERISTICS .............................................................................................................................21 PRECAUTION ....................................................................................................................................................27 CONNECTION EXAMPLES OF PLURAL SEGMENT DRIVERS ........................................................................28 TIMING CHART OF 4-DEVICE CASECADE CONNECTION OF SEGMENT DRIVERS......................................29 CONNECTION EXAMPLES OF PLURAL COMMON DRIVERS .........................................................................30
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160 COM / SEG DRIVER FOR STN LCD
PRELIMINARY SPEC. VER. 1.1
KS0794
INTRODUCTION
The KS0794 is a 160-output segment / common driver LSI suitable for driving large scale dot matrix LC panels using as personal computers / work stations. Through the use of SST (Super Slim TCP) technology, it is ideal for substantially decreasing the size of the frame section of the LC module. The KS0794 is good both segment driver and common driver, and a low power consuming, high-precision LC panel display can be assembled. In case of segment mode, the data input is selected 4bit parallel input mode and 8bit parallel input mode by a mode (MD) pin. In case of common mode, data input/output pins are bi-directional, four data shift directions are pin-selectable.
FEATURES
BOTH SEGMENT MODE AND COMMON MODE
- Supply voltage for LC driver: +15.0 to +32.0V - Number of LC driver outputs: 160 - Low output impedance - Low power consumption - Supply voltage for the logic system: +2.4V to +5.5V - CMOS silicon gate process (P-type silicon substrate) - Package: 190-pin TCP (Tape Carrier Package) & Au bump chip
Segment Mode - Shift clock frequency: 14MHz (Max.) (Vdd = +5V ± 10%) 8MHz (Max.) (Vdd = +2.4V to +4.5V) - Adopts a data bus system - 4-bit / 8-bit parallel input modes are selectable with a mode (MD) pin - Automatic transfer function of an enable signal - Automatic counting function which, in the chip select, causes the internal clock to be stopped by automatically counting 160 of input data - Line latch circuit reset function when DISPOFFB active Common Mode - Shift clock frequency: 4.0MHz (Max.) (Vdd = +2.4V to +5.5V) - Built-in 160 bits bi-directional shift register (divisible into 80-bits ×2) - Available in a single mode (160 bits shift register) or in a dual mode (80 bits shift register ×2) - Shift register circuit reset function when DISPOFFB active
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KS0794
PRELIMINARY SPEC. VER. 1.1
160 COM / SEG DRIVER FOR STN LCD
BLOCK DIAGRAM
V OR
190
V 12R
189
V 43R
188
V 5L
164
Y1
1
Y2
2
Y 159
159
Y 160
160 187
FR DISPOFFB
V 5L V 43L V 12L V OL
182 179
LEVEL SHIFTER
160 BITS 4-LEVEL DRIVER 160
163
162
EIO1 EIO2
181
169
ACTIVE CONTROL
160 BITS LEVEL SHIFTER 160 160 BITS LINE LATCH/SHIFTER REGISTER
16 16 16 16 16 16 16 16 16 16 161
LP XCK L/R MD S/C
180
178
CONTROL LOGIC
8BITS*2 DATA LATCH
166
DATA LATCH CONTROL
183
8 SP CONVERSION & DATA CONTROL (4 to 8 or 8to 8)
170 171 172 173 174 175 176 177 167 165 186
168
DI 0
DI 1
DI 2
DI 3
DI4
DI5
DI6
DI7
V DD
V SS
V SS
Figure 1. Block Diagram
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160 COM / SEG DRIVER FOR STN LCD
PRELIMINARY SPEC. VER. 1.1
KS0794
PAD CONFIGURATION
160
1
ððððððððððððððððððððð - - - - - - - - - - ðððððððððððððððððððð
161 Y 190
ðððð
Dummy 165
ðððð
KS0794
(TOP VIEW,Pad up) (0,0)
X
186 Dummy
164
ðððððððððððððð
ðððððððððð
187
Figure 2. KS0794 Chip Configuration
Table 1. KS0794 Pad Dimensions Item Chip size Pad pitch Pad No. 1 to 160 161 to 190 1 to 160 Bumped pad size 161 to 164 187 to 190 165 to 186 Bumped pad height 1 to 190 43 76 58 14 (Typ.) Size X 11000 Y 1100 Unit
65 (Min.) 260 (Min.) 108 58 76 µm
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KS0794
PRELIMINARY SPEC. VER. 1.1
160 COM / SEG DRIVER FOR STN LCD
PAD CENTER COORDINATES
Table 2. Pad Location [Unit: µm]
NO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NAME
Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 Y24 Y25 Y26 Y27 Y28 Y29 Y30 Y31 Y32 Y33 Y34 Y35 Y36 Y37 Y38 Y39 Y40 Y41 Y42 Y43 Y44 Y45 Y46 Y47 Y48 Y49 Y50
X
5167.5 5102.5 5037.5 4972.5 4907.5 4842.5 4777.5 4712.5 4647.5 4582.5 4517.5 4452.5 4387.5 4322.5 4257.5 4192.5 4127.5 4062.5 3997.5 3932.5 3867.5 3802.5 3737.5 3672.5 3607.5 3542.5 3477.5 3412.5 3347.5 3282.5 3217.5 3152.5 3087.5 3022.5 2957.5 2892.5 2827.5 2762.5 2697.5 2632.5 2567.5 2502.5 2437.5 2372.5 2307.5 2242.5 2177.5 2112.5 2047.5 1982.5
Y
395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395
NO
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
NAME
Y51 Y52 Y53 Y54 Y55 Y56 Y57 Y58 Y59 Y60 Y61 Y62 Y63 Y64 Y65 Y66 Y67 Y68 Y69 Y70 Y71 Y72 Y73 Y74 Y75 Y76 Y77 Y78 Y79 Y80 Y81 Y82 Y83 Y84 Y85 Y86 Y87 Y88 Y89 Y90 Y91 Y92 Y93 Y94 Y95 Y96 Y97 Y98 Y99 Y100
X
1917.5 1852.5 1787.5 1722.5 1657.5 1592.5 1527.5 1462.5 1397.5 1332.5 1267.5 1202.5 1137.5 1072.5 1007.5 942.5 877.5 812.5 747.5 682.5 617.5 552.5 487.5 422.5 357.5 292.5 227.5 162.5 97.5 32.5 -32.5 -97.5 -162.5 -227.5 -292.5 -357.5 -422.5 -487.5 -552.5 -617.5 -682.5 -747.5 -812.5 -877.5 -942.5 -1007.5 -1072.5 -1137.5 -1202.5 -1267.5
Y
395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395
NO
101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150
NAME
Y101 Y102 Y103 Y104 Y105 Y106 Y107 Y108 Y109 Y110 Y111 Y112 Y113 Y114 Y115 Y116 Y117 Y118 Y119 Y120 Y121 Y122 Y123 Y124 Y125 Y126 Y127 Y128 Y129 Y130 Y131 Y132 Y133 Y134 Y135 Y136 Y137 Y138 Y139 Y140 Y141 Y142 Y143 Y144 Y145 Y146 Y147 Y148 Y149 Y150
X
-1332.5 -1397.5 -1462.5 -1527.5 -1592.5 -1657.5 -1722.5 -1787.5 -1852.5 -1917.5 -1982.5 -2047.5 -2112.5 -2177.5 -2242.5 -2307.5 -2372.5 -2437.5 -2502.5 -2567.5 -2632.5 -2697.5 -2762.5 -2827.5 -2892.5 -2957.5 -3022.5 -3087.5 -3152.5 -3217.5 -3282.5 -3347.5 -3412.5 -3477.5 -3542.5 -3607.5 -3672.5 -3737.5 -3802.5 -3867.5 -3932.5 -3997.5 -4062.5 -4127.5 -4192.5 -4257.5 -4322.5 -4387.5 -4452.5 -4517.5
Y
395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395 395
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160 COM / SEG DRIVER FOR STN LCD
PRELIMINARY SPEC. VER. 1.1
KS0794
Table 2. Pad Location (Continued) [Unit: µm]
NO
151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190
NAME
Y151 Y152 Y153 Y154 Y155 Y156 Y157 Y158 Y159 Y160 VOL V12L V43L V5L DUMMY1 VSS LR VDD SC EIO2 DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 XCK DISPOFFB LP EIO1 FR MD NC NC VSS DUMMY2 V5R V43R V12R V0R
X
-4582.5 -4647.5 -4712.5 -4777.5 -4842.5 -4907.5 -4972.5 -5037.5 -5102.5 -5167.5 -5369 -5369 -5369 -5369 -4860 -4600 -4340 -4080 -3820 -3560 -3300 -3040 -2780 -2520 -2260 -2000 -1740 -1480 2290 2550 2810 3070 3330 3590 3850 4110 4370 4630 5369 5369 5369 5369
Y
395 395 395 395 395 395 395 395 395 395 330 90 -120 -330 -419 -419 -419 -419 -419 -419 -419 -419 -419 -419 -419 -419 -419 -419 -419 -419 -419 -419 -419 -419 -419 -419 -419 -419 -330 -120 90 330
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KS0794
PRELIMINARY SPEC. VER. 1.1
160 COM / SEG DRIVER FOR STN LCD
PIN DESCRIPTION
Table 3. Pin Description
Pin No.
1 to 160 161, 190 162, 189 163, 188 164, 187 166 167 168 169 170 to 176 177 178 179 180 181 182 183 165, 186
Symbol
Y1 – Y160 V0L, V0R V12L, V12R V43L, V43R V5L, V5R L/R VDD S/C EIO2 DI0 – DI6 DI7 XCK DISPOFFB LP EIO1 FR MD VSS
I/O
O I I I/O I I I I I I/O I I LC driver output Power supply for LC driver Power supply for LC driver Power supply for LC driver Power supply for LC driver
Description
Display data shift direction selection Power supply for logic system (+2.4 to +5.5V) Segment mode/common mode selection Input / output for chip select or data of shift register Display data input for segment mode Display data input for segment mode / dual mode data input Display data shift clock input for segment mode Control input for deselect output level Latch pulse input / shift clock input for shift register Input/output for chip select or data of shift register AC-converting signal input for LC driver waveform Mode selection input Ground (0V)
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160 COM / SEG DRIVER FOR STN LCD
PRELIMINARY SPEC. VER. 1.1
KS0794
FUNCTIONAL DESCRIPTION
BLOCK FUNCTION . Active Control In case of segment mode, controls the selection or deselection of the chip. Following a LP signal, and after the chip select signal is input, a select signal is generated internally until 160 bits of data have been read in. Once data input has been completed, a select signal for cascade connection is output, and the chip is deselected. In case of common mode, controls the input/output data of bidirectional pins. . SP Conversion & Data Control In case of segment mode, keep input data which are 2 clocks of XCK at 4-bit parallel mode into latch circuit, or keep input data which are 1 clock of XCK at 8-bits parallel mode into latch circuit, after that they are put on the internal data bus 8 bits at a time. . Data Latch Control In case of segment mode, selects the state of the data latch which reads in the data bus signals. The shift direction is controlled by the control logic, for every 16 bits of data read in, the selection signal shifts one bit based on the state of the control circuit. . Data Latch In case of segment mode, latches the data on the data bus. The latched state of each LC driver output pin is controlled by the control logic and the data latch control, 160 bits of data are read in 20 sets of 8 bits. . Line Latch / Shift Register In case of segment mode, all 160 bits which have been read into the data latch are simultaneously latched on the falling edge of the LP signal, and output to the level shifter block. In case of common mode, shifts data from the data input pin on the falling edge of the LP signal. . Level Shifter The logic voltage signal is level-shifted to the LC driver voltage level, and output to the driver block. . 4-level Driver Driver the LC driver output pins from the line latch/shift register data, selecting one of 4 levels (V0, V12, V43, V5) based on the S/C, FR and DISPOFFB signals. . Control Logic Controls the operation of each block. In case of segment mode, when a LP signal has been input, all blocks are reset and the control logic waits for the selection signal output from the active control block. Once the selection signal has been output, operation of the data latch and data transmission are controlled, 160 bits of data are read in, and the chip is deselected. In case of common mode, controls the direction of data shift.
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KS0794
PRELIMINARY SPEC. VER. 1.1
160 COM / SEG DRIVER FOR STN LCD
PIN FUNCTION
Segment Mode Symbol VDD VSS V0R, V0L V12R , V12L V43R , V43L Function Logic system power supply pin connects to +2.4 to +5.5V Ground pin connects to 0 V Power supply pin for LC driver voltage bias. . Normally, the bias voltage used is set by a resistor divider. . Ensure that voltage are set such that VSS
