KS5514B-12

JAN. 1998 SPECIFICATION for KS5514B-XX SYSTEM LSI BUSINESS SAMSUNG ELECTRONICS CO. SPECIFICATION for KS5514B-XX CONTENTS Important Notice Copyright 1998 by SAMSUNG The information in this publication has been carefully checked and is believed to be accurate at the time of publication. Samsung assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein. Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes. This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others. Samsung makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any liability, including without limitation any consequence or incidental damages. *Typical* parameters can and do vary in different applications. All operating parameters, including *Typicals,* must be validated for each customer application by the customer*s technical experts. Samsung products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, for other applications intended to support or sustain life, or for any other application in which the failure of the Samsung product could cause personal injury or death. Should the buyer purchase or use a Samsung product for any such unintended or unauthorized application, the buyer shall indemnify and hold Samsung and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damag es, expenses, and reasonable attorney fees arising out of, either directly or indirectly, any claim of personal injury or death that may be associated with such unintended or unauthorized use, even if such claim alleg es that Samsung was negligent regarding t he design or manufacture or manufacture of said product. • FUNCTIONS ------------------------------• FEATURES -------------------------------• BLOCK DIAGRAM ---------------------• PIN DESCRIPTION ---------------------• ABSOLUTE MAXIMUM RATINGS -- 3 3 3 4 5 • ELECTRICAL CHARACTERISTICS - 6 • OPERATION DESCRIPTION ---------- 7 • TEST CIRCUIT ---------------------------- 13 • APPLICATION CIRCUIT --------------- 14 • PACKAGE DIMENSIONS -------------- 16 SPECIFICATION KS5514B -XX ON SCREEN DISPLAY PROCESSOR ON SCREEN DISPLAY PROCESSOR The KS5514B is a BICMOS LSI with on screen display function, sync. separator & expander function. 24 - SDIP - 300 FUNCTIONS • On screen display • Sync separator and sync detector • General expander FEATURES • Character capacity : 240 ( 24 column • Construction of character : 12 • 128 kinds of character • Display position : 62 horizontal position : 64 vertical position • Character size : 4 • Blinking : character unit • Background coloring : 8 colors • Synchronous ways : automatic selection internal or external synchronization via MICOM control • General output : 3 ports ( by serial data ) • Built-in sync separator & sync detector • NTSC / PAL / SECAM mode • Clamp circuit KS5514B-XX 24-SDIP-300 - 20 ~ + 70 Ø 10 row ) Ø 18 dots ORDERING INFORMATION Device Package Operating Temprature Ø 4 times of normal OPTION CODE INFORMATION Code No. - 02 - 03 - 06 - 07 - 09 - 10 - 12 - 13 - 14 - 15 - 16 FSC 17 AVDD 16 VSYNC DET Î Remark English English, Russian English Korean Korean, English English, German English, Arabic English Korean, English English, Chinese English, Russian, Arabic BLOCK DIAGRAM DVDD 24 P3 23 P2 22 XTOUT XTIN 21 20 SYD AFCR 19 4FSC BLUE BACK GENERATOR DISPLAY CONTROL SHIFT REGISTER CVOUT 15 SCCR 14 CVIN 13 CLAMP 18 OSD ROM SYNC DETECT OSD RAM AFC INTERNAL BIAS CKT VIDEO MIXER SYNC SEP DATA REGISTER ADDR REGISTER CONTROL REGISTER INPUT CONTROL DISPLAY OSC CLAMP 1 2 3 4 5 6 7 SIN 8 9 10 AGND 11 LPF 12 AFCFIL DGND SCK ACB OSCIN OSCOUT CSB P1 CLAMPIN 98-05-14 3 SPECIFICATION KS5514B -XX ON SCREEN DISPLAY PROCESSOR PIN DESCRIPTION Pin No. 1 2 Symbol DGND SCK I/O I Digital Ground Serial clock input. When CSB pin is `L` then serial data is inputted by micom. Hysteresis input. 3 ACB I Auto clear pin. If `L`, then all circuit is reset. Built-in pull up resistor. Hysteresis input. 4 OSCIN I LC oscillation pin. Standard frequency is 7MHz & the horizontal start position is controlled by the 5 OSCOUT O clock of oscillation block. 6 CSB I While pin 6 is low, serial data input is active. Built - in pull up resistor 7 8 9 10 11 12 13 14 15 16 17 18 19 SIN P1 CLAMPIN AGND LPF AFCFIL CVIN SCCR CVOUT AVDD FSC AFCR SYD I O I I I O I I O Serial data input pin. Built-in pull up resistor General output port 1 Clamp input pin of composite video signal Analog ground Low pass filter AFC filter output Composite video signal input SECAM chroma input Composite video output : 2 Vp-p Analog VDD FSC input (Not use) VCO oscillation frequency control When sync signal is inputted, then SYD is high. Function 98-05-14 4 SPECIFICATION KS5514B -XX ON SCREEN DISPLAY PROCESSOR PIN DESCRIPTION ( Continued ) Pin No. 20 21 22 23 24 Symbol XTIN XTOUT P2 P3 DVDD I/O I O O O X-TAL X-TAL General output port 2 General output port 3 Digital VDD Function ABSOLUTE MAXIMUM RATINGS ( Ta = 25 Characteristics Supply Voltage Input Voltage Power Dissipation Operating Temperature Storage Temperature Symbol VDD VIN Pd Topr Tstg Î) Value - 0.3 ~ 6.0 VSS - 0.3 Unit V V mW õ VIN 300 õ VDD + 0.3 - 20 ~ + 70 - 40 ~ + 125 Î Î 98-05-14 5 SPECIFICATION KS5514B -XX ON SCREEN DISPLAY PROCESSOR ELECTRICAL CHARACTERISTICS ( Ta = 25 , AVDD = DVDD = 5V ) Characteristics Operating Voltage Operating Voltage Operating Current Pin 12 DC Voltage Pin 13 DC Voltage AFC Freerun Frequency AFC Pulse Width AFC Delay Time AFC Lock Range H AFC Lock Rnage L AFC Capture Range H AFC Capture Rrange L SYNC DET. Lock Range H SYNC DET. Lock Range L SYNC DET. Capture Range H SYNC DET. Capture V - SYNC Delay Time Oscillation Level Oscillation Frequency Blueback Sync Tip Level Blueback Pedestal Level Blueback Color Burst Level H Blueback Color Level H Range L Symbol DVDD AVDD Icc Vpi2 Vpi3 Ffr twd td Falh Fall Fach Fac1 Flh Fll Fch Fc1 tvd Vosc Fosc Vbst Vbpd Vbbh Vbch Min 3.5 4.5 10 2.3 1.3 15.5 3.7 1.0 +600 +400 143 6.7 100 14.3 10 4.0 6.3 1.85 2.5 2.75 3.1 Typ 5.0 5.0 20 2.5 1.45 15.7 4.0 2.5 153 7.7 107 15.3 14 4.5 7.0 2.05 2.7 2.95 3.3 Max 5.5 5.5 25 2.7 1.6 15.9 4.3 4.0 -900 -700 163 8.7 114 16.3 5.0 7.7 2.25 2.9 3.15 3.5 Unit V V mA V V KHz usec usec Hz Hz Hz Hz KHz KHz KHz KHz usec Vpp MHz V V V V Î 98-05-14 6 SPECIFICATION KS5514B -XX OPERATION DESCRIPTION MEMORY STRUCTURE ON SCREEN DISPLAY PROCESSOR After KS5514B records, in DATA RAM and CONTROL REGISTER, the serial DATA that is inputted from MICOM, in recording to the V-SYNC and H-SYNC signal, mix the COMPOSITE VIDEO signal and the font ROM data that is mapped to data RAM. In case that there is no composite video signal that is inputted to KS5514B, the SYNC detector becomes low, KS5514B makes the blue back signal in dividing the 4fsc signal and the blue back signal is outputted. The following table is the data structure that is inputted from MICOM. • Memory address consists of 16 bit • The data of address 0 ~ 239 are character data which are display on the screen. • The address 240 ~ 244 are the control registers. • Don`t care bit : the upper 8 bits (DA8 ~ DAF) in address 0 ~ address 239, the upper 5bits (DAB ~ DAF) in address 240 ~ address 244 Bit Addr 0 DAF DAE DAD DAC DAB DAA DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 * * * * * * * * BLI C6 C5 C4 C3 C2 C1 C0 (Font ROM Address) · · · 239 240 · · · · · · BLI C6 C5 C4 · · · C3 C2 C1 C0 HP0 * * * * * * * * * * * * * INT/ HSZ HSZ HSZ HSZ HP5 NON 21 20 11 10 BLI2 VSZ VSZ VSZ VSZ VP5 21 20 11 10 DSP DSP RAM TEST TC 2 1 ERS LE BK LE DSP BLK BLK CHA ON 1 0 PD3 PD2 - HP4 HP3 HP2 HP1 241 * * * * * VP4 VP3 VP2 VP1 VP0 242 * * * * * DSP 3 - LEV LEV PH2 PH1 1 0 BLI 1 BLI 0 EX PH0 243 * * * * * YM BCO 244 * * * * * SECAM NT/ PAL PD0 PC3 PC2 PC1 PC0 98-05-14 7 SPECIFICATION KS5514B -XX CONTROL REGISTER 1) Register 240 ON SCREEN DISPLAY PROCESSOR DA0 ~ DAA 0 Content Register State HP0 0 1 Function HS is horizontal display start position HS = Tc * Horizontal Start Position Remark 1 HP1 0 1 ^ 4 * ê ( HPn * 2 5 n=o n) +N ` Tc : osc. period ( 1 / 7MHz = 143 nsec ) 2 HP2 0 1 3 HP3 0 1 4 HP4 0 1 5 HP5 0 1 6 HSZ10 0 1 7 HSZ11 0 1 8 HSZ20 0 1 9 HSZ21 0 1 1 A INT/ NON 0 1 Interlace Mode Non-interlace Mode 3X 4X 2nd ~ 10 th line 1st line HSZ10 HSZ11 0 1 HSZ20 HSZ21 0 0 1X 3X 1 2X 4X HSZ11 HSZ21 0 0 1 1 HSZ10 HSZ20 0 1 0 1 9 10 11 12 N 1st line character size control to horizontaldirection 0 1X 1 2X 2nd ~ 10th line character size control to horizontaldirection 98-05-14 8 SPECIFICATION KS5514B -XX ON SCREEN DISPLAY PROCESSOR 2) Register 241 Content Register State VP0 0 1 1 VP1 0 1 2 VP2 0 1 3 VP3 0 1 4 VP4 0 1 5 VP5 0 1 6 VSZ10 0 1 7 VSZ11 0 1 8 VSZ20 0 1 9 VSZ21 0 1 1 A BLI2 0 1 V - SYNC 64 divide ( = 1 sec ) V - SYNC 32 divide ( = 0.5 sec ) Control the blink period 3X 4X VSZ21 0 VSZ11 0 1 VSZ10 0 1X 3X 1 2X 4X 2nd ~ 10th line character size control to vertical direction 1st line character size control to vertical direction V-SYNC HS VS Function VS is vertical start position VS = H * Vertical Start Position Remark DA0 ~ DAA 0 ^ 4 * ê ( VPn * 2 5 n=o n) +3 ` H : horizontal synchronous pulse time H-SYNC VSZ20 0 1X 1 2X 98-05-14 9 SPECIFICATION KS5514B -XX ON SCREEN DISPLAY PROCESSOR 3) Register 242 Content DA0 ~ DAA 0 Register State PH0 0 1 1 PH1 0 1 2 PH2 0 1 P2 P1 P0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 level 0 level 1 0 1 1H = 454Tc 1H = 455Tc Active mode Test mode RAM no erase RAM erase Display method of the 1st is fixed by BLK0 & BLK1 Display method of the 1st is variable Display method of 2nd - 9th is fixed by BLK0 & BLK1 Display method of 2nd - 9th is variable Display method of 10th is fixed by BLK0 & BLK1 Display method of 10th is variable Function NTSC PAL Remark E/4 E/2 7E/4 E 3E/4 3E/2 5E/4 0 Internal bias 1 Tc = 2 / fosc 0 E/4 E/2 -E/4 0 Back ground color control bit ²E 3E/4 3E/2 5 E/4 1 Internal bias 2 Internal bias 3 Color level control 3 LEVEL0 0 1 4 LEVEL1 0 1 5 TC 0 1 6 TEST 0 1 7 RAM ERS 0 1 0 1 8 DSP1 9 DSP2 0 1 A DSP3 0 1 98-05-14 10 SPECIFICATION KS5514B -XX ON SCREEN DISPLAY PROCESSOR 4) Register 243 DA0 ~ DAA Content Register State 0 BCO 0 1 1 YM 0 1 2 EX 0 1 3 BLI0 0 1 4 BLI1 0 1 5 BLK0 0 1 6 BLK1 0 1 7 DSP ON 8 LECHA 0 1 0 1 9 LEBLK 0 1 A 0 1 Display off Display on Character luminance level 1 Character luminance level 2 Blank luminance level 1 Blank luminance level 2 Blanking area coloring Full TV screen coloring The same luminance level character and back ground Variable background luminance level available External mode available Internal mode available Blinking mode BLI0 BLI1 control 0 1 0 OFF 1 DUTY 25% Blinking duty control Determined by BCO, BLK0 & BLK1 Remark Function Determined by BLK0 & BLK1 DUTY 50% DUTY 75% BLK0 Blanking mode BLK1 control 0 1 0 OFF O 1 C R C : character O : outline R : raster 98-05-14 11 SPECIFICATION KS5514B -XX ON SCREEN DISPLAY PROCESSOR 5) Register 244 Content Register State PC0 0 1 1 PC1 0 1 2 PC2 0 1 3 PC3 0 1 1 4 PD0 0 1 5 0 1 6 PD2 0 1 7 PD3 0 1 8 0 1 9 NT/ PAL A SECAM 0 1 0 1 L output H output L output H output L output H output NTSC mode PAL mode NTSC or PAL mode SECAM mode Pin 22 output data setting Pin 23 output data setting PC3 0 PC1 0 1 PC2 PC0 0 Hsync+Vsync output Port(PD0) output 0 1 Character1 output 1 Pin 22/23 output mode setting Pin 8 output mode setting Function Remark DA0 ~ DAA 0 Hsync(pin22) & Test mode Vsync(pin23) output Port(PD2/PD3) Character2, BLK2 output output Pin 8 output data setting 98-05-14 12 SPECIFICATION KS5514B -XX TEST CIRCUIT ON SCREEN DISPLAY PROCESSOR VSYNC HSYNC DVDD IN/OUT IN/OUT XTOUT XTIN SYD AFCR FSC AVDD CVOUT CVIN 1 + 0.82K 0.82K 12K 100K Ó 24 23 22 21 20 19 18 17 16 VSYNC DET 15 SYNC DETECT AFC 14 13 CLAMP OSD ROM OSD RAM 4 FSC BLUE BACK GENERATOR DATA REGISTER ADDR REGISTER DISPLAY CONTROL CONTROL REGISTER INPUT CONTROL DISPLAY OSC SHIFT REGISTER VIDEO MIXER INTERNAL BIAS CKT SYNC SEP CLAMP 1 2 3 SW1 A 4 B 10uH 5 6 7 8 4.7 0.82K 9 10 200K 100p 11 12 1K + 0.47 Ó + 104 68p 56p Ó DGND SCK ACB OSCIN OSCOUT CSB SIN P1 CLAMPIN AGND LPF AFCFIL 98-05-14 13 SPECIFICATION KS5514B -XX APPLICATION CIRCUIT (APP-082) ON SCREEN DISPLAY PROCESSOR R177 75 5V L104 100uH Q116 KA78T05 9V R176 430 C153 220 Ó+ Q116 A733 VIDEO OUT L105 R100 100 100uH 1N4148 CR104 CR105 DVDD P3 XTOUT C139 Y101 P2 XTIN C140 C152 203 SYD AFCR FSC Vin : 2Vpp Vsync: > 0.3Vpp C144 100 + Ó SECAM VIDEO IN C138 1 R172 100K + Ó 24 23 22 21 20 19 18 R175 12K C143 104 CVOUT CVIN 17 16 VSYNC DET 15 SYNC DETECT AFC 14 13 CLAMP OSD ROM OSD RAM 4 FSC BLUE BACK GENERATOR DATA REGISTER ADDR REGISTER DISPLAY CONTROL CONTROL REGISTER INPUT CONTROL DISPLAY OSC SHIFT REGISTER VIDEO MIXER INTERNAL BIAS CKT SYNC SEP CLAMP 1 2 C147 + 1 3 4 L106 10uH C142 68p 5 6 C141 82p 7 8 C137 4.7 9 10 + 11 C148 100p C149 122 12 DC 2.5V + Ó Ó R173 200K R174 1K C150 0.33 Ó DGND SCK ACB OSCIN OSCOUT CSB SIN P1 CLAMPIN AGND LPF AFCFIL DGND AGND The circuit drawn above is for Demo Board. • Y101 (4fsc X-TAL ) â NTSC : 14.31818MHz PAL : 17.734475MHz • C139 / C140 : The load CAP of X-TAL Y101 has a difference each according to its manufacturer. 98-05-14 14 SPECIFICATION KS5514B -XX APPLICATION CIRCUIT (APP-306) * Control Program : osd-3.exe 5V L105 100uH L104 100uH ON SCREEN DISPLAY PROCESSOR R177 Q116 KA7805 430 9V R176 C153 220 Ó+ 75 VIDEO OUT Q115 A733 AFCR FSC Vin : 2Vpp Vsync: > 0.3Vpp C144 100 R100 100 1N4148 CR104 CR105 DVDD P3 P2 XTOUT XTIN C152 203 SYD + Ó SECAM VIDEO IN C138 1 R172 100K + Ó 24 23 22 21 20 19 18 R175 12K CVOUT 17 16 VSYNC DET 15 SYNC DETECT AFC 14 13 CVIN CLAMP OSD ROM OSD RAM 4 FSC BLUE BACK GENERATOR DATA REGISTER ADDR REGISTER DISPLAY CONTROL CONTROL REGISTER INPUT CONTROL DISPLAY OSC SHIFT REGISTER VIDEO MIXER INTERNAL BIAS CKT SYNC SEP CLAMP 1 2 C147 + 1 3 4 L106 10uH C142 68p 5 6 C141 82p 7 8 C137 4.7 9 10 + R173 200K C148 100p 11 C149 122 12 DC 2.5V R174 + 1K C150 0.33 Ó Ó Ó DGND R101 1K SCK ACB OSCIN OSCOUT CSB SIN P1 CLAMPIN AGND LPF AFCFL KSR1001 Y102 14.31818MHz C154 15pF Y103 17.734475MHz To Pin 20 ( XT IN ) To Pin 21 ( XT OUT ) KSR2001 C155 47pF C157 47pF DGND AGND The circuit drawn above is for Demo Board. • Y102 (4fsc X-TAL ) â NTSC : 14.31818MHz Y103 (4fsc X-TAL ) â PAL : 17.734475MHz 98-05-14 15 SPECIFICATION KS5514B -XX PACKAGE DIMENSIONS 24-SDIP-300 ON SCREEN DISPLAY PROCESSOR Dimensions in Milimeters/Inches 98-05-14 16 SPECIFICATION MEMO HEAD OFFICE : 8/11FL., SAMSUNG MAIN BLDG. 250, 2 - KA. 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